Communication method between virtual devices, front-end device and rear-end device
By receiving inter-core interrupts and reading information directly from the ring buffer, the latency problem caused by CPU context switching in communication between virtual devices is solved, and real-time communication is achieved.
Patent Information
- Application Number
- CN202410296040.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-14
- Publication Date
- 2025-09-16
AI Technical Summary
In the prior art, during the communication process between virtual devices, the context switching of the CPU between the virtual machine and the virtual machine monitor causes delay and communication complexity, and lacks real-time performance.
By receiving the inter-core interrupt sent by the front-end device, the back-end interrupt service routine is triggered, the target information is read from the ring buffer, and the corresponding operation is performed according to the target information, avoiding the CPU context switching between the virtual machine and the virtual machine monitor, and directly interrupting the communication.
The context switching delay between the virtual machine and the virtual machine monitor is reduced, ensuring the real-time communication between virtual devices.
Smart Images
Figure CN120653357A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of embedded technology, and in particular to a communication method between virtual devices, a front-end device and a back-end device, as well as an electronic device, a computer-readable storage medium and a vehicle for implementing the communication method between virtual devices. Background Art
[0002] Currently, the front-end device (Guest Virtual Machine, Guest VM) and the back-end device (Host Virtual Machine, Host VM) transmit data through a ring buffer or shared memory, and notify each other via interrupt notifications after data transfer is complete. Specifically, if the back-end device needs to notify the front-end device, it uses a hypercall to the Virtual Machine Monitor (VMM), which then injects an interrupt into the Guest VM to complete the notification. If the Guest VM needs to notify the Host VM, it updates its status register (IO / MMIO trap) to trap the VMM, and the VMM then injects a notification interrupt into the Host VM to complete the notification. During this process, the CPUs of the Guest VM and Host VM need to perform at least one context switch between the VM and VMM, incurring additional latency and making the communication process complex and uncertain. Summary of the Invention
[0003] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a communication method between virtual devices, a front-end device and a back-end device, as well as an electronic device, a computer-readable storage medium and a vehicle for implementing the communication method between virtual devices, which can avoid CPU context switching between VM and VMM, reduce latency and ensure real-time performance.
[0004] In order to achieve the above objectives, the technical solutions provided by the embodiments of the present disclosure are as follows:
[0005] In a first aspect, the present disclosure provides a method for communication between virtual devices, comprising:
[0006] receiving a first inter-core interrupt sent by a front-end device;
[0007] In response to the first inter-core interrupt, triggering a backend interrupt service routine to read target information from the ring buffer, wherein the target information includes a read instruction or data to be processed;
[0008] Execute the corresponding target operation according to the target information.
[0009] As an optional implementation of the embodiment of the present disclosure, the target information is a read instruction; corresponding operations are performed according to the target information, including: parsing the read instruction to determine the target data identifier; reading the target data corresponding to the target data identifier from the simulation file; writing the target data into the ring buffer; obtaining the first CPU address information of the front-end device; sending a second inter-core interrupt to the first CPU corresponding to the front-end device according to the first CPU address information to notify the front-end device that the target data has been written into the ring buffer.
[0010] As an optional implementation of the embodiment of the present disclosure, the target information is data to be processed; and corresponding operations are performed according to the target information, including: writing the data to be processed into a simulation file.
[0011] As an optional implementation of the embodiment of the present disclosure, in response to the first inter-core interrupt, the back-end interrupt service program is triggered to drive the reading of target information from the ring buffer, including: parsing the first inter-core interrupt to determine the interrupt vector corresponding to the first inter-core interrupt; determining the back-end interrupt service program corresponding to the interrupt vector from the preset interrupt service table; triggering the back-end interrupt service program to drive the reading of target information from the ring buffer.
[0012] As an optional implementation of the embodiment of the present disclosure, the number of front-end devices is multiple; the ring buffer includes: a private ring buffer corresponding to each front-end device, and a public ring buffer shared by all front-end devices; the method also includes: parsing the first inter-core interrupt to determine the front-end device identifier corresponding to the first inter-core interrupt; and writing the front-end device identifier to the public buffer.
[0013] In a second aspect, the present disclosure provides a method for communication between virtual devices, comprising:
[0014] Initiate a target instruction and write the target information into the ring buffer; where the target instruction is a read instruction, the corresponding target information is a read instruction; where the target instruction is a write instruction, the corresponding target information is the data to be processed;
[0015] Get the second CPU address information of the backend device;
[0016] Based on the second CPU address information, a first inter-core interrupt is sent to the second CPU corresponding to the backend device to notify the backend device to read target information from the ring buffer and perform a corresponding operation.
[0017] As an optional implementation of the embodiment of the present disclosure, the target instruction is a read instruction, and the corresponding target information is a read instruction; the method also includes: receiving a second inter-core interrupt sent by the back-end device; in response to the second inter-core interrupt, triggering the front-end interrupt service program to drive the reading of target data from the ring buffer.
[0018] In a third aspect, the present disclosure provides a backend device, the backend device comprising:
[0019] A receiving module, configured to receive a first inter-core interrupt sent by a front-end device;
[0020] a first processing module, configured to trigger a backend interrupt service routine in response to a first inter-core interrupt, so as to read target information from a ring buffer, wherein the target information includes a read instruction or data to be processed;
[0021] The execution module is used to execute the corresponding target operation according to the target information.
[0022] As an optional implementation of the embodiment of the present disclosure, the target information is a read instruction; the execution module is specifically used to parse the read instruction and determine the target data identifier; read the target data corresponding to the target data identifier from the simulation file; write the target data into the ring buffer; obtain the first CPU address information of the front-end device; send a second inter-core interrupt to the first CPU corresponding to the front-end device according to the first CPU address information to notify the front-end device that the target data has been written into the ring buffer.
[0023] As an optional implementation of the embodiment of the present disclosure, the target information is data to be processed; the execution module is specifically used to write the data to be processed into a simulation file.
[0024] As an optional implementation of the embodiment of the present disclosure, the first processing module is specifically used to parse the first inter-core interrupt, determine the interrupt vector corresponding to the first inter-core interrupt; determine the back-end interrupt service program corresponding to the interrupt vector from the preset interrupt service table; trigger the back-end interrupt service program to drive the reading of target information from the ring buffer.
[0025] As an optional implementation of the embodiment of the present disclosure, there are multiple front-end devices; the ring buffer includes: a private ring buffer corresponding to each front-end device, and a public ring buffer shared by all front-end devices; the first processing module is also used to parse the first inter-core interrupt and determine the front-end device identifier corresponding to the first inter-core interrupt; and write the front-end device identifier to the public buffer.
[0026] In a fourth aspect, the present disclosure provides a front-end device, the front-end device comprising:
[0027] The second processing module is used to initiate a target instruction and write target information into the ring buffer; wherein, if the target instruction is a read instruction, the corresponding target information is a read instruction; if the target instruction is a write instruction, the corresponding target information is data to be processed;
[0028] An acquisition module is used to obtain the second CPU address information of the backend device;
[0029] The sending module is used to send a first inter-core interrupt to the second CPU corresponding to the backend device based on the second CPU address information, so as to notify the backend device to read target information from the ring buffer and perform corresponding operations.
[0030] As an optional implementation of the embodiment of the present disclosure, the target instruction is a read instruction, and the corresponding target information is a read instruction; the back-end device also includes a receiving module, which receives a second inter-core interrupt sent by the back-end device; in response to the second inter-core interrupt, the front-end interrupt service program is triggered to drive the reading of target data from the ring buffer.
[0031] In a fifth aspect, the present disclosure provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and runnable on the processor; when the computer program is executed by the processor, the computer program implements the communication method between virtual devices as described in the first aspect or any one of its optional embodiments, or implements the communication method between virtual devices as described in the second aspect or any one of its optional embodiments.
[0032] In a sixth aspect, the present disclosure provides a computer-readable storage medium, comprising: a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements the communication method between virtual devices as described in the first aspect or any one of its optional embodiments, or implements the communication method between virtual devices as described in the second aspect or any one of its optional embodiments.
[0033] In a seventh aspect, the present disclosure provides a vehicle comprising: a back-end device as described in the third aspect or any one of its optional embodiments, and a front-end device as described in the fourth aspect or any one of its optional embodiments.
[0034] In an eighth aspect, the present disclosure provides a computer program product, comprising: the computer program product comprises a computer program, and when the computer program runs on a computer, the computer implements the communication method between virtual devices as described in the first aspect or any one of its optional embodiments, or implements the communication method between virtual devices as described in the second aspect or any one of its optional embodiments.
[0035] The technical solution provided by the embodiments of the present disclosure has the following advantages over the prior art:
[0036] The embodiments of the present disclosure provide a communication method between virtual devices, a front-end device and a back-end device, as well as an electronic device, a computer-readable storage medium and a vehicle for implementing the communication method between virtual devices. The method first receives a first inter-core interrupt sent by the front-end device, and then triggers a back-end interrupt service program in response to the first inter-core interrupt to read target information from a ring buffer, and further executes corresponding target operations based on the target information. In this way, the interrupt sent by the front-end device in the embodiment of the present disclosure passes directly to the back-end device without falling into the virtual machine monitor, thereby reducing the delay caused by context switching between the virtual machine and the virtual machine monitor, and ensuring the real-time nature of communication between virtual devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0038] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0039] Figure 1 A flow chart of a communication method between virtual devices according to an embodiment of the present disclosure Figure 1 ;
[0040] Figure 2 A schematic diagram of CPU partitioning provided in an embodiment of the present disclosure;
[0041] Figure 3 A flow chart of a communication method between virtual devices provided in an embodiment of the present disclosure Figure 2 ;
[0042] Figure 4A Interaction of a communication method between virtual devices provided by the embodiment of the present disclosure Figure 1 ;
[0043] Figure 4B Schematic diagram of communication between virtual devices provided in the embodiment of the present disclosure Figure 1 ;
[0044] Figure 4C Schematic diagram of communication between virtual devices provided in the embodiment of the present disclosure Figure 2 ;
[0045] Figure 5 Interaction of a communication method between virtual devices provided by the embodiment of the present disclosure Figure 2 ;
[0046] Figure 6 Interaction of a communication method between virtual devices provided by the embodiment of the present disclosure Figure 3 ;
[0047] Figure 7 A schematic diagram of the structure of a front-end device provided in an embodiment of the present disclosure;
[0048] Figure 8 A schematic diagram of the structure of the back-end device provided in an embodiment of the present disclosure;
[0049] Figure 9 A structural diagram of an electronic device is provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION
[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following briefly introduces the technical terms required to be used in the embodiments or the prior art description:
[0051] A virtual machine (VM) is a complete computer system that is simulated by software and has complete hardware system functions and runs in a completely isolated environment.
[0052] A ring buffer is a data structure used to represent a fixed-size, end-to-end connected buffer, suitable for caching data streams. It is a first-in-first-out circular buffer that provides mutually exclusive access to the buffer to communicating programs.
[0053] VCPU is the virtualization technology of CPU. CPU virtualization is that a single CPU simulates multiple CPUs in parallel, allowing a platform to run multiple operating systems at the same time, and applications can run in independent spaces without affecting each other, thereby significantly improving the computer's work efficiency.
[0054] A physical CPU (pCPU) typically consists of numerous transistors on an integrated circuit board and can execute various arithmetic, logic, and control instructions. A physical CPU is a hardware component in a computer, serving as the core of the computer and controlling and executing its instructions. A virtual CPU, on the other hand, is created within a virtualized environment and primarily used to run virtualized operating systems and applications. A virtual CPU is essentially a software emulation, and the resources allocated to it from the physical CPU are limited, as multiple virtual CPUs may share the same physical CPU.
[0055] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.
[0056] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.
[0057] In order to solve some or all of the technical problems existing in the relevant technology, the embodiments of the present disclosure provide a communication method between virtual devices, a front-end device and a back-end device, as well as an electronic device, a computer-readable storage medium and a vehicle for implementing the communication method between virtual devices, wherein the method first receives a first inter-core interrupt sent by the front-end device, and then triggers a back-end interrupt service program in response to the first inter-core interrupt to read target information from a ring buffer, and further executes corresponding target operations based on the target information. In this way, the interrupt sent by the front-end device in the embodiment of the present disclosure passes directly to the back-end device without falling into the virtual machine monitor, thereby reducing the delay caused by context switching between the virtual machine and the virtual machine monitor, and ensuring the real-time nature of communication between virtual devices.
[0058] A communication method between virtual devices provided in the embodiments of the present disclosure can be implemented by a front-end device, a back-end device or an electronic device, and the electronic device includes but is not limited to a vehicle terminal, a server, a personal computer, a laptop computer, a tablet computer, a smart phone, etc. The operating system of the electronic device may include Android, a mobile operating system (iOS) developed by Apple, an operating system (Windows) developed by Microsoft Corporation of the United States, etc., and the embodiments of the present disclosure are not limited to this. The electronic device can be run alone to implement the present disclosure, or it can be connected to a network and implement the present disclosure through interactive operations with other computer devices in the network. Among them, the network where the electronic device is located includes but is not limited to the Internet, a wide area network, a metropolitan area network, a local area network, a virtual private network (VPN) network, etc.
[0059] It should be noted that the protection scope of the communication method between virtual devices described in the embodiment of the present disclosure is not limited to the execution order of the steps listed in this embodiment. All solutions implemented by adding, reducing or replacing steps in the existing technology based on the principles of the present disclosure are included in the protection scope of the present disclosure.
[0060] like Figure 1 As shown, Figure 1 A flow chart of a communication method between virtual devices according to an embodiment of the present disclosure Figure 1 The method is applied to the backend device Host VM and mainly includes the following steps S101 to S103:
[0061] S101: Receive a first inter-core interrupt sent by a front-end device.
[0062] On the Guest VM side of the front-end device, the front-end device first initiates a target instruction and writes the target information into the ring buffer. Then, the front-end device obtains the second CPU address information of the back-end device, and then based on the second CPU address information, sends a first inter-processor interrupt (IPI) to the second CPU corresponding to the back-end device to notify the back-end device to read the target information from the ring buffer and perform the corresponding operation.
[0063] The target instruction includes a read instruction or a write instruction. When the target instruction is a read instruction, the corresponding target information is also a read instruction. It can be understood that the front-end device initiates a read instruction and writes the read instruction into the ring buffer to instruct the back-end device to provide the data to be processed for the front-end device to read. When the target instruction is a write instruction, the corresponding target information is the data to be processed, which is the data to be written to the back-end device. It can be understood that the front-end device initiates a write instruction and writes the data to be processed into the ring buffer so that the back-end device can write the data to be processed.
[0064] The second CPU address information is the physical central processing unit (pCPU) address information of the backend device. In the embodiment of the present disclosure, the central processing unit is pre-allocated so that the vCPU and pCPU used by each VM are in one-to-one correspondence.
[0065] For example, Figure 2 As shown, Figure 2 This is a CPU partition diagram provided by an embodiment of the present disclosure. In this disclosure, pCPU0 230 and pCPU1 231 are allocated to the virtual cores vCPU0 213 and vCPU1 214 of the backend device Host VM 210, respectively, and pCPU2 232 and pCPU3 233 are allocated to the virtual cores vCPU0 223 and vCPU1 224 of the front-end device Guest VM 220, respectively.
[0066] It should be noted that when the front-end device and the back-end device are started, the front-end device and the back-end device inform the other end of their respective CPU address information (ipi_virt_vector@CPU_ID) through the startup parameters, or inform the other end during initialization through the protocol of the I / O paravirtualization solution (virtio).
[0067] The CPU address information includes the interrupt vector or interrupt number (ipi_virt_vector) and the inter-processor interrupt (IPI) address information (CPU_ID) of the physical core pCPU. The IPI address information includes: the IPI address identifier, or the interrupt routing address, exemplarily, the APIC ID and the CPU ID.
[0068] The front-end device sends the first inter-core interrupt to the second CPU corresponding to the back-end device according to the second CPU address, so that the first inter-core interrupt is directly passed through the second CPU of the back-end device without falling into the virtual machine monitor VMM, reducing the generation of VM-EXIT, and eliminating the need for VMM to perform interrupt distribution processing, avoiding additional delays and ensuring real-time communication.
[0069] In some embodiments, during the process of the backend device executing step S101, the first inter-core interrupt is directly sent to the second CPU of the backend device, and real-time performance is guaranteed.
[0070] S102 : In response to the first inter-core interrupt, trigger a backend interrupt service routine to read target information from the ring buffer.
[0071] In the embodiment of the present disclosure, a backend interrupt service routine (ipi_isr_backend) is pre-added in the kernel of the backend device.
[0072] In some embodiments, when executing S102, the back-end device first parses the first inter-core interrupt, determines the interrupt vector corresponding to the first inter-core interrupt, and then determines the back-end interrupt service program corresponding to the interrupt vector from the preset interrupt service table, and further triggers the back-end interrupt service program to read the target information from the ring buffer.
[0073] The preset interrupt service table is used to store the corresponding relationship between the interrupt vector and the back-end interrupt service program.
[0074] Specifically, the backend device triggers the backend interrupt service routine ipi_isr_backend in response to the first inter-core interrupt, notifies the backend simulation device, and the backend simulation device executes step S103 in response to the notification. The backend simulation device implements an interface through software for the backend device to call. The backend simulation device can be a driver for the backend device.
[0075] S103: Execute corresponding target operation according to the target information.
[0076] As mentioned above, the target information includes a read instruction or data to be processed. The following will illustrate the execution process of step S103 from two aspects:
[0077] (1) The target information is a read instruction
[0078] If the target information is a read instruction, indicating that the front-end device needs to read certain data from the back-end device, then during the execution of step S103, the read instruction is first parsed to determine the target data identifier, then the target data corresponding to the target data identifier is read from the simulation file, and then the target data is written into the ring buffer. Furthermore, the address information of the first CPU of the front-end device is obtained, and then a second inter-core interrupt is sent to the first CPU corresponding to the front-end device based on the first CPU address information to notify the front-end device that the target data has been written into the ring buffer.
[0079] The first CPU address information is the physical core pCPU address information of the front-end device, which is similar to the second core address information mentioned above. It is pre-assigned and corresponds to the virtual core vCPU of the front-end device. Figure 2 shown.
[0080] Specifically, when the back-end device reads a read instruction from the ring buffer, it indicates that the front-end device needs to read the target data from the back-end device, and thus issues a read instruction. The back-end device then parses the read instruction, determines the target data identifier contained in the instruction, reads the target data from the simulation file according to the target data identifier, and then writes the read target data into the ring buffer. Based on the address information of the first CPU of the front-end device, a second inter-core interrupt is sent to the first CPU of the front-end device, thereby directly connecting to the first CPU of the front-end device via the inter-core interrupt. The target data has been written into the ring buffer and can be read by the front-end device itself. This implements the execution of a read operation in response to the read instruction.
[0081] In some embodiments, there are multiple front-end devices, and the ring buffer includes a private ring buffer corresponding to each front-end device and a public ring buffer shared by all front-end devices. The first inter-core interrupt is parsed to obtain the front-end device identifier corresponding to the first inter-core interrupt, and the front-end device identifier is then written to the public buffer. It will be understood that the public ring buffer is used to store the device identifiers of multiple front-end devices to distinguish between different front-end devices.
[0082] Optionally, when the target information is a read instruction, after the back-end device writes the target data into the ring buffer, it needs to notify the front-end device that the target data has been written. The back-end device first reads the front-end device identifier corresponding to the first inter-core interrupt from the public buffer, and then determines the first CPU address information corresponding to the front-end device indicated by the front-end device identifier, and then sends the second inter-core interrupt to the first CPU corresponding to the front-end device based on the first CPU address information.
[0083] Specifically, considering a possible scenario, there is one back-end device and multiple front-end devices in the scenario, and the number of available interrupt vectors is limited. If the number of front-end devices is too large, there will be a situation where the interrupt vectors are insufficient. At this time, a public ring buffer is added to store the device identification (VM+Device ID) of each front-end device. After receiving the first inter-core interrupt sent by a front-end device, the back-end device parses it to obtain the front-end device identification (VM+Device ID) corresponding to the first inter-core interrupt, and then writes the front-end device identification into the public buffer to indicate that the back-end device is communicating with this front-end device. In the subsequent communication process, the back-end device determines which front-end device it is through the device identification in the public ring buffer. It should be emphasized that the second inter-core interrupt sent by the back-end device to the front-end device carries the device identification (Device ID) of the back-end device, which is different from the fields contained in the front-end device identification (VM+Device ID).
[0084] (2) The target information is the data to be processed
[0085] When the target information is data to be processed, it indicates that the front-end device needs to write the data to be processed to the back-end device. During the execution of step S103, the back-end device has read the data to be processed from the ring buffer and then written the data to be processed into the simulation file, thereby executing a write operation in response to the write instruction.
[0086] In summary, the embodiments of the present disclosure provide a communication method between virtual devices, which is applied to a back-end device. First, a first inter-core interrupt sent by a front-end device is received, and then a back-end interrupt service program is triggered in response to the first inter-core interrupt to drive the reading of target information from a ring buffer, and further execute corresponding target operations based on the target information. In this way, the interrupt sent by the front-end device in the embodiments of the present disclosure passes directly through the back-end device without falling into the virtual machine monitor, thereby reducing the delay caused by the context switching between the virtual machine and the virtual machine monitor, and ensuring the real-time nature of communication between virtual devices.
[0087] like Figure 3 As shown, Figure 3 A flow chart of a communication method between virtual devices provided in an embodiment of the present disclosure Figure 2 The method is applied to a front-end device and mainly includes the following steps S301 to S303:
[0088] S301: Initiate a target instruction and write target information into a ring buffer.
[0089] The target instruction includes a read instruction or a write instruction.
[0090] The following describes the execution process of step S301 from two different perspectives: a target instruction is a read instruction, or a target instruction is a write instruction.
[0091] (1) The target instruction is a read instruction
[0092] When the target instruction is a read instruction, the corresponding target information is also a read instruction. It can be understood that the front-end device initiates a read instruction and writes the read instruction into the ring buffer to instruct the back-end device to provide data to be processed for the front-end device to read.
[0093] In some embodiments, the application app of the front-end device Guest VM first initiates a data write operation, and then the driver of the front-end device responds to the data write operation and writes the to-be-processed data into the ring-buffer.
[0094] (2) The target instruction is a write instruction
[0095] When the target instruction is a write instruction, the corresponding target information is the data to be processed, which is the data to be written to the back-end device. It can be understood that the front-end device initiates the write instruction and writes the data to be processed into the ring buffer so that the back-end device can write the data to be processed.
[0096] In some embodiments, the application program app of the front-end device Guest VM first initiates a read operation, and then the driver of the front-end device responds to the read operation and writes the read command into the ring-buffer.
[0097] S302: Acquire the second CPU address information of the backend device.
[0098] The second CPU address information is the physical CPU (pCPU) address information of the backend device.
[0099] In some embodiments, when the front-end device and the back-end device are started, the front-end device and the back-end device inform the other end of their respective CPU address information (ipi_virt_vector@CPU_ID) through startup parameters, or inform the other end during initialization through the protocol of the I / O semi-virtualization solution (virtio).
[0100] The CPU address information includes the interrupt vector or interrupt number, and the inter-core interrupt IPI address information (CPU_ID) of the physical core pCPU. The IPI address information includes: an IPI address identifier, or an interrupt routing address, exemplarily, an APIC ID and a CPU ID.
[0101] S303: Send a first inter-core interrupt to the second CPU corresponding to the backend device based on the second CPU address information to notify the backend device to read target information from the ring buffer and perform corresponding operations.
[0102] The front-end device sends the first inter-core interrupt to the second CPU corresponding to the back-end device according to the second CPU address information, so that the first inter-core interrupt is directly passed through the second CPU of the back-end device without falling into the virtual machine monitor VMM, and there is no need for the VMM to perform interrupt distribution processing, thereby avoiding additional delays and ensuring the real-time nature of communication.
[0103] like Figure 4A As shown, Figure 4A Interaction of a communication method between virtual devices provided by the embodiment of the present disclosure Figure 1 The method is applied to the front-end device and the back-end device, and includes the following steps S401 to S406:
[0104] It should be noted that the communication interaction between the front-end device and the back-end device also includes a preparation phase and a startup phase.
[0105] During the preparation phase, cores (CPUs) are pre-allocated so that each VM has a one-to-one correspondence between its virtual cores (vCPUs) and physical cores (pCPUs). This allows interrupts between VMs to flow directly to the other VM without falling through to the virtual machine monitor (VMM).
[0106] Add a front-end interrupt service routine (ipi_isr_frontend) to the kernel of the front-end device, and add a back-end interrupt service routine (ipi_isr_backend) to the kernel of the back-end device. Optionally, if the device itself has inter-core interrupt processing logic, add the interrupt service processing code to the device.
[0107] Exemplarily, the front-end device includes an IPI template, an interrupt service processing code is pre-added, and a front-end interrupt service program (ipi_isr_frontend) is generated according to the IPI template and the interrupt service processing code.
[0108] During the startup phase, the front-end device and the back-end device inform each other of their respective CPU address information (ipi_virt_vector@CPU_ID) through startup parameters, or inform the other end during initialization through the protocol of the I / O paravirtualization solution (virtio).
[0109] The CPU address information includes the interrupt vector or interrupt number, and the inter-core interrupt IPI address information (CPU_ID) of the physical core pCPU. The IPI address information includes: an IPI address identifier, or an interrupt routing address, exemplarily, an APIC ID and a CPU ID.
[0110] After the preparation and startup phases are completed, the communication interaction phase begins, such as S401 to S406:
[0111] S401: The front-end device initiates a target instruction and writes target information into a ring buffer.
[0112] S402: The front-end device obtains the second CPU address information of the back-end device.
[0113] S403: The front-end device sends a first inter-core interrupt to the second CPU corresponding to the back-end device based on the second CPU address information.
[0114] S404: The backend device receives a first inter-core interrupt sent by the frontend device.
[0115] S405 : The backend device triggers a backend interrupt service program in response to the first inter-core interrupt to drive reading of target information from the ring buffer.
[0116] S406: The backend device performs the corresponding target operation according to the target information.
[0117] For example, Figure 4B As shown, Figure 4B Schematic diagram of communication between virtual devices provided in the embodiment of the present disclosure Figure 1 , the figure shows the backend device Host VM 210 and the frontend device Guest VM 220, as well as the private ring buffer 401.
[0118] The backend device Host VM 210 includes: user layer user 211, kernel layer kernel 212, vCPU0 213 and vCPU1 214. The user layer user 211 includes a device model, and the kernel layer kernel 212 includes: driver, backend terminal service program ipi_isr_backend and virtual machine monitor model VMM-mod.
[0119] The front-end device Guest VM 220 includes: user layer user 221, kernel layer kernel 222, vCPU0 223 and vCPU1 224. The user layer user 221 includes application programs, and the kernel layer kernel 222 includes: driver driver and front-end terminal service program ipi_isr_frontend.
[0120] refer to Figure 4BThe front-end device Guest VM 220 initiates a target instruction by the application, writes the target information into the private ring buffer 401, and then sends a first inter-core interrupt IPI to the second CPU (such as vCPU 213) corresponding to the back-end device Host VM 210 based on the second CPU address information of the back-end device Host VM 210; after receiving the first inter-core interrupt IPI, the back-end device triggers the back-end interrupt service program, and the back-end interrupt service program notifies the back-end simulation device to read the target information from the private ring buffer 401 and execute the target operation corresponding to the target information.
[0121] For example, in a scenario where a backend device communicates with multiple frontend devices, if there are not enough interrupt vectors to allocate, a ring buffer is added as a common ring buffer shared by all frontend devices. Figure 4C As shown, Figure 4C Schematic diagram of communication between virtual devices provided in the embodiment of the present disclosure Figure 2 ,exist Figure 4B The backend device Host VM 210 and the frontend device Guest VM 220 are shown, as well as a private ring buffer 401 and a public ring buffer 402 . Figure 4C More front-end devices are not shown in the figure. The public ring buffer 402 is used to store the device identifications of multiple front-end devices.
[0122] For example, taking the front-end device Guest VM 220 reading target data from the back-end device Host VM 210 as an example, the front-end device Guest VM 220 initiates a read instruction and writes the read instruction into the private ring buffer 401, and then sends a first inter-core interrupt IPI to the second CPU (such as vCPU 213) of the back-end device Host VM 210. The back-end device receives the first inter-core interrupt IPI, parses it to obtain the device identifier of the front-end device, to determine which front-end device in the multi-front-end device scenario sent the first inter-core interrupt, and writes the front-end device identifier into the public ring buffer 402. Then, in response to the first inter-core interrupt IPI, the back-end interrupt service program is triggered, and the read command is obtained from the private ring buffer 401. The read command is then parsed to determine the identifier of the target data that the front-end device expects to read, so as to read the target data from the simulation file based on this, and then the target data is written into the private ring buffer 401. It is further necessary to notify the front-end device Guest VM 220. At this time, the corresponding front-end device Guest is determined according to the device identifier of the front-end device Guest VM 220 stored in the public ring buffer 401. The first CPU address information of VM220 is used to send a second inter-core interrupt to the first CPU (such as vCPU 223) of the front-end device Guest VM 220, notifying the front-end device that the target data has been written into the private ring buffer 401 and is available for reading.
[0123] The following describes the execution process of target operations according to the different target instructions and target information:
[0124] 1) The target instruction is a write instruction
[0125] like Figure 5 As shown, Figure 5 Interaction of a communication method between virtual devices provided by the embodiment of the present disclosure Figure 2 The method is applied to the front-end device and the back-end device, and includes the following steps S501 to S506:
[0126] S501: The front-end device initiates a write instruction to write the data to be processed into the ring buffer.
[0127] S502: The front-end device obtains the second CPU address information of the back-end device.
[0128] S503: The front-end device sends a first inter-core interrupt to the second CPU corresponding to the back-end device based on the second CPU address information.
[0129] S504: The backend device receives a first inter-core interrupt sent by the frontend device.
[0130] S505 : The backend device triggers a backend interrupt service program in response to the first inter-core interrupt, so as to drive reading of the to-be-processed data from the ring buffer.
[0131] S506: The back-end device writes the data to be processed into a simulation file.
[0132] In the above steps S501 to S506, the application app of the front-end device Guest VM first initiates a data write operation, and then the driver of the front-end device responds to the data write operation and writes the data to be processed into the ring buffer ring-buffer, and then sends the first inter-core IPI interrupt to the back-end device according to the CPU address information of the back-end device. The first inter-core interrupt sent by the front-end device is received, and in response to the first inter-core interrupt, the back-end interrupt service program ipi_isr_frontend is triggered to notify the back-end simulation device to read the data to be processed from the ring buffer. After receiving the notification, the back-end simulation device reads the data to be processed from the ring buffer and writes the data to be processed into the simulation file. In this way, the interrupt is passed directly to the CPU through the pre-allocated CPU, achieving the purpose of notifying the opposite device without falling into the VMM, thereby reducing the delay caused by the context switch between the VM and the VMM and ensuring the real-time performance of the system.
[0133] It should be emphasized that the specific implementation of the above steps S501 to S506 can refer to the above steps S101 to S103 and S301 to S303, and will not be elaborated herein.
[0134] 2) The target instruction is a read instruction
[0135] like Figure 6 As shown, Figure 6 Interaction of a communication method between virtual devices provided by the embodiment of the present disclosure Figure 3 The method is applied to the front-end device and the back-end device, and includes the following steps S601 to S612:
[0136] S601: The front-end device initiates a read instruction and writes the read instruction into the ring buffer.
[0137] S602: The front-end device obtains the second CPU address information of the back-end device.
[0138] S603: The front-end device sends a first inter-core interrupt to the second CPU corresponding to the back-end device based on the second CPU address information.
[0139] S604: The backend device receives a first inter-core interrupt sent by the frontend device.
[0140] S605 , the backend device triggers a backend interrupt service routine in response to the first inter-core interrupt to read a read instruction from the ring buffer;
[0141] S606: The back-end device parses the read instruction and determines the target data identifier.
[0142] S607: The backend device reads the target data corresponding to the target data identifier from the simulation file.
[0143] S608: The backend device writes the target data into the ring buffer.
[0144] S609: The backend device obtains the first CPU address information of the frontend device.
[0145] S610: The backend device sends a second inter-core interrupt to the first CPU corresponding to the front-end device according to the first CPU address information.
[0146] S611. The front-end device receives a second inter-core interrupt sent by the back-end device.
[0147] S612: The front-end device triggers a front-end interrupt service program in response to the second inter-core interrupt to read target data from the ring buffer.
[0148] In steps S601 to S612, the front-end device application first initiates a read operation. The front-end device driver then responds to the read operation by writing a read command into the ring buffer and then sending a first inter-core interrupt to the back-end device based on the second CPU address information of the back-end device. The back-end device receives the first inter-core interrupt sent by the front-end device and, in response to the first inter-core interrupt, triggers a back-end interrupt service routine to notify the back-end simulation device to read a read instruction from the ring buffer. Upon receiving the notification, the back-end simulation device reads the read instruction from the ring buffer, parses the read instruction, and, in response to the read instruction, reads target data from the simulation file, writes the target data into the ring buffer, and then sends a second inter-core interrupt to the first CPU of the front-end device based on the first CPU address information of the front-end device. The front-end device receives the second inter-core interrupt sent by the back-end device and, in response to the second inter-core interrupt, triggers a front-end interrupt service routine to notify the front-end simulation device to read the target data from the ring buffer and then returns the target data to the application.
[0149] The specific implementations corresponding to the above steps S601 to S612 can refer to the above steps S101 to S103 and S301 to S303, and are not described in detail in this disclosure.
[0150] like Figure 7 As shown, Figure 7 A schematic diagram of the structure of a backend device provided in an embodiment of the present disclosure, the backend device includes:
[0151] A receiving module 701 is configured to receive a first inter-core interrupt sent by a front-end device;
[0152] A first processing module 702 is configured to trigger a backend interrupt service routine in response to a first inter-core interrupt to read target information from a ring buffer, wherein the target information includes a read instruction or data to be processed;
[0153] The execution module 703 is used to execute the corresponding target operation according to the target information.
[0154] As an optional implementation of the embodiment of the present disclosure, the target information is a read instruction; the execution module 703 is specifically used to parse the read instruction and determine the target data identifier; read the target data corresponding to the target data identifier from the simulation file; write the target data into the ring buffer; obtain the first CPU address information of the front-end device; send a second inter-core interrupt to the first CPU corresponding to the front-end device according to the first CPU address information to notify the front-end device that the target data has been written into the ring buffer.
[0155] As an optional implementation of the embodiment of the present disclosure, the target information is data to be processed; the execution module 703 is specifically used to write the data to be processed into a simulation file.
[0156] As an optional implementation of the embodiment of the present disclosure, the first processing module 702 is specifically used to parse the first inter-core interrupt, determine the interrupt vector corresponding to the first inter-core interrupt; determine the back-end interrupt service program corresponding to the interrupt vector from the preset interrupt service table; trigger the back-end interrupt service program to drive the reading of target information from the ring buffer.
[0157] As an optional implementation of the embodiment of the present disclosure, the number of front-end devices is multiple; the ring buffer includes: a private ring buffer corresponding to each front-end device, and a public ring buffer shared by all front-end devices; the first processing module 702 is also used to parse the first inter-core interrupt, determine the front-end device identifier corresponding to the first inter-core interrupt; and write the front-end device identifier to the public buffer.
[0158] like Figure 8 As shown, Figure 8 This is a schematic diagram of the structure of a front-end device provided in an embodiment of the present disclosure, which includes:
[0159] The second processing module 801 is used to initiate a target instruction and write target information into the ring buffer; wherein, if the target instruction is a read instruction, the corresponding target information is a read instruction; if the target instruction is a write instruction, the corresponding target information is data to be processed;
[0160] An acquisition module 802 is configured to acquire address information of a second CPU of a backend device;
[0161] The sending module 803 is configured to send a first inter-core interrupt to the second CPU corresponding to the backend device based on the second CPU address information, so as to notify the backend device to read target information from the ring buffer and perform corresponding operations.
[0162] As an optional implementation of the embodiment of the present disclosure, the target instruction is a read instruction, and the corresponding target information is a read instruction; the back-end device also includes a receiving module, which receives a second inter-core interrupt sent by the back-end device; in response to the second inter-core interrupt, the front-end interrupt service program is triggered to drive the reading of target data from the ring buffer.
[0163] like Figure 9 As shown, Figure 9 The present disclosure provides a schematic diagram of the structure of an electronic device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor. When executed by the processor, the computer program implements the various steps of the method described in the embodiment of the method for communication between virtual devices. The aforementioned embodiments achieve the same technical effects, and to avoid repetition, they are not described here.
[0164] An embodiment of the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the communication method between virtual devices in the above-mentioned method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
[0165] The computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
[0166] An embodiment of the present disclosure provides a vehicle, which includes the front-end device and the back-end device as described above, or the electronic device as described above, so as to implement the various processes of the communication method between virtual devices in the above method embodiment and achieve the same technical effect. To avoid repetition, they will not be described here.
[0167] An embodiment of the present disclosure provides a computer program product, which stores a computer program. When the computer program is executed by a processor, the various processes of the communication method between virtual devices in the above method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
[0168] Those skilled in the art will appreciate that embodiments of the present disclosure may be provided as methods, systems, or computer program products. Thus, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code.
[0169] In the several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of the code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.
[0170] In the present disclosure, a processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.
[0171] In this disclosure, memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.
[0172] In this disclosure, computer-readable media includes permanent and non-permanent, removable and non-removable storage media. Storage media can be implemented by any method or technology to store information, and the information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory media such as modulated data signals and carrier waves.
[0173] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.
[0174] The above are merely specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not limited to these embodiments, but is to be construed in the broadest manner consistent with the principles and novel features disclosed herein.
Claims
1. A communication method between virtual devices, characterized in that: include: receiving a first inter-core interrupt sent by a front-end device; In response to the first inter-core interrupt, triggering a backend interrupt service routine to read target information from a ring buffer, wherein the target information includes a read instruction or data to be processed; Execute the corresponding target operation according to the target information.
2. The method according to claim 1, characterized in that The target information is a read instruction; The performing corresponding operations according to the target information includes: Parsing the read instruction to determine the target data identifier; Read the target data corresponding to the target data identifier from the simulation file; Writing the target data into the ring buffer; Acquire first CPU address information of the front-end device; A second inter-core interrupt is sent to the first CPU corresponding to the front-end device according to the first CPU address information to notify the front-end device that the target data has been written into the ring buffer.
3. The method according to claim 1, characterized in that The target information is data to be processed; The performing corresponding operations according to the target information includes: The data to be processed is written into a simulation file.
4. The method according to claim 1, wherein The step of triggering a backend interrupt service routine in response to the first inter-core interrupt to drive reading of target information from a ring buffer includes: parsing the first inter-core interrupt to determine an interrupt vector corresponding to the first inter-core interrupt; Determine the backend interrupt service routine corresponding to the interrupt vector from a preset interrupt service table; The backend interrupt service routine is triggered to drive the reading of the target information from the ring buffer.
5. The method according to claim 4, characterized in that There are multiple front-end devices; the ring buffer includes: a private ring buffer corresponding to each front-end device, and a public ring buffer shared by all front-end devices; The method further comprises: parsing the first inter-core interrupt to determine a front-end device identifier corresponding to the first inter-core interrupt; The front-end device identifier is written into the public buffer.
6. A communication method between virtual devices, characterized in that: include: Initiate a target instruction to write target information into a ring buffer; wherein, if the target instruction is a read instruction, the corresponding target information is the read instruction; if the target instruction is a write instruction, the corresponding target information is data to be processed; Get the second CPU address information of the backend device; Based on the second CPU address information, a first inter-core interrupt is sent to the second CPU corresponding to the backend device to notify the backend device to read the target information from the ring buffer and perform a corresponding operation.
7. The method according to claim 6, characterized in that The target instruction is a read instruction, and the corresponding target information is the read instruction; The method further comprises: receiving a second inter-core interrupt sent by the backend device; In response to the second inter-core interrupt, a front-end interrupt service routine is triggered to drive the reading of target data from the ring buffer.
8. A backend device, characterized in that: include: A receiving module, configured to receive a first inter-core interrupt sent by a front-end device; a first processing module, configured to trigger a backend interrupt service routine in response to the first inter-core interrupt, so as to read target information from a ring buffer, wherein the target information includes a read instruction or data to be processed; An execution module is used to execute a corresponding target operation according to the target information.
9. A front-end device, characterized in that: include: A second processing module is configured to initiate a target instruction and write target information into a ring buffer; wherein, if the target instruction is a read instruction, the corresponding target information is the read instruction; and if the target instruction is a write instruction, the corresponding target information is data to be processed; An acquisition module is used to obtain the second CPU address information of the backend device; The sending module is used to send a first inter-core interrupt to the second CPU corresponding to the back-end device based on the second CPU address information, so as to notify the back-end device to read the target information from the ring buffer and perform a corresponding operation.
10. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the method for communication between virtual devices according to any one of claims 1 to 5, or claims 6 to 7.
11. A computer-readable storage medium, characterized in that include: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for communication between virtual devices according to any one of claims 1 to 5 or claims 6 to 7 is implemented.
12. A vehicle, characterized in that: include: The back-end device as claimed in claim 8, and the front-end device as claimed in claim 9.