Dynamic delay adaptive asynchronous time sequence control circuit for SAR ADC (Synthetic Aperture Radar Analog to Digital Converter)

Abstract

The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a dynamic delay adaptive asynchronous time sequence control circuit for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). According to the circuit disclosed by the invention, through an innovative circuit architecture and a control method, remarkable breakthrough is realized in the aspects of conversion precision and speed. According to the circuit, a unique two-stage dynamic delay adjustment mechanism is adopted, intelligent optimization of delay time is achieved based on real-time comparison frequency monitoring, the effective conversion rate under 16-bit precision is improved by 25% or above, and meanwhile it is kept that ENOB is not lower than 15 bits. The innovative current charging capacitance type delay unit is combined with the PVT compensation technology, and the delay time stability is superior to + / -3% within the working temperature range of-40 DEG C to 125 DEG C. Through a dynamic adjustment algorithm of cooperative work of a shift register and a lookup table, the system can automatically adapt to establishment time change of 10 ns to 50 ns, and compared with a fixed delay scheme, invalid waiting time is saved by more than 30%.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital converters, and in particular relates to a dynamic delay adaptive asynchronous timing control circuit for SAR ADC. Background Art

[0002] SAR ADCs are widely used in high-precision data acquisition systems due to their simple structure and low power consumption. In traditional SAR ADC designs, asynchronous timing control circuits typically use a fixed delay mechanism to coordinate the timing of the comparator, capacitor-to-digital converter (CDAC), and logic control unit. However, this fixed-delay design suffers from the following technical drawbacks: 1. Inadequate delay adaptability: Because the required settling time of the CDAC and comparator varies with factors such as the reference signal amplitude and PVT, a fixed delay can result in excessive (reduced conversion speed) or insufficient (comparison errors), impacting the overall ADC performance. 2. High PVT sensitivity: Timing consistency in fixed-delay circuits is difficult to guarantee when PVT varies, potentially introducing additional nonlinear errors, especially in high-precision applications. 3. Low energy efficiency: To ensure worst-case timing margins, traditional designs often use a fixed maximum delay setting, which increases ineffective waiting time and limits the energy efficiency of SAR ADCs. Therefore, there is an urgent need for an asynchronous timing control circuit that can adaptively adjust the delay in real time to balance conversion speed, accuracy, and robustness of SAR ADCs. The existing patent CN117978173A uses a fixed delay chain to control the SAR ADC timing (see claims 2, Figure 4 and Figure 6 ), which is a mechanism that measures the optimal delay value and then compensates, but the delay time cannot adapt to changes in the reference voltage amplitude during the comparison process. Summary of the Invention

[0003] In response to the above technical problems, the present invention proposes a dynamic delay adaptation mechanism based on comparison number monitoring. By adjusting the delay time, the signal settling time requirements required under different reference voltages are achieved, significantly improving the performance of the SAR ADC.

[0004] The technical solution of the present invention is:

[0005] A dynamic delay adaptive asynchronous timing control circuit for SAR ADC, the SAR ADC includes a high-precision comparator and a CDAC, wherein the CDAC is a differential CDAC with two sides, each side including 16 capacitors and 16 groups of drive switches, one end of the 16 capacitors is connected to the common-mode signal VCM through the common-mode switch, the other end of the 16 capacitors is respectively connected to one end of the 16 groups of drive switches, the other end of the 16 groups of drive switches is a three-input switch selector, the three input signals are respectively an input signal, a differential reference voltage Vrefp and Vrefn, wherein the input signal is respectively connected to the input signal VIN and the common-mode signal VCM through two input selectors; one end of the 16 capacitors on both sides connected to the common-mode switch is respectively connected to the two input ends of the high-precision comparator; the high-precision The high-precision comparator outputs a signal DOUT_CMP and a signal DATA_VALID to the asynchronous timing control circuit, respectively, where the signal DOUT_CMP is the comparison result output by the high-precision comparator, and the signal DATA_VALID is used to indicate whether the output signal of the high-precision comparator is valid; the asynchronous timing control circuit receives an external oscillation start signal RST_OSC, and outputs an oscillation signal CLK_OSC to the high-precision comparator. At the same time, the asynchronous timing control circuit outputs control signals for 16 groups of drive switches on both sides respectively; the asynchronous timing control circuit includes a first adjustable delay module, a second adjustable delay module, an oscillation signal enabling unit, and a shift register;

[0006] The oscillation signal enabling unit includes a first NOR gate, a second NOR gate, a first OR gate, and a second OR gate; the first NOR gate is a two-input NOR gate, one input end of which is the first input end of the oscillation signal enabling unit, the other input end of which is connected to the output end of the second NOR gate, and the output end of the first NOR gate is the first output end of the oscillation signal enabling unit; the second NOR gate is a three-input NOR gate, a first input end of which is connected to the output end of the first NOR gate, a second input end of which is connected to the output end of the first OR gate, and a third input end of which is the second input end of the oscillation signal enabling unit, and the output end of the second NOR gate outputs an oscillation signal CLK_OSC; one input end of the first OR gate is connected to an external oscillation start signal RST_OSC, and the other input end is connected to a signal DATA_VALID; one input end of the second OR gate is connected to the output end of the second NOR gate, the other input end is connected to the external oscillation start signal RST_OSC, and the output end of the second OR gate is the second output end of the oscillation signal enabling unit;

[0007] The first and second adjustable delay modules have the same structure, including a programmable current source array, a variable capacitor array, a current source, a capacitor, a MOS transistor, and a comparator; the programmable current source array and the current source are connected in parallel, with one end of the parallel connection connected to a power supply and the other end connected to the positive input of the comparator, one end of the variable capacitor array, one end of the capacitor, and the drain of the MOS transistor; the other end of the variable capacitor array, the other end of the capacitor, and the source of the MOS transistor are grounded; the gate of the MOS transistor is the input of the adjustable delay module; the negative input of the comparator is connected to a reference voltage, and the output of the comparator is the output of the adjustable delay module; the output of the programmable current source array is controlled by a 3-bit trimming signal, and the value of the variable capacitor array is controlled by a 3-bit delay control signal; the output of the first adjustable delay module is connected to the first input of the oscillation signal enable unit, the input of the first adjustable delay module is connected to the first output of the oscillation signal enable unit, the output of the second adjustable delay module is connected to the second input of the oscillation signal enable unit, and the input of the second adjustable delay module is connected to the second output of the oscillation signal enable unit;

[0008] The shift register is composed of 16 stages of shift D flip-flops connected in series, 16 stages of data storage D flip-flops and a 16-bit lookup table; the clock signal terminals of all 16 stages of shift D flip-flops are connected to the oscillation signal CLK_OSC, the D input terminal of the first stage of shift D flip-flops is connected to a high level, and the D input terminals of the remaining shift D flip-flops are connected to the Q output terminals of the previous stage of shift D flip-flops; the D input terminals of all 16 stages of data storage D flip-flops are connected to the signal DOUT_CMP, and the clock signal input terminal of each stage of data storage D flip-flops is connected to the Q input terminal of the corresponding shift D flip-flop. Output end, the Q output end output signal of all data storage D flip-flops constitutes the control signal of the asynchronous timing control circuit; the address line input end of the 16-bit lookup table corresponds to the Q output end of the 16-stage shift D flip-flop in reverse order, that is, the Q output end of the 16-stage shift D flip-flop is connected to the address line of the 1st lookup table, and the Q output end of the 1st stage shift D flip-flop is connected to the address line of the 16-bit lookup table, and the 16-bit lookup table outputs a 3-bit delay control signal to control the variable capacitor array in the first adjustable delay module and the variable capacitor array in the second adjustable delay module respectively;

[0009] The method for implementing dynamic delay adaptive control in an asynchronous timing control circuit is as follows: when the comparator completes j comparisons, the shift D flip-flop generates a data latch signal W[j] driven by the oscillation signal CLK_OSC, W[j] is transmitted to the clock input of the corresponding data storage D flip-flop, and the signal DOUT_CMP is transmitted to the D input of the data storage D flip-flop, and the comparator output signal DOUT_CMP is stored using the data latch signal W; the input of the lookup table is connected to the data latch signal W[j] of each comparison, thereby outputting a 3-bit delay control signal for controlling the capacitor array of the dynamically adjustable delay module to obtain a dynamic delay time, which is then output to the oscillation signal enable unit to obtain an adaptive oscillation signal CLK_OSC.

[0010] The beneficial effects of the present invention are as follows: the present invention provides a dynamic delay adaptive asynchronous timing control circuit for high-precision SAR ADC, which has achieved significant breakthroughs in conversion accuracy and speed through innovative circuit architecture and control methods. The circuit adopts a unique two-stage dynamic delay adjustment mechanism, which realizes intelligent optimization of delay time based on real-time comparison number monitoring, thereby increasing the effective conversion rate under 16-bit accuracy by more than 25%, while maintaining ENOB (effective number of bits) of not less than 15 bits. The innovative current-charged capacitive delay unit is combined with PVT compensation technology, and the delay time stability is better than ±3% in the operating temperature range of -40°C to 125°C. Through the dynamic adjustment algorithm of the shift register and the lookup table working together, the system can automatically adapt to the setup time changes of 10ns to 50ns, saving more than 30% of invalid waiting time compared to the fixed delay solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 : is the overall principle diagram of the SAR ADC in the present invention;

[0012] Figure 2 A schematic diagram showing the connection principle of the dynamic delay adaptive asynchronous timing control circuit of the present invention;

[0013] Figure 3 A schematic diagram showing the connection principle of the dynamically adjustable delay circuit of the present invention;

[0014] Figure 4 A schematic diagram showing the connection principle of the shift register circuit of the present invention;

[0015] Figure 5 This is a schematic diagram showing the connection principle of the oscillation signal enabling unit of the present invention;

[0016] Figure 6 This is a timing diagram of the dynamic delay adaptive asynchronous timing control circuit of the present invention. DETAILED DESCRIPTION

[0017] The present invention will be further described below with reference to the accompanying drawings.

[0018] like Figure 1 Figure 1 shows a schematic diagram of a SAR ADC with the asynchronous SAR logic control proposed in the present invention. The asynchronous SAR logic is the dynamic delay adaptive asynchronous timing control circuit proposed in the present invention. The SAR ADC includes the dynamic delay adaptive asynchronous timing control circuit, a comparator, and a CDAC. The CDAC is a traditional differential binary capacitor array with 16 capacitors on one side, and the other side has an identical structure. The top plates of the 16 capacitors and one end of the common-mode switch are connected to the positive input of the high-precision comparator. One end of the common-mode switch is connected to the common-mode signal VCM. The bottom plates of the 16 capacitors are connected to one end of 16 corresponding groups of drive switches. The 16 groups of drive switches are three-input switch selectors, and their other ends are respectively connected to the differential reference voltages Vrefp and Vrefn and one end of 16 two-input selectors. To ensure differential switching signals, the inputs of the 16 groups of drive switches on the other side are respectively connected to the reference voltages Vrefn and Vrefp and one end of the 16 two-input selectors. The other ends of the 16 two-input selectors are respectively connected to the input signal VIN and the common-mode signal VCM. The high-precision comparator uses a combination of a preamplifier and a dynamic latch, which can improve the accuracy and speed of the comparator circuit. The positive input port of the high-precision comparator is connected to the first output port VOUTP of the CDAC, and the negative input port is connected to the second output port VOUTN of the CDAC. The first input port of the comparator is connected to the CLK_OSC port of the dynamic delay adaptive asynchronous timing control circuit to receive the oscillation clock generated by the dynamic delay adaptive asynchronous timing control circuit. The first output port of the comparator is connected to the DOUT_CMP port of the dynamic delay adaptive asynchronous timing control circuit to output the comparator result. The second output port of the comparator is connected to the DATA_VALID port of the dynamic delay adaptive asynchronous timing control circuit to indicate that the comparator output signal is valid.

[0019] The dynamic delay adaptive asynchronous timing control circuit proposed in the present invention includes three core functional modules:

[0020] 1. Dynamically adjustable delay module: the output of the first dynamically adjustable delay module is connected to the VIN1 port of the oscillation signal enable unit, the output of the second dynamically adjustable delay module is connected to the VIN2 port of the oscillation signal enable unit, and the 3-bit delay control bus COUNT is driven by the lookup table module of the shift register.

[0021] 2. The input end of the shift register module is connected to the comparator output signal DATA_CMP and the oscillation clock signal CLK_OSC of the oscillation signal enable unit. The 16-bit comparison count signal W is output to the lookup table module (n is the number of SAR ADC bits), and the 3-bit delay control bus COUNT is output.

[0022] 3. Oscillation signal enabling unit, wherein the clock starting module receives the oscillation starting signal RST_OSC, which is used to start the oscillation signal generating module, and the oscillation clock generating module outputs the oscillation clock signal CLK_OSC.

[0023] The dynamically adjustable delay module of the present invention uses a capacitor charging and discharging mechanism to achieve programmable delay. The technical solution is as follows:

[0024] The dynamically adjustable delay module includes a programmable current source array, which provides adjustable charge and discharge currents. Its main purpose is to perform the first factory calibration after the device leaves the factory to ensure the charging current accuracy. Its control end is connected to the 3-bit trim bus TRIM; a variable capacitor array, which is used to adjust the charge and discharge time, and its capacitance value is controlled by the 3-bit delay control bus COUNT signal; a comparator, which is used to detect whether the capacitor voltage has reached the flip threshold, and its output end is connected to the dynamic adjustable delay module output signal OUT; a reset switch, which is used to discharge the capacitor after the delay period ends, and its control end is connected to the dynamic adjustable delay module input signal IN.

[0025] Delay time T delay Determined by the following formula:

[0026]

[0027] Wherein, C is the equivalent capacitance of the variable capacitor array, VREF is the flip threshold voltage of the comparator, and I is the output current of the programmable current source.

[0028] The principle of dynamic delay control is as follows:

[0029] When the low level of the input trigger signal IN reaches the port of the dynamically adjustable delay module, the reset switch is disconnected and the capacitor begins to charge. During the charging process, the comparator circuit monitors the capacitor voltage in real time. When the voltage reaches VREF, it outputs the delayed signal. After the delay ends, IN changes from a low level to a high level, activating the reset switch and resetting the capacitor. The single dynamically adjustable delay module only ensures that the delay function is enabled when the input trigger signal IN is at a low level. To ensure that the oscillation clock has a symmetrical duty cycle, dual dynamically adjustable delay modules are used, so that the oscillation signal CLK_OSC output by the oscillation signal enable unit has the same delay time at high and low levels.

[0030] The shift register module of the present invention adopts a multi-stage cascade structure to realize the storage of comparison results, and its technical solution is as follows:

[0031] The shift register consists of 16 stages of serially connected shift D flip-flops and 16 stages of data storage D flip-flops. The data input D of each shift D flip-flop is connected to the output Q of the preceding shift D flip-flop (except for the data input D of the first flip-flop REG1n, which is connected to a high level). The clock input CLK of each shift D flip-flop is connected to the oscillation clock CLK_OSC. The data output Q of each shift D flip-flop is connected to the output D of the succeeding shift D flip-flop, a 16-bit lookup table address line W, and the clock CLK of the corresponding data storage D flip-flop. The clock input CLK of each stage of data storage D flip-flop is connected to the output Q of the corresponding shift D flip-flop. The data input D of each stage of data storage D flip-flop is connected to the comparator input signal DATA_CMP. The data output Q of each stage of data storage D flip-flop is connected to the control port of CDAC in the SAR ADC.

[0032] When the comparator completes j comparisons, the shift D flip-flop generates a data latch signal W[j] driven by the oscillation clock signal CLK_OSC, which is transmitted to the clock input port CLK of the corresponding data storage D flip-flop. The comparator output signal DOUT_CMP is transmitted to the input terminal D of the data storage D flip-flop, and the comparator output signal DOUT_CMP is stored using the data latch signal W. A lookup table module is used, whose input terminal is connected to the data latch signal W[j] of each comparison, and the output signal 3-bit delay control bus COUNT is used to control the capacitor array of the dynamically adjustable delay module.

[0033] The oscillation signal enabling unit of the present invention adopts a multivibrator structure composed of gate-level control and triggers, and includes an oscillation signal starting module responsible for enabling oscillation and determining the initial value; an oscillator generating module based on an RS latch and a dynamic delay module.

[0034] The oscillation signal start module receives the external RST_OSC start signal and outputs a global enable signal via OR gate logic, ensuring that RST_OSC triggers oscillation initiation. The oscillation signal generation module utilizes an innovative RS latch combined with a dynamically adjustable delay module to form a multivibrator with a variable oscillation period. The RS latch's set terminal is connected to the output of the first dynamic delay module, and its reset terminal is connected to the output of the second dynamic delay module, forming a closed oscillation loop. During operation, the RS latch's initial state is set when the RST_OSC signal is asserted. When the oscillator reset signal, RST_OSCS, is deasserted, the RS latch's reset and set terminals, R and S, are connected to the external dynamic delay module, repeatedly setting and resetting the RS latch and generating a square wave output at its output terminal, CLK_OSC.

[0035] The present invention provides a dynamic delay adaptive asynchronous timing control circuit for high-precision SAR ADC. Figure 2As shown in the figure, the shift register module receives the comparator output signal DOUT_CMP and generates a 16-bit latch signal W for storing the comparison result through 16 stages of serially connected shift D flip-flops REG116 to REG11. The latch signal W is connected to the lookup table as the 16-bit address line of the lookup table, which is used to generate the 3-bit delay control line COUNT that controls the dynamic delay adjustable delay module. The shift register and the second adjustable delay module are parameterized via dedicated buses and control signals, respectively. The oscillation signal enable unit outputs the CLK_OSC clock signal through a specific port.

[0036] The specific implementation of the dynamically adjustable delay module provided by the present invention is as follows Figure 3 As shown in FIG, the module adopts an architecture in which a programmable current source array and a binary weighted capacitor array work together to achieve precise delay control.

[0037] Specifically, the current source consists of an adjustable current source with a 3-bit binary switch and a fixed current source. The main purpose of the adjustable current source with a 3-bit binary switch is to perform a trimming after the chip leaves the factory to eliminate the current deviation caused by process deviation, which leads to inaccurate delay. After testing, it was found that after trimming with a 3-bit binary bus, the current accuracy is maintained within ±1%. The variable capacitor array consists of 3 unique hot code controlled MIM capacitors and a fixed MIM capacitor C charge Composition, the total capacitance adjustment range is C charge to 2.C charge Each capacitor unit controls its access state through a transmission gate switch, and the common upper plate of the array is connected to V CHARGE The comparator is implemented by combining a pre-amplifier with a low-power dynamic latch, and its positive input is connected to the V CHARGE Node, the negative input terminal is connected to the threshold voltage generation circuit output V REF The comparator output is connected to the OUT port of the dynamic adjustable delay module. The dynamic adjustable delay module input port IN is connected to the gate of the first NMOS transistor, and the drain of the first NMOS transistor is connected to V CHARGE Node, source connected to GND node.

[0038] The specific implementation of the shift register module provided by the present invention is as follows Figure 4As shown in the figure, this module uses 16 shift D flip-flops REG116-REG11, data D flip-flops REG216-REG21, and a lookup table to store comparison results and search the output delay control bus based on the number of comparisons. The 16-stage shift D flip-flops form the basic shift unit. The data input D of each shift flip-flop REG1n is connected to the output Q of the previous stage (except for the 16th shift D flip-flop REG116, where the data input D is connected high), the clock input CLK of the corresponding data D flip-flop REG1n, and the address line of the lookup table. The clock input CLK is connected to the oscillating clock signal CLK_OSC, and the output Q is connected to the data input D of the next shift D flip-flop. The data input D of each data D flip-flop REG2n is connected to the comparator output signal DATA_CMP, and the data output Q is connected to the capacitor array switch of the CDAC of the SAR ADC. The address lines of the lookup table module are connected to the 16-bit data output bus W of 16 shift D flip-flops. The data lines output the 3-bit delay control code COUNT to the dynamically adjustable delay module. Specifically, the lookup table is implemented using the hardware description language Verilog code. The specific judgment rules are as follows:

[0039] When 0≤Sum(W[16:1])≤3, COUNT[2:0]=3'b000

[0040] When 4≤Sum(W[16:1])≤7, COUNT[2:0]=3'b001

[0041] When 8≤Sum(W[16:1])≤11, COUNT[2:0]=3'b011

[0042] When 12≤Sum(W[16:1])≤16, COUNT[2:0]=3'b111

[0043] Among them, Sum() is a summation operation.

[0044] The specific implementation of the oscillation signal enabling unit provided by the present invention is as follows Figure 5 As shown, it consists of an oscillation signal start module and an oscillation signal generation module. Its first input is connected to the asynchronous clock start signal RST_OSC, and its second input is connected to the comparator output valid signal DATA_VALID. The clock start control module's oscillation signal start module is composed of two OR gates OR1 and OR2, and the oscillation signal generation module is an RS latch composed of cross-coupled NOR gates NOR1 and NOR2.

[0045] Specifically, the oscillation signal startup module is connected as follows: the first and second input terminals are connected to the input port of the first dual-input OR gate OR1, and the first input terminal and the output port of the second NOR gate OR2 are connected to the input port of the second dual-input OR gate OR2. The oscillation signal generation module is connected as follows: the third input terminal is connected to VIN2 and the reset terminal R of the RS latch, the fourth input terminal is connected to VIN1 and the set terminal S of the RS latch, the first output terminal is connected to RST2 and the Q-terminal of the RS latch, and the second output terminal is connected to CLK_OSC and the Q-terminal of the RS latch. The set terminal S is connected to the output of the first dynamically adjustable delay module, and the reset terminal R is connected to the output of the second dynamically adjustable delay module.

[0046] The specific working process of the dynamic delay adaptive asynchronous timing control circuit for high-precision SAR ADC provided by the present invention is as follows:

[0047] Step 1: Initial state: When there is no external sampling trigger clock, RST_OSC is high, the entire oscillation signal enable unit is in the initial state, CLKS_OSC is low, RST1 is high, RST2 is high, the set terminal S is low, and the reset terminal is low. When the external sampling trigger clock arrives, RST_OSC changes from high to low, contacting the latch state of the RS latch, and entering step 2;

[0048] Step 2: Oscillation state, after RST_OSC is pulled low, CLK_OSC is equal to RST1. First, RST1 changes from high level to low level and is transmitted to the first dynamic delay adjustable delay module input port IN. After t1 / 2 time and reverse, the high level is transmitted to the RS latch set terminal S, RST1 changes from low level to high level, RST2 changes from high level to low level, RST2 is transmitted to the second dynamic delay adjustable delay module input port IN, after t1 / 2 time and reverse, the high level is transmitted to the RS latch reset terminal R, RST1 changes from high level to low level, RST2 changes from low level to high level, and repeats in sequence to realize the repeated setting and resetting of the RS latch, so that the RS latch output terminal CLK_OSC outputs a square wave. It is worth noting that as the number of comparisons increases, the lookup table in the shift register module is used to realize the dynamic adjustment of the delay in the dynamic delay adjustable delay module, thereby changing the period of CLK_OSC, such as Figure 6 When the conversion is complete, proceed to step 1.

Claims

1. A dynamic delay adaptive asynchronous timing control circuit for a SAR ADC. The SAR ADC includes a high-precision comparator and a CDAC, wherein the CDAC is a differential CDAC with two sides. Each side includes 16 capacitors and 16 groups of drive switches. One end of the 16 capacitors is connected to a common-mode signal VCM through a common-mode switch, and the other ends of the 16 capacitors are respectively connected to one end of the 16 groups of drive switches. The other ends of the 16 groups of drive switches are connected to a three-input switch selector. The three input signals are an input signal, a differential reference voltage Vrefp, and a differential reference voltage Vrefn. The input signal is respectively connected to an input signal VIN and a common-mode signal VCM through two input selectors. The ends of the 16 capacitors on both sides connected to the common-mode switches are respectively connected to two input ends of the high-precision comparator. The invention is characterized in that: The high-precision comparator outputs a signal DOUT_CMP and a signal DATA_VALID to the asynchronous timing control circuit, respectively, where the signal DOUT_CMP is the comparison result output by the high-precision comparator, and the signal DATA_VALID is used to indicate whether the output signal of the high-precision comparator is valid; the asynchronous timing control circuit receives an external oscillation start signal RST_OSC, and outputs an oscillation signal CLK_OSC to the high-precision comparator. At the same time, the asynchronous timing control circuit outputs control signals for 16 groups of drive switches on both sides respectively; the asynchronous timing control circuit includes a first adjustable delay module, a second adjustable delay module, an oscillation signal enable unit, and a shift register; The oscillation signal enabling unit includes a first NOR gate, a second NOR gate, a first OR gate, and a second OR gate; the first NOR gate is a two-input NOR gate, one input end of which is the first input end of the oscillation signal enabling unit, the other input end of which is connected to the output end of the second NOR gate, and the output end of the first NOR gate is the first output end of the oscillation signal enabling unit; the second NOR gate is a three-input NOR gate, a first input end of which is connected to the output end of the first NOR gate, a second input end of which is connected to the output end of the first OR gate, and a third input end of which is the second input end of the oscillation signal enabling unit, and the output end of the second NOR gate outputs an oscillation signal CLK_OSC; one input end of the first OR gate is connected to an external oscillation start signal RST_OSC, and the other input end is connected to a signal DATA_VALID; one input end of the second OR gate is connected to the output end of the second NOR gate, the other input end is connected to the external oscillation start signal RST_OSC, and the output end of the second OR gate is the second output end of the oscillation signal enabling unit; The first and second adjustable delay modules have the same structure, including a programmable current source array, a variable capacitor array, a current source, a capacitor, a MOS transistor, and a comparator; the programmable current source array and the current source are connected in parallel, with one end of the parallel connection connected to a power supply and the other end connected to the positive input of the comparator, one end of the variable capacitor array, one end of the capacitor, and the drain of the MOS transistor; the other end of the variable capacitor array, the other end of the capacitor, and the source of the MOS transistor are grounded; the gate of the MOS transistor is the input of the adjustable delay module; the negative input of the comparator is connected to a reference voltage, and the output of the comparator is the output of the adjustable delay module; the output of the programmable current source array is controlled by a 3-bit trimming signal, and the value of the variable capacitor array is controlled by a 3-bit delay control signal; the output of the first adjustable delay module is connected to the first input of the oscillation signal enable unit, the input of the first adjustable delay module is connected to the first output of the oscillation signal enable unit, the output of the second adjustable delay module is connected to the second input of the oscillation signal enable unit, and the input of the second adjustable delay module is connected to the second output of the oscillation signal enable unit; The shift register is composed of 16 stages of shift D flip-flops connected in series, 16 stages of data storage D flip-flops and a 16-bit lookup table; the clock signal terminals of all 16 stages of shift D flip-flops are connected to the oscillation signal CLK_OSC, the D input terminal of the first stage of shift D flip-flops is connected to a high level, and the D input terminals of the remaining shift D flip-flops are connected to the Q output terminals of the previous stage of shift D flip-flops; the D input terminals of all 16 stages of data storage D flip-flops are connected to the signal DOUT_CMP, and the clock signal input terminal of each stage of data storage D flip-flops is connected to the Q input terminal of the corresponding shift D flip-flop. Output end, the Q output end output signal of all data storage D flip-flops constitutes the control signal of the asynchronous timing control circuit; the address line input end of the 16-bit lookup table corresponds to the Q output end of the 16-stage shift D flip-flop in reverse order, that is, the Q output end of the 16-stage shift D flip-flop is connected to the address line of the 1st lookup table, and the Q output end of the 1st stage shift D flip-flop is connected to the address line of the 16-bit lookup table, and the 16-bit lookup table outputs a 3-bit delay control signal to control the variable capacitor array in the first adjustable delay module and the variable capacitor array in the second adjustable delay module respectively; The method for implementing dynamic delay adaptive control in an asynchronous timing control circuit is as follows: when the comparator completes j comparisons, the shift D flip-flop generates a data latch signal W[j] driven by the oscillation signal CLK_OSC, W[j] is transmitted to the clock input of the corresponding data storage D flip-flop, and the signal DOUT_CMP is transmitted to the D input of the data storage D flip-flop, and the comparator output signal DOUT_CMP is stored using the data latch signal W; the input of the lookup table is connected to the data latch signal W[j] of each comparison, thereby outputting a 3-bit delay control signal for controlling the capacitor array of the dynamically adjustable delay module to obtain a dynamic delay time, which is then output to the oscillation signal enable unit to obtain an adaptive oscillation signal CLK_OSC.

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