Method for non-self-aligned high-voltage CMOS device

Abstract

The invention discloses a process method of a non-self-aligned high-voltage CMOS (complementary metal oxide semiconductor) device. The method comprises the following steps: providing a semiconductor substrate and forming a shallow trench isolation structure comprising a chemical mechanical polishing stop layer; patterning the stop layer in a preset high-voltage device area to form a hard mask with a trapezoidal cross section (a preset angle theta formed by a bevel edge and the substrate is smaller than 90 degrees); before a well region is formed, carrying out inclined lightly doped drain electrode ion implantation by using the trapezoidal hard mask; and then the hard mask is removed, and a well region, a gate structure covering a channel region, a source electrode heavily doped region and a drain electrode heavily doped region are sequentially formed. The hard mask with the inclined side wall is combined with inclined injection, doping distribution of the lightly-doped drain electrode can be effectively optimized, the overlapping area of the grid electrode and the drain electrode is enlarged, and meanwhile injection of the lightly-doped drain electrode can increase the follow-up thermal process and improve the hot carrier injection performance in advance. The method improves the voltage resistance and reliability of the device, reduces the electric leakage, is good in process compatibility, and does not affect the shape of the grid electrode.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, in particular to a method for producing a non-self-aligned high-voltage CMOS device. Background Art

[0002] The semiconductor integrated circuit industry continues to pursue higher integration density and performance, driving the evolution of manufacturing process nodes towards smaller sizes. Advanced process technologies are reducing the size of the various structural features that make up transistors. One notable trend is the continuous reduction in gate structure thickness, particularly the gate conductive material layer (such as the commonly used polysilicon layer).

[0003] For high voltage CMOS devices that need to withstand higher operating voltages (e.g., devices operating at 5V), reducing gate thickness presents a series of challenges. Figure 1 To better understand the relevant structures, let's take a typical high-voltage NMOS device as an example. Its cross-section typically includes: a semiconductor substrate 100; shallow trench isolation 101 for isolating the device's active area; a high-voltage P-type well 102 accommodating the channel; a high-voltage N-type lightly doped drain region 103 for electric field mitigation; a high-voltage gate insulating dielectric layer 104 beneath the gate; and a gate conductive material layer 105. Furthermore, it includes a first spacer dielectric layer 107 and a second spacer dielectric layer 108 on the gate sidewalls, as well as N-type heavily doped source / drain regions 109 for forming low-resistance contacts. The lightly doped drain (LDD) structure (such as 103) is crucial for this type of device. It plays a key role in mitigating the electric field distribution between the channel and the heavily doped source / drain regions, improving the device's withstand voltage (breakdown voltage, BV), suppressing hot carrier injection (HCI), and reducing leakage current. Typically, such high-voltage devices are integrated on the same chip with standard-voltage CMOS devices, which also have similar structures, such as their own P-type well 202, gate insulating dielectric layer 204, and LDD region 206 that may contain different doping structures (such as ultra-shallow junction N-type LDD combined with P-type halo / pocket injection, Halo / Pocket).

[0004] In a conventional self-aligned LDD process, the LDD ion implantation step (forming a region such as 103) is typically performed after the gate structure (including 104 and 105) is formed and before the sidewalls (such as 107) are formed, cleverly utilizing the formed gate as part of the implantation mask. However, as the gate material layer (105) becomes thinner and thinner in advanced processes, its ability to block high-energy ion implantation decreases. This limits the maximum LDD implantation energy that can be applied in the self-aligned process, making it difficult to form an LDD region 103 with an ideal doping concentration gradient and sufficient lateral extension (i.e., the overlap width between the gate and the source / drain region, such as the dimension marked as y in the accompanying drawings) under the gate. This suboptimal LDD structure directly restricts the improvement space of the device breakdown voltage and may lead to unnecessary leakage increase. Research and practice have shown that moderately increasing the overlap width (y dimension) between the LDD region 103 and the gate 105 is beneficial to improving the breakdown voltage and reducing leakage.

[0005] In order to break through the energy limitations of the self-aligned process, the industry has turned to the development of non-self-aligned LDD process solutions. The core idea of ​​this solution is to adjust the LDD injection step from after the gate is formed to a certain process stage before the gate is formed. Although this timing adjustment provides a larger process window for LDD injection, such as allowing the use of higher injection energy or a more sophisticated injection strategy, the existing non-self-aligned technology still has room for improvement in terms of comprehensively optimizing device performance (especially improving HCI characteristics). For example, ion implantation at an inclined angle is a common technical means to control the LDD doping profile and increase the effective overlap area. However, the physical limitations of ion implantation equipment usually impose an upper limit on the maximum available inclined injection angle (for example, usually not exceeding 45 degrees). This angle limitation restricts the effect of relying solely on inclined injection to optimize the LDD doping distribution gradient and significantly expand the width of the overlapping area.

[0006] Therefore, in the context of current advanced process technology, a more effective non-self-aligned high-voltage CMOS device manufacturing method is urgently needed. The method needs to be able to further optimize the structure and doping characteristics of the LDD region (103) without sacrificing process compatibility (for example, preferably using the thin film layer in the existing process flow as a mask) and without affecting the precise formation of subsequent key structures (such as the gate). The goal is to effectively increase the effective distance between the gate edge and the final heavily doped drain region (109) (that is, equivalently increase the overlap region size y) and improve the doping gradient of the LDD region. Through these improvements, it is expected that the device breakdown voltage can be significantly improved, the leakage current can be greatly reduced, and the HCI reliability of the device can be improved, thereby meeting the needs of modern high-performance and high-reliability integrated circuits. Summary of the Invention

[0007] The present application aims to solve the problems existing in the prior art. With the continuous advancement of semiconductor process technology, the gate material layer (such as polysilicon) tends to be thinner, which limits the maximum available energy of lightly doped drain ion implantation when using traditional self-aligned processes to manufacture high-voltage CMOS devices. As a result, it is difficult to form a lightly doped drain structure with sufficient overlap width (y dimension) and optimized doping gradient, which poses challenges to the breakdown voltage improvement and leakage control of the device. Although the non-self-aligned lightly doped drain process provides a certain degree of flexibility, the existing non-self-aligned method still has limitations in utilizing a limited ion implantation tilt angle (e.g., a maximum of 45 degrees) to fully optimize the lightly doped drain doping distribution, effectively increase the overlap area, and improve the hot carrier injection performance.

[0008] To achieve the above-mentioned and other related purposes, the present invention provides a method for a non-self-aligned high-voltage CMOS device, comprising:

[0009] Step 1: providing a semiconductor substrate; forming a shallow trench isolation structure on the semiconductor substrate, wherein the shallow trench isolation structure formation process includes depositing a chemical mechanical polishing stop layer;

[0010] Step 2: patterning the chemical mechanical polishing stop layer to form a hard mask above the predetermined high-voltage device active region of the semiconductor substrate, wherein the hard mask has a trapezoidal cross-sectional structure, and the hypotenuse of the trapezoidal cross-sectional structure forms a predetermined angle θ with the surface of the semiconductor substrate;

[0011] Step 3: Before forming the well region of the high-voltage device, perform tilted ion implantation into the semiconductor substrate using the hard mask as an implantation mask to form a lightly doped drain region of the high-voltage device;

[0012] Step 4: removing the hard mask;

[0013] Step 5: After forming the lightly doped drain region, forming a well region of the high-voltage device in the semiconductor substrate;

[0014] Step 6: forming a gate structure on the semiconductor substrate, wherein the gate structure covers the channel region between the lightly doped drain regions; and

[0015] Step seven: forming heavily doped source and drain regions of the high-voltage device.

[0016] Preferably, in step 1, the chemical mechanical polishing stop layer is a silicon nitride layer.

[0017] Preferably, in step 2, the predetermined angle θ is greater than or equal to 30° and less than 90°.

[0018] Preferably, in step three, the injection angle of the inclined ion injection is 15° to 45°.

[0019] Preferably, in step 1, before depositing the chemical mechanical polishing stop layer, the method further includes forming a pre-oxidation layer on the semiconductor substrate.

[0020] Preferably, after forming the well region of the high-voltage device in step five and before forming the gate structure in step six, the method further includes removing the pre-oxide layer.

[0021] Preferably, in step 2, patterning the chemical mechanical polishing stop layer includes: forming a photoresist pattern on the chemical mechanical polishing stop layer; and etching the chemical mechanical polishing stop layer using the photoresist pattern as a mask to form the hard mask.

[0022] Preferably, in step three, before performing the tilted ion implantation, the photoresist pattern is removed; or, in step three, the tilted ion implantation is performed using the hard mask and the photoresist pattern together as an implantation mask, and the photoresist pattern is removed after the implantation.

[0023] Preferably, in step five, the method further comprises selectively implanting at least one additional well region in a region of the semiconductor substrate used for forming other types of CMOS devices.

[0024] Preferably, the high-voltage CMOS device is a high-voltage NMOS device. In step three, the lightly doped drain region is N-type doped; in step five, the well region is a high-voltage P-type well; and in step seven, the source and drain heavily doped regions are N-type heavily doped.

[0025] Preferably, the high-voltage CMOS device is a high-voltage NMOS device, the well region is a high-voltage P-type well, and the at least one additional well region includes a P-type well for forming a low-voltage or other type of CMOS device.

[0026] Preferably, the high-voltage CMOS device is a high-voltage PMOS device. In step three, the lightly doped drain region is P-type doped; in step five, the well region is a high-voltage N-type well; and in step seven, the source and drain heavily doped regions are P-type heavily doped.

[0027] As described above, the method of the non-self-aligned high-voltage CMOS device of the present invention has the following beneficial effects:

[0028] LDD doping gradient optimization and increased overlap area y: The combination of the unique beveled edge morphology of the trapezoidal mask and the tilted injection technology can more finely control the lateral doping profile of the LDD region, forming a flatter PN junction gradient and effectively increasing the lateral distance y between the gate edge and the final heavily doped drain.

[0029] Improved breakdown voltage (BV) and leakage suppression: A more optimized LDD structure and an expanded effective overlap area y help significantly reduce the maximum electric field strength in the area near the drain during device operation, thereby directly improving the device's ability to withstand reverse bias, that is, increasing the breakdown voltage.

[0030] Improved HCI performance: By placing the LDD implantation step in the front-end, it can benefit from subsequent thermal treatment steps, including well activation. This helps to more fully repair the lattice damage that may be introduced by ion implantation and optimizes the activation state and final distribution of dopants. All of these help enhance the device's ability to resist hot carrier effects, thereby improving its long-term reliability and stability.

[0031] Excellent process compatibility and lossless gate morphology: This method utilizes the CMP stop layer (silicon nitride) commonly found in STI process modules as a functional mask, avoiding the introduction of additional material layers or complex dedicated process steps, ensuring good compatibility with existing mature CMOS technology platforms. More importantly, because the temporary mask used for LDD implantation is completely removed before the gate structure is constructed, the subsequent critical gate etch process and its final morphology are not disturbed or affected by any previous steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram showing that the thickness of the gate material in the prior art limits the maximum energy of the self-aligned LDD injection in high-voltage CMOS (such as 5VCMOS), thereby limiting the width of the overlap region;

[0033] Figure 2 Shown is a schematic diagram of the process flow of the present invention;

[0034] Figure 3 Shown is a schematic diagram of forming a shallow trench isolation structure according to the present invention;

[0035] Figure 4 Schematic diagram showing the patterning process of the silicon nitride layer used as a CMP stop layer according to the present invention;

[0036] Figure 5 Shown is a schematic diagram of a lightly doped drain (LDD) region required for forming a high voltage device according to the present invention;

[0037] Figure 6 Shown is a schematic diagram of forming a well region according to the present invention;

[0038] Figure 7 Shown is a schematic diagram of depositing a gate conductive material layer according to the present invention;

[0039] Figure 8 It is a schematic diagram showing a gate structure having a specific width and length according to the present invention;

[0040] Figure 9 Shown is a schematic diagram of performing specific implantation for other CMOS devices (such as low-voltage logic devices) coexisting on the chip according to the present invention;

[0041] Figure 10 Schematic diagram showing the step-by-step formation of the first sidewall and the second sidewall according to the present invention;

[0042] Figure 11 Shown is a schematic diagram of forming the source and drain heavily doped regions according to the present invention;

[0043] Figure 12 A schematic diagram showing an increase in the overlap dimension y value of the device channel surface of the present invention compared to the conventional method;

[0044] Figure 13 It is a schematic diagram showing that when θ is 45°, BV increases by about 1V and leakage current decreases by about 1 order of magnitude according to the present invention. DETAILED DESCRIPTION

[0045] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] See also Figure 2 This application aims to provide an optimized non-self-aligned high-voltage CMOS device process method, the core purpose of which is to effectively increase the device's breakdown voltage, reduce leakage current, and improve its hot carrier injection (HCI) characteristics. The process flow mainly includes the following steps:

[0047] Step 1: Provide a semiconductor substrate 100. Shallow trench isolation (STI) structures will be formed on the substrate. In a standard STI process, a stop layer will be deposited for the subsequent chemical mechanical polishing step.

[0048] In some embodiments, the chemical mechanical polishing stop layer in step 1 is preferably a silicon nitride (SiN) layer 112. Using silicon nitride as a CMP stop layer is a mature and widely used STI process option, which has excellent etch selectivity and reliable stopping performance, helping to simplify process control.

[0049] In some embodiments, to further optimize the process, a pre-oxide layer 111 may be pre-formed on the semiconductor substrate 100 before depositing the silicon nitride stop layer 112 in step 1. This pre-oxide layer acts as a stress buffer, improves adhesion of the silicon nitride layer, and protects the substrate surface from damage during certain subsequent steps. The specific process for forming the shallow trench isolation structure can generally follow the following sequence: the pre-oxide layer 111 and the silicon nitride layer 112 are sequentially grown or deposited on the semiconductor substrate 100. Next, using photolithography and etching techniques, a trench is defined and etched through the silicon nitride layer 112, the pre-oxide layer 111, and ultimately the semiconductor substrate 100. The trench is then filled with an isolation dielectric (e.g., silicon oxide), forming a portion 101-1 embedded in the substrate and a portion covering the substrate surface. A CMP process is then performed, using the silicon nitride layer 112 as the polishing endpoint, to remove excess isolation dielectric above the active area, thereby obtaining a planarized STI structure. This structure isolates the device areas (such as the high voltage CMOS area HV-CMOS and other CMOS areas) from each other. The STI oxide portion remaining on the surface of the active area after grinding is marked as 101-2, forming Figure 3 The structure shown.

[0050] Step 2: Patterning the silicon nitride layer as a CMP stop layer. The key is to shape the silicon nitride layer 112 into a hard mask with a specific geometric shape above the predetermined high-voltage device active area. The innovation of this hard mask is that its cross section is trapezoidal, and the hypotenuse of the trapezoidal cross section forms a preset tilt angle θ with the surface of the semiconductor substrate 100, forming a hard mask with a specific geometric shape. Figure 4 The structure shown.

[0051] In some embodiments, the preset tilt angle θ in step 2 is set to be greater than or equal to 30° and less than 90°. The selection of angle θ is one of the core elements for achieving the technical effects of the present application. When θ is less than 90°, the mask sidewall is in an inclined state, which is significantly different from the vertical sidewall pursued in traditional processes. It is this inclined sidewall that can produce special technical effects in the subsequent ion implantation step. The angle range (30° to <90°) provides the possibility of adjusting the process window to optimize device characteristics.

[0052] In some embodiments, the specific operation of forming the trapezoidal hard mask in step 2 includes: first, using standard photolithography technology, a clearly defined photoresist pattern 501 is formed above the silicon nitride layer 112 in the target high-voltage device area. Subsequently, using this photoresist pattern 501 as a mask, a dry etching technology with precise anisotropy control capability (such as reactive ion etching RIE) is used to etch the silicon nitride layer 112 below. By finely controlling parameters such as the gas type and flow rate, chamber pressure, and bias power during the etching process, the degree of anisotropy of the etching rate can be effectively controlled, thereby shaping a trapezoidal sidewall with a predetermined tilt angle θ. This step directly utilizes the silicon nitride layer that already exists in the STI process as a hard mask for LDD injection, without the need to introduce additional complex mask materials or increase process steps, significantly improving the compatibility and economy of the process flow.

[0053] Step 3: Before performing the ion implantation for forming the high voltage device well region, the trapezoidal hard mask 112 formed in step 2 is used as the main implantation mask to perform an ion implantation operation at an inclined angle on the semiconductor substrate 100, in order to form the lightly doped drain (LDD) region 103 required for the high voltage device, forming the following: Figure 5 This timing adjustment means that the LDD implant is integrated into the STI process module, occurring before the traditional well formation step.

[0054] In some embodiments, the tilted ion implantation in step three has an implantation angle set between 15° and 45°. The use of tilted implantation itself helps to form a wider LDD doping distribution under the future gate structure, thereby increasing the effective overlap width y between the LDD and the gate edge, and improving the doping concentration gradient. The maximum tilt capability of an ion implanter is usually limited (for example, a maximum of 45 degrees). However, the advantage of this method lies in the synergistic effect of the trapezoidal hard mask (with a tilt angle θ<90°) and the tilted implantation: even if the actual tilt angle of the implanter does not reach the limit value (such as only 15° or 30°), the slope shape of the mask edge can effectively guide the incident ions, so that its lateral doping range is more significantly expanded. This is equivalent to increasing the actual implantation effect angle, further optimizing the doping distribution gradient of the non-self-aligned LDD, and promoting the increase in the overlapping area y size of the device.

[0055] In some embodiments, step three can be performed by first removing the photoresist pattern 501 before performing the tilted ion implantation; or, retaining the photoresist pattern 501 and using it together with the silicon nitride layer 112 as a combined implantation mask to perform the tilted implantation, and then removing the photoresist 501 after the implantation is completed. The specific choice depends on the thickness of the photoresist itself, its blocking efficiency for the implanted ions, and the convenience of the overall process integration. If the photoresist is thick enough or the implantation energy is relatively low, retaining the photoresist can provide additional masking. Otherwise, it may be necessary to remove the photoresist and rely on the excellent blocking properties and thermal stability of the silicon nitride hard mask 112 itself to complete the implantation.

[0056] In some embodiments, if the goal is to manufacture a high-voltage NMOS device, the lightly doped drain region 103 formed in step three should be N-type doped, such as by injecting phosphorus (P) or arsenic (As) ions. Correspondingly, in other embodiments, if a high-voltage PMOS device is manufactured, the LDD region 103 should be P-type doped, such as by injecting boron (B) or boron difluoride (BF2) ions. An important benefit of advancing the LDD injection step to before the well injection is that the LDD region is able to undergo more subsequent thermal treatment processes (such as activation annealing after the well injection). A more adequate thermal budget helps the activation and diffusion of dopants, making the doping gradient of the LDD region smoother, and can also more effectively repair the lattice damage caused by ion injection. This ultimately helps to improve the HCI performance of the device and improve its long-term reliability.

[0057] Step 4: After the LDD implantation is complete, the trapezoidal silicon nitride hard mask 112, which served as the implantation mask, needs to be removed. Typically, this removal step is accomplished by selective wet etching, for example using a hot phosphoric acid (H3PO4) solution. Hot phosphoric acid has a high etching selectivity for silicon nitride and minimally erodes silicon oxide (such as the pre-oxide layer 111 and the STI filler 101) and the silicon substrate 100. After removing the hard mask, the active area surface of the semiconductor substrate 100 is ready for the subsequent well region formation step.

[0058] Step 5: Based on the previously formed lightly doped drain region 103, a well region required for a high voltage device is formed in the semiconductor substrate 100 by ion implantation, forming a well region as shown in FIG. Figure 6 This step is located after the LDD implantation in terms of timing, which is another feature that distinguishes this process from traditional processes.

[0059] Depending on the device type, in some embodiments, for a high-voltage NMOS device, the well region formed in step 5 is a high-voltage P-type well 102. Correspondingly, in other embodiments, for a high-voltage PMOS device, the well region formed is a high-voltage N-type well.

[0060] In addition, to be compatible with complex CMOS platforms, in some embodiments, step five can also selectively implant one or more additional well regions 202 in other areas of the semiconductor substrate 100 (i.e., non-high-voltage device areas). Additional photolithography masks and implantation steps can be used within or after the process window for forming the high-voltage P-type well 102 to form the P-type well 202 or N-type well required for low-voltage CMOS or other types of devices. This demonstrates that the high-voltage device LDD improvement solution proposed in this application has good process integration flexibility and can be seamlessly integrated into complex CMOS technology platforms that require the simultaneous manufacture of multiple different types of devices.

[0061] The well implantation process itself typically includes: after removing the LDD hard mask 112, using photolithography technology to precisely define the range of the well region to be implanted, then performing ion implantation, and subsequently activating and diffusing the implanted dopants through high-temperature annealing, ultimately forming a well region with a target doping concentration profile and junction depth.

[0062] Step 6: constructing a gate structure on the semiconductor substrate 100. The gate structure will accurately cover the area between the previously formed LDD regions 103, that is, the channel region of the device.

[0063] In some embodiments, if a pre-oxide layer 111 is introduced in step one, it is usually necessary to remove the pre-oxide layer 111 after all well regions are formed (step five) and before the gate dielectric is grown (step six). For example, a diluted hydrofluoric acid (DHF) solution can be used for cleaning. The purpose of removing this native or deposited thin oxide layer is to ensure that the subsequently grown gate dielectric can form a high-quality, low-defect interface with the silicon substrate. It should be noted that in the process of removing the pre-oxide layer 111, the portion 101-2 of the STI structure that is higher than the surface of the active area may also suffer a certain degree of thickness loss.

[0064] The formation of gate structure is one of the core links of CMOS manufacturing. Its general process includes: first, growing or depositing a gate dielectric layer on the surface of the semiconductor substrate according to the device requirements. For high-voltage devices, a relatively thick high-voltage gate dielectric 104 is formed; for low-voltage devices in other areas, a correspondingly thinner gate dielectric 204 is formed. Subsequently, a gate conductive material layer 105 is uniformly deposited on the entire wafer surface, usually polysilicon. In advanced processes, metal gate material stacking may also be used to form a gate structure. Figure 7 After the material deposition is completed, the gate strip pattern is defined on the gate material layer using photolithography technology, and then the gate material 105 and the underlying gate dielectric layer 104, 204 that are not protected by the photoresist are accurately removed by dry etching, ultimately forming a gate structure with a specific width and length, as shown in FIG. Figure 8The structure shown. During the gate etch process, the top of the STI oxide 101-2 typically also experiences some etching loss. Crucially, because the present method places the trapezoidal hard mask used to form the LDD and its associated implantation steps before the gate is constructed, and the mask is completely removed before the gate is formed, the fabrication process of the high-voltage CMOS region gate and its final physical morphology (including critical dimension (CD) control and sidewall profile) are not affected by the previous LDD formation step.

[0065] Step 7: Complete the formation of the source and drain heavily doped regions of the high voltage device.

[0066] Depending on the device type, in some embodiments, for high-voltage NMOS devices, the source and drain heavily doped regions 109 formed in step seven are heavily N-type doped. In other embodiments, for high-voltage PMOS devices, P-type heavy doping is performed. The formation of the source and drain heavily doped regions generally follows the standard back-end process of CMOS technology. After the gate 105 is patterned, it may be necessary to first perform specific implantations for other CMOS devices coexisting on the chip (such as low-voltage logic devices), such as LDD implantations and / or halo / pocket implantations for suppressing short channel effects (for example, a first sidewall 107 may be formed first, and then the implantation region 206 may be defined by a photolithography mask 502 to form a structure such as Figure 9 The sidewall structure usually includes one or more layers of dielectric material (such as silicon nitride, silicon oxide or a combination thereof) which are formed by conformal deposition on the entire wafer surface and then anisotropic dry etching to leave a dielectric strip of predetermined width on the gate sidewall (the first sidewall 107 and the second sidewall 108 may be formed in steps to form a dielectric strip as shown in FIG. Figure 10 The last step is to use the gate 105 and the complete sidewall structure 107, 108 as a self-aligned mask to perform high-dose ion implantation to form low-resistance source and drain heavily doped regions 109, forming Figure 11 The implantation is usually followed by a high-temperature annealing step to activate the dopants and repair the damage. During the sidewall formation and heavy doping implantation process, the STI structure 101-2 may continue to experience a certain degree of etching loss.

[0067] In summary, by implementing the process described in detail above, particularly by using a CMP stop layer (silicon nitride) with a trapezoidal cross-section as a hard mask for non-self-aligned tilted LDD implantation and placing this implantation step before well formation, significant technical advantages can be achieved:

[0068] LDD doping gradient optimization and overlap area y increase: The combination of the unique bevel shape of the trapezoidal mask and the tilted injection technology can more finely control the lateral doping profile of the LDD region, forming a smoother PN junction gradient and effectively increasing the lateral distance y between the gate edge and the final heavily doped drain. Figure 12 ,As shown by the simulation results, when the trapezoidal mask angle θ is 45°, the overlap dimension y value of the ,device channel surface can be increased by approximately 100% compared ,with the traditional method.

[0069] Improved breakdown voltage (BV) and leakage suppression: A more optimized LDD structure and an expanded effective overlap area y help significantly reduce the maximum electric field strength near the drain during device operation, thereby directly improving the device's ability to withstand reverse bias, that is, increasing the breakdown voltage. Figure 13 Simulation data shows that when θ is 45°, BV can be improved by approximately 1V. Furthermore, the improved electric field distribution helps suppress various leakage mechanisms, particularly gate-induced drain leakage (GIDL), significantly reducing the overall static leakage current of the device. Simulations show that leakage levels can be reduced by approximately one order of magnitude.

[0070] Improved HCI performance: By placing the LDD implantation step in the front-end, it can benefit from subsequent thermal treatment steps, including well activation. This helps to more fully repair the lattice damage that may be introduced by ion implantation and optimizes the activation state and final distribution of dopants. All of these help enhance the device's ability to resist hot carrier effects, thereby improving its long-term reliability and stability.

[0071] Excellent process compatibility and lossless gate morphology: This method utilizes the CMP stop layer (silicon nitride) commonly found in STI process modules as a functional mask, avoiding the introduction of additional material layers or complex dedicated process steps, ensuring good compatibility with existing mature CMOS technology platforms. More importantly, because the temporary mask used for LDD implantation is completely removed before the gate structure is constructed, the subsequent critical gate etch process and its final morphology are not disturbed or affected by any previous steps.

[0072] Therefore, the present application provides an innovative, effective and easy-to-integrate and manufacture non-self-aligned high-voltage CMOS device process strategy, which can effectively and significantly improve the key electrical performance parameters of the device and meet the needs of modern high-performance integrated circuits for high-voltage devices.

[0073] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0074] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for a non-self-aligned high voltage CMOS device, characterized in that: At least: Step 1: providing a semiconductor substrate; forming a shallow trench isolation structure on the semiconductor substrate, wherein the shallow trench isolation structure formation process includes depositing a chemical mechanical polishing stop layer; Step 2: patterning the chemical mechanical polishing stop layer to form a hard mask above the predetermined high-voltage device active region of the semiconductor substrate, wherein the hard mask has a trapezoidal cross-sectional structure, and the hypotenuse of the trapezoidal cross-sectional structure forms a predetermined angle θ with the surface of the semiconductor substrate; Step 3: Before forming the well region of the high-voltage device, perform tilted ion implantation into the semiconductor substrate using the hard mask as an implantation mask to form a lightly doped drain region of the high-voltage device; Step 4: removing the hard mask; Step 5: After forming the lightly doped drain region, forming a well region of the high-voltage device in the semiconductor substrate; Step 6: forming a gate structure on the semiconductor substrate, wherein the gate structure covers the channel region between the lightly doped drain regions; and Step seven: forming heavily doped source and drain regions of the high-voltage device.

2. The method of claim 1 , wherein: In step 1, the chemical mechanical polishing stop layer is a silicon nitride layer.

3. The method of claim 1 , wherein: In step 2, the predetermined angle θ is greater than or equal to 30° and less than 90°.

4. The method of claim 1 , wherein: In step three, the angle of the inclined ion implantation is 15° to 45°.

5. The method of non-self-aligned high voltage CMOS device according to claim 1, characterized in that: In step 1, before depositing the chemical mechanical polishing stop layer, a pre-oxidation layer is formed on the semiconductor substrate.

6. The method of claim 5, wherein: After forming the well region of the high-voltage device in step five and before forming the gate structure in step six, the method further includes removing the pre-oxidation layer.

7. The method of claim 1 , wherein: In step 2, patterning the chemical mechanical polishing stop layer includes: forming a photoresist pattern on the chemical mechanical polishing stop layer; and etching the chemical mechanical polishing stop layer using the photoresist pattern as a mask to form the hard mask.

8. The method of claim 7, wherein: In step three, before performing the tilted ion implantation, the photoresist pattern is removed; or, in step three, the tilted ion implantation is performed using the hard mask and the photoresist pattern together as an implantation mask, and the photoresist pattern is removed after the implantation.

9. The method of claim 1, wherein: In step five, the method further includes selectively implanting at least one additional well region in a region of the semiconductor substrate used for forming other types of CMOS devices.

10. The method of non-self-aligned high voltage CMOS device according to claim 1, characterized in that: The high-voltage CMOS device is a high-voltage NMOS device. In step three, the lightly doped drain region is N-type doped; in step five, the well region is a high-voltage P-type well; in step seven, the source and drain heavily doped regions are N-type heavily doped.

11. The method of claim 9, wherein: The high-voltage CMOS device is a high-voltage NMOS device, the well region is a high-voltage P-type well, and the at least one additional well region includes a P-type well for forming a low-voltage or other type of CMOS device.

12. The method of claim 1, wherein: The high-voltage CMOS device is a high-voltage PMOS device. In step 3, the lightly doped drain region is P-type doped. In step 5, the well region is a high-voltage N-type well. In step seven, the source and drain heavily doped regions are heavily P-type doped.

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