Method for producing electrical circuit arrangement and electrical circuit arrangement

Abstract

The invention relates to a method for producing an electrical circuit arrangement, primarily for the microwave and / or millimeter wave frequency range, and to an electrical circuit arrangement, preferably produced by said method. The invention relates to a method for producing an electrical circuit arrangement, comprising the following steps: a) producing a support structure (20), in which a first sub-region (120) of the support structure (20) is produced by a free-form microstructure method, in which at least one second sub-region (220) of the support structure (20) comprises an electrically insulating material, and in which the support structure (20) has at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) with respect to a projection direction (100); and b) producing the at least one electrical circuit structure (1) by coating the support structure (20) with at least one electrically conductive material, the coating comprising at least one spatially oriented coating process which is oriented in the projection direction (100) in alignment with the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h). The invention makes it possible to provide a support structure (20) with an integrated undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h), in particular for producing an electrical circuit structure (1) on a substrate (40, 41) of a high-frequency (HF) chip, or for producing an electrical circuit transition (60a-60c, 61a-61c) for an existing electrical circuit structure (50a-50c, 51a-51c).

Description

Technical Field

[0001] The present invention belongs to the field of microwave technology and relates to a method for producing an electrical circuit arrangement, in particular for use in the microwave and / or millimeter-wave frequency range, and to an electrical circuit arrangement preferably produced by the method. The invention allows for the provision of a support structure with an integrated undercut, in particular for producing an electrical circuit structure on a substrate of a high-frequency (HF) chip or for an electrical circuit transition to an already existing electrical circuit structure. By appropriately designing the support structure, a variety of different electrical circuit arrangement designs can be produced. Background Art

[0002] Standaert et al. (Three techniques for the fabrication of high precision, mm-sized metal components based on two-photon lithography, applied for manufacturing horn antennas for THz transceivers, J. Micromech. Microeng. 28, 035008, 2018) describe the current status of producing HF components using two-photon lithography. In one of the methods presented therein, a support structure is first produced using two-photon lithography, and then its entire surface is evaporated in a PVD process. Afterwards, a thicker copper layer is formed using electroplating. With this method, it is possible not to generate an insulating conductive structure because the entire surface of the structure is covered by evaporation, in particular in order to uniformly wet the entire structure by providing a "seed layer" for subsequent electroplating. After production is completed, the structure is manually or mechanically positioned; this makes it impossible to manufacture the corresponding components on a substrate with other circuit structures.

[0003] M. Sterner et al. (Electrochemically Assisted Maskless Selective Removal of Metal Layers for Three-Dimensional Micromachined SOI RF MEMS Transmission Lines and Devices, J. Microelectromechanical Systems 20(4), pp. 899-908, 2011) describe a method for producing an electrical circuit arrangement by using evaporation of a silicon cover layer that is first selectively etched with the help of a mask and subsequent under-etching of a silicon dioxide intermediate layer arranged between the silicon wafer and the silicon cover layer. In this case, electrical circuit arrangements are formed on the surface of the silicon cover layer that is in direct “visual contact” with the evaporation source, which remain electrically insulated from each other because the shadow cast by the silicon cover layer on the silicon wafer can be achieved by under-etching the intermediate layer. This makes it possible to produce conductive structures that are insulated from each other; however, due to the fixed and low height of the silicon dioxide intermediate layer, the conductive structures produced on the surface of the silicon wafer by direct “visual contact” with the evaporation source are inadvertently directly close to the actual circuit structures on the surface of the silicon cover layer and can, for example, be electrically cross-coupled. Therefore, these unwanted structures must be removed to ensure the electrical insulation of the conductive structures. Furthermore, due to the use of a planar layer structure consisting of silicon and silicon dioxide, followed by selective etching of the silicon capping layer using a mask, this method is limited to planar line layouts and, in particular, cannot accommodate line transitions.

[0004] AQ Liu et al., "Low-loss lateral micromachined switches for high-frequency applications," Journal of Micromechanics and Microengineering 15.1, 2004, pp. 157-167, present two lateral RF MEMS switches. These switches are implemented in a quasi-finite coplanar waveguide (FGCPW) structure and actuated by electrostatic forces applied to high-aspect-ratio cantilevers. The lateral switches are fabricated on a silicon-on-insulator (SOI) wafer using a shadow mask technique by deep reactive ion etching (DRIE).

[0005] EP 511360A1 discloses an electron source, which comprises, on a substrate, a dielectric layer having at least one cavity (in which a cathode electrode is arranged in projected form), a first gate located on top of the dielectric layer and at least partially surrounding the cavity, and at least one second gate (which is on the same side as the first gate relative to the top of the dielectric layer), wherein the first gate is located between the cavity and the second gate, the two gates are insulated from each other, and both gates are arranged on top of the dielectric layer, and the second gate is thicker than the first gate.

[0006] US2002 / 0167009 A1 discloses a thin-film transistor for liquid crystal displays and a method for producing the same. Compared to conventional methods, this method can reduce the number of photomasks used in the photolithography process. The passivation film is formed as a single organic insulating film, reducing the number of exposure steps and the number of photomasks required, thereby improving the efficiency of the production process.

[0007] DE 102007010462 A1 discloses a method for producing a micromechanical particle beam source having at least one field emitter tip for emitting particles, wherein the method comprises the following steps: - applying at least one surface layer of an electrically semiconducting or electrically conductive material to a substrate surface, - structuring the at least one surface layer applied to the substrate in such a way that the narrowest possible electrically conductive paths of low height are produced, - partially removing exposed areas of the electrically insulating substrate surface located between the paths in such a way that covering of the newly formed areas of the electrically insulating substrate surface is prevented by the upper surface layer, - applying a further electrically conductive layer to the surface produced in this way, - applying the field emitter tip over the narrow path, so that the field emitter tip can be precisely positioned with an accuracy of a few nanometers in the center of the optical axis of the micromechanical particle beam source.

[0008] DE 102020102372 A1 discloses a component carrier comprising a stack having at least one electrically conductive layer structure and / or at least one electrically insulating layer structure, a conical blind hole formed in the stack, and a conductive electroplated layer extending along at least part of the horizontal surface of the stack outside the blind hole and along at least part of the surface of the blind hole, wherein the minimum thickness of the electroplated layer at the bottom of the blind hole is at least 8 μm.

[0009] Purpose of the Invention

[0010] On this basis, it is an object of the present invention to provide a method for producing an electrical wiring arrangement and an electrical wiring arrangement which at least partially overcome the disadvantages and limitations of the prior art.

[0011] In particular, the present invention aims to enable the production of components having electrically conductive structures that are insulated from one another in cross section, without having to remove additional electrically conductive structures that are unnecessarily produced by direct "line of sight" to the evaporation source, thereby ensuring the electrical insulation of the wiring arrangement. Furthermore, the present invention is not intended to be limited to the production of planar wiring arrangements. Summary of the Invention

[0012] This object is achieved by a method for producing an electrical wiring arrangement and an electrical wiring arrangement having the features of the independent claims. Advantageous developments, which can be realized individually or in any combination, are specified in the dependent claims.

[0013] In a first aspect, the present invention relates to a method for producing an electrical wiring arrangement. Taken individually, the steps of the method are as follows:

[0014] a) producing a support structure, wherein at least one first subregion of the support structure is produced by using a freeform microstructuring method, wherein at least one second subregion of the support structure comprises an electrically insulating material, and wherein the support structure has at least one undercut relative to the projection direction; and

[0015] b) producing at least one electrical line structure by coating the support structure with at least one electrically conductive material, wherein the coating comprises at least one spatially directed coating process which is oriented in the projection direction aligned with the at least one undercut.

[0016] The term "electrical wiring arrangement" refers to an arrangement designed for transmitting and / or modifying electromagnetic waves. The electrical wiring arrangement proposed herein comprises a support structure which has been produced in at least one first subregion of the support structure by using a free-form microstructuring method in at least one second subregion of the support structure consisting of an electrically insulating material, and wherein the electrical wiring structure is applied to the support structure. In this case, the electrical wiring structure comprises one or more electrically conductive structures, which can also be designed in particular as electrical lines or waveguides. The entirety or subset of electrically conductive structures, which are electrically insulated from one another or electrically connected to one another in a defined manner within one or more cross sections, form the desired electrical wiring structure. By the specific design of a plurality of electrically conductive structures, in particular by connecting them outside specific cross sections, this allows a plurality of different electrical wiring structures to be produced on the support structure, which together with the electrical wiring structure form the electrical wiring arrangement.

[0017] The present invention relates to any type of electromagnetic waves as long as they can be guided in an electrical circuit designed as a waveguide. However, electromagnetic waves having a wavelength λ of 3μm ≤ λ ≤ 1m are preferred. In a more preferred embodiment, the electromagnetic waves are as follows:

[0018] - 3 μm ≤ λ ≤ 3 mm, also known as “terahertz waves” or “THz waves”; and / or

[0019] -300μm≤λ≤1cm, referred to as "millimeter wave"; and / or

[0020] -1mm≤λ≤1m, called "microwave".

[0021] According to method step a), the support structure is produced, at least in the first subregion, using a freeform microstructuring process. The term "freeform microstructuring process" herein refers to a three-dimensional structuring process, including subtractive or additive manufacturing processes, that allows the production of three-dimensional structures, preferably freeform structures. In this context, "freeform structures" are understood to mean structures that, within technical limitations regarding resolution and precision, can have arbitrary curvature, at least in certain regions. Thus, freeform structures differ significantly from the structural geometries produced by conventional planar microstructuring processes, particularly by a combination of thin-film deposition processes, two-dimensional photolithography processes (e.g., projection lithography), and etching processes on planar substrates. These combinations typically result in prismatic three-dimensional structural geometries, each having a base and a top surface that are essentially parallel to the substrate surface, are identical in shape or very similar to one another, and, depending on the deposition and etching processes used in each case, are connected to one another by sidewalls that are perpendicular or inclined relative to the substrate surface and / or curved inwards or outwards. The shape of the base and top surfaces is essentially determined by a mask, which typically employs a photolithographic structure, for the localized etching or deposition. By repeating the deposition and etching process multiple times using different masks, multilayer structures consisting of multiple prismatic substructures can be constructed. However, the additional effort associated with this repetition is considerable and, in many cases, limited by the overlay accuracy, so the number of layers that can be produced in practice is often limited to a small number, for example, only three. This leads to geometric limitations on the structures that can be produced with reasonable effort using known microstructuring methods, and thus to functional limitations on the resulting components.

[0022] In contrast, freeform structures produced using freeform microstructuring processes are not subject to these limitations, or to the same extent, because their structural geometry is not restricted to the combination of a relatively small number of planar, prismatic substructures. Therefore, subregions of the support structure defined by the freeform structures can be used, in particular, to design electrical wiring arrangements that no longer necessarily have a planar form. It should be noted that in many cases, freeform structures are actually produced from a large number of individual layers—particularly by using multiple layers of material in 3D printing or solidifying different layers in 3D lithography processes. However, freeform microstructuring processes make it possible to select a sufficiently large number of these layers with acceptable production effort to achieve a good approximation of the freeform structure, and the discretization into individual layers no longer represents a functional limitation on the structural geometry that can be produced in practice. Structures preferably consist of more than 10, particularly preferably more than 20, and especially more than 40 or 50 layers. When producing electrical wiring arrangements designed for a vacuum operating wavelength of approximately 1 mm, the layer thickness is preferably between 100 nm and 10 μm, particularly preferably between 500 nm and 5 μm, and in particular between 100 nm and 1 μm. Thus, electrical circuit structures can be produced with an accuracy of preferably better than 10 μm, in particular preferably better than 5 μm, in particular better than 1 μm. The resolution of the free-form microstructuring method is preferably better than 20 μm, in particular preferably better than 5 μm, in particular better than 1 μm. The above values ​​refer to the production of electrical circuit arrangements designed for a vacuum operating wavelength of about 1 mm. For other vacuum operating wavelengths, the dimensions of the structures and the requirements for the accuracy and resolution of the micromachining process used for production can be scaled accordingly, in particular taking into account the refractive index of the materials used. Depending on the design, the same or different free-form microstructuring processes can be used to produce the sub-regions of the support structure produced by the free-form microstructuring process, the optional additional shielding structures and the optional mechanical protection structures or protective layers, wherein all structures can be produced in a common operation when the same free-form microstructuring process is used.

[0023] In preferred embodiments, the freeform microstructuring process and / or the freeform microstructuring units formulated for such a process can be based on a photolithographic process, particularly using stereolithography or direct writing (preferably three-dimensional direct writing) photolithographic methods. Additive or subtractive manufacturing methods can be used for this purpose, where the term "additive manufacturing process" refers to a production process in which material is gradually deposited on or applied to a structure, while the term "subtractive manufacturing process" describes an alternative manufacturing process in which material is gradually removed from a structure. In preferred embodiments, the material application or removal can be achieved by photolithographic methods using suitable photoresists (particularly negative or positive photoresists). In preferred embodiments, surface light modulators that allow for rapid structuring can be used for the stereolithographic process. In preferred embodiments, multiphoton lithography, particularly using a pulsed laser source, can be used as the direct writing photolithographic method. In this case, light pulses can be used with a pulse duration of at most 10 ps, ​​preferably at most 1 ps, particularly preferably at most 200 fs, in particular at most 100 fs, and a repetition rate of preferably at least 1 MHz, preferably 10 MHz, particularly preferably at least 25 MHz, and in particular at least 80 MHz. Laser light sources particularly suitable for this purpose are selected from fiber-based femtosecond lasers or pulsed solid-state lasers, preferably titanium:sapphire lasers or diode lasers, which can be combined with frequency conversion units, in particular configured for frequency multiplication, sum frequency generation or differential frequency generation. In particular, depending on the lithography method used for this purpose, wavelengths in the near-infrared, visible or ultraviolet spectral range or in the extreme UV radiation (EUV) or X-ray wavelength range can preferably be used. In particularly preferred embodiments, the wavelength can be in the range of 150 nm to 1700 nm, in particular in the range of 300 nm to 1100 nm. For pulsed lasers, two-photon, three-photon or multi-photon absorption effects can be achieved by selecting the pulse duration and pulse energy. In single-photon absorption lithography processes using continuous wave lasers or LEDs, suitable emission wavelengths are between 360 nm and 550 nm, in particular around 365 nm, 385 nm, 405 nm, 550 nm and 532 nm. In order to increase the resolution of photolithographic processes, the "stimulated emission depletion" (STED) principle can be used with suitable photoinitiators depending on the corresponding microscopy method.

[0024] In a specific embodiment, it may happen that a sub-area of ​​the support structure produced by the free-form microstructuring process, an additional shielding structure, a mechanical protection structure or a protective layer is larger than the available write field size of the machine used for production via the free-form microstructuring process. In these cases, the structure in question can be divided into individual parts, each part being located within a write field, and produced by precisely stitching these segments together. When choosing the write field size, particular consideration may be given to the achievable resolution (a smaller write field generally increases the resolution) and stitching errors at the write field boundaries (using a large write field may reduce the number of errors). The write field size is preferably in the range of 50×50 μm. 2 and 5×5mm 2 between 100×100 μm, especially preferably between 100×100 μm 2 and 3×3mm 2 between 200×200 μm, and most preferably between 200×200 μm 2 and 1×1mm 2 The alignment accuracy of a single writing field is preferably better than 5 μm, particularly preferably better than 1 μm, and in particular better than 500 nm or 100 nm. In a specific embodiment, a two-photon lithography system is used for production. In this case, for a lens with a numerical aperture of 1.4 and a magnification of 40, the available writing field can be in the form of a circular surface with a diameter of 400 μm.

[0025] In certain embodiments, the first subregion of the support structure produced by the free-form microstructuring process may also include a conductive material. In this case, methods for metal 3D printing may preferably be used, which may be based in particular on material extrusion, powder bed fusion, material jetting, binder jetting, replica imprinting, selective laser sintering, laser metal deposition or electron beam melting. In a particularly preferred embodiment, a polymer with a high proportion of particles (slurry) can be produced, the particles being selected from, for example, copper, stainless steel or other conductive materials. By then baking the component in an oven, the polymer compound is opened and burned out (debinding and sintering), leaving behind a conductive workpiece that largely reflects the properties of the material of which the particles are composed.

[0026] In addition to the subregions produced by the freeform microstructuring process, the support structure may also include other subregions that are unstructured or structured by other methods. Thus, it is possible that the support structure comprises a substantially flat substrate on which a further subregion of the support structure is produced by the freeform microstructuring process, said subregion having an undercut as defined below, either independently or together with the substrate. Suitable substrates are, in particular, silicon (Si), gallium arsenide (GaAs), indium phosphide (InP), aluminum oxide (Al2O3), beryllium oxide, quartz glass, sapphire, (woven) PTFE / glass, polyolefins, ferrite / granite or ceramics. Furthermore, the substrate may also include conductive subregions. During the coating process of the support structure comprising the substrate, it is particularly possible that at least one exposed surface, defined by at least one undercut in the support structure and designed to insulate adjacent conductive structures, can be arranged on the substrate and not, for example, on a subregion of the support structure produced by the freeform microstructuring process or on a subregion of the support structure consisting of insulating material.

[0027] The support structure produced according to method step a) further comprises at least one second sub-region comprising an electrically insulating material, which

[0028] - on the one hand, providing a mechanically stable and, at least in certain areas, electrically insulating basis for the subsequent coating with at least one electrically conductive material carried out according to method b); and

[0029] On the other hand, it can be produced in a desired geometrical, not necessarily planar, shape, on which the desired electrical circuit structure is formed by coating according to method step b).

[0030] For the purposes of the present invention, "electrically insulating material" refers to a material with an electrical conductivity σ not greater than 10 -4 S / m, preferably not more than 10 -7 S / m, especially not more than 10 -10The electrically insulating material preferably has a high dielectric strength and preferably low losses, in particular in the form of a low loss factor tan δ of no more than 0.1, preferably no more than 0.05, and in particular no more than 0.01 at the respective operating frequency of the electrical wiring structure. In this context, the term "operating frequency" refers to the frequency of the electromagnetic wave for which the selected electrical wiring arrangement is preferably designed. Similarly, the term "operating wavelength" designates the wavelength of the electromagnetic wave for which the selected electrical wiring arrangement is preferably designed. Suitable materials for the at least one electrically insulating region of the support structure are preferably ceramics, glass, polymers, or other organic compounds or appropriately doped semiconductors, as well as composites made from these materials. Suitable materials are particularly those that can be three-dimensionally structured using suitable methods, wherein, in preferred embodiments, the methods and the relevant materials are selected in such a way as to enable the production of free-form structures. In preferred embodiments, polymer-based materials are used to produce the support structure, preferably comprising optically additively or subtractively structured polymers, such as those from the class of acrylates, epoxies, or fluoropolymers. If, in method step a), a photolithographic method is used to structure the polymer-based material, preference is given to using polymers which, in particular, may be fluorinated or may have silicone-based components.

[0031] In a particularly preferred embodiment, the first sub-region produced in method step a) by the free-form microstructuring process can be identical to the second sub-region comprising an electrically insulating material. However, the two regions can also be disjoint or non-intersecting, or they can completely or partially contain each other. When the conductive area of ​​the substrate is replaced by an insulating substrate, an embodiment in which the second sub-region completely includes the first sub-region is produced, so that only the insulating second sub-region is produced by 3D printing. In another embodiment in which the two regions do not intersect, the support structure has a metal core comprising a metal substrate and an insulating coating. The core filling the first sub-region is produced in the first sub-region of the support structure by the free-form microstructuring process, and the insulating coating can be applied independently to the second sub-region of the support structure in a subsequent process, in particular by an isotropic coating method. In this embodiment, the two sub-regions do not intersect.

[0032] According to method step a), the support structure is produced in such a way that it has at least one undercut relative to the projection direction. The term "undercut" refers to a protrusion defined relative to the projection direction that is introduced into the surface of the support structure. The geometric definition of the term "undercut" is given by way of example in Figure 3 Shown, Figure 3A support structure with an undercut defined relative to a projection direction p is shown, with an associated shaded area. The shaded area includes the sum of all points P on the surface of the support structure where a semi-line g emanating from point P and oriented opposite to the projection direction P passes through the support structure. The sum of the portions of all these semi-line g located within the support structure defines a subregion of the support structure known as the overhang. The overhang defines a shaded area that includes the sum of lines PP' connecting points P located outside the support structure to the entry point P' of the associated semi-line g into the nearest support structure opposite to the projection direction.

[0033] At least one undercut is designed to produce a shadow in at least one spatially oriented coating of the support structure, the shadow layer being applied in the projection direction using at least one electrically conductive material. The term "shadow" refers to the result of coating the support structure with the at least one electrically conductive material, wherein at least one exposed area on the surface of the support structure remains uncoated and not covered by the electrically conductive material. Depending on the design of the coating process according to method step b) and the direction of the spatially anisotropic material flow, the uncoated area can be geometrically identical to the shadow area, surround at least some area of ​​the shadow area, or become part of the shadow area.

[0034] According to method step b), the circuit structure is produced by coating the support structure with at least one electrically conductive material. In certain embodiments, the coating of the support structure may involve a plurality of coating methods and / or materials, wherein at least one coating method is spatially directional, and wherein at least one material must be electrically conductive within the meaning defined herein. In a preferred embodiment, the at least one electrically conductive material is applied in a directional coating process.

[0035] The support structure can be coated using a coating process suitable for this purpose. The coating process is preferably selected from: a physical vapor deposition (PVD) process, in particular thermal evaporation, electron beam evaporation, laser beam evaporation, arc evaporation, molecular beam epitaxy, ion plating or sputtering deposition, wherein sputtering deposition includes DC sputtering, RF sputtering, magnetron sputtering, reactive sputtering, ion beam sputtering or atomic beam sputtering; or a chemical vapor deposition (CVD) process, which includes plasma assisted chemical vapor deposition (PECVD), hot injection or electroplating. In these methods, the degree of spatial anisotropy, i.e. the directionality of material transport during coating, can be adjusted by using various parameters (in particular the pressure at which the coating is performed). In addition to spatial anisotropy, i.e. directional coating processes, isotropic processes can also be used, in which all sides of the structure are coated. A wide range of processes can be envisioned here, such as immersion or spraying processes, spin coating, atomic layer deposition (ALD) or electrochemical processes. In a particular embodiment, after directional coating with metal, an isotropic coating with an inert protective material can be applied, in particular to prevent oxidation of the metal area. In certain embodiments, the thickness of the at least one electrically conductive material applied to the electrically conductive structure can be increased by electrogrowth in order to increase the robustness of the coating, particularly under mechanical stress. In this case, the achieved thickness of the electrically conductive structure is preferably greater than 1 μm, particularly preferably greater than 10 μm, and in particular greater than 20 μm or 50 μm. The achieved thickness can be adjusted, in particular, by adjusting process parameters such as current density, temperature, and time for the respective materials.

[0036] For the purposes of the present invention, "conductive material" refers to a material having an electrical conductivity σ of preferably at least 10 6 S / m, particularly preferably at least 10 7 S / m, especially at least 5×10 7 S / m substances. Particularly suitable materials for this purpose include silver, copper, gold, and aluminum; however, other metals may also be used. In this case, the electrical circuit structure may include a homogeneous region of a single conductive material, a mixed phase composed of at least two different conductive materials, in particular an alloy of at least two different metals, and / or a layered structure composed of at least two different layers, each comprising a homogeneous phase or a mixed phase.

[0037] In a preferred embodiment, the order of the layers in the layer structure can be selected in a preferred manner. The preferred layer sequence can particularly include a first layer directly or indirectly adjacent to the support structure, which has an adhesion promoter with good adhesion properties relative to the substrate arranged below and / or the layer arranged above, wherein the first layer can particularly include titanium, a core of a highly conductive material (preferably copper or gold), and an outer passivation layer made of a chemically resistant non-oxidizing material (preferably gold, silicon nitride or silicon dioxide) adjacent to the surrounding environment. In addition, at least one further layer, preferably titanium, can be introduced between the core material and the passivation layer for diffusion protection. The use of other materials is also possible. Thus, the electrical circuit structure can be designed for both particularly high charge transport and particularly high resistance to environments (where substances corrosive to the conductive material, in particular oxygen, may be present). The application of these layers does not necessarily need to be carried out in a spatially oriented process. Therefore, it can be helpful, especially for the passivation layer, to use an isotropic process that protects the electrical circuit arrangement from multiple sides, preferably from all sides, during high-pressure atomic layer deposition or evaporation.

[0038] In many cases, the thickness γ of the conductive layer of the electrical circuit structure can be roughly estimated based on the skin effect and taking into account the vacuum operating frequency, in particular using formula (1):

[0039]

[0040] Here, the conductive layer thickness γ is defined as the resulting wall thickness of a notional circular conductor that has the same DC resistance as a solid conductor due to the skin effect at frequency f. Absolute magnetic permeability μ = μ0μ r From the magnetic permeability constant μ o =1,256·10 -6 N / A 2 and the relative permeability μ of the conductive material for circular conductors r Composition. The conductivity of conductive materials is represented by σ. Taking copper as an example, the working wavelength in vacuum is about 1mm and the conductivity σ=5.8·10 3 At 100 μm / s, the resulting conductive layer thickness is r = 0.12 μm. Therefore, when implementing the coating process, the layer thickness of the conductive material is preferably selected to be at least sufficiently large so that the layer thickness is preferably three times, particularly preferably five times, and in particular ten times, the thickness of the conductive layer at the desired operating frequency or wavelength. For other operating wavelengths, the layer thickness can be scaled proportionally to the root of the wavelength, taking into account the conductivity of the conductive material used.

[0041] According to method step b), the coating of the support structure includes at least one spatially oriented coating process, which is oriented in the projection direction aligned with the at least one undercut. Thus, the conductive material is applied to the support structure as an electrical wiring structure in the form of one or more conductive structures, which are electrically isolated from one another or electrically connected to one another in a defined manner within the cross section, wherein the coating direction corresponds to the projection direction associated with the undercut. As described above, the at least one undercut introduced into the support structure results in the formation of at least one uncoated exposed area on the surface of the support structure, which provides electrical insulation at a desired location on the surface of the support structure between the conductive structures adjacent to the at least one exposed area. In this way, the desired electrical wiring structure is formed on the surface of the support structure, which comprises a plurality of conductive structures, which are electrically isolated from one another or electrically connected to one another in a defined manner within the cross section. In this case, it is particularly advantageous to produce at least one undercut during method step a) and to have appropriate knowledge of the projection direction required during method step b), in particular so that, via the shape of the support structure and the at least one undercut introduced therein, the final form of the desired electrical line structure can be freely defined in space, comprising a plurality of electrically conductive structures that are electrically isolated from one another or electrically connected to one another in a defined manner, taking into account a direct line of sight between each point P on the support structure to be coated and the position of the evaporation source providing the electrically conductive material for coating the support structure.

[0042] In a preferred embodiment, a physical vapor deposition (PVD) method, in particular electron or laser beam evaporation, can be used. In this case, by selecting a sufficient working distance between the location of the evaporation source and the support structure to be coated, the evaporation direction defined by the connecting line between the evaporation source and the support structure to be coated can be well approximated, corresponding to the projection direction associated with the undercut as desired according to the present invention. In this case, the distance between the evaporation source and the support structure to be coated is preferably greater than 25 cm, particularly preferably greater than 50 cm, and in particular greater than 75 cm and 100 cm, so that the divergence of the evaporation beam emanating from the evaporation source about the defined projection direction at the location of the support structure to be coated is preferably less than 10°, particularly preferably less than 5°, and in particular less than 2°. "Divergence" at the location of the support structure to be coated is understood to mean the variance or standard deviation of the direction of the beam emitted by the evaporation source impinging on a certain point on the support structure. This variance can be determined, in particular, by the ratio of the lateral extent of the evaporation source to the distance from the evaporation source to the support structure to be coated. Large variances in the direction of the incident beam generally lead to corresponding blurring of the edges of the shadow cast by at least one undercut, which can be accompanied by adverse effects on the properties of the electrical circuit arrangement to be produced. The deviation between the actual evaporation direction according to the invention and the desired projection direction relative to the undercut is preferably at most 20°, particularly preferably at most 10°, in particular at most 5° or 2°. Preferably, the operating pressure in the chamber of the coating system is selected so that the mean free path length of the particles transferred during the evaporation process exceeds the distance between the evaporation source and the support structure to be coated. The term "mean free path length" is understood here to mean the path length that a particle, in particular one of an atom, molecule, ion or electron, travels on average in a given material before colliding with another particle. If a particle flow in a material has traveled the mean free path length, then a fraction 1 / e of the particle flow has not yet collided with another particle. The mean free path length preferably exceeds the distance between the evaporation source and the support structure to be coated by a factor of at least 3, particularly preferably by a factor of at least 8 or 20, in particular by a factor of at least 100 or 200. The pressure can generally be assumed to be around 10 -7 Pa to 10 -3 Pa, especially depending on the material chosen.

[0043] In a specific embodiment, when performing method step b), not only the desired electrical circuit structure can be formed, but also at least one other conductive structure can be generated, which is not necessarily a functionally relevant component of the desired electrical circuit structure. Therefore, in this case, it is desirable that at least one undercut is designed so that at least one other conductive structure can be arranged sufficiently far away from the desired electrical circuit structure. In such an arrangement, the influence of the additionally generated conductive structure on the electromagnetic waves (also referred to as "modes") guided in the desired electrical circuit structure can preferably be minimized. In particular, in order to avoid coupling of the modes guided in the desired electrical circuit structure with at least one other conductive structure, a distance can be set between the two structures, the size of which is sufficient to exceed the penetration depth ε of the electromagnetic waves guided in the desired electrical circuit structure into the surrounding spatial region, preferably at least twice, particularly preferably five times, and in particular ten times the penetration depth ε. The term "penetration depth ε" here refers to the depth at which the evanescent electric field associated with the mode guided in the electrical circuit structure drops by 1 / e.

[0044] The methods described herein allow a wide range of different electrical wiring configurations to be produced on a support structure.

[0045] In a preferred embodiment, the electrical line structure may include a single microstrip line formed from a conductive structure that is electrically insulated from the environment in all cross-sections along the electrical line structure. The electrical insulation of the conductive structure from the environment can preferably be achieved by at least one exposed area on the surface of the support structure, which remains uncoated during the coating step due to a shadow cast by at least one undercut. The conductive structure can be implemented on the support structure in particular as an electrical line or as a waveguide.

[0046] In another preferred embodiment, the electrical wiring structure may include at least two conductive structures that are spatially separated from each other, arranged at intervals on the support structure, and electrically insulated from each other in all cross-sections along the electrical wiring structure. In this case, by arranging at least one exposed area created by at least one undercut between the at least two conductive structures, the at least two conductive structures can be preferably spatially separated from each other and electrically insulated from each other.

[0047] In this embodiment, the electrical circuit structure may include multiple individual conductive structures electrically isolated from one another in the form of multiple microstrip lines. At least two of the isolated microstrip lines may be at the same electrical potential or at different electrical potentials. For example, the microstrip lines may be arranged parallel to one another. However, other configurations of the microstrip lines are contemplated.

[0048] In this embodiment, the electrical line structure can be or in particular include a slotted line, wherein the slotted line has two electrically conductive structures which are spatially separated from one another and electrically insulated from one another in all cross sections along the electrical line structure, wherein the two electrically conductive structures are at the same electrical potential.

[0049] In this embodiment, the electric line structure (1) can be or include a coplanar line, wherein the coplanar line has three conductive structures that are spatially separated from each other and electrically insulated from each other in all cross-sections along the electric line structure, wherein two of the conductive structures are at the same electrical potential and the third conductive structure is at a different electrical potential.

[0050] In another preferred embodiment, the electrical conductor structure can be designed in the form of an antenna. In this embodiment, the electrical conductor structure can preferably include a plurality of individual electrically conductive structures that are electrically insulated from one another in one cross section, which vary in a defined manner along the conductor structure and, in particular, can also be electrically connected in a defined manner in at least one further cross section of the electrical conductor structure. In this embodiment, the at least one exposed area created by the at least one undercut can be specifically configured to convert the conductor-bound electrical signal into a free-space wave.

[0051] In another preferred embodiment, in addition to the required conductive structures within the cross section, the electrical line structure may include at least one further conductive structure described in greater detail above, in particular to achieve certain functionalities. In this configuration, the electrical line structure may be designed in particular as an electrical line coupler. The electrical line coupler may include two conductive structures in the form of two waveguides, which are arranged spaced apart on a support structure and may be electrically insulated from one another along all cross sections of the line structure. The two waveguides guide different signals and are spaced apart from one another at a distance such that a desired coupling of the electric field from one conductive structure to the other can be adjusted via the at least one further conductive structure.

[0052] In another preferred embodiment, the electrical line structure can be embodied in the form of an electrical probe tip, which is suitable for contacting an electrical circuit, in particular a radio frequency (RF) circuit, and preferably has at least one contact element for this purpose. By appropriately shaping the support structure to be coated, the at least one contact element can be configured as a contact tip or based on a suitable structural element protruding in a direction perpendicular to the coating surface, which allows geometrically precise contacting of a corresponding contact surface (pad or probe pad) on a chip or a planar substrate.

[0053] The methods described herein can be used to produce additional electrical circuit structures having special geometries or that may be suitable for special applications.

[0054] A particular advantage of the method described herein is that the at least one undercut allows the support structure for the electrical conductor structure to be designed in such a way that, based on the conductive material of the electrical conductor structure and the geometry of the support structure, the effective dielectric constant of the mode guided in the electrical conductor structure can be set and varies along the propagation direction of the conductor structure or the electromagnetic field present in the conductor structure. The effective dielectric constant of the mode guided in the at least one electrical conductor structure along the propagation direction of the mode perpendicular to the corresponding drawing plane is preferably set to 20Ω to 100Ω. This type of configuration can be particularly advantageous for reducing the effects of high dielectric constants (e.g., of the substrate) on the antenna by gradually moving the mode guided in the electrical conductor structure away from the substrate, in particular by varying the at least one undercut along the conductor structure. This allows the dielectric constant of the mode to be effectively detected to be adapted to local conditions, thereby reducing line losses or gradually adjusting the line impedance. The term "gradually" here refers to a continuous transition of a characteristic quantity (in particular, impedance) of the mode, preferably starting from a substrate with a high dielectric constant to a subregion of the support structure based on a material with a lower dielectric constant, in particular by a linear transformation of the geometry at the transition.

[0055] In another embodiment, the methods described herein can be used to provide at least one electrical wiring transition to at least one existing electrical wiring structure (previously produced using the methods described herein and / or by using conventional manufacturing methods on a substrate). To this end, a support structure can be aligned with the existing electrical wiring structure, such that coating the support structure with at least one electrically conductive material occurs along a projection aligned with at least one undercut; thereby, at least one electrical wiring transition is produced from the existing electrical wiring structure to the electrically conductive structure being developed within the electrical wiring structure. Thus, the support structure can ensure that the existing electrical wiring structure remains electrically isolated in all cross-sections along the wiring structure by using at least one undercut.

[0056] However, with this type of coating, the entire substrate outside of the support structure subregions produced by the free-form microstructuring process using conductive material can be covered, thereby undesirably coating existing electrical wiring structures and other components or circuits present on the substrate. To prevent this undesirable coating, at least one additional shielding structure can be aligned with at least one electrical wiring transition between the existing electrical wiring structure and the newly produced electrical wiring structure using the method described herein, so that during coating in the projection direction, the existing electrical wiring structure can remain electrically isolated in all cross-sections along the wiring structure. This also prevents an overall short circuit of the electrical wiring structure to further conductive structures being deposited.

[0057] In a preferred embodiment, at least one additional shielding structure can cover other surfaces of the substrate in such a way that these other surfaces of the substrate remain protected from global coverage by the conductive material. For this purpose, it is particularly conceivable to completely cover these other surfaces with a protective structure, in particular in the form of a protective layer, so that the influence of the electrical circuit structure being developed on the electrical circuit structure existing on the substrate is minimized by a protective structure of sufficient thickness, in particular the protective layer. Alternatively, the additional protective structure or shielding structure, in particular the protective layer, can be optionally removed after coating, in particular by simply peeling them off using a suitable tool (preferably a pair of tweezers) or using a peeling process, thereby allowing the entire surface to be covered with the conductive material to prevent other conductive structures formed as by-products from separating again. Preferably, the areas to be protected by the protective layer can be selectively covered before coating. In a preferred embodiment, the selective application of the protective layer can be carried out by inkjet printing, using a dispenser and / or by lithographic structuring. After applying the conductive material, the protective layer can be removed again, so that other conductive structures can also be formed on the protective layer to expose the existing electrical circuit structure again. It is advantageous in this case that, during the long exposure period, neither the protective materials used nor any substances used to remove them (such as solvents) damage or otherwise adversely affect the support structures, in particular the sub-areas produced by the free-form microstructuring process. In a preferred embodiment, PMMA (polymethyl methacrylate) or another suitable substance can be used as the protective material for the protective layer, which can be removed again with PGMEA (propylene glycol monomethyl acetate) without affecting other areas of the support structure produced using two-photon lithography. The advantages of this lift-off process include faster global coverage of the substrate, in particular by using a deposition process, if the protective structures or shielding structures cannot be produced using a free-form microstructuring process due to the size of the surface to be covered.

[0058] In another preferred embodiment, the electrical circuit structure can include at least two electrical circuit transitions and is thus configured as a connecting element between at least two circuit structures provided on separate substrates, which circuit structures have previously been produced using the methods described herein and / or using conventional manufacturing methods. The support structure can include at least two substrates mounted on a common base plate and at least one subregion produced using a freeform microstructuring process, which can be connected to existing circuit structures on both substrates via the electrical circuit transitions and has at least one undercut according to the invention relative to the projection direction. To protect the surfaces of the two substrates, during the coating process in method step b), corresponding temporary or permanent protective structures, in particular shielding structures or protective layers, can be provided again, at least in certain areas.

[0059] In another preferred embodiment, the electrical circuit structure can be embodied in the form of an interdigitated capacitor. An electrical circuit structure in the form of an interdigitated capacitor can include a plurality of conductive structures that can be arranged substantially alternately in two different planes running parallel to each other and can be at different electrical potentials. Preferably, the conductive structures can be located in a common first plane defined by grooves in the support structure, while the remaining conductive structures can be located in a second plane defined by webs between the grooves. To create the electrical circuit arrangement, at least one undercut is introduced into the support structure relative to the projection direction, so that at least one exposed area ensures electrical insulation between the conductive structures applied in the two different planes. In a preferred embodiment, the divergence of the evaporation beam emitted from the evaporation source about the defined projection direction at the location of the support structure to be coated can be used to increase the width of the strip-shaped conductive structures produced in the first plane so that, when projected along the projection direction, they overlap with the conductive structures in the second plane. This particularly helps to increase the capacitance between the structures in the two planes. The conductive structures located in the common plane can be electrically connected to each other in another cross-section of the electrical circuit structure, thereby forming a common power supply line. Since sub-regions of the support structure are designed as 3D free-form structures, the design may provide more degrees of freedom in arrangement, in particular with improved resolution, compared to prior art methods.

[0060] In another aspect, the present invention relates to an electrical wiring arrangement, in particular an electrical wiring arrangement produced using the method described herein. The electrical wiring arrangement comprises:

[0061] - a support structure comprising

[0062] at least one first subregion which is designed as a three-dimensional free-form structure and produced using a free-form microstructuring process, and

[0063] a second subregion comprising electrically insulating material,

[0064] wherein the support structure has at least one undercut relative to the projection direction; and

[0065] At least one electrical line structure, applied as a coating on the support structure using at least one spatially oriented coating process with at least one electrically conductive material, is aligned with the at least one undercut in the projection direction.

[0066] For further details of the present electrical wiring arrangement, reference is made to the description of the method for producing the electrical wiring arrangement also described herein and to the exemplary embodiments.

[0067] The terms "having," "exhibiting," "comprising," or "including," or any grammatical form thereof, are used in a non-exclusive manner. Thus, these terms may refer to the absence of features other than the features introduced by these terms, or the presence of one or more other features. For example, the expression "A has B," "A exhibits B," "A comprises B," or "A includes B" may refer to the absence of elements other than B in A (i.e., A consists entirely of B), or the presence of one or more elements other than B in A (e.g., element C, element C and D, or other elements).

[0068] It should also be noted that the terms "at least one" and "one or more" and their grammatical forms, when used in conjunction with one or more elements or features and intended to indicate the fact that the elements or features may be provided one or more times, are usually used only once, for example, when the feature or element is first introduced. When the feature or element is mentioned again later, the corresponding terms "at least one" or "one or more" are generally not used again, but this does not limit the possibility that the feature or element may be provided one or more times.

[0069] Furthermore, the terms "preferably", "preferably", "in particular", "for example" or similar terms are used herein in conjunction with optional features without thereby limiting the optional embodiments. The features introduced by these terms are therefore optional features and it is not intended that the scope of protection of the claims, in particular the independent claims, be limited by these features. Therefore, as will be appreciated by those skilled in the art, the present invention can also be implemented using other embodiments. Similarly, features introduced by "in one embodiment of the invention" or "in an exemplary embodiment of the invention" are to be understood as optional features without thereby limiting the optional embodiments or intending to limit the scope of protection of the independent claims. Furthermore, these introductory expressions are intended to leave all possibilities open for combining the features introduced by them with other features, whether optional or non-optional.

[0070] Advantages of the present invention

[0071] In contrast to known methods for producing electrical wiring arrangements, which typically rely on the use of masks and are therefore largely limited to planar support structures and the production of wiring arrangements of varying heights, the present method does not require masks for production. This makes it possible, in particular, to produce 3D free-form wiring structures. The use of 3D printing technology for producing the support structures allows for the production of complex three-dimensional support structures, which is particularly suitable for improving coupling efficiency and bandwidth between transmission lines compared to known methods. Because the free-form support structures are produced using a free-form microstructuring method, masks are not required for production, and the electrical wiring arrangements can be produced in situ (i.e., directly) at the point of use, such as on a chip. This allows the electrical wiring arrangements to be directly aligned with existing circuits and electrically connected with high bandwidth and low loss, eliminating the typically necessary precise assembly steps. This enables the realization of a wide variety of assemblies, including connecting elements between multiple chips and even antennas, designed as free-form structures for more efficient radiation and separated from the surface.

[0072] From the prior art cited at the outset, there is no known first sub-region of the support structure generated by using a free-form microstructuring process. Consequently, the cited prior art also does not disclose the production of the non-planar electrical wiring arrangement specified in the present invention. In particular, the present invention solves the problem of producing components with conductive structures that are insulated from one another in the cross section, without first having to remove additional conductive structures that are unnecessarily generated by a direct “line of sight” to the evaporation source in order to ensure the electrical insulation of the desired wiring arrangement. In a further distinction from the above-mentioned prior art, the present invention therefore also solves the problem of packaging so-called next-generation radio frequency components, which are particularly designed for millimeter-wave and THz frequencies.

[0073] Furthermore, using the current production methods, microwave components (particularly antennas), chip-to-chip connection elements, or electrical probe tips can be produced directly on a substrate that serves as a support structure. The printing of subregions of the support structure on the substrate that define the electrical wiring structure or that are also contained in the support structure, as well as the protection of the support structure or substrate through the use of shielding structures, particularly protective layers, enables a wide variety of implementable structures with 3D free-form geometries and, in particular, allows the electrical wiring structure to be adapted to the conditions of the existing structure. This is particularly important in RF technology, where changes to the electrical wiring structure on a chip are typically time-consuming and expensive. However, the functionality and design of the electrical wiring structure according to the present invention can be flexibly varied through appropriate shaping of the subregions of the support structure produced using the free-form microstructuring process. For example, the possibility of three-dimensional design of the support structure means that electromagnetic waves can be directed away from the substrate, so that the effects of the high dielectric constant of the substrate or support structure can be easily adapted to local requirements within the cross-sectional area as needed. Similarly, electrical probe tips with a variety of geometries can be flexibly implemented on standardized and therefore cost-effective support substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] Further details and features of the invention can be found in the following description of preferred exemplary embodiments, in particular in relation to the dependent claims. In the text, the corresponding features can be implemented both individually and in combination with one another. The invention is not limited to the exemplary embodiments. Exemplary embodiments are schematically illustrated in the following figures. In these figures, the same reference numerals in the figures refer to identical or functionally identical elements or to corresponding elements with respect to their function. In the figures, taken individually:

[0075] Figure 1 and Figure 2 each showing a preferred exemplary embodiment of a method according to the invention for producing an electrical wiring arrangement in a schematic cross-sectional view;

[0076] Figure 3 Schematically illustrates the geometrical definition of the undercut according to the invention relative to the projection direction in the support structure according to the invention;

[0077] Figures 4 to 10 each showing an exemplary embodiment of an electrical wiring arrangement according to the invention in a schematic cross-sectional view;

[0078] Figures 11 to 14 A method sequence for producing another electrical wiring arrangement according to the invention is schematically shown;

[0079] Figure 15 and Figure 16 each showing a preferred exemplary embodiment of an electrical wiring arrangement according to the invention;

[0080] Figure 18 A further exemplary embodiment of the method sequence according to the invention for producing a further electrical wiring arrangement is shown in a microscope image; and

[0081] Figure 19 and Figure 20 A further exemplary embodiment of an electrical wiring arrangement according to the invention is shown in each case in microscope images. DETAILED DESCRIPTION

[0082] Figure 1 and Figure 2 In each case, preferred exemplary embodiments of the method according to the invention for producing an electrical wiring arrangement are shown in the form of schematic cross-sectional views. Figure 1 Schematically represents method step a), Figure 2 Method step b) is schematically represented. The illustrations and in particular the shapes of the support structures 20 selected for this purpose are to be understood as examples; a wide variety of other arrangements and shapes are possible according to expert considerations.

[0083] Figure 1 Method step a) is schematically shown, which comprises the production of a support structure 20, wherein a first subregion 120 of the support structure 20 is produced by using a free-form microstructuring method, wherein a second subregion 220 of the support structure 20 comprises an electrically insulating material, and the support structure 20 has undercuts 20a, 20b, 20c, 20d relative to the projection direction 100. In the case shown, the subregions 120, 220 are identical and form the support structure 20.

[0084] Figure 2Schematically, method step b) is shown, which involves producing at least one electrical wiring structure 1 by coating a support structure 20 with at least one electrically conductive material along a projection direction 100 aligned with the undercuts 20a, 20b, 20c, 20d. In this step, the support structure 20 (including the undercuts 20a, 20b, 20c, 20d included in the support structure 20) is coated from the projection direction 100. The areas 30a, 30b, 30c, 30d that are obscured by the undercuts 20a, 20b, 20c, 20d present in the support structure 20 result from the defined projection direction 100, which is known in advance, and are not affected, or only insignificantly affected, by the spatially oriented coating of the support structure 20 using the electrically conductive material. In this case, the expression "only insignificantly" means that, although edge regions of the shaded areas 30a, 30b, 30c, 30d (for example due to the non-vanishing divergence 105 of the evaporation beam emitted by the evaporation source around the defined projection direction 100) can be covered by the conductive material, there are still exposed areas 30a, 30b, 30c, 30d that are not covered by the conductive material, resulting in electrical insulation of the conductive structures 10a, 10b, 10c within the simplified cross-section of the line structure 1.

[0085] like Figure 2 As shown schematically, a plurality of conductive structures 10a, 10b, 10c and other conductive structures 11a, 11b are formed on the surface of the support structure 20 by coating the conductive material in the cross-sectional plane. Figure 2 In this exemplary embodiment, three conductive structures 10a, 10b, and 10c are located at a common height and each has a shape predetermined by the three-dimensional shape of the surface of support structure 20. Due to the undercuts 20a, 20b, 20c, and 20d included in support structure 20, exposed areas 30a, 30b, 30c, and 30d are additionally formed on the surface of support structure 20 by coating the surface of support structure 20 with a conductive material relative to projection direction 100. Exposed areas 30a, 30b, 30c, and 30d insulate conductive structures 10a, 10b, and 10c from one another and are further designed to electrically insulate conductive structures 10a, 10b, and 10c within the cross-sectional plane from additional conductive structures 11a and 11b that are inevitably formed in the recesses of support structure 20 during method step b). By appropriately shaping the support structure 20, a configuration can be achieved in which the additional conductive structures 11a, 11b are distinct from the conductive structures 10a, 10b, 10c, so that the electrical signals conducted by the conductive structures 10a, 10b, 10c do not interact with the other conductive structures 11a, 11b, see also Figure 6In this case, the three electrically conductive structures 10a, 10b, 10c form the required electrical wiring structure 1. The electrical wiring structure 1 together with the support structure 20 and the exposed areas 30a, 30b, 30c, 30d present therein form an electrical wiring arrangement.

[0086] Figure 3 The projection direction p100 and the associated undercut 20a according to the invention and the associated definition of a shadowing region 30a in a support structure 20 according to the invention are schematically illustrated. In the illustrated case, the two sub-regions 120, 220 are identical and form the support structure 20. The shadowing region 30a comprises the sum of all points P1015 on the surface of the support structure 20, wherein a half-line g1016 emanates from the point P1015 and is oriented opposite to the projection direction p100, passing through the support structure 20. The sum of the portions 1030 of all such half-lines g1016 located within the support structure 20 defines a sub-region of the support structure 20 referred to as the overhang 1020. The overhang 1020 defines an occlusion region 1040 comprising the sum of connecting lines PP′ 1031 from a point P 1015 outside the support structure 20 to an entry point P′ of the associated half-line g 1016 nearest the support structure 20 opposite to the projection direction p 100 into the support structure 20 .

[0087] Figure 4 An exemplary embodiment of an electrical line arrangement according to the invention is shown in a schematic cross-sectional view, wherein the support structure 20 comprises a substrate 40. A first subregion 120 of the support structure is produced from an electrically insulating material using a free-form microstructuring process. As substrate 40, an electrically insulating carrier material is used, which is produced using a different production process than the first subregion 120 of the support structure 20. In this exemplary embodiment, the electrically insulating second subregion 220 of the support structure 20 comprises the substrate 40 and the first subregion 120 of the support structure 20, which is produced using a free-form microstructuring process. The support structure 20 is similar to Figure 2 The illustration in - is coated with at least one conductive material relative to the projection direction 100. The coating is formed - also similar to Figure 2 - electrically conductive structures 10a, 10b, 10c and additional electrically conductive structures 11a, 11b which are insulated from one another. Figure 2 In contrast to the illustration, the additional conductive structures 11a, 11b and the exposed areas 30a, 30b, 30c, 30d are here on the surface of the substrate 40, rather than (or not entirely; not shown here) on the surface of the first sub-area 120 of the support structure 20 produced by the free-form microstructuring process.

[0088] Figure 5A further exemplary embodiment of an electrical wiring arrangement according to the invention is shown in a schematic cross-sectional view, wherein an isotropic coating with an inert protective material 26 is applied to a support structure 20, forming the conductive structures 10a, 10b, 10c and the additional conductive structures 11a, 11b of the electrical wiring structure 1. In this case, similar to Figure 1 and Figure 2 The process described in the Figure 5 The wiring arrangement is shown as an example in the diagram. Figure 5 In the embodiment shown, the two sub-areas 120, 220 are identical and form the support structure 20. After production, the inert protective material 26 can be applied by an isotropic process, in which all sides of the structure are coated. The inert protective material 26 can be designed, for example, to prevent oxidation of the metal areas 10a, 10b, 10c, 11a, 11b.

[0089] Figure 6 A cross section of another electrical wiring arrangement according to the invention which can be produced using the method is schematically shown. Figure 6 In the embodiment shown, the two sub-areas 120, 220 are identical and form the support structure 20. Figure 6 The electrical circuit structure 1 forms a coplanar circuit and includes three conductive structures 10a, 10b, 10c, which are electrically insulated from one another in all cross-sectional planes along the circuit structure 1. In this case, the two conductive structures 10a, 10c can be at the same potential, for example in a so-called "ground-signal-ground" configuration. In order to prevent any short circuits between the generated conductive structures 10a, 10b, 10c and further conductive structures 11a, 11b, the recesses introduced into the support structure 20 between the areas to be coated, also during the directional coating of the surface of the support structure 20 in the projection direction 100, are provided with undercuts 20a, 20b, 20c, 20d, which are designed to provide exposed areas 30a, 30b, 30c, 30d for insulation purposes. The undercuts 20a, 20b, 20c, 20d in the support structure 20 in this exemplary embodiment are designed to be deep enough so that the signals routed in the desired electrical line structure 1 (which includes the conductive structures 10a, 10b, 10c) are not affected by the conductive structures 11a, 11b that are still inevitably present on the support structure 20. This refers to the field lines of the electric field 80 at Figure 6 , which process is not adversely affected by further conductive structures 11a, 11b, in particular due to sufficient spacing. Therefore, the additional conductive structures 11a, 11b produced as "by-products" in this exemplary embodiment can remain in their position on the surface of the support structure 20 (or optionally on the surface of the substrate 40; not shown here) and do not need to be removed.

[0090] Figure 7 A cross section of another electrical wiring arrangement according to the invention which can also be produced using the method is shown schematically. Figure 7 In the embodiment shown, the two sub-regions 120, 220 are identical and form the support structure 20. In this case, the electrical line structure 1 is designed in the form of an electrical line coupler. The electrical line structure 1 in the form of an electrical line coupler comprises three conductive structures 10a, 10b, 10c, wherein the two conductive structures 10a, 10c are electrically insulated from one another in all cross-sections along the line structure 1 and are at different electrical potentials. The distance between the two conductive structures 10a, 10c is selected so that the cross-coupling of the electric field 80 from one conductive structure 10a to the other conductive structure 10c (or vice versa) can be adjusted via the third conductive structure 10b located in the cutout of the support structure 20, as shown. Figure 7 Schematically shown. In this case, the width of the third conductive structure 10b is determined by using undercuts 20b, 20c inserted into the support structure 100 (these undercuts 20b, 20c are designed as shielding structures relative to the projection direction 20) and exposed areas 30b, 30c defined by these shielding structures. This embodiment is particularly advantageous in the case of strong cross-coupling, since a small distance between the two conductive structures 10a, 10c is required, which is more difficult to produce using a planar lithography process with limited lateral resolution. By using a third conductive structure 10b that can be produced by coating a conductive material, the strength of the cross-coupling can be increased while maintaining a constant distance. By inserting additional undercuts 20a, 20d in the support structure 20, the other conductive structures 11a, 11b produced as "by-products" on the two outer sides of the support structure 20 can be prevented from having a negative influence on the electrical wiring structure 1. These two undercuts 20a, 20d are larger than those according to Figure 7 The undercuts 20 b and 20 c in the exemplary embodiment of FIG. 3 are deeper, which is why the distance between the further conductive structures 11 a and 11 b determined based on the defined exposed areas 30 a and 30 d and the conductive structures 10 a and 10 c of the electrical wiring structure 1 is greater. Consequently, cross-coupling of the electric field 80 from the electrical wiring structure 1 to the further conductive structures 11 a and 11 b can be prevented.

[0091] Figure 8 A cross section of another electrical wiring arrangement according to the invention which can also be produced using the method is shown schematically. Figure 8In the embodiment shown, the two sub-regions 120, 220 are identical and form the support structure 20. In this case, the electrical circuit structure 1 is designed in the form of an electrical interdigital capacitor. The electrical circuit structure 1 in the form of an interdigital capacitor comprises, for example, seven conductive structures 10a, 10b, 10c, 10d, 10e, 10f, 10g, which are arranged essentially alternately in two different parallel planes 35, 36, which can be at different electrical potentials. For example, four conductive structures 10a, 10c, 10e, 10g lie in a common first plane 35 defined by the grooves of the support structure 20, while the remaining three conductive structures 10b, 10d, 10f lie in a second plane 36 defined by the webs between the grooves. To produce the electrical wiring arrangement 1, undercuts 20a, 20b, 20c, 20d, 20e, 20f are introduced into the support structure 20 relative to the projection direction 100. By using exposed areas 30a, 30b, 30c, 30d, 30e, 30f, this ensures electrical insulation of the conductive structures 10a, 10b, 10c, 10d, 10e, 10f, 10g applied on two different planes 35, 36. In this case, the evaporation beam emitted by the evaporation source exhibits a divergence 105 about the defined projection direction 100 at the location of the support structure 20 to be coated. This means that the strip-shaped conductive structures 10a, 10c, 10e, 10g produced in the first plane 35 have an increased width, so that, when projected along the projection direction 100, they overlap with the conductive structures 10b, 10d, 10f located in the second plane 36. This can particularly contribute to increasing the capacitance between the structures on the two planes 35, 36. The conductive structures 10a, 10c, 10e, 10g and / or 10b, 10d, 10f located in the common planes 35, 36 may be electrically connected to each other in another cross section of the electrical line structure 1, thereby forming a common power supply line.

[0092] Figure 9 An exemplary embodiment of an electrical wiring arrangement according to the invention is shown in the form of a schematic cross-sectional view, wherein a support structure 20 comprises a substrate 40 comprising an upper electrically conductive sub-region 320 and a lower electrically insulating second sub-region 220. The first sub-region 120 of the support structure 20 is produced from an electrically insulating material using a free-form microstructuring process. In this case, the electrically insulating second sub-region 220 of the support structure 20 consists of a plurality of elements and comprises the lower second sub-region 220 of the substrate 40 and all the first sub-regions 120 of the support structure 20, which are produced using a free-form microstructuring process. The support structure 20-similar Figure 4 - coating at least one conductive material relative to the projection direction 100. Coating formation - also similar to Figure 4 - electrically conductive structures 10a, 10b, 10c and additional electrically conductive structures 11a, 11b which are insulated from one another. Figure 4 In contrast to the illustration of FIG, a further first subregion 120 of the support structure 20 can be produced on the substrate 40 using a free-form microstructuring process in such a way that, during coating, a path 15 is produced between at least one of the conductive structures 10a, 10c and at least one further conductive structure present in the arrangement using the conductive subregion 320 of the substrate 40. This can be achieved, for example, by corresponding ramp structures in the first subregion 120 produced using the free-form microstructuring process.

[0093] Figure 10 An exemplary embodiment of an electrical line arrangement according to the invention is shown in the form of a schematic cross-sectional view, wherein a support structure 20 comprises a conductive or insulating substrate 40, a first sub-region 120 applied thereto and produced by a free-form microstructuring process, and an insulating coating 25 substantially uniformly surrounding the substrate 40 and the first sub-region 120, wherein the insulating coating 25 forms an insulating second sub-region 220 of the support structure 20 and is applied, for example, by an isotropic coating process. In this case, the two sub-regions 120, 220 are therefore disjoint, i.e., do not intersect. The support structure 20 shown then—similar to Figure 2 - At least one conductive material may be applied along the projection direction 100 to form an electrical circuit structure 1 consisting of a conductive structure 10a. Figure 2 In contrast to the illustration of , here the additional electrically conductive structures 11 a , 11 b and the exposed areas 30 a , 30 b are on the surface of the insulating coating 25 and not on the surface of the first sub-area 120 of the support structure 20 produced by the free-form microstructuring process.

[0094] In a specific embodiment (not shown here), Figure 2 、 4The conductive structures 10a, 10b, 10c, etc. and the additional conductive structures 11a, 11b, etc. of the electrical circuit structure 1 schematically shown in Figures 5, 6, 7, 8, 9, and 10 can vary in cross-section and / or follow a non-planar trajectory along the propagation direction of the electromagnetic signal (in this case, running approximately perpendicular to the respective drawing plane). This non-planar trajectory can be predetermined by the corresponding non-planar shape of the support structure 20, wherein the use of the free-form microstructuring process according to the present invention opens up new implementation options. In another embodiment, the substrate 40 contained in the support structure 20 can also have a non-planar shape that defines or significantly influences the trajectory of the line profile. In addition, for example, the cross-section of the electrical circuit structure 1 can vary along the propagation direction of the electromagnetic wave. This allows for locally matched line impedances according to different cross-sections, or for the creation of two-end matched line transitions 60a, 61a in the electrical connection element. Alternatively, certain components, in particular components having capacitive, resistive, or inductive effects, can be generated, which are defined by the corresponding shape of the electrical circuit structure 1.

[0095] Figures 11 to 14 Schematically illustrated is a process sequence for producing an additional electrical wiring arrangement according to the invention embodied as a non-planar electrical connection element between two separate substrates 40 , 41 according to the herein described manufacturing method using additional shielding structures 70 , 71 .

[0096] Figure 11 The schematic diagram shows an initial situation in which two insulating substrates 40 and 41 are approximately aligned with one another. Each of the two substrates 40 and 41 includes an existing line structure 50a, 50b, 50c; 51a, 51b, 51c, which are described here as conventional coplanar lines, for example, wherein the line structure has been previously produced using the methods described herein and / or using conventional manufacturing methods. The coplanar lines each include three conductive structures that are electrically isolated from one another in all cross-sections along the line structure, wherein the two existing conductive structures 50a, 50c; 51a, 51c each have the same electrical potential.

[0097] Figure 12 A first method step is schematically shown, according to which the first subregion 120 of the support structure 20 is produced from an electrically insulating material using a free-form microstructuring process. In this embodiment, the first subregion 120 of the support structure 20 forms a connection between conventional coplanar lines and thereby bridges at least one possible gap between the two substrates 40, 41.

[0098] By using the free-form microstructuring process according to the present invention, Figures 11 to 14In the illustrated configuration, it is particularly possible to adapt the geometry of the first subregion 120 of the support structure 20 to the positioning of the two substrates 40, 41, which is not always precisely controllable. Thus, it is particularly possible to initially mount these substrates 40, 41 using an inexpensive method with relatively large positioning tolerances, then record the exact positions of the ends of the existing line structures 50a, 50b, 50c; 51a, 51b, 51c to be connected, and design the first subregion 120 of the support structure 20 to be produced using a free-form microstructuring process based on this information. The first subregion 120, adapted to the position of the line ends to be connected, can then be implemented on the substrates 40, 41 with high precision, allowing for precisely defined (e.g., broadband and / or low-loss) electrical line transitions 60a, 60b, 60c; 61a, 61b, 61c) between the existing line structures 50a, 50b, 50c; 51a, 51b, 51c. To precisely record the positions of the ends of existing line structures 50a, 50b, 50c; 51a, 51b, 51c to be connected, and to precisely align first subregion 120 adapted to the position of the line ends to be connected on substrates 40, 41, the apparatus for implementing the freeform microstructuring process can be equipped with additional image acquisition functions that, for example, allow for the precise detection of markings or structural elements on substrates 40, 41. In the case of two-photon lithography, these functions can be based on, for example, camera-based 2D or 3D imaging methods or scanning methods, such as those based on confocal microscopy principles. The accuracy with which structures can be detected on substrates 40, 41 and the corresponding first subregion 120 can be placed on substrates 40, 41 is preferably better than 100 μm, particularly preferably better than 10 μm, and even more preferably better than 1 μm, 300 nm, or 100 nm.

[0099] In order to prevent the support structure 20 from Figure 13 During the coating of the conductive material in the projection direction 100 shown, a short circuit is generated between the resulting conductive structures 10a, 10b, 10c; 11a, 11b, 11c, 11d, 11e, 11f by using suitable undercuts 20a, 20b, 20c, 20d, 20e, 20f to produce corresponding exposed areas 30a, 30b, 30c, 30d, 30e, 30f between these structures. The undercuts 20a, 20b, 20c, 20d, 20e, 20f are designed to be deep enough in the cross section of the electrical line structure 1 so that - similar to Figure 6 The electrically conductive structures 10a, 10b, 10c in the illustration are not affected by the electrically conductive structures 11a, 11b, 11c, 11d, 11e, 11f produced as “by-products” or are only insignificantly or locally affected in a desired manner.

[0100] In order to further prevent the coating from also causing a short circuit between the existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c, additional shielding structures 70, 71 are used in the form of a plurality of protruding arms. The additional shielding structures 70, 71 are aligned with the transition between the existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c and the electrical conductor structure 1 in such a way that during the coating process in a defined projection direction 100, no connection is created between the existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c in any cross section along the conductor structure 1.

[0101] The additional shielding structures 70, 71 can preferably be produced together with the first sub-region 120 of the support structure 20 using the same free-form microstructuring process as in method step a). Due to the coating in the projection direction 100 in method b), e.g. Figure 13 and 14 As shown schematically, first electrical line transitions 60a, 60b, 60c are formed between the conductive structures 50a, 50b, 50c already present on the first substrate 40 and the conductive structures 10a, 10b, 10c of the electrical line structure 1, and additional electrical line transitions 61a, 61b, 61c are formed between the conductive structures 51a, 51b, 51c already present on the additional substrate 41 and the conductive structures 10a, 10b, 10c of the electrical line structure 1. Additional conductive structures 11a, 11b, 11c, 11d, 11e, 11f are also formed as "by-products" on the substrates 40, 41 of the support structure 20, which do not affect the electrical line structure 1, or only affect it insignificantly or in a precisely known manner that can be taken into account during implementation.

[0102] Figure 14 The schematic diagram shows the completed electrical wiring arrangement after previously removing the additional shielding structures 70, 71. The additional shielding structures 70, 71 can preferably be removed by simply peeling them off using a pair of tweezers or by the lifting process already mentioned above. In addition to the additional shielding structures 70, 71 described above, the two substrates 40, 41 can be provided with at least a corresponding temporary or permanent protective layer 75 (not shown here) to prevent undesired coating of the substrate surface or corresponding sub-areas during the coating process in method step b). These protective layers can be produced, for example, by suitable photolithographic, printing, or dispensing methods and removed again using a suitable solvent after carrying out method step b).

[0103] Figure 15A further exemplary embodiment of an electrical conductor arrangement according to the present invention, here embodied in the form of a non-planar dipole antenna, is schematically shown. The electrical conductor arrangement comprises an insulating substrate 40, which includes a conventionally manufactured coplanar conductor consisting of three existing conductive structures 50a, 50b, and 50c, two of which can be at the same electrical potential. In this embodiment, the electrical conductor structure 1 initially comprises three separate conductive structures 10a, 10b, and 10c, which are electrically insulated from one another in cross section. These structures change their respective geometries in a defined manner along the conductor structure 1 and, in particular, are also electrically connected in at least one further cross section of the electrical conductor structure 1.

[0104] Method step a) comprises Figure 15 Production of the first sub-region 120 of the support structure 20 produced from an electrically insulating material by a free-form microstructuring process. In order to be able to coat the surface at an angle of 90° to the surface of the substrate 40, the projection direction 100 is set here at an angle of, for example, 45° to the surface of the substrate 40. Figure 15 In the region of the slope structure shown, the side walls of the grooves between the structures to be coated and the outer walls of the first subregion 120 of the support structure 20 are provided with undercuts 20a, 20b, 20c, 20d, 20e, 20f, which are designed to produce exposed areas 30a, 30b, 30c, 30d, 30e, 30f along the slope structure. The undercuts 20a, 20b, 20c, 20d, 20e, 20f are designed to be deep enough so that the electrical line structure 1 (which includes the conductive structures 10a, 10b, 10c) - similar to Figure 6 The illustration in FIG is not affected by the conductive structures 11 a, 11 b, 11 c produced as “by-products”, or is affected only insignificantly or in a known manner that must be taken into account during implementation. The further undercuts 20 g, 20 h introduced by the foot and flanks of the first sub-region 120 of the support structure 20 produced by the free-form microstructuring process are designed to produce exposed areas 30 g, 30 h, which provide electrical insulation of the conductive structures 10 a, 10 b, 10 c, which consist of the electrical line structure 1 from the substrate 40, and / or the conductive structures 11 c formed on the substrate 40 as “by-products”.

[0105] By applying a conductive material to support structure 20 in projection direction 100, electrical line transitions 60a, 60b, 60c are formed between existing conductive structures 50a, 50b, 50c on substrate 40 and conductive structures 10a, 10b, 10c of electrical line structure 1. Conductive structures 10a, 10b, 10c are insulated from one another in the exemplary cross-section A (a cross-section in the (x,z) plane) and routed upward via a ramp structure. In at least another exemplary cross-section B (a cross-section in the (x,z) plane), two outer conductive structures 10a, 10c are centrally combined with a middle conductive structure 10b configured as a signal conductor, thereby forming a dipole antenna. If designed correctly, this effectively matches the line impedance of electrical line structure 1 to the wave impedance of free space, resulting in radiation from the dipole antenna, so that a possible increase in the permittivity of substrate 40 does not pose a problem.

[0106] Also in this exemplary embodiment, similar to Figure 12 and 13 In the arrangement shown, an additional shielding structure 70 (not shown here) can be used to electrically connect the conductive structures 10a, 10b, 10c to the existing conductive structures 50a, 50b, 50c without creating a short circuit between the conductive structures 10a, 10b, 10c or the existing conductive structures 50a, 50b, 50c and the substrate 40 and / or the conductive structures 11a, 11b, 11c formed on the substrate 40 as a "by-product".

[0107] Figure 16 A further exemplary embodiment of an electrical wiring arrangement according to the invention is schematically shown, which here is embodied in the form of an electrical probe tip which may be particularly suitable for contacting RF circuits. Figure 16 The production of the electrical wiring arrangement schematically shown in FIG. 1 can preferably be similar to that according to Figures 11 to 14 Method steps and Figure 15 The electrical wiring arrangement is shown. Therefore, for further details, see Figures 11 to 15 Description.

[0108] exist Figure 16 In FIG. 1 , the projection direction 100 is set at an angle of 90° to the surface of the insulating substrate 40. By applying a conductive material to the support structure 20 along the projection direction 100, electrical line transitions 60a, 60b, 60c are formed between the conductive structures 50a, 50b, 50c already present on the substrate 40 and the conductive structures 10a, 10b, 10c of the electrical line structure 1. The conductive structures 10a, 10b, 10c (which remain insulated in all cross sections along the line structure 1) are also connected here by Figure 16The schematically shown ramp structures are routed upwards and meet at a specified distance to form three contact elements 500. The production of the first sub-region 120 according to the invention with the aid of a free-form microstructuring process again allows a very precise alignment of the structures already present on the substrate 40 (see Figures 11 to 15 ), and a very dimensionally accurate production of an electrical line structure 1 with flexibly adjustable electrical parameters, such as the impedance of the line arrangement and the impedance of the transition to another test substrate (not shown) defined by the contact elements 500.

[0109] Figure 16 The structure shown also includes contact elements 500, which are produced by appropriate shaping of the support structure 20 to be coated and with which geometrically precise contact can be made with corresponding contact surfaces on the chip or the planar substrate. Figure 16 In the embodiment shown, the contact element 500 is based on a structural element protruding in a direction perpendicular to the coating surface, which structural element in this depiction takes the form of a truncated pyramid. Other geometric configurations of the contact element 500 are also conceivable.

[0110] Furthermore, in this exemplary embodiment, Figure 12 and 13 As shown, an additional shielding structure 70 (not shown) can be used to electrically connect the conductive structures 10a, 10b, 10c to the existing conductive structures 50a, 50b, 50c in all cross sections along the line structure 1 without creating a short circuit between the conductive structures 10a, 10b, 10c or the existing conductive structures 50a, 50b, 50c and the substrate 40 and / or the conductive structures 11a, 11b, 11c, 11d formed on the substrate 40 as a "by-product".

[0111] In this case, the support structure 20 can be designed in particular so that the three contact elements 500—such as Figure 16 As shown - protrudes to the right beyond the edge of the substrate 40 and thus remains visible for contacting even in a rotated arrangement of the electrical line structure 1, wherein the contact element 500 points downward and the camera image taken from above is used for positioning. The various options for designing the first subregion 120 of the support structure 20 produced by the free-form microstructuring process also allow the generation of a mechanical protection structure 600 by using the free-form microstructuring process according to method step a) or by using a different free-form microstructuring process, thereby preventing undesirable mechanical damage to the electrical probe tip, for example due to a collision or misalignment when placed on the underlying test substrate. As Figure 16As shown, the mechanical protection structure 600 can be designed as a solid protection structure 600, which prevents the electrical probe tip from undesirably approaching objects that could damage the probe tip. Alternatively or additionally, the protection structure 600 can be designed such that the approach of the electrical probe tip or the contact element 500 to an object that could damage them (e.g., the substrate 41) results in a significant elastic or partially elastic deformation of the protection structure 600 or parts thereof, see Figure 17 For this purpose, a dedicated monitoring structure 2000 with an indicator structure 2200 can be used to convert an approach 2300 of the electrical probe tip to a potentially destructive object substantially along the viewing direction 2100 into a visually detectable deformation 2400 of the monitoring structure 2000 lateral to the viewing direction 2100. In a preferred embodiment, the monitoring structure 2000 or parts thereof can be produced jointly with the first subregion 120 of the support structure 20 by a free-form microstructuring process.

[0112] exist Figure 18 According to the invention, a method for producing another electrical wiring arrangement is provided. Figures 11 to 14 Another exemplary embodiment of the method sequence is shown in the form of a microscope image. For further details, please refer to Figures 11 to 14 The above description.

[0113] Figure 18 (a) shows an additional electrical circuit arrangement according to the invention, comprising two substrates 40, 41, each having an existing electrical circuit structure with existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c, wherein both conductive structures of the two existing conductive structures 50a, 50c; 51a, 51c each have the same electrical potential. In each case, in the second sub-region 220, the substrates 40, 41 comprise - similar to Figure 9 The structure depicted is an insulating support made of aluminum oxide (Al2O3) with a layer thickness of 625 μm and a conductive region 320 produced on the insulating support using a gold layer with a layer thickness of 3 μm. The existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c are produced by structuring this gold layer, for example using conventional photolithographic processes or laser ablation processes.

[0114] The existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c are then connected in an electrically conductive manner to their respective counterparts. Figure 18(b) shows a first subregion 120 of the support structure 20 produced from an insulating material using a two-photon lithography process. In this embodiment, the electrically insulating second subregion 220 of the support structure 20 comprises the lower second subregion 220 of the substrate 40, 41 and the first subregion 120 of the support structure 20 produced using a free-form microstructuring process. Due to limitations on the write field size, the electrical wiring arrangement is divided into multiple segments and manufactured in multiple steps.

[0115] To avoid Figure 18 In (c), a short circuit is produced between the conductive structures 10a, 10b, 10c; 11a, 11b, 11c, 11d, 11e, 11f obtained by coating the support structure with a conductive material (using a PVD process at a 90° angle to the surface of the substrate 40, 41 along the projection direction 100), and the first sub-region 120 of the support structure 20 has a narrow groove, and undercuts 20a, 20b, 20c, 20d, 20e, 20f are formed in its side walls, which are designed to produce exposed areas 30a, 30b, 30c, 30d, 30e, 30f. The undercuts 20a, 20b, 20c, 20d, 20e, 20f are designed to be deep enough so that the electrical circuit structure 1 (which includes the conductive structures 10a, 10b, 10c) - similar to Figure 6 The illustration in - is either not affected by the electrically conductive structures 11a, 11b, 11c, 11d, 11e, 11f produced as "by-products" or is affected only insignificantly or in a known manner which has to be taken into account in the implementation.

[0116] Due to the coating in the projection direction 100, on the one hand Figure 18 (b) shows a first electrical circuit transition 60a, 60b, 60c formed between the conductive structures 50a, 50b, 50c already existing on the substrate 40 on the left and the conductive structures 10a, 10b, 10c produced according to the present invention of the electrical circuit structure 1. Figure 18 Additional electrical line transitions 61a, 61b, 61c are formed between the additional conductive structures 51a, 51b, 51c present on the right-hand substrate 41 (shown in (b)) and the conductive structures 10a, 10b, 10c of the electrical line structure 1. Consequently, the coating produced on the support structure 20 has a total layer thickness of approximately 600 nm in the projection direction 100 and primarily comprises a copper layer due to its high electrical conductivity. A thin layer of titanium serves as an adhesion promoter between the support structure 20 and the copper layer; a thin layer of gold is also applied as an outer layer to prevent environmental passivation. To prevent gold diffusion from the gold layer into the copper layer, another thin layer of titanium can be inserted between the copper and gold layers.

[0117] However, in order to prevent the existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c from also short-circuiting themselves and with the respectively adjacent substrate 40, 41, additional shielding structures 70, 71 in the form of a plurality of protruding arms are used, which are preferably previously produced using the same two-photon lithography process as the first sub-region 120 of the support structure 20. The additional shielding structures 70, 71 are aligned with the electrical line transitions 60a, 60b, 60c; 61a, 61b, 61c between the existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c and the electrical line structure 1, so that during coating in a defined projection direction 100, no conductive connections can occur between the existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c or to the substrates 40, 41. The conductive structures 11a, 11b, 11c, 11d, 11e, 11f formed as "byproducts" are also electrically insulating. For this purpose, the shadow effect cast by the additional shielding structures 70, 71 on the respective electrical line transitions 60a, 60b, 60c; 61a, 61b, 61c in the projection direction 100 is exploited. In this way, Figure 18 The three-dimensional electrical connection element shown can be produced between coplanar lines already present on the two substrates 40 , 41 , wherein the individual conductive structures 10 a , 10 b , 10 c remain electrically insulated from one another in all cross sections along the line structure 1 .

[0118] Due to the limited writing field size of the printing process, according to Figure 18 The additional shielding structures 70, 71 in the exemplary embodiment are only designed to protect the direct environment of the electrical line transitions 60a, 60b, 60c; 61a, 61b, 61c, which is why a protective layer 75 of PMMA (polymethyl methacrylate) covers the existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c on the remaining surface of the substrate 40, 41. In this exemplary embodiment, the protective layer 75 is applied by using an inkjet printing process. Figure 18 In (b) the left side of the additional shielding structure 70 on the left substrate 40 and the right side of the shielding structure 71 on the right substrate 41 can be seen. In principle, further methods are conceivable that allow large areas of the substrates 40, 41 to be covered with sufficient precision, such as photolithography, dispensing or simple covering with an adhesive film. Figure 18 (c) During the coating process, the protective layer is further covered with a metal layer. By dissolving PMMA with PGMEA (propylene glycol monomethyl acetate), the metal layer can be separated from the surface previously covered by the PMMA layer during the stripping process, thus - Figure 18 (d) shows that the existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c remain electrically isolated.

[0119] In principle, as described above, it is conceivable and desirable to perform the entire covering of the substrates 40, 41 using the same free-form microstructuring process that is also used to produce the first sub-region 120 of the support structure 20 and the additional shielding structures 70, 71, as long as the chosen free-form microstructuring process allows this. Due to the write field limitations of the two-photon lithography process used here, a complete covering of the substrates 40, 41 would take too long in practice due to the large surface area of ​​the substrates 40, 41, which is why the printing and lift-off process described here is used instead. The conductive structures 11c, 11d, 11e, 11f formed as "by-products" usually remain on the substrates 40, 41 without affecting the line structure 1, but as Figure 18 A comparison of (c) and 18(d) shows that it can preferably be removed by peeling it off using tweezers.

[0120] Figure 18 (e) and 18 (f) schematically show the completed electrical wiring arrangement after the additional shielding structures 70, 71 are removed in advance. During the coating process, the shadows produced by the additional shielding structures 70, 71 on the support structure 20 are Figure 18 In (e), this is clearly visible in the form of dark areas at the electrical line transitions 60a, 60b, 60c; 61a, 61b, 61c.

[0121] Figure 19 Microscope image showing the basis of a non-planar dipole antenna Figure 15 Another exemplary embodiment of the electrical wiring arrangement according to the present invention. For further details, refer to Figure 15 Description.

[0122] Figure 19 An electrical circuit arrangement comprising a substrate 40 is shown, which comprises a conventionally manufactured coplanar circuit consisting of three existing conductive structures 50a, 50b, 50c, wherein two existing conductive structures 50a, 50c can be at the same electrical potential. In each case, the substrate 40 comprises - similar to Figure 9The structure depicted is an insulating support made of aluminum oxide (Al2O3) with a layer thickness of 625 μm and a conductive area 320, which is produced on the insulating support by using a gold layer with a layer thickness of 3 μm. The existing conductive structures 50a, 50b, 50c are produced by structuring this gold layer, for example by using conventional photolithography processes or laser ablation processes. In order to produce a non-planar dipole antenna at a fixed distance from the substrate 40, here too, a first sub-area 120 of the carrier structure 20 is produced by using a two-photon photolithography process and then coated with conductive material using a PVD process. Due to the limitations of the write field size, the electrical circuit arrangement is divided into multiple segments and manufactured in multiple steps. Since the support structure 20 in this exemplary embodiment also has a surface at a 90° angle to the surface of the substrate 40, coating at this angle is not practical here in order to produce the required distance of the non-planar dipole antenna from the substrate 40. Therefore, the coating is not as good as in the example Figure 15 The projection direction 100 shown is applied at an angle of, for example, 45° to the surface of the substrate 40. The side walls of the slits introduced into the support structure 20 between the surfaces to be coated are similar to those according to Figure 18 Here, the undercuts 20a, 20b, 20c, 20d are also designed to be deep enough so that the electrical circuit structure 1 (including the conductive structures 10a, 10b, 10c) is similar to Figure 6 The illustration in FIG is not affected by the conductive structures 11a, 11b, 11c produced as "by-products," or is affected only insignificantly or in a known manner that must be taken into account during implementation. The coating on the support structure 20, which is mostly implemented as a copper layer or consists of a suitable sequence of different materials, also has a total layer thickness of approximately 600 nm in the projection direction 100. A thin titanium layer serves as an adhesion promoter between the support structure 20 and the copper layer; a thin gold layer is applied as an outer layer for passivation relative to the environment, wherein another thin titanium layer can also be inserted between the copper and gold layers.

[0123] from Figure 19As can be seen in (c), further undercuts 20e, 20f, 20g, 20h introduced at the foot and flanks of the support structure 20 are also designed here to produce exposed areas 30e, 30f, 30g, 30h, which electrically insulate the conductive structures 10a, 10b, 10c formed by the electrical circuit structure 1 from the substrate 40. By coating the support structure 20 with an electrically conductive material in the projection direction 100, electrical circuit transitions 60a, 60b, 60c are formed between the conductive structures 50a, 50b, 50c already present on the substrate 40 and the conductive structures 10a, 10b, 10c of the electrical circuit structure 1. Conductive structures 10a, 10b, and 10c are also routed upward via a ramp structure. Initially, conductive structures 10a, 10b, and 10c remain insulated from one another across all cross-sections along line structure 1. At the apex of the ramp, two outer conductive structures 10a and 10c are slotted and then converged with a central conductive structure 10b, which is designed as a signal conductor within the cross-section, to form a dipole antenna. Proper design effectively matches the line impedance of electrical line structure 1 to the wave impedance of free space, thereby enabling efficient radiation from the resulting dipole antenna.

[0124] Furthermore, in this exemplary embodiment, additional shielding structures 70, 71 are used to achieve electrical connection of the conductive structures 10a, 10b, 10c of the electrical circuit structure 1 with the existing conductive structures 50a, 50b, 50c without creating a short circuit between the conductive structures 10a, 10b, 10c or the existing conductive structures 50a, 50b, 50c and the substrate 40 and / or the conductive structures 11a, 11b, 11c formed on the substrate 40 as a "by-product".

[0125] Figure 19 (c) schematically shows a substrate 40 with three dipole antennas after removing the additional shielding structures 70 and 71. In order to protect the existing conductive structures 50a, 50b, 50c, the entire surface of the substrate 40 is short-circuited. Figure 18 As shown in the exemplary embodiment of , a protective layer 75 made of PMMA is also used here, which is removed again with PGMEA during the stripping process.

[0126] Figure 20 The microscope image shows that Figure 16 The electrical wiring arrangement according to the present invention is another exemplary embodiment of an electrical probe tip, in particular for contacting an RF circuit. For further details, see Figure 16 Description.

[0127] Figure 20An electrical circuit arrangement comprising a substrate 40 is shown, comprising a conventionally manufactured coplanar circuit consisting of three existing conductive structures 50a, 50b, 50c, wherein two existing conductive structures 50a, 50c may be at the same electrical potential. In each case in the second sub-region 220, the substrate 40 comprises - similar to Figure 9 The structure depicted consists of an insulating support made of aluminum oxide (Al2O3) with a layer thickness of 625 μm and a conductive region 320 produced on the insulating support by using a gold layer with a layer thickness of 3 μm. The existing conductive structures 50a, 50b, 50c are produced by structuring this gold layer, for example using conventional photolithography processes or laser ablation processes. In order to produce the electrical probe tip, the first subregion 120 of the carrier structure 20 is also structured here using a two-photon photolithography process. Subsequently, the conductive region 320 is formed by using a PVD process along a 90° angle to the surface of the substrate 40, as shown in FIG. Figure 16 The conductive material is applied to the support structure 20 in the projection direction 100 shown. The side walls of the slits introduced into the support structure 20 between the surfaces to be coated are similar to those according to Figure 18 and 19 Here, the undercuts 20a, 20b, 20c, 20d, 20e, 20f are also designed to be deep enough so that the electrical line structure 1 (which includes the conductive structures 10a, 10b, 10c) is either not affected by the conductive structures 11a, 11b, 11c, 11d generated as "by-products" - similar to Figure 6 The illustration in FIG is either only insignificantly affected or affected in a known manner that must be taken into account during implementation. The coating on the support structure 20, which is mostly implemented as a copper layer, also has a total layer thickness of approximately 600 nm in the projection direction 100. A thin titanium layer serves as an adhesion promoter between the support structure 20 and the copper layer; a thin gold layer is applied as an outer layer for passivation relative to the environment, wherein another thin titanium layer can also be inserted between the copper and gold layers.

[0128] By coating the support structure 20 with a conductive material in the projection direction 100, electrical line transitions 60a, 60b, 60c are formed between the conductive structures 50a, 50b, 50c already present on the substrate 40 and the conductive structures 10a, 10b, 10c of the electrical line structure 1. The conductive structures 10a, 10b, 10c (which remain insulated in all cross-sectional planes along the line structure 1) are also routed upward via a ramp structure and converge at a specified distance to form a contact element 500. In this case, the contact element 500 is a pyramidal frustum-shaped structure.

[0129] Furthermore, in this exemplary embodiment, the additional shielding structure 70 is used to electrically connect the conductive structures 10a, 10b, 10c of the electrical wiring structure 1 to the existing conductive structures 50a, 50b, 50c, without generating a short circuit between the conductive structures 10a, 10b, 10c or the existing conductive structures 50a, 50b, 50c and the substrate 40 and / or the conductive structures 11a, 11b, 11c, 11d formed as a "by-product" on the substrate 40. In order to prevent the existing conductive structures 50a, 50b, 50c from short-circuiting over the entire surface of the substrate 40, as shown in FIG. Figure 18 and 19 As shown in the exemplary embodiment of - here also a protective layer 75 made of PMMA is used, which is removed with PGMEA during the stripping process.

[0130] In addition to the exemplary embodiment shown, other embodiments are possible. The use of lithographic processes with a significantly larger writing field, while still having a sufficiently high lateral resolution in the micrometer range, such as projection microstereolithography (PμSL), allows the substrate surface 40 to be completely covered as a protective layer during coating and eliminates the complex stripping processes previously used with PMMA and PGMEA. In the same lithographic step, large-area protective structures can be produced directly together with the support structure 20 and the additional shielding structure 70 - according to Figure 12 A considerable amount of time can be saved and the method greatly simplified, and by eliminating the need to apply chemicals to the substrate 40 and the support structure 20 (particularly to the first sub-region 120 ), sensitive components can be extensively protected, thereby allowing greater freedom in the choice of the material of the support structure 20 .

[0131] Reference Signs List

[0132]

[0133]

Claims

1. A method for producing an electrical wiring arrangement, comprising the following steps: a) producing a support structure (20), wherein at least one first subregion (120) of the support structure (20) is produced by using a free-form microstructuring method, wherein at least one second subregion (220) of the support structure (20) comprises an electrically insulating material, and wherein the support structure (20) has at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) relative to the projection direction (100); and b) producing at least one electrical line structure (1) by coating at least one electrically conductive material on a support structure (20), wherein the coating comprises at least one spatially oriented coating process which is oriented in alignment with at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) in a projection direction (100).

2. The method according to the preceding claim, wherein the coating of the support structure (20) comprises at least one spatially directed coating process using at least two electrically conductive materials that are different from each other.

3. The method according to any of the preceding claims, wherein the thickness of at least one electrical line structure (1) comprising an electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) is increased by electrogrowth.

4. The method according to claim 1 , wherein the at least one electrical line structure ( 1 ) is produced in such a way that at least one electrically conductive structure ( 10 a , 10 b , 10 c , 10 d , 10 e , 10 f , 10 g ) is formed by using at least one exposed area ( 30 a , 30 b , 30 c , 30 e ) generated by at least one undercut ( 20 a , 20 b , 20 c , 20 d , 20 e , 20 f , 20 g , 20 h ). 30d, 30e, 30f, 30g, 30h) are electrically insulated relative to the additional conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g), and the additional conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) is adjacent to at least one conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) within the cross section of the at least one electrical line structure (1).

5. The method according to any of the preceding claims, wherein the support structure (20) comprises a substrate (40, 41).

6. The method according to any of the preceding claims, wherein the production of the at least one electrical wiring structure (1) is selected from the group consisting of: - a microstrip line comprising the production of a single structure (10a) which is electrically conductive in all cross sections along at least one electrical line structure (1); - a slotted line comprising the production of two electrically conductive structures (10a, 10b) electrically insulated from one another in all cross sections along at least one electrical line structure (1); - a coplanar line comprising the production of three electrically conductive structures (10a, 10b, 10c) electrically insulated from one another in all cross sections along at least one electrical line structure (1); - an antenna comprising the production of at least one conductive structure (10a), interacting with at least one exposed area (30a, 30b, 30c, 30d, 30e, 30f, 30g, 30h) produced by at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h), configured to provide a transition of an electrical signal bound to the at least one conductive structure (10a) to free-wave space; - an electrical line coupler comprising the production of three electrically conductive structures (10a, 10b, 10c) electrically insulated from one another in all cross sections along at least one electrical line structure (1), two electrically conductive structures (10a, 10c) being placed at different electrical potentials from one another, wherein the distance between the two electrically conductive structures (10a, 10c) is selected in such a way that a cross-coupling of the electric field (80) from one electrically conductive structure (10a) to the other electrically conductive structure (10c) is regulated via the third electrically conductive structure (10b); - an electrical probe tip having at least one contact element (500) suitable for contacting a corresponding contact surface; - an electrical connection element, which is arranged on a separate substrate (40, 41) between at least two electrical line structures (50a-50c, 51a-51c), wherein the support structure (20) comprises at least two substrates (40, 41) and a first sub-region (120); - an interdigitated capacitor comprising a plurality of conductive structures (10a, 10b, 10c, 10d, 10e, 10f, 10g) arranged alternately in two different planes (35, 36) running parallel to each other.

7. The method according to the preceding claim, wherein in method step a) an additional mechanical protection structure (600) or monitoring structure (2000) is produced which is designed to prevent undesired mechanical damage to the electrical probe tip.

8. Method according to any of the preceding claims, wherein the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) is introduced into the support structure (20) in such a way that the effective dielectric constant of the mode (80) guided in the at least one electrical line structure (1) is adjusted along the propagation direction of the mode (80).

9. The method according to the preceding claim, wherein in the at least one electrical line structure (1), the effective dielectric constant of the modes (80) guided perpendicularly to the respective drawing plane in the propagation direction of the modes (80) is set to 20Ω to 100Ω.

10. Method according to any of the preceding claims, wherein the free-form microstructuring method comprises producing a first sub-region (120) of the support structure (20) from a plurality of individual layers, the first sub-region (120) of the support structure (20) consisting of more than 10 layers.

11. The method according to any of the preceding claims, wherein the support structure (20) is produced by using a multiphoton polymerization process or a stereolithography process.

12. Method according to any of the preceding claims, wherein the cross section of the at least one electrical line structure (1) varies along the propagation direction of the electromagnetic signal or follows a non-planar trajectory specified by the non-planar shape of the support structure (20).

13. The method according to any of the preceding claims, wherein the first sub-region (120) of the support structure (20) and the second sub-region (220) of the support structure (20) - contain each other in whole or in part; or - do not intersect or cross; or - at least partially overlap; or -same.

14. The method according to claim 1, wherein an electrical line transition (60a-60c, 61a-61c) is formed between at least one existing electrical line structure (50a-50c, 51a-51c, 51) and at least one electrical line structure (1).

15. The method according to the preceding claim, wherein the at least one additional shielding structure (70, 71) is produced at at least one electrical line transition (60a-60c, 61a-61c) in such a way that, when coating the support structure (20) with an electrically conductive material in the projection direction (100), - forming at least one additional electrically conductive connection between at least two existing electrical circuit structures (50a-50c, 51a-51c, 51) and at least one electrical circuit structure (1); or At least two existing electrical line structures ( 50 a - 50 c , 51 a - 51 c ) remain insulated from one another.

16. Method according to the preceding claim, wherein at least one additional shielding structure (70, 71) or protective layer (75) is applied to the further portion of the substrate (40, 41) in such a way that it is protected from being covered by the conductive material.

17. Method according to either of the two preceding claims, wherein at least one additional shielding structure (70, 71) or protective layer (75) is produced by using a free-form microstructuring method, in particular selected from a multiphoton polymerization process or a projection lithography process.

18. A method according to any of the three preceding claims, wherein at least one additional shielding structure (70, 71) or a protective layer (75) is removed after coating of the support structure (20), in particular by using a stripping process or by stripping at least one additional shielding structure (70, 71).

19. An electrical wiring arrangement comprising: - a support structure (20) comprising at least one first sub-region (120) designed as a three-dimensional free-form structure and produced using a free-form microstructuring process, and a second sub-region comprising an electrically insulating material (220), wherein the support structure (20) has at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) relative to the projection direction (100); and - at least one electrical line structure (1) applied as a coating on a support structure (20) using at least one spatially directional coating process with at least one electrically conductive material aligned in a projection direction (100) with at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h).

20. The electrical wiring arrangement according to the preceding claim, wherein the coating of the support structure (20) comprises at least two electrically conductive materials that are different from one another.

21. The electrical wiring arrangement according to any of the preceding claims relating to an electrical wiring arrangement, wherein the thickness of at least one electrical wiring structure (1) comprising the electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) is increased by electrical growth.

22. An electrical circuit arrangement according to any of the preceding claims relating to an electrical circuit arrangement, wherein the free-form microstructure method comprises producing a first sub-region (120) of the support structure (20) from a plurality of individual layers, wherein the first sub-region (120) of the support structure (20) consists of more than 10 layers.

23. An electrical wiring arrangement according to any of the preceding claims relating to an electrical wiring arrangement, wherein at least one electrical wiring structure (1) comprises at least one electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) which is electrically insulated relative to further electrically conductive structures (10a, 10b, 10c, 10d, 10e, 10f, 10g) adjacent to the at least one electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) within a cross section of the at least one electrical wiring structure (1) by using at least one exposed area (30a, 30b, 30c, 30d, 30e, 30f, 30g, 30h) generated by at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h).

24. The electrical wiring arrangement according to any of the preceding claims relating to an electrical wiring arrangement, wherein the support structure (20) comprises a substrate (40, 41).

25. The electrical wiring arrangement according to any one of the preceding claims relating to an electrical wiring arrangement, wherein the at least one electrical wiring structure (1) is selected from: - a microstrip line comprising a single structure (10a) which is electrically conductive in all cross sections along at least one electrical line structure (1); - a slotted line comprising two electrically conductive structures (10a, 10b) electrically insulated from one another in all cross sections along at least one electrical line structure (1); - a coplanar line comprising three electrically conductive structures (10a, 10b, 10c) electrically insulated from one another in all cross sections along at least one electrical line structure (1); - an antenna comprising the production of at least one conductive structure (10a) configured to provide a transition of an electrical signal bound to the at least one conductive structure (10a) to free-wave space through interaction with at least one exposed area (30a, 30b, 30c, 30d, 30e, 30f, 30g, 30h) produced by at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h); - an electrical line coupler comprising three electrically conductive structures (10a, 10b, 10c) which are insulated from one another in all cross sections along at least one electrical line structure (1), two electrically conductive structures (10a, 10c) being placed at different electrical potentials from one another, wherein the distance between the two electrically conductive structures (10a, 10c) is selected in such a way that a cross-coupling of the electric field (80) from one electrically conductive structure (10a) to the other electrically conductive structure (10c) is regulated via the third electrically conductive structure (10b); - an electrical probe tip having at least one contact element (500) suitable for contacting a corresponding contact surface; - an electrical connection element between at least two electrical line structures (50a-50c, 51a-51c) arranged on separate substrates (40, 41), wherein the support structure (20) comprises the at least two substrates (40, 41) and the first subregion (120); or - an interdigitated capacitor comprising a plurality of conductive structures (10a, 10b, 10c, 10d, 10e, 10f, 10g) arranged alternately in two different planes (35, 36) running parallel to each other and wherein these can be at different electrical potentials.

26. The electrical wiring arrangement according to the preceding claim, comprising an additional mechanical protection structure (600) or monitoring structure (2000) designed to prevent undesired mechanical damage to the electrical probe tip.

27. An electrical wiring arrangement according to any of the preceding claims relating to an electrical wiring arrangement, wherein the undercuts (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) in the support structure (20) are configured in such a way that the effective dielectric constant of the mode (80) guided in at least one electrical wiring structure (1) is adjusted along the propagation direction of the mode (80).

28. The electrical line arrangement according to the preceding claim, wherein the effective dielectric constant of the modes (80) guided perpendicularly to the respective drawing plane in the propagation direction of the modes (80) in at least one electrical line structure (1) is set to 20Ω to 100Ω.

29. An electrical wiring arrangement according to any of the preceding claims relating to electrical wiring arrangements, wherein the cross-section of the at least one electrical wiring structure (1) varies along the propagation direction of the electromagnetic signal, or follows a non-planar trajectory specified by the non-planar shape of the support structure (20).

30. The electrical wiring arrangement according to any of the preceding claims relating to an electrical wiring arrangement, wherein the first sub-area (120) of the support structure (20) and the second sub-area (220) of the support structure (20) - contain each other in whole or in part; or - do not intersect or cross; or - at least partially overlap; or -same.

31. An electrical wiring arrangement according to any of the preceding claims relating to an electrical wiring arrangement, comprising at least one additional shielding structure (70, 71) or a protective layer (75) applied to another part of the substrate (40, 41) in such a manner as to protect the other part of the substrate (40, 41) from being covered by the conductive material.

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