Band-gap reference voltage source and power supply chip

Abstract

The embodiment of the invention provides a band-gap reference voltage source and a power supply chip, the band-gap reference voltage source comprises a band-gap reference module, a sampling and holding module and a voltage buffer module, under a sampling phase, the sampling and holding module obtains a reference sampling voltage equal to a reference voltage, and the voltage buffer module obtains an offset sampling voltage; the sampling holding module is used for holding the reference sampling voltage and eliminating the third input offset voltage and the fourth input offset voltage based on the target sampling voltage so as to output a buffer voltage equal to the reference sampling voltage, the sampling holding module keeps the reference sampling voltage equal to the reference voltage under the holding phase, and the voltage buffer module obtains the target sampling voltage; and the first input offset voltage, the second input offset voltage, the third input offset voltage and the fourth input offset voltage are offset based on the offset sampling voltage to output the buffer voltage, so that high precision and low power consumption of the voltage source can be realized, and the suppression capability of load interference can also be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular to a bandgap reference voltage source and a power supply chip. Background Art

[0002] High-precision voltage sources are essential components of precision mixed-signal systems, but they consume significant quiescent current, reducing the system's energy efficiency in idle mode. A sample-and-hold circuit is typically incorporated into a high-precision voltage source to store the source's output voltage as a charge in a storage device such as a capacitor, maintaining a relatively stable voltage over a long period of time. This allows the source to operate at a low duty cycle, significantly reducing its energy consumption.

[0003] In existing technology, a voltage buffer circuit can be incorporated into a high-precision voltage source to prevent the voltage stored in the capacitor from being easily disturbed by various resistive and capacitive load couplings. However, the offset voltage introduced by the voltage buffer circuit itself ultimately negates the precision advantage of high-precision voltage sources that utilize sample-and-hold circuits to reduce power consumption. Consequently, existing voltage sources cannot simultaneously meet the requirements of high precision and low power consumption. Summary of the Invention

[0004] The present disclosure provides a bandgap reference voltage source and a power supply chip, which can simultaneously achieve high precision and low power consumption of the voltage source.

[0005] In a first aspect, the present disclosure provides a bandgap reference voltage source, comprising a bandgap reference module, a sampling and holding module, and a voltage buffer module, wherein the input offset voltage of the voltage buffer module comprises the first input offset voltage, the second input offset voltage, the third input offset voltage, and the fourth input offset voltage.

[0006] The sampling and holding module is configured to, in a sampling phase, sample the reference voltage output by the bandgap reference module to obtain and output a reference sampling voltage equal to the reference voltage; and in a holding phase, maintain the reference sampling voltage equal to the reference voltage.

[0007] The voltage buffer module is configured to, in the sampling phase, sample the first input offset voltage and the second input offset voltage to obtain an offset sampling voltage, and cancel the third input offset voltage and the fourth input offset voltage based on a target sampling voltage to output a buffered voltage equal to the reference sampling voltage; and in the holding phase, sample the reference sampling voltage, the third input offset voltage, and the fourth input offset voltage to obtain the target sampling voltage, and cancel the first input offset voltage, the second input offset voltage, the third input offset voltage, and the fourth input offset voltage based on the offset sampling voltage to output the buffered voltage.

[0008] In some embodiments of the present disclosure, the sample-and-hold module includes a first sampling switch, a second sampling switch, a third sampling switch, and a first sampling capacitor. The first sampling switch and the second sampling switch are controlled by a sampling signal, and the third sampling switch is controlled by an inverted sampling signal.

[0009] The source of the first sampling switch is connected to the output end of the bandgap reference module, the drain of the first sampling switch is connected to the source of the second sampling switch, the back gate of the second sampling switch, the drain of the third sampling switch, an intermediate node, and the first input end of the voltage buffer module, the drain of the second sampling switch is connected to the first plate of the first sampling capacitor and the second input end of the voltage buffer module, the second plate of the first sampling capacitor is grounded, and the output end of the voltage buffer module is connected to the output end of the bandgap reference voltage source.

[0010] In some embodiments of the present disclosure, the voltage buffer module includes a first gain unit and a second gain unit. The first gain unit includes a second sampling capacitor and a third sampling capacitor, and the second gain unit includes a fourth sampling capacitor. The first input of the first gain unit is connected to the drain of the first sampling switch, the source of the second sampling switch, the back gate of the second sampling switch, the drain of the third sampling switch, and the intermediate node. The second input of the first gain unit is connected to the first input of the second gain unit, the drain of the second sampling switch, and the first plate of the first sampling capacitor. The output of the first gain unit is connected to the second input of the second gain unit, and the output of the second gain unit is connected to the source of the third sampling switch and the output of the bandgap reference voltage source.

[0011] The first gain unit is configured to, in the sampling phase, connect the second sampling capacitor to the output end of the first gain unit and the third sampling capacitor to the intermediate node to obtain the offset sampling voltage; and in the hold phase, disconnect the second sampling capacitor from the output end of the first gain unit and disconnect the third sampling capacitor from the intermediate node.

[0012] The second gain unit is configured to, in the hold phase, connect the fourth sampling capacitor to the output end of the first gain unit to obtain the target sampling voltage; and in the sampling phase, disconnect the fourth sampling capacitor from the output end of the first gain unit.

[0013] In some embodiments of the present disclosure, the first gain unit further includes a first operational amplifier, a second operational amplifier, a third operational amplifier, a fourth sampling switch, and a fifth sampling switch, wherein the first input offset voltage is superimposed on the input end of the first operational amplifier, and the second input offset voltage is superimposed on the input end of the second operational amplifier; and the fourth sampling switch and the fifth sampling switch are controlled by the sampling signal.

[0014] A non-inverting input terminal of the first operational amplifier is connected to the drain of the second sampling switch and the first plate of the first sampling capacitor; an inverting input terminal of the first operational amplifier is connected to the source of the second sampling switch, the back gate of the second sampling switch, the drain of the third sampling switch, and the intermediate node; and an output terminal of the first operational amplifier is connected to the output terminal of the second operational amplifier and the input terminal of the third operational amplifier.

[0015] An inverting input terminal of the second operational amplifier is connected to the first plate of the second sampling capacitor and the first terminal of the fourth sampling switch. A second terminal of the fourth sampling switch is connected to the output terminal of the third operational amplifier and the second input terminal of the second gain unit. A non-inverting input terminal of the second operational amplifier is connected to the first plate of the third sampling capacitor and the first terminal of the fifth sampling switch. A second terminal of the fifth sampling switch is connected to the drain of the first sampling switch, the source of the second sampling switch, the back gate of the second sampling switch, the drain of the third sampling switch, and the intermediate node. The second plate of the second sampling capacitor and the second plate of the third sampling capacitor are grounded.

[0016] In some embodiments of the present disclosure, the second gain unit further includes a sixth sampling switch, a fourth operational amplifier, a fifth operational amplifier, and a sixth operational amplifier; wherein the input end of the fourth operational amplifier is superimposed with the third input offset voltage, the input end of the fifth operational amplifier is superimposed with the fourth input offset voltage, and the sixth sampling switch is controlled by the inverted sampling signal.

[0017] An inverting input terminal of the fourth operational amplifier is connected to a first terminal of the sixth sampling switch and a first plate of the fourth sampling capacitor; a second terminal of the sixth sampling switch is connected to an output terminal of the first gain unit; a second plate of the fourth sampling capacitor is grounded; and a non-inverting input terminal of the fourth operational amplifier is connected to a non-inverting input terminal of the fifth operational amplifier, a first plate of the first sampling capacitor, and a drain of the second sampling switch.

[0018] The output end of the fourth operational amplifier is connected to the output end of the fifth operational amplifier and the input end of the sixth operational amplifier, and the inverting input end of the fifth operational amplifier is connected to the output end of the sixth operational amplifier, the source of the third sampling switch, and the output end of the bandgap reference voltage source.

[0019] In some embodiments of the present disclosure, the target sampling voltage is VREF_samp+Vos_4*A5 / A4+Vos_3; wherein VREF_samp is the reference sampling voltage, A4 is the gain of the fourth operational amplifier, A5 is the gain of the fifth operational amplifier, Vos_3 is the third input offset voltage, and Vos_4 is the fourth input offset voltage.

[0020] In some embodiments of the present disclosure, the target sampling voltage is VREF_samp+[Vos_1*A1-(Vos_samp-Vos_2)*A2]*A3+Vos_4*A5 / A4+Vos_3; wherein VREF_samp is the reference sampling voltage, Vos_1 is the first input offset voltage, Vos_2 is the second input offset voltage, Vos_3 is the third input offset voltage, Vos_4 is the fourth input offset voltage, A1 is the gain of the first operational amplifier, A2 is the gain of the second operational amplifier, A3 is the gain of the third operational amplifier, A4 is the gain of the fourth operational amplifier, A5 is the gain of the fifth operational amplifier, and Vos_samp is the offset sampling voltage.

[0021] In some embodiments of the present disclosure, the offset sampling voltage is a voltage difference between a voltage across the second sampling capacitor and a voltage across the third sampling capacitor, and Vos_samp=Vos_1*A1 / A2+Vos_2.

[0022] In some embodiments of the present disclosure, the buffer voltage is VREF_samp+Vos_4+(VREF_samp-Vsamp-Vos_3)*A4 / A5; wherein Vsamp is the target sampling voltage.

[0023] In a second aspect, the present disclosure provides a power supply chip, comprising any bandgap reference voltage source provided in the first aspect.

[0024] The technical solution disclosed in the present invention provides a bandgap reference voltage source, including a bandgap reference module, a sampling and holding module, and a voltage buffer module. In the sampling phase, the sampling and holding module samples the reference voltage output by the bandgap reference module, obtains and outputs a reference sampling voltage equal to the reference voltage, and the voltage buffer module samples the first input offset voltage and the second input offset voltage to obtain an offset sampling voltage, and eliminates the third input offset voltage and the fourth input offset voltage based on the target sampling voltage to output a buffer voltage equal to the reference sampling voltage. In the holding phase, the sampling and holding module maintains the reference sampling voltage. The voltage is equal to the reference voltage, the voltage buffer module samples the reference sampling voltage, the third input offset voltage and the fourth input offset voltage to obtain a target sampling voltage, and offsets the first input offset voltage, the second input offset voltage, the third input offset voltage and the fourth input offset voltage based on the offset sampling voltage to output a buffer voltage. The stable buffer voltage can be continuously output, and the load interference suppression capability can be improved. The reference sampling power supply can be stabilized to the reference voltage in the phase holding stage to achieve high precision of the voltage source, and the bandgap reference module can be made inoperative in the phase holding stage to achieve low power consumption of the voltage source. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0026] Figure 1 A circuit diagram of a voltage source provided in the prior art.

[0027] Figure 2 The present invention provides a working schematic diagram of a voltage source provided by the prior art.

[0028] Figure 3 for Figure 1 Simulation graph of the output voltage of the voltage source shown.

[0029] Figure 4 A circuit diagram of another voltage source provided in the prior art.

[0030] Figure 5 A circuit diagram of another voltage source provided in the prior art.

[0031] Figure 6 A schematic structural diagram of a bandgap reference voltage source provided in an embodiment of the present disclosure.

[0032] Figure 7 A circuit diagram of a bandgap reference voltage source provided by an embodiment of the present disclosure.

[0033] Figure 8 Schematic diagram of the equivalent circuit of the bandgap reference voltage source in the sampling phase provided by an embodiment of the present disclosure.

[0034] Figure 9 Schematic diagram of an equivalent circuit of a phase-maintaining bandgap reference voltage source provided by an embodiment of the present disclosure.

[0035] Figure 10 A simulation diagram of the output voltage of a bandgap reference voltage source provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0038] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiment" in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0039] In addition, the terms "first", "second", etc. in the description and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more such features.

[0040] In this disclosure, the term "and / or" simply describes an association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0041] In the description of the present disclosure, unless otherwise specified, "multiple" and "at least two" mean more than two (including two). Similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0042] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0043] Figure 1 A circuit diagram of a voltage source provided by the prior art, such as Figure 1 As shown, the voltage source 100 includes a bandgap reference module 110 and a sample-and-hold circuit 120 , and the output end of the bandgap reference module 110 is connected to the output end of the voltage source 100 through the sample-and-hold circuit 120 .

[0044] The sample-and-hold circuit 120 includes a first sampling switch M1 and a first sampling capacitor CS1. The source of the first sampling switch M1 is connected to the output of the bandgap reference module 110. The drain of the first sampling switch M1 is connected to the first plate of the first sampling capacitor CS1 and the output of the voltage source 100. The second plate of the first sampling capacitor CS1 is grounded. The enable terminal of the bandgap reference module 110 is connected to the enable signal EN, and the gate of the first sampling switch M1 is connected to the sampling signal SAMP.

[0045] Exemplarily, the first sampling switch M1 is an N-type metal oxide semiconductor field effect transistor (NMOS).

[0046] Figure 2 A working timing diagram of a voltage source provided by the prior art, such as Figure 2As shown, when the enable signal EN is set high, the bandgap reference module 110 is activated. After the bandgap reference module 110 is fully established, the sampling signal SAMP is set high, turning on the first sampling switch M1. At this point, the reference signal VREF output by the bandgap reference module 110 charges the first sampling capacitor CS1, generating a reference sampling voltage VREF_samp. When the sampling signal SAMP is set low, the first sampling capacitor CS1 is no longer connected to the bandgap reference module 110, and the charge stored in the first sampling capacitor CS1 is fixed, preventing the reference sampling voltage VREF_samp from decreasing.

[0047] Repeating the above operation ultimately brings the reference sample voltage VREF_samp equal to the reference voltage VREF. Since the reference sample voltage VREF_samp remains unchanged, the enable signal EN only needs to maintain a low duty cycle to reduce the static power consumption of the bandgap reference module 110 itself, thereby meeting the low power consumption requirements of the voltage source. For example, if the enable signal EN is high for 200 μs every 20 ms, i.e., the duty cycle is 1%, the average power consumption of the voltage source 100 becomes 1% of the static power consumption of the bandgap reference module 110.

[0048] However, first, the first sampling switch M1 is subject to subthreshold channel leakage when the drain-source voltage is non-zero. Second, the first sampling switch M1 is subject to drain-induced barrier lowering (DIBL), which can cause leakage, particularly in short-channel devices. Third, when the drain-body voltage is non-zero, the first sampling switch M1 is susceptible to band-to-band tunneling, which can cause leakage. This effect is particularly pronounced in modern deep-submicron CMOS processes due to the use of strong halo doping. Consequently, the first sampling switch M1 in the sample-and-hold circuit 120 introduces leakage current, and the first sampling capacitor CS1 typically requires a significant area to mitigate the leakage introduced by the first sampling switch M1.

[0049] When both the enable signal EN and the sampling signal SAMP are low, the drain-source voltage of the first sampling switch M1 is equal to VREF. This high drain-source voltage causes the first sampling switch M1 to continue leaking current, causing the reference sampling voltage VREF_samp to slowly drop. When the enable signal EN is next set high, the bandgap reference module 110 is restarted. When both the enable signal EN and the sampling signal SAMP are set high, the bandgap reference module 110 replenishes the charge lost from the leakage of the first sampling switch M1 on the first sampling capacitor CS1 until VREF_samp = VREF.

[0050] For example, Figure 3 for Figure 1 The simulation diagram of the output voltage of the voltage source is shown in FIG. Figure 3 As shown, assuming that the reference voltage VREF=450 mV, the reference sampling voltage VREF_samp output by the voltage source 100 causes 9 mV of periodic noise due to leakage current.

[0051] As a result, the reference sampling voltage VREF_samp will periodically change. In some noise-sensitive systems, this periodic change in the reference sampling voltage VREF_samp can directly reduce the accuracy of the voltage source 100. Furthermore, since the reference sampling voltage VREF_samp lacks any buffer circuit, the first sampling capacitor CS1 is easily interfered with by various resistive and capacitive load couplings. Consequently, the reference sampling voltage VREF_samp stored on the first sampling capacitor CS1 is easily interfered with by various resistive and capacitive load couplings.

[0052] In order to solve the problem of load coupling, another voltage source is currently proposed, such as Figure 4 As shown, Figure 4 The circuit diagram of another voltage source provided by the prior art is as follows: the voltage source 200 includes a bandgap reference module 210 and a sample-and-hold circuit 220 , wherein the output of the bandgap reference module 210 is connected to the output of the voltage source 200 via the sample-and-hold circuit 220 .

[0053] The sample-and-hold circuit 220 includes a first sampling switch M1, a first sampling capacitor CS1, a first operational amplifier OPA1, a second sampling switch M2, and a third sampling switch M3. The source of the first sampling switch M1 is connected to the output of the bandgap reference module 210. The drain of the first sampling switch M1 is connected to the source of the second sampling switch M2, the back gate of the second sampling switch M2, the drain of the third sampling switch M3, and an intermediate node. The drain of the second sampling switch M2 is connected to the non-inverting input of the first operational amplifier OPA1 and the first plate of the first sampling capacitor CS1. The second plate of the first sampling capacitor CS1 is grounded.

[0054] The source of the third sampling switch M3 is connected to the inverting input terminal of the first operational amplifier OPA1, the output terminal of the first operational amplifier OPA1 and the output terminal of the voltage source 200. The enable terminal of the bandgap reference module 210 is connected to the enable signal EN. The gate of the first sampling switch M1 and the gate of the second sampling switch M2 are connected to the sampling signal SAMP. The gate of the third sampling switch M3 is connected to the inverted sampling signal There is an input offset voltage Vos at the inverting input terminal of the first operational amplifier OPA1, and the input offset voltage Vos is much smaller than the reference voltage VREF.

[0055] Exemplarily, the first sampling switch M1 , the second sampling switch M2 , and the third sampling switch M3 are NMOS.

[0056] The working sequence of the voltage source 200 is as follows: Figure 2 As shown, when the enable signal EN and the sampling signal SAMP are high, the inverted sampling signal is low, the first sampling switch M1 and the second sampling switch M2 are turned on, the third sampling switch M3 is turned off, and the first sampling capacitor CS1 samples the reference voltage VREF to obtain a reference sampling voltage VREF_samp, and VREF_samp=VREF=mid-node voltage Vmid.

[0057] When the enable signal EN and the sampling signal SAMP are low, the inverted sampling signal is high, the first sampling switch M1 and the second sampling switch M2 are turned off, the third sampling switch M3 is turned on, the drain-source voltage and the drain-backgate voltage of the second sampling switch M2 are modulated to the input offset voltage Vos, the first operational amplifier OPA1 forms a voltage buffer circuit, and the buffer voltage VREF_buf output by the voltage buffer circuit is the output voltage of the voltage source 200, and VREF_buf=Vmid.

[0058] Since the input offset voltage Vos is much smaller than the reference voltage VREF, the drain-source voltage and the drain-back gate voltage of the second sampling switch M2 are smaller than Figure 1 The drain-source voltage and drain-backgate voltage of the first sampling switch M1 are shown, and the leakage current on the first sampling capacitor CS1 is greatly reduced, so that the periodic noise generated by charging and discharging of the first sampling capacitor CS1 is greatly reduced.

[0059] However, the input offset voltage Vos is a non-zero voltage, typically ranging from several millivolts to more than ten millivolts in a low-power voltage source 200. Even at high temperatures, the second sampling switch M2 still exhibits non-negligible leakage current. Furthermore, due to the input offset voltage Vos, the buffer voltage VREF_buf output by the voltage buffer circuit is not equal to the reference voltage VREF, thereby compromising the high precision of the voltage source 200.

[0060] In order to meet the demand for high precision of voltage source, another voltage source is proposed, such as Figure 5 As shown, Figure 5 The circuit diagram of another voltage source provided in the prior art is as follows: the voltage source 300 includes a bandgap reference module 310 and a sample-and-hold circuit 320 , wherein the output of the bandgap reference module 310 is connected to the output of the voltage source 300 via the sample-and-hold circuit 320 .

[0061] The sample-and-hold circuit 320 includes a first sampling switch M1, a first sampling capacitor CS1, a first operational amplifier OPA1, a second sampling switch M2, a third sampling switch M3, a fourth sampling switch M4, and a second sampling capacitor CS2. The source of the first sampling switch M1 is connected to the output of the bandgap reference module 310. The drain of the first sampling switch M1 is connected to the source of the second sampling switch M2, the back gate of the second sampling switch M2, the drain of the third sampling switch M3, the first plate of the second sampling capacitor CS2, and an intermediate node. The drain of the second sampling switch M2 is connected to the non-inverting input of the first operational amplifier OPA1 and the first plate of the first sampling capacitor CS1. The second plate of the first sampling capacitor CS1 is grounded.

[0062] The source of the third sampling switch M3 is connected to the source of the fourth sampling switch M4, the output of the first operational amplifier OPA1, and the output of the voltage source 300. The drain of the fourth sampling switch M4 is connected to the second plate of the second sampling capacitor CS2 and the inverting input of the first operational amplifier OPA1. The enable terminal of the bandgap reference module 310 is connected to the enable signal EN. The gates of the first sampling switch M1, the second sampling switch M2, and the fourth sampling switch M4 are connected to the sampling signal SAMP. The gate of the third sampling switch M3 is connected to the inverted sampling signal There is an input offset voltage Vos at the inverting input terminal of the first operational amplifier OPA1, and the input offset voltage Vos is much smaller than the reference voltage VREF.

[0063] Exemplarily, the first sampling switch M1 , the second sampling switch M2 , the third sampling switch M3 and the fourth sampling switch M4 are NMOS.

[0064] The working sequence of the voltage source 300 is as follows: Figure 2 As shown, when the enable signal EN and the sampling signal SAMP are high, the inverted sampling signal is low, the first sampling switch M1, the second sampling switch M2 and the fourth sampling switch M4 are turned on, the third sampling switch M3 is turned off, VREF_samp=VREF=Vmid, the drain-source voltage and the drain-back gate voltage of the second sampling switch M2 are equal to the voltage across the second sampling capacitor CS2, that is, the input offset voltage Vos.

[0065] When the enable signal EN and the sampling signal SAMP are low, the inverted sampling signal =Vmid = VREF_samp + Vos - Vos = VREF_samp. At this point, the drain-source voltage and drain-backgate voltage of the second sampling switch M2 are both zero, and the leakage of the second sampling switch M2 becomes extremely small.

[0066] Thus, the first operational amplifier OPA1 uses auto-zero technology to store the input offset voltage Vos on the second sampling capacitor CS2. However, because the auto-zero scheme operates in discrete time, the output of the first operational amplifier OPA1 is not a continuous value, but switches back and forth between VREF and VREF + Vos. This is equivalent to generating a periodic noise with a peak-to-peak value of Vos, making the first operational amplifier OPA1 unable to be used as a voltage buffer circuit for the subsequent stage.

[0067] In summary, the existing voltage source cannot meet the requirements of low power consumption and high precision at the same time. The present disclosure provides a bandgap reference voltage source, including a bandgap reference module, a sampling and holding module and a voltage buffer module. In the sampling phase, the sampling and holding module samples the reference voltage output by the bandgap reference module, obtains and outputs a reference sampling voltage equal to the reference voltage, and the voltage buffer module samples the first input offset voltage and the second input offset voltage to obtain an offset sampling voltage, and eliminates the third input offset voltage and the fourth input offset voltage based on the target sampling voltage to output a buffer voltage equal to the reference sampling voltage. In the holding phase, the sampling and holding module samples the reference voltage output by the bandgap reference module, obtains and outputs a reference sampling voltage equal to the reference voltage, and outputs a buffer voltage equal to the reference sampling voltage. The holding module maintains the reference sampling voltage equal to the reference voltage, the voltage buffer module samples the reference sampling voltage, the third input offset voltage and the fourth input offset voltage to obtain a target sampling voltage, and offsets the first input offset voltage, the second input offset voltage, the third input offset voltage and the fourth input offset voltage based on the offset sampling voltage to output a buffer voltage. The stable buffer voltage can be continuously output, and the load interference suppression capability can be improved. The reference sampling power supply can be stabilized to the reference voltage during the holding phase stage to achieve high precision of the voltage source, and the bandgap reference module can be disabled during the holding phase stage to achieve low power consumption of the voltage source.

[0068] The technical solutions provided by the present disclosure are described in detail below with reference to several specific embodiments.

[0069] Figure 6 A schematic diagram of the structure of a bandgap reference voltage source provided by an embodiment of the present disclosure is shown in FIG. Figure 6 As shown, the bandgap reference voltage source 400 includes a bandgap reference module 410, a sample and hold module 420, and a voltage buffer module 430. The input offset voltage Vos of the voltage buffer module 430 includes a first input offset voltage Vos_1, a second input offset voltage Vos_2, a third input offset voltage Vos_3, and a fourth input offset voltage Vos_4.

[0070] The output end of the bandgap reference module 410 is connected to the first input end of the sampling and holding module 420, the input end of the voltage buffer module 430 is connected to the output end of the sampling and holding module 420, and the output end of the voltage buffer module 430 is connected to the second input end of the sampling and holding module 420 and the output end of the bandgap reference voltage source 400.

[0071] The sampling and holding module 420 is configured to, in the sampling phase, sample the reference voltage VREF output by the bandgap reference module 410, obtain and output a reference sampling voltage VREF_samp equal to the reference voltage VREF; in the holding phase, maintain the reference sampling voltage VREF_samp equal to the reference voltage VREF.

[0072] The voltage buffer module 430 is configured to, during a sampling phase, sample the first input offset voltage Vos_1 and the second input offset voltage Vos_2 to obtain a sampled offset voltage Vos_samp, and cancel the third input offset voltage Vos_3 and the fourth input offset voltage Vos_4 based on a target sampled voltage Vsamp to output a buffered voltage VREF_buf equal to a reference sampled voltage VREF_samp. During a hold phase, the voltage buffer module 430 samples the reference sampled voltage VREF_samp, the third input offset voltage Vos_3, and the fourth input offset voltage Vos_4 to obtain a target sampled voltage Vsamp, and cancel the first input offset voltage Vos_1, the second input offset voltage Vos_2, the third input offset voltage Vos_3, and the fourth input offset voltage Vos_4 based on the sampled offset voltage Vos_samp to output a buffered voltage VREF_buf.

[0073] Exemplarily, the bandgap reference module 410 is a conventional bandgap reference circuit. The enable terminal of the bandgap reference module 410 is connected to the enable signal EN. In the sampling phase, the enable signal EN is high, and the bandgap reference module 410 works to output the reference voltage VREF. In the holding phase, the enable signal EN is low, and the bandgap reference module 410 does not need to work to reduce the power consumption of the voltage source.

[0074] Figure 7 A circuit diagram of a bandgap reference voltage source provided by an embodiment of the present disclosure is shown in FIG. Figure 7As shown, the sample-and-hold module 420 includes a first sampling switch M1, a second sampling switch M2, a third sampling switch M3, and a first sampling capacitor CS1. The source of the first sampling switch M1 is connected to the output of the bandgap reference module 410, the drain of the first sampling switch M1 is connected to the source of the second sampling switch M2, the back gate of the second sampling switch M2, the drain of the third sampling switch M3, an intermediate node, and the first input of the voltage buffer module 430, the drain of the second sampling switch M2 is connected to the first plate of the first sampling capacitor CS1 and the second input of the voltage buffer module 430, and the second plate of the first sampling capacitor CS1 is grounded. The first sampling switch M1 and the second sampling switch M2 are controlled by a sampling signal SAMP, and the third sampling switch M3 is controlled by an inverted sampling signal SAMP.

[0075] For example, Figure 7 As shown, the voltage buffer module 430 includes a first gain unit 431 and a second gain unit 432. The first input end of the first gain unit 431 is connected to the source of the second sampling switch M2, the back gate of the second sampling switch M2, the drain of the third sampling switch M3, and the intermediate node. The second input end of the first gain unit 431 is connected to the first input end of the second gain unit 432, the drain of the second sampling switch M2, and the first plate of the first sampling capacitor CS1. The output end of the first gain unit 431 is connected to the second input end of the second gain unit 432. The output end of the second gain unit 432 is connected to the source of the third sampling switch M3 and the output end of the bandgap reference voltage source 400.

[0076] Continue to see Figure 7 The first gain unit 431 includes a first operational amplifier OPA1, a second operational amplifier OPA2, a third operational amplifier OPA3, a fourth sampling switch M4, a fifth sampling switch M5, a second sampling capacitor CS2, and a third sampling capacitor CS3. The first input offset voltage Vos_1 is superimposed on the input terminal of the first operational amplifier OPA1, the second input offset voltage Vos_2 is superimposed on the input terminal of the second operational amplifier OPA2, and the fourth sampling switch M4 and the fifth sampling switch M5 are controlled by a sampling signal SAMP.

[0077] A non-inverting input terminal of the first operational amplifier OPA1 is connected to the drain of the second sampling switch M2 and the first plate of the first sampling capacitor CS1 to receive a reference sampling voltage VREF_samp. An inverting input terminal of the first operational amplifier OPA1 is connected to the source of the second sampling switch M2, the back gate of the second sampling switch M2, the drain of the third sampling switch M3, and the intermediate node to receive the intermediate node voltage Vmid. An output terminal of the first operational amplifier OPA1 is connected to the output terminal of the second operational amplifier OPA2 and the input terminal of the third operational amplifier OPA3.

[0078] An inverting input terminal of the second operational amplifier OPA2 is connected to the first plate of the second sampling capacitor CS2 and the first terminal of the fourth sampling switch M4. A second terminal of the fourth sampling switch M4 is connected to the output terminal of the third operational amplifier OPA3 and the second input terminal of the second gain unit 432. A non-inverting input terminal of the second operational amplifier OPA2 is connected to the first plate of the third sampling capacitor CS3 and the first terminal of the fifth sampling switch M5. A second terminal of the fifth sampling switch M5 is connected to the drain of the first sampling switch M1, the source of the second sampling switch M2, the back gate of the second sampling switch M2, the drain of the third sampling switch M3, and the intermediate node. The second plate of the second sampling capacitor CS2 and the second plate of the third sampling capacitor CS3 are grounded.

[0079] The second gain unit 432 includes a sixth sampling switch M6, a fourth operational amplifier OPA4, a fifth operational amplifier OPA5, a sixth operational amplifier OPA6 and a fourth sampling capacitor CS4, wherein the input end of the fourth operational amplifier OPA4 is superimposed with the third input offset voltage Vos_3, the input end of the fifth operational amplifier OPA5 is superimposed with the fourth input offset voltage Vos_4, and the sixth sampling switch M6 is controlled by the inverted sampling signal

[0080] The inverting input of the fourth operational amplifier OPA4 is connected to the first terminal of the sixth sampling switch M6 and the first plate of the fourth sampling capacitor CS4. The second terminal of the sixth sampling switch M6 is connected to the output of the first gain unit 431. The second plate of the fourth sampling capacitor CS4 is grounded. The non-inverting input of the fourth operational amplifier OPA4 is connected to the non-inverting input of the fifth operational amplifier OPA5, the first plate of the first sampling capacitor CS1, and the drain of the second sampling switch M2. The output of the fourth operational amplifier OPA4 is connected to the output of the fifth operational amplifier OPA5 and the input of the sixth operational amplifier OPA6. The inverting input of the fifth operational amplifier OPA5 is connected to the output of the sixth operational amplifier OPA6, the source of the third sampling switch CS3, and the output of the bandgap reference voltage source 400.

[0081] The working sequence of the bandgap reference voltage source 400 is as follows: Figure 2 As shown, in the sampling phase, the enable signal EN and the sampling signal SAMP are high, and the inverted sampling signal = low, the first sampling switch M1 and the second sampling switch M2 are turned on, the third sampling switch M3 is turned off, VREF_samp = VREF, as Figure 8 As shown, Figure 8 Schematic diagram of the equivalent circuit of the bandgap reference voltage source in the sampling phase provided by an embodiment of the present disclosure.

[0082] At the same time, the fourth sampling switch M4 and the fifth sampling switch M5 are turned on, and the sixth sampling switch M6 is turned off. The first gain unit 431 can connect the second sampling capacitor CS2 to the output end of the third operational amplifier OPA3, that is, to the output end of the first gain unit 431, and connect the third sampling capacitor CS3 to the intermediate node. The second gain unit 432 can disconnect the fourth sampling capacitor CS4 from the output end of the first gain unit 431.

[0083] At this time, the second operational amplifier OPA2 and the third operational amplifier OPA3 form a negative feedback circuit, so that the input offset voltage of the first operational amplifier OPA1, that is, the first input offset voltage Vos_1, and the input offset voltage of the third operational amplifier OPA3, that is, the second input offset voltage Vos_2, are stored on the second sampling capacitor CS2 and the third sampling capacitor CS3.

[0084] If the gain A3 of the third operational amplifier OPA3 is large enough, the voltage difference between the voltage across the second sampling capacitor CS2 and the voltage across the third sampling capacitor CS3, that is, the offset sampling voltage Vos_samp, can be expressed as:

[0085] Vos_samp=Vos_1*A1 / A2+Vos_2 (1)

[0086] Wherein, A1 is the gain of the first operational amplifier OPA1, and A2 is the gain of the second operational amplifier OPA2.

[0087] The fifth operational amplifier OPA5 and the sixth operational amplifier OPA6 form another negative feedback circuit. The fourth operational amplifier OPA4 serves as the zeroing input stage of the negative feedback loop. The voltage across the fourth sampling capacitor CS4 is the target sampling voltage Vsamp. The target sampling voltage Vsamp is the same as that in the previous phase and remains unchanged. The buffer voltage VREF_buf output by the voltage buffer module 430 can be expressed as:

[0088] VREF_buf=VREF_samp+Vos_4+(VREF_samp-Vsamp-Vos_3)

[0089] *A4 / A5 (2)

[0090] Wherein, A4 is the gain of the fourth operational amplifier OPA4, and A5 is the gain of the fifth operational amplifier OPA5.

[0091] Figure 9 This is a schematic diagram of an equivalent circuit of a bandgap reference voltage source under phase preservation provided by an embodiment of the present disclosure, as shown in FIG. Figure 9 As shown, under the phase maintenance, the enable signal EN and the sampling signal SAMP are low, and the inverted sampling signal is high, the first sampling switch M1 and the second sampling switch M2 are turned off, and the third sampling switch M3 is turned on, then VREF_buf=Vmid.

[0092] At the same time, the fourth sampling switch M4 and the fifth sampling switch M5 are turned off, and the sixth sampling switch M6 is turned on. The first gain unit 431 can disconnect the second sampling capacitor CS2 from the output end of the third operational amplifier OPA3, that is, disconnect the second sampling capacitor CS2 from the output end of the first gain unit 431, and disconnect the third sampling capacitor CS3 from the intermediate node. The second gain unit 432 can connect the fourth sampling capacitor CS4 to the output end of the first gain unit 431.

[0093] At this time, the first operational amplifier OPA1, the third operational amplifier OPA3, the fourth operational amplifier OPA4, the fifth operational amplifier OPA5 and the sixth operational amplifier OPA6 constitute a dual path feedback amplifier, and the input voltage of the dual path feedback amplifier is the reference sampling voltage VREF_samp, and the output voltage is the buffer voltage VREF_buf.

[0094] The second operational amplifier OPA2 is a zero-adjusted input stage, and the target sampling voltage Vsamp can be expressed as:

[0095] Vsamp=VREF_samp+[Vos_1-(Vos_samp-Vos_2*A2)]*A3

[0096] +Vos__4*A5 / A4+Vos_3 (3)

[0097] Wherein, A3 is the gain of the third operational amplifier OPA3.

[0098] Substituting formula (3) into formula (2) can obtain the expression of the buffer voltage VREF_buf with respect to the offset sampling voltage Vos_samp, and combining with formula (1) can obtain VREF_buf=VREF_samp.

[0099] In this way, when the phase is maintained, the input offset voltages connected to the voltage buffer module 430 include the first input offset voltage Vos_1, the second input offset voltage Vos_2, the third input offset voltage Vos_3, and the fourth input offset voltage Vos_4. Based on the offset sampling voltage Vos_samp, the first input offset voltage Vos_1, the second input offset voltage Vos_2, the third input offset voltage Vos_3, and the fourth input offset voltage Vos_4 can be offset, thereby obtaining VREF_buf=VREF_samp.

[0100] Substituting formula (1) into formula (3), we can obtain formula (4):

[0101] Vsamp=VREF_samp+Vos_4*A5 / A4+Vos_3 (4)

[0102] Substituting formula (4) into formula (2) yields VREF_buf=VREF_samp.

[0103] Thus, in the sampling phase, the input offset voltages connected to the voltage buffer module 430 include the third input offset voltage Vos_3 and the fourth input offset voltage Vos_4 . The third input offset voltage Vos_3 and the fourth input offset voltage Vos_4 can be offset based on the target sampling voltage Vsamp, thereby obtaining VREF_samp=VREF_buf.

[0104] Furthermore, in the hold phase, the source voltage and back-gate voltage of the second sampling switch M2 are both equal to the mid-node voltage Vmid, and Vmid=VREF_buf. The drain voltage of the second sampling switch M2 is VREF_samp. Since VREF_buf=VREF_samp=VREF, the drain-source voltage and drain-back-gate voltage of the first sampling switch M1 are both close to 0V. Therefore, the leakage current of the first sampling switch M1 can be ignored, so that VREF_samp remains equal to VREF in the hold phase.

[0105] For example, Figure 10 This is a simulation diagram of the output voltage of a bandgap reference voltage source provided by an embodiment of the present disclosure. Assuming that the reference voltage VREF = 450mV, the periodic output noise of the buffer voltage VREF_buf output by the bandgap reference voltage source 400 due to leakage is only 18uV. Figure 1 The output of the voltage source 100 shown in FIG. 1 is shown. The accuracy of the bandgap reference voltage source 400 provided by the embodiment of the present disclosure is improved by 500 times, and the ability of the buffer voltage VREF_buf to suppress load interference is greatly improved.

[0106] In summary, during the hold phase, sample-and-hold module 420 does not need to sample, and bandgap reference module 410 is inoperative, thereby reducing power consumption of the voltage source. Furthermore, throughout the entire operation period, voltage buffer module 430 provides a stable buffer voltage, VREF_buf, improving the ability to suppress load interference. Furthermore, VREF_samp stabilizes to VREF during the hold phase, thereby improving the accuracy of the voltage source.

[0107] The embodiment of the present disclosure further provides a power supply chip, including the bandgap reference voltage source 400 provided in any of the above embodiments, and having the functional modules and beneficial effects of the bandgap reference voltage source 400, which will not be described in detail here.

[0108] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

[0109] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A bandgap reference voltage source, characterized in that: It includes a bandgap reference module, a sample-and-hold module, and a voltage buffer module; The sampling and holding module is configured to, in a sampling phase, sample the reference voltage output by the bandgap reference module to obtain and output a reference sampling voltage equal to the reference voltage; in a holding phase, maintain the reference sampling voltage equal to the reference voltage; The voltage buffer module is configured to, in the sampling phase, sample the first input offset voltage and the second input offset voltage to obtain an offset sampling voltage, and eliminate the third input offset voltage and the fourth input offset voltage based on a target sampling voltage to output a buffer voltage equal to the reference sampling voltage; In the hold phase, sampling the reference sampling voltage, the third input offset voltage, and the fourth input offset voltage to obtain the target sampling voltage, and offsetting the first input offset voltage, the second input offset voltage, the third input offset voltage, and the fourth input offset voltage based on the offset sampling voltage to output the buffered voltage; The input offset voltage of the voltage buffer module includes the first input offset voltage, the second input offset voltage, the third input offset voltage and the fourth input offset voltage.

2. The bandgap reference voltage source according to claim 1, wherein: The sampling and holding module includes a first sampling switch, a second sampling switch, a third sampling switch and a first sampling capacitor; The source of the first sampling switch is connected to the output end of the bandgap reference module, the drain of the first sampling switch is connected to the source of the second sampling switch, the back gate of the second sampling switch, the drain of the third sampling switch, an intermediate node, and the first input end of the voltage buffer module, the drain of the second sampling switch is connected to the first plate of the first sampling capacitor and the second input end of the voltage buffer module, the second plate of the first sampling capacitor is grounded, and the output end of the voltage buffer module is connected to the output end of the bandgap reference voltage source; The first sampling switch and the second sampling switch are controlled by a sampling signal, and the third sampling switch is controlled by an inverted sampling signal.

3. The bandgap reference voltage source according to claim 2, wherein: The voltage buffer module includes a first gain unit and a second gain unit, the first gain unit includes a second sampling capacitor and a third sampling capacitor, and the second gain unit includes a fourth sampling capacitor; A first input end of the first gain unit is connected to the drain of the first sampling switch, the source of the second sampling switch, the back gate of the second sampling switch, the drain of the third sampling switch, and the intermediate node; a second input end of the first gain unit is connected to the first input end of the second gain unit, the drain of the second sampling switch, and the first plate of the first sampling capacitor; an output end of the first gain unit is connected to the second input end of the second gain unit; and an output end of the second gain unit is connected to the source of the third sampling switch and the output end of the bandgap reference voltage source; The first gain unit is configured to, in the sampling phase, connect the second sampling capacitor to the output end of the first gain unit and the third sampling capacitor to the intermediate node to obtain the offset sampling voltage; and in the hold phase, disconnect the second sampling capacitor from the output end of the first gain unit and disconnect the third sampling capacitor from the intermediate node; The second gain unit is configured to, in the hold phase, connect the fourth sampling capacitor to the output end of the first gain unit to obtain the target sampling voltage; and in the sampling phase, disconnect the fourth sampling capacitor from the output end of the first gain unit.

4. The bandgap reference voltage source according to claim 3, wherein: The first gain unit further includes a first operational amplifier, a second operational amplifier, a third operational amplifier, a fourth sampling switch and a fifth sampling switch; A non-inverting input terminal of the first operational amplifier is connected to the drain of the second sampling switch and the first plate of the first sampling capacitor; an inverting input terminal of the first operational amplifier is connected to the source of the second sampling switch, the back gate of the second sampling switch, the drain of the third sampling switch, and the intermediate node; and an output terminal of the first operational amplifier is connected to the output terminal of the second operational amplifier and the input terminal of the third operational amplifier; An inverting input terminal of the second operational amplifier is connected to the first plate of the second sampling capacitor and the first terminal of the fourth sampling switch; a second terminal of the fourth sampling switch is connected to the output terminal of the third operational amplifier and the second input terminal of the second gain unit; a non-inverting input terminal of the second operational amplifier is connected to the first plate of the third sampling capacitor and the first terminal of the fifth sampling switch; a second terminal of the fifth sampling switch is connected to the drain of the first sampling switch, the source of the second sampling switch, the back gate of the second sampling switch, the drain of the third sampling switch, and the intermediate node; and a second plate of the second sampling capacitor and a second plate of the third sampling capacitor are grounded. The first input offset voltage is superimposed on the input end of the first operational amplifier, and the second input offset voltage is superimposed on the input end of the second operational amplifier; the fourth sampling switch and the fifth sampling switch are controlled by the sampling signal.

5. The bandgap reference voltage source according to claim 4, wherein: The second gain unit further includes a sixth sampling switch, a fourth operational amplifier, a fifth operational amplifier, and a sixth operational amplifier; An inverting input terminal of the fourth operational amplifier is connected to a first terminal of the sixth sampling switch and a first plate of the fourth sampling capacitor, a second terminal of the sixth sampling switch is connected to an output terminal of the first gain unit, a second plate of the fourth sampling capacitor is grounded, and a non-inverting input terminal of the fourth operational amplifier is connected to a non-inverting input terminal of the fifth operational amplifier, a first plate of the first sampling capacitor, and a drain of the second sampling switch; The output end of the fourth operational amplifier is connected to the output end of the fifth operational amplifier and the input end of the sixth operational amplifier, and the inverting input end of the fifth operational amplifier is connected to the output end of the sixth operational amplifier, the source of the third sampling switch, and the output end of the bandgap reference voltage source; The third input offset voltage is superimposed on the input end of the fourth operational amplifier, the fourth input offset voltage is superimposed on the input end of the fifth operational amplifier, and the sixth sampling switch is controlled by the inverted sampling signal.

6. The bandgap reference voltage source according to claim 5, characterized in that: The target sampling voltage is VREF_samp+Vos_4*A5 / A4+Vos_3; Wherein, VREF_samp is the reference sampling voltage, A4 is the gain of the fourth operational amplifier, A5 is the gain of the fifth operational amplifier, Vos_3 is the third input offset voltage, and Vos_4 is the fourth input offset voltage.

7. The bandgap reference voltage source according to claim 5, wherein: The target sampling voltage is VREF_samp+[Vos_1*A1-(Vos_samp-Vos_2)*A2]*A3+Vos_4*A5 / A4+Vos_3; Wherein, VREF_samp is the reference sampling voltage, Vos_1 is the first input offset voltage, Vos_2 is the second input offset voltage, Vos_3 is the third input offset voltage, Vos_4 is the fourth input offset voltage, A1 is the gain of the first operational amplifier, A2 is the gain of the second operational amplifier, A3 is the gain of the third operational amplifier, A4 is the gain of the fourth operational amplifier, A5 is the gain of the fifth operational amplifier, and Vos_samp is the offset sampling voltage.

8. The bandgap reference voltage source according to claim 7, wherein: The offset sampling voltage is a voltage difference between a voltage across the second sampling capacitor and a voltage across the third sampling capacitor, and Vos_samp=Vos_1*A1 / A2+Vos_2.

9. The bandgap reference voltage source according to claim 6 or 8, characterized in that: The buffer voltage is VREF_samp+Vos_4+(VREF_samp-Vsamp-Vos_3)*A4 / A5; wherein Vsamp is the target sampling voltage.

10. A power chip, characterized in that: The invention comprises the bandgap reference voltage source according to any one of claims 1 to 9.

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