Processor loading storage unit function verification method and device, electronic equipment and storage medium

Abstract

The invention relates to the technical field of function verification, in particular to a processor loading storage unit function verification method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out formalized verification on a processor loading storage unit through a formalized verification tool, and extracting feature data which does not cover a critical path; wherein the feature data at least comprises a time sequence feature, an address feature and a data dependence feature; converting the feature data into constraint rules available for the dynamic simulation platform, and generating test excitation; and executing dynamic simulation verification based on the test excitation to obtain a coverage rate result. According to the processor loading storage unit function verification method provided by the invention, through formalized verification and dynamic simulation closed-loop cooperation, the directional constraint is generated by extracting the key path features, the verification period is greatly shortened, and the coverage rate convergence efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of functional verification technology, and in particular to a method and device for verifying the function of a processor loading a storage unit, as well as electronic equipment and a storage medium. Background Art

[0002] In the verification of the load store unit (LSU) of RISC-V architecture processors, traditional dynamic simulation relies on random constraints. It is generally difficult to achieve convergence in verification coverage for complex scenarios such as various memory properties, address overlap, dependencies between read and write instructions, parallel processing between multiple pipelines, and memory consistency in multi-core systems.

[0003] Existing techniques attempt to optimize the verification process through regression testing combined with manual intervention. These include: 1) analyzing code coverage and functional coverage reports generated by dynamic simulation to identify areas of low coverage; 2) manually adjusting constraint weights (e.g., forcing an increase in the probability of address overlap); and 3) constructing targeted test cases through waveform debugging to cover specific scenarios. However, these approaches have significant drawbacks. First, manual analysis of coverage reports requires checking tens of thousands of coverage points one by one. For complex designs like LSUs, engineers can spend weeks trying to identify all problematic points. Second, some scenarios that are logically impossible to cover (e.g., a specific out-of-order instruction sequence where the path does not exist due to hardware design limitations) require repeated verification and elimination, resulting in wasted resources. Furthermore, when there are too many random variables (e.g., memory access order between multiple cores or multi-cycle pipeline timing constraints), verification time remains difficult to manage, even with significant computational resources. Furthermore, a high proportion of redundant test cases further hinders convergence. These inconsistencies highlight the unsustainability of existing approaches for large-scale LSU verification.

[0004] To address these technical issues, existing technologies attempt to integrate formal verification tools (such as JasperGold) with dynamic simulation. While formal methods can theoretically exhaustively explore the state space through symbolic execution, they still face the problem of "state explosion." While relying solely on dynamic simulation can reduce complexity, it requires massive amounts of random test cases to cover all possible paths. This not only consumes significant computing resources but also fails to effectively locate deep-seated dependency vulnerabilities (such as address conflicts that occur after multiple cycles). Furthermore, existing tools lack intelligent coverage guidance mechanisms, forcing engineers to rely on manual experience to write corner case tests, resulting in slow convergence and difficulty in quantitatively evaluating verification completeness. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide a method and device for verifying the function of a processor loading a storage unit, as well as an electronic device and a storage medium.

[0006] In a first aspect, an embodiment of the present invention provides a method for verifying a processor load storage unit function, the method comprising: Perform formal verification on the processor load and store unit using a formal verification tool to extract feature data of uncovered critical paths; the feature data includes at least timing features, address features, and data dependency features; Convert feature data into constraint rules that can be used by the dynamic simulation platform to generate test stimuli; Perform dynamic simulation verification based on test stimuli to obtain coverage results; Compare the formal path characteristics with the dynamic simulation coverage to determine whether there are uncovered paths; If so, the hybrid verification mode is triggered and fed back to the formal verification tool to loop verification until the path is fully covered and the verification is completed.

[0007] In conjunction with the first aspect, the steps of performing formal verification on the processor load storage unit using a formal verification tool and extracting characteristic data of uncovered critical paths include: Identify at least one core signal related to the uncovered critical path in the formal counterexample waveform; For each core signal, obtain the core signal's address bus, data dependency flag, and pipeline conflict signal; Analyze the formalized counterexample waveform to extract the conflict signal, timing characteristics and address characteristics of the address bus containing boundary address values; Analyze the full path of Load-Store instructions through the dependency graph and calculate the longest dependency chain length. At the same time, when there is a closed loop in the dependency graph and all instructions in the loop are in the pending state, mark the deadlock point; Determine data dependency characteristics by combining the longest dependency chain length and deadlock points.

[0008] In conjunction with the first aspect, before the step of identifying at least one core signal related to the path in the waveform, the method further includes: A dynamic compression algorithm based on signal change rate is used to merge adjacent events whose timing differences are less than a specified difference to generate a simplified counterexample waveform.

[0009] In combination with the first aspect, the steps of converting the characteristic data into constraint rules usable by the dynamic simulation platform and generating test stimuli containing random weights include: The feature data is converted through the constraint conversion script to obtain the constraint rules that can be executed by the dynamic simulation platform; Adopting the Actor-Critic reinforcement learning framework to dynamically adjust the constraint weights of the constraint rules; Implement real-time weight optimization for formally marked high-risk paths.

[0010] In combination with the first aspect, the constraint rules include address constraints, timing constraints and dependency constraints; The steps of converting the feature data through the constraint conversion script to obtain constraint rules executable by the dynamic simulation platform include: The address characteristics are set as a high-risk path address set constrained by the dynamic simulation platform to construct the address constraint; Increase the specified weight ratio of timing characteristics and the weight ratio of load-store sequences, and build dependency constraints based on the longest dependency chain length.

[0011] In conjunction with the first aspect, the steps of triggering the hybrid verification mode to the formal verification tool include: Locate the timing window of uncovered paths; Freeze dynamic simulation within the timing window and switch to formal verification tools for local in-depth verification; Extract new counterexample features generated by local deep verification; Based on the address characteristics and data dependency characteristics of new counterexamples, the constraint rules are dynamically updated.

[0012] In combination with the first aspect, after comparing the formalized path characteristics with the dynamic simulation coverage to determine whether there are uncovered paths, the following steps are also included: If not, it is determined that the load storage unit verification is completed, and the constraint weight of the constraint rule is reset to the base value.

[0013] In a second aspect, the present application provides a processor loading storage unit function verification device, the device comprising: A formal verification module is used to perform formal verification on the processor load storage unit using a formal verification tool to extract feature data of uncovered critical paths; wherein the feature data includes at least timing features, address features, and data dependency features; Dynamic conversion module, used to convert feature data into constraint rules of dynamic simulation platform and generate test stimulus; An execution module is used to perform dynamic simulation verification based on test stimuli to obtain coverage results; The judgment module is used to compare the formal path characteristics with the dynamic simulation coverage to determine whether there is an uncovered path; The trigger verification module is used to trigger the hybrid verification mode to feedback to the formal verification tool when there is an uncovered path, so as to loop the verification until the path is fully covered and the verification is completed.

[0014] In a third aspect, the present application provides an electronic device, which includes a memory and a processor. The memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to execute the above method.

[0015] In a fourth aspect, the present application provides a readable storage medium, in which computer program instructions are stored. When the computer program instructions are read and executed by a processor, the above-mentioned method is executed.

[0016] The embodiments of the present invention bring the following beneficial effects: The present application provides a method, device, electronic device, and storage medium for verifying the function of a processor loading storage unit, the method comprising: performing formal verification on the processor loading storage unit through a formal verification tool, and extracting characteristic data of uncovered critical paths; wherein the characteristic data includes at least timing characteristics, address characteristics, and data dependency characteristics; converting the characteristic data into constraint rules that can be used by a dynamic simulation platform to generate test stimuli; performing dynamic simulation verification based on the test stimuli to obtain coverage results; comparing the formal path characteristics with the dynamic simulation coverage to determine whether there is an uncovered path; if so, triggering a hybrid verification mode to feed back to the formal verification tool to perform cyclic verification until the path is completely covered to complete the verification.

[0017] The processor loading and storage unit function verification method provided in this application, through the collaboration of formal verification and dynamic simulation closed loop, generates directional constraints by extracting key path features (timing, address, data dependency), greatly shortens the verification cycle, and improves coverage convergence efficiency.

[0018] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purposes and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A flowchart of a method for verifying a processor loading a storage unit function provided by an embodiment of the present invention; Figure 2 A schematic diagram of the structure of a device for verifying the function of a processor loading a storage unit provided by an embodiment of the present invention; Figure 3A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention; Figure 4 A schematic diagram of the overall flow of a method for verifying a processor loading storage unit function provided by an embodiment of the present invention.

[0022] Reference numerals: 10-Formal Verification Module, 20-Dynamic Conversion Module, 30-Execution Module, 40-Judgment Module, 50-Trigger Verification Module; 130 - processor, 131 - memory, 132 - bus, 133 - communication interface. DETAILED DESCRIPTION

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present invention.

[0024] To facilitate understanding of this embodiment, the following is a brief introduction to the technical terms used in this application.

[0025] LSU (Load Store Unit) is responsible for executing all load and store instructions, generating virtual addresses for load and store operations, and loading data from memory or storing data from registers back to memory.

[0026] RSIC-V is an open source Reduced Instruction Set Computer (RISC) architecture.

[0027] After introducing the technical terms involved in this application, the application scenarios and design concepts of the embodiments of this application are briefly introduced.

[0028] Although formal verification can exhaustively explore the state space, it has limitations for superscalar multi-issue architectures (such as 4-way superscalars), where the number of state combinations grows exponentially. When verifying a dual-issue 10-stage pipeline, Jasper Gold used more than 48GB of memory, resulting in a state space explosion and the inability to complete full state traversal. It also made it impossible to directly generate the test stimulus required for dynamic simulation.

[0029] Dynamic simulation relies on random test vectors, which makes it difficult to cover complex LSU scenarios (such as non-aligned address access and atomic operation conflicts), resulting in lengthy verification cycles and low verification efficiency.

[0030] Based on this, the embodiments of the present application provide a method, device, electronic device, and storage medium for verifying the function of a processor loading a storage unit. The method actively analyzes coverage vulnerabilities through formal tools, outputs key feature data, and automatically converts them into dynamic simulation constraint rules to optimize constraint weights for dynamic simulation verification. Feedback is then provided based on the dynamic simulation verification results to form a closed-loop verification process, thereby achieving rapid convergence of coverage.

[0031] Example 1 This application provides a method for verifying the function of a processor loading a storage unit, combining Figure 1 As shown, the method includes: S110 , performing formal verification on the processor load storage unit using a formal verification tool to extract feature data of uncovered critical paths; wherein the feature data includes at least timing features, address features, and data dependency features.

[0032] S120: Convert the characteristic data into constraint rules that can be used by the dynamic simulation platform to generate test stimuli.

[0033] S130, performing dynamic simulation verification based on the test stimulus to obtain coverage results.

[0034] S140 , comparing the formalized path characteristics with the dynamic simulation coverage to determine whether there is an uncovered path.

[0035] If so, execute step S150.

[0036] S150, triggering the hybrid verification mode to feed back to the formal verification tool, so as to loop the verification until the path is completely covered and the verification is completed.

[0037] First, formal tools proactively analyze the characteristic data of output key paths and convert this data into dynamic simulation constraints to guide the dynamic simulation platform in generating test stimuli for uncovered paths. Constraint-driven simulation is then performed to collect coverage results, which are then compared with the formalized path characteristics. If any uncovered paths remain, the simulation information is fed back to the formal tool to update the constraints and restart the process until all paths are covered. This allows for vulnerability discovery based on formal functional verification and targeted testing based on dynamic simulation, forming a bidirectional feedback closed-loop optimization loop that aims to efficiently and thoroughly cover all critical paths.

[0038] The formal verification tool in step S110 can be Cadence JasperGold, Synopsys VCFormal, Siemens EDA Questa Formal, etc. When exhaustively searching the state space, the formal verification tool identifies which paths (or properties) it fails to prove or disprove (i.e., "not covered"). Unlike traditional formal verification, which simply reports pass / fail or counterexamples, the formal verification tool extracts characteristic data for critical paths that were not covered. This characteristic data includes at least: timing features, address features, and data dependency features. Timing features refer to the timing characteristics of a path, such as the clock cycles involved, setup / hold time relationships, and critical path delays. Address features refer to the specific address ranges, address alignment, and address conflict conditions involved in a path. Data dependency features refer to the path's dependencies on load / store data, such as specific data values, data patterns (e.g., all 0s, all 1s, address-dependent data), and data race conditions. That is, step S110 utilizes the "exhaustiveness" of formal verification to discover complex or edge cases that may be missed by dynamic simulation, and extracts the key attributes (features) of these cases.

[0039] In combination with the first aspect, step S110 includes: S111 , identifying at least one core signal related to an uncovered critical path in the formalized counterexample waveform.

[0040] S112 , for each core signal, obtaining the address bus, data dependency flag, and pipeline conflict signal of the core signal.

[0041] S113, parsing the formalized counterexample waveform, extracting the conflict signal, timing characteristics, and address characteristics including boundary address values ​​of the address bus.

[0042] S114, analyze the full path Load-Store instructions through the dependency graph and calculate the longest dependency chain length. At the same time, when there is a closed loop in the dependency graph and the status of all instructions in the loop is suspended, mark the deadlock point.

[0043] S115, combining the longest dependency chain length and the deadlock point to determine the data dependency characteristics.

[0044] Step S111 automatically identifies core signals that are strongly correlated with uncovered paths. Subsequently, step S112 performs feature extraction on the core signals. Specifically, the address bus is extracted by extracting the access address range, alignment mode, and cross-boundary behavior (for example, unaligned access to address 0x1000-0x1003); data dependency marks are extracted based on data value constraints and read-write data matching relationships (for example, a conflict is triggered when the Store data must be 0xFF); and conflict signals are extracted through bus contention and resource contention flags (for example, two load instructions request the same cache line at the same time).

[0045] Then, step S113 performs an in-depth analysis of the address bus, and further extracts the conflict signal, timing characteristics, and address characteristics of the boundary address value of the address bus through timing detection and conflict type classification.

[0046] Step S114 analyzes the nodes and edges based on the dependency graph to determine the data dependency relationship and calculate the dependency depth to obtain the longest dependency chain and identify the closed loop. If a closed loop exists and the state of each instruction in the closed loop is suspended, the deadlock point is marked, and then in step S115, the data dependency feature is synthesized based on the obtained longest dependency chain length and deadlock point (for example, deadlock is triggered when the address is 0x2000 and the data is 0x0).

[0047] In this way, dependency graph closed loop detection exposes hidden system-level deadlock risks, which are extremely difficult to trigger in traditional dynamic simulation verification processes. The above steps convert the formal counterexamples into the accurate feature data source required for dynamic simulation.

[0048] In combination with the first aspect, before step S111, the method further includes: S1110 uses a dynamic compression algorithm based on the signal change rate to merge adjacent events whose timing differences are less than a specified difference to generate a simplified counterexample waveform.

[0049] It can be understood that by merging adjacent events with timing differences less than a threshold (such as a small clock offset of the same continuous data bus), the large counterexample waveform can be simplified into a small counterexample waveform to retain key events and eliminate redundant jumps, thereby solving the problem of excessive amount of formal counterexample waveform data, reducing the complexity of subsequent signal analysis, and avoiding noise interference in core feature extraction.

[0050] In this embodiment, the specified difference is 10%, that is, adjacent events with a timing difference of less than 10% are merged into a single event. For example, when the address bus change amplitude is less than 5% within multiple consecutive clock cycles, it is merged into a single event.

[0051] In combination with the first aspect, step S120 includes: S121, converting the feature data through a constraint conversion script to obtain constraint rules executable by the dynamic simulation platform.

[0052] S122, uses the Actor-Critic reinforcement learning framework to dynamically adjust the constraint weights of constraint rules.

[0053] S123, performing real-time weight optimization on the formally marked high-risk paths.

[0054] In combination with the first aspect, the constraint rules include address constraints, timing constraints, and dependency constraints; step S121 includes: S1211 , setting the address feature as a high-risk path address set constrained by the dynamic simulation platform to construct an address constraint.

[0055] S1212 increases the specified weight ratio of the timing feature and the weight ratio of the load-store sequence, and constructs a dependency constraint based on the longest dependency chain length.

[0056] After formal verification is performed to output feature data in step S110, step S120 converts the feature data into constraint rules that can be executed by the dynamic simulation platform, and then adjusts the constraint weights and optimizes the weights of high-risk paths based on the preconfigured Actor-Critic reinforcement learning framework.

[0057] Specifically, the address features extracted in step S110, including boundary addresses, are prioritized as the high-risk path address set for constructing address constraints. As can be understood, when converting feature data into constraint rules, initial weights are assigned to address features, data dependency features, conflict signals, and so on, and then the weights corresponding to each feature are adjusted. Furthermore, dependency constraints are constructed using the longest dependency chain length obtained through formal verification.

[0058] Subsequently, we increased the weight of the timing features in the formalized counterexamples and the weight of the load-store sequences in the formally extracted critical paths. The weight of the load-store sequences includes the frequency of load (data read) and store (data write) instructions, as well as the distribution priority of instruction sequence patterns (such as continuous load and alternating load-store), which directly impact the coverage of the load-store unit (LSU) critical path.

[0059] Next, in step S122, the preset Actor-Critic framework is used within the dynamic simulation platform (UVM) to adjust the constraint weights of each constraint rule in the action space based on relevant parameters in the state space. The state space includes the current coverage progress, the progress of uncovered paths, and the constraint violation count. Specifically, the dynamic simulation platform runs a simulation verification based on the constraint rules obtained in step S121 to obtain the coverage progress, the criticality of uncovered paths, and the constraint violation count for this verification, thereby optimizing the constraint weights. Subsequently, in step S123, the constraint weights of the formally marked high-risk paths are increased according to preset rules. In this embodiment, the preset rule is to increase the constraint weights of high-risk paths by 50%-100%, while simultaneously decaying the weights by 15% after each test round to prevent local optima. Based on steps S121-S123, the formalized feature data extracted in step S110 is converted, and appropriate constraint weights are matched. Weight optimization is then performed on high-risk paths. Test stimuli are generated by combining these constraints and their constraint weights, thereby accurately constraining the dynamic simulation platform for functional verification. Then, step S130 obtains coverage results obtained by testing the dynamic simulation platform using the test stimulus generated in step S120.

[0060] Step S140 compares the coverage result obtained in step S130 with the formalized path features to determine whether the coverage meets the requirements, that is, whether there are still uncovered paths.

[0061] In combination with the first aspect, step S150 includes: S151, locating the timing window of the uncovered path.

[0062] S152, freeze the dynamic simulation within the timing window and switch to the formal verification tool to perform local deep verification.

[0063] S153, extracting new counterexample features generated by local deep verification.

[0064] S154, dynamically update the constraint rules based on the address characteristics and data dependency characteristics of the new counterexample.

[0065] As you can understand, when uncovered paths exist, simulation information is fed back to the formal verification tool, constraints are refined, and formal verification is restarted. Feature data is converted into constraint rules, constraint weights are adjusted and optimized, and dynamic simulation verification is performed. Coverage results are compared with the formal features to determine if there are still uncovered critical paths. This continues until all paths are covered, completing functional verification. This allows for loopholes to be discovered through formal verification, combined with targeted testing through dynamic simulation, and rapid convergence through closed-loop optimization using bidirectional feedback, thereby improving verification speed.

[0066] After receiving feedback that there are still uncovered paths, first, the timing window of the uncovered path can be located based on factors such as the signal active period, address orientation range, and key state machine jumps, with high positioning accuracy and improved address range recognition accuracy. Subsequently, when performing dynamic simulation verification on the timing window, the register state of the dynamic simulation is directly imported into the formal environment, and local formal verification is used to deeply extract and generate new counterexample features. Then, based on the new counterexample features, the constraint engine is injected, the constraint rules and constraint weights are updated, and the dynamic simulation platform is dynamically updated, thereby realizing millisecond-level switching and intelligent co-evolution of formal verification and dynamic simulation to improve the verification efficiency of the load storage unit (LSU).

[0067] In combination with the first aspect, after step S140, the method further includes: S160 , determining that the load storage unit verification is completed, and resetting the constraint weight of the constraint rule to a base value.

[0068] Dynamic simulation testing is performed on the dynamic simulation platform using the generated test stimulus. The comparison between the coverage results and the formal path characteristics indicates that the path has been fully covered and the verification has been completed. At this time, the constraint weights of the constraint rules are reset to the basic value (i.e., the initial value) for the next verification.

[0069] Combine Figure 4 As shown, formal analysis is first performed to extract counterexample features and identify key paths, and then data conversion is performed to obtain constraint rules. Subsequently, intelligent constraint optimization is performed, and coverage analysis is performed after dynamic simulation execution based on the optimized constraint rules. The results of the coverage analysis (i.e., the aforementioned coverage results) are compared with the formal path features obtained by formal verification to determine whether the coverage meets the standards. When the coverage meets the standards, the verification is completed. When the coverage does not meet the standards, feedback is given to the formal analysis process, and the above steps are repeated until the coverage obtained again meets the standards and the verification is completed. In the second aspect, the present application provides a processor loading storage unit function verification device, combined with Figure 2 As shown, the device includes: a formal verification module 10 , a dynamic conversion module 20 , an execution module 30 , a judgment module 40 and a trigger verification module 50 .

[0070] The formal verification module 10 is used to perform formal verification on the processor load storage unit through a formal verification tool to extract feature data of uncovered critical paths; wherein the feature data at least includes timing features, address features and data dependency features.

[0071] The dynamic conversion module 20 is used to convert the characteristic data into the constraint rules of the dynamic simulation platform and generate test stimuli.

[0072] The execution module 30 is used to perform dynamic simulation verification based on the test stimulus to obtain coverage results.

[0073] The judgment module 40 is used to compare the formalized path characteristics with the dynamic simulation coverage to determine whether there is an uncovered path.

[0074] The trigger verification module 50 is used to trigger the hybrid verification mode to feedback to the formal verification tool when there is an uncovered path, so as to loop the verification until the path is completely covered and the verification is completed.

[0075] In a third aspect, the present application provides an electronic device, Figure 3 As shown, the electronic device includes a memory 131 and a processor 130. The memory 131 is used to store computer programs, and the processor 130 runs the computer programs to enable the electronic device to perform the above method.

[0076] Further, combined with Figure 3 The electronic device shown further includes a bus 132 and a communication interface 133 , and the processor 130 , the communication interface 133 and the memory 131 are connected via the bus 132 .

[0077] The memory 131 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage. The communication connection between the system network element and at least one other network element is achieved through at least one communication interface 133 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used. The bus 132 may be an ISA bus, a PCI bus, or an EISA bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0078] The processor 130 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in the processor 130 or by software instructions. The processor 130 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in conjunction with the embodiments of the present invention can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in memory 131, and processor 130 reads information in memory 131 and, in conjunction with its hardware, completes the steps of the method of the aforementioned embodiment.

[0079] In a fourth aspect, an embodiment of the present application provides a readable storage medium, in which computer program instructions are stored. When the computer program instructions are read and executed by a processor, the above-mentioned method is executed.

[0080] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems and devices can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0081] In addition, in the description of the embodiments of the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0082] If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0083] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0084] Finally, it should be noted that the above embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for verifying the function of a processor loading a storage unit, characterized in that: The method comprises: Performing formal verification on the processor load storage unit using a formal verification tool to extract feature data of uncovered critical paths; wherein the feature data includes at least timing features, address features, and data dependency features; Convert the characteristic data into constraint rules that can be used by a dynamic simulation platform to generate test stimuli; Perform dynamic simulation verification based on the test stimulus to obtain coverage results; Compare the formal path characteristics with the dynamic simulation coverage to determine whether there are uncovered paths; If so, the hybrid verification mode is triggered and fed back to the formal verification tool to loop verification until the path is fully covered and the verification is completed.

2. The method according to claim 1, characterized in that The steps of using a formal verification tool to formally verify the processor load and store units and extracting characteristic data of uncovered critical paths include: Identify at least one core signal related to the uncovered critical path in the formal counterexample waveform; For each core signal, obtaining an address bus, a data dependency flag, and a pipeline conflict signal of the core signal; Analyze the formalized counterexample waveform to extract the conflict signal, timing characteristics and address characteristics of the address bus containing boundary address values; Analyze the full path of Load-Store instructions through the dependency graph and calculate the longest dependency chain length. At the same time, when there is a closed loop in the dependency graph and all instructions in the loop are in the pending state, mark the deadlock point; The data dependency feature is determined based on the longest dependency chain length and the deadlock point.

3. The method according to claim 2, characterized in that Before the step of identifying at least one core signal associated with the path in the waveform, the method further includes: A dynamic compression algorithm based on signal change rate is used to merge adjacent events whose timing differences are less than a specified difference to generate a simplified counterexample waveform.

4. The method according to claim 2, characterized in that The steps of converting the characteristic data into constraint rules that can be used by a dynamic simulation platform and generating a test stimulus containing random weights include: Converting the feature data using a constraint conversion script to obtain constraint rules executable by the dynamic simulation platform; Adopting the Actor-Critic reinforcement learning framework to dynamically adjust the constraint weights of the constraint rules; Implement real-time weight optimization for formally marked high-risk paths.

5. The method according to claim 4, characterized in that Constraint rules include address constraints, timing constraints, and dependency constraints; The step of converting the feature data by using a constraint conversion script to obtain constraint rules executable by the dynamic simulation platform includes: Setting the address feature as a high-risk path address set constrained by a dynamic simulation platform to construct the address constraint; The timing feature is increased by a specified weight ratio, the weight ratio of the load-store sequence, and the dependency constraint is constructed based on the length of the longest dependency chain.

6. The method according to claim 4, characterized in that The steps to trigger the hybrid verification mode to the formal verification tool include: Locate the timing window of uncovered paths; Freeze the dynamic simulation within the timing window and switch to a formal verification tool to perform local deep verification; Extracting new counterexample features generated by the local deep verification; The constraint rules are dynamically updated based on the address characteristics and data dependency characteristics of the new counterexample.

7. The method according to claim 1, characterized in that After comparing the formalized path characteristics with the dynamic simulation coverage to determine whether there are uncovered paths, the following steps are also included: If not, it is determined that the load storage unit verification is completed, and the constraint weight of the constraint rule is reset to a base value.

8. A processor loading storage unit function verification device, characterized in that: The device comprises: A formal verification module is used to perform formal verification on the processor load storage unit through a formal verification tool to extract feature data of uncovered critical paths; wherein the feature data includes at least timing features, address features, and data dependency features; A dynamic conversion module, used to convert the characteristic data into constraint rules of a dynamic simulation platform to generate test stimuli; An execution module, configured to perform dynamic simulation verification based on the test stimulus to obtain a coverage result; The judgment module is used to compare the formal path characteristics with the dynamic simulation coverage to determine whether there is an uncovered path; The trigger verification module is used to trigger the hybrid verification mode to feedback to the formal verification tool when there is an uncovered path, so as to loop the verification until the path is fully covered and the verification is completed.

9. An electronic device, characterized in that: The electronic device includes a memory and a processor, the memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to perform the method according to any one of claims 1 to 7.

10. A storage medium, characterized in that: The storage medium stores computer program instructions, and when the computer program instructions are read and executed by a processor, the method according to any one of claims 1 to 7 is executed.

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