System and method for DFT ECO

Abstract

The invention provides a DFT ECO system and method, and the method comprises the steps: receiving a DFT reference netlist inputted by a user as first input information, and enabling the DFT reference netlist to be a netlist which is complete in DFT logic and can be detected through an ATPG tool; receiving a to-be-ECO DFT pre ECO netlist input by the user as second input information, wherein the DFT pre ECO netlist is a netlist of which DFT logic needs to be repaired; extracting a DFT correlation structure and a logic signal from the DFT reference netlist; performing DFT DRC check on the DFT pre ECO netlist according to the extracted DFT structure and the logic signal, and identifying an error type; the DFT structure and the DFT DRC violation in the DFT pre ECO netlist are repaired according to the check result; carrying out ECO (Error Correction Oscillation) operation after chain loading and unloading on the basis of the repaired netlist; generating a repaired DFT netlist and providing a comparison report; and the efficiency of the DFT ECO is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the field of ECO technology, and in particular relates to a DFT ECO system and method. Background Art

[0002] In actual projects, ECOs performed to change circuit logic functions are called Functional ECOs. The Functional ECO process inevitably changes and damages the Design For Test (DFT) logic. Furthermore, changes to logical functions such as new registers, without corresponding updates to the DFT logic, can reduce DFT coverage and impact product quality. In these scenarios, DFT logic needs to be repaired and updated, which is called DFT ECO.

[0003] Mainstream DFT tools themselves do not provide ECO for DFT logic, but in professional ECO tools, there are now methods to repair the scan chain in DFT: During the Functional ECO process, the DFT logic is repaired synchronously, which makes the engineering implementation very complicated, the actual effect is not good, and it cannot meet business needs; Repair the DFT logic separately, but because only an ECOed netlist is read, the complete DFT solution information cannot be obtained, and only simple DFT logic can be repaired. DFT DRC checks cannot be performed, and the help of ATPG tools is required, which makes the design process complicated; Existing tools cannot handle complex DFT logic, especially designs with multiple scan modes and multiple compressors. There are limitations on the ECO of DFT logic. It may be repaired in one scan mode, but there will still be violations in another scan mode. Summary of the Invention

[0004] To address existing technical deficiencies, this invention proposes a new advanced DFT ECO system and method. This system not only independently performs more accurate and complete repairs on DFT logic, but also automatically checks DFT DRCs and reports the differences before and after repairs. It is a complete solution that can significantly improve engineering efficiency.

[0005] The scheme of the present invention is as follows: In a first aspect, the present invention provides a DFT ECO system, comprising: a first input module, a second input module, a DFT structure extraction module, a DFT inspection module, a DFT repair module, a DFT ECO module, and an output module, wherein the first input module and the second input module are respectively connected to the DFT structure extraction module.

[0006] The first input module is used to receive a DFT reference netlist input by a user as first input information. The DFT reference netlist is a netlist with complete DFT logic and can be detected by an ATPG tool.

[0007] The second input module is used to receive a DFT pre ECO netlist to be ECO input by a user as second input information, where the DFT pre ECO netlist is a netlist whose DFT logic needs to be repaired.

[0008] The DFT structure extraction module is used to extract DFT-related structures and logic signals from the DFT reference netlist.

[0009] The DFT checking module is connected to the DFT structure extraction module and is used to perform DFT DRC checking on the DFT pre ECO netlist according to the extracted DFT structure and logic signals to identify error types.

[0010] The DFT repair module is connected to the DFT check module and is used to repair DFT structure and DFT DRC violations in the DFT pre ECO netlist according to the identified error type.

[0011] The DFT ECO module is connected to the DFT repair module and is used to perform ECO operations after uplink and downlink based on the repaired netlist.

[0012] The output module is connected to the DFT ECO module and is used to generate a repaired DFT netlist and provide a comparison report.

[0013] Furthermore, the DFT-related structure includes a compression / decompression module and an on-chip clock management module, and the logic signal includes a controllable clock signal, a controllable reset signal and a scan enable signal.

[0014] Furthermore, the DFT DRC check performed by the DFT check module includes: Check the DFT structure or logic signal connection; check the number of registers on the scan chain; check the drive signals of the clock and reset signals of the registers on the scan chain.

[0015] Furthermore, the DFT repair module performs repair according to the inspection result, so that the DFT logic in the repaired netlist is consistent with the DFT logic in the DFT reference netlist.

[0016] Furthermore, the DFT ECO module supports two operation modes: automatic ECO and ECO based on user instructions.

[0017] Furthermore, the comparison report generated by the output module includes scan chain length comparison, statistics on the number of newly added / deleted registers, and DFT DRC check results.

[0018] In a second aspect, the present invention provides a DFT ECO method, which is implemented based on the system of the first aspect, and the method comprises the following steps: Step S1: receiving a DFT reference netlist input by a user as first input information, wherein the DFT reference netlist is a netlist with complete DFT logic and can be tested by an ATPG tool.

[0019] Step S2: receiving a DFT pre ECO netlist to be ECO input by a user as second input information, wherein the DFT pre ECO netlist is a netlist of DFT logic that needs to be repaired.

[0020] Step S3: extracting DFT-related structures and logic signals from the DFT reference netlist.

[0021] Step S4: performing a DFT DRC check on the DFT pre-ECO netlist according to the extracted DFT structure and logic signals to identify error types.

[0022] Step S5: repairing DFT structure and DFT DRC violations in the DFT pre ECO netlist according to the inspection result.

[0023] Step S6: Perform ECO operations after uplink and downlink based on the repaired netlist.

[0024] Step S7: Generate a repaired DFT netlist and provide a comparison report.

[0025] Furthermore, the DFT-related structure includes a compression / decompression module and an on-chip clock management module, and the logic signal includes a controllable clock signal, a controllable reset signal and a scan enable signal.

[0026] Furthermore, the DFT DRC check includes: DFT structure or logic signal connection check; check of the number of registers on the scan chain; check of drive signals such as clock and reset signals of the registers on the scan chain.

[0027] Furthermore, the repair operation makes the DFT logic in the repaired netlist consistent with the DFT logic in the DFT reference netlist, and supports two operation modes: automatic ECO and user-instruction-based ECO.

[0028] Compared with the prior art, the present invention has the following beneficial effects: The present invention introduces a DFT reference netlist to fully obtain the original DFT solution information, providing a standard reference file for the DFT ECO. DFT logic repair can be completely implemented according to the reference netlist rather than some other alternative solutions. Built-in DFT DRC checks can be performed to verify the quality of test results without the need for third-party ATPG tools. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of the DFT ECO system of the present invention; Figure 2 This is a flow chart of the DFT ECO method of the present invention. DETAILED DESCRIPTION

[0030] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention are described clearly and completely below. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0031] Example 1 like Figure 1 FIG2 is a schematic diagram of a DFT ECO system according to the present invention. The system includes: a first input module, a second input module, a DFT structure extraction module, a DFT inspection module, a DFT repair module, a DFT ECO module, and an output module. The first input module and the second input module are respectively connected to the DFT structure extraction module.

[0032] The system features a modular architecture. For example, the first and second input modules are connected to the DFT structure extraction module. These two input modules utilize a standard interface protocol and support input in a variety of netlist formats, including Verilog, VHDL, and Liberty. The connection mechanism utilizes asynchronous processing to prevent blocking when processing large netlists.

[0033] For example, in real-world applications, when a user enters a netlist file through the GUI or command-line tool, the system first performs file format verification and integrity checks. For example, if the DFT reference netlist entered is "reference_design.v," the system parses the file's syntax and extracts key information such as port information, module hierarchy, and timing constraints. Furthermore, for the netlist to be ECOed, "pre_eco_design.v," the system establishes a mapping relationship with the reference netlist.

[0034] The first input module is used to receive a DFT reference netlist input by a user as first input information. The DFT reference netlist is a netlist with complete DFT logic and can be detected by an ATPG tool.

[0035] The DFT reference netlist must meet several key conditions: first, it must contain the complete DFT logic structure, including all scan chains, compressors, decompressors, and related control logic; second, it must be able to pass the verification of the ATPG (Automatic Test Pattern Generation) tool, that is, all fault points in the netlist can be effectively detected.

[0036] For example, suppose we have a 32-bit processor design. Its DFT reference netlist should include the following key elements: 8 scan chains, each chain contains about 500 flip-flops; an 8:1 compressor module to compress the outputs of the 8 scan chains into 1; a 1:8 decompressor module to distribute the test vectors to the 8 scan chains; complete clock control logic, including the switching mechanism of the test clock and functional clock; reset control logic to ensure that all flip-flops can be reset correctly in test mode.

[0037] During the actual verification process, this reference netlist must pass the complete test flow of ATPG tools such as Synopsys TetraMAX or Mentor Tessent, including fault simulation, test vector generation, and fault coverage analysis. Only when the fault coverage reaches a preset threshold (usually above 95%) can the netlist be used as a valid reference standard.

[0038] The second input module is used to receive a DFT pre ECO netlist to be ECO input by a user as second input information, where the DFT pre ECO netlist is a netlist whose DFT logic needs to be repaired.

[0039] The DFT pre-ECO netlist to be ECOed is typically generated during the functional ECO process, and its DFT logic structure may contain various issues. These issues include: scan chain breaks, incorrect insertion of newly added registers into the scan chain, timing violations caused by clock domain changes, and incorrect control signal connections.

[0040] For example, suppose a cache control module containing 64 new registers is added to the original design. During functional ECO, these registers are added directly to the design without updating the DFT logic accordingly. As a result, these 64 registers are not inserted into any scan chains, making them uncontrollable and observable during testing, thus reducing fault coverage.

[0041] Another typical example is a clock domain change. Suppose a module in the original design uses system_clk as its operating clock. However, during the ECO process, due to performance optimization, the module is switched to use the high-frequency clock high_freq_clk. This change affects the test clock distribution logic, potentially preventing the module's registers from correctly receiving the test clock signal in test mode.

[0042] The DFT structure extraction module is used to extract DFT-related structures and logic signals from the DFT reference netlist.

[0043] The DFT structure extraction module uses graph theory algorithms and pattern matching technology to identify and extract DFT-related structural information; the module's workflow includes: netlist parsing, structure identification, signal tracing, dependency analysis and other steps.

[0044] During the netlist parsing phase, the system creates a complete design hierarchy diagram, including inter-module connectivity, port mapping, signal flow, and other information. For example, for a complex SoC design consisting of a CPU core, memory controller, and peripheral interfaces, the system identifies the DFT structure of each module, including its scan chain configuration, clock domain division, and reset strategy.

[0045] The structure recognition phase uses a feature-matching algorithm that can automatically identify various DFT structural patterns. For example, the system can identify the cascaded scan chain structure: scan_in → FF1 → FF2 → FF3 → scan_out, and can distinguish between different types of scan chains, such as normal scan chains, clock-gated scan chains, and reset scan chains.

[0046] The signal tracing phase uses backward and forward tracing algorithms to identify the source and destination of various control signals. For example, for the scan_enable signal, the system traces its complete path from the top-level port to each scan flip-flop, identifying all intermediate logic such as buffers, inverters, and multiplexers.

[0047] The DFT-related structure includes a compression / decompression module and an on-chip clock management module, and the logic signal includes a controllable clock signal, a controllable reset signal and a scan enable signal.

[0048] The compression / decompression module is used to reduce test data volume and test time. The compressor typically uses an XOR tree structure to compress the outputs of multiple scan chains into a smaller number of output signals. For example, an 8:1 compressor might have the following structure: a three-stage XOR gate. The first stage contains four XOR gates, corresponding to (chain0^chain1), (chain2^chain3), (chain4^chain5), and (chain6^chain7). The second stage contains two XOR gates that calculate the XOR of the first-stage results. The third stage contains one XOR gate that outputs the final compressed result.

[0049] The decompressor uses a linear feedback shift register (LFSR) or phase shifter structure to expand the smaller input signal into the input of multiple scan chains. A typical 1:8 decompressor may include: an 8-bit LFSR with a feedback polynomial of ; 8 XOR gates, connected to different positions of LFSR, generate pseudo-random test vectors for each scan chain.

[0050] The on-chip clock management module is responsible for switching clock signals between functional mode and test mode. This module typically includes: a clock selector (Clock Mux), which selects the functional clock or test clock under the control of the test_mode signal; clock gating logic (Clock Gating), which disables unnecessary clock signals in test mode to reduce power consumption; and a clock divider (Clock Divider), which provides clocks of different frequencies for different test requirements.

[0051] The management of controllable clock signals involves multiple layers: the top-level test clock (test_clk) is distributed to each module through the clock tree; the clock gating unit (ICG) within each module must be properly controlled in test mode; and the synchronization logic at clock domain crossings requires special handling during testing.

[0052] Controllable reset signals include: an asynchronous reset signal (async_reset) that initializes all flip-flops at the start of the test; a synchronous reset signal (sync_reset) that controls the state of specific flip-flops during the scan process; and reset release logic that ensures that all flip-flops are in a known state before the test vector is applied.

[0053] The DFT checking module is connected to the DFT structure extraction module and is used to perform DFT DRC checking on the DFT pre ECO netlist according to the extracted DFT structure and logic signals to identify error types.

[0054] The DFT check module implements a complete set of design rule checking (DRC) systems to ensure that the DFT logic in the netlist meets the test requirements. The module adopts a multi-level checking strategy: structural layer checking verifies the integrity and correctness of the DFT module; connection layer checking verifies the correctness of signal connection; and timing layer checking verifies the rationality of test timing.

[0055] During the structural check, the system verifies that the configuration of each compressor and decompressor is consistent with the reference netlist. For example, if an 8:1 compressor is defined in the reference netlist, the system checks whether the pre-ECO netlist contains the same compressor configuration, including the number of input ports, number of output ports, internal logic structure, and so on. If any mismatch is found, the system generates a detailed error report, identifying the specific differences.

[0056] Connection layer checking involves signal tracing and connectivity verification. The system checks the integrity of each scan chain, ensuring that the signal path from scan_in to scan_out is intact. For example, for a scan chain containing 100 flip-flops, the system verifies that the Q output of FF1 is correctly connected to the scan_in input of FF2, and so on. The system also checks the connection of clock and reset signals to ensure that each scan flip-flop receives the correct control signals.

[0057] Timing layer checks focus on the rationality of test timing. The system analyzes the propagation delay of the clock signal to ensure that no setup or hold time violations occur at the test frequency. For example, if the test clock frequency is 100MHz, the system calculates the propagation delay from the clock source to each flip-flop to ensure that the clock skew is within an acceptable range.

[0058] The DFT DRC check performed by the DFT check module includes: Check the DFT structure or logic signal connection; check the number of registers on the scan chain; check the drive signals of the clock and reset signals of the registers on the scan chain.

[0059] The system verifies the correctness of the connection of each DFT signal one by one, including: whether the scan_enable signal is correctly connected to the enable terminals of all scan flip-flops; whether the scan_in signal is correctly connected to the first scan flip-flop; whether the scan output of each flip-flop is correctly connected to the scan input of the next flip-flop; and whether the scan_out signal is correctly connected to the output of the last scan flip-flop.

[0060] For example, suppose the scan output of flip-flop 50 in a scan chain is disconnected due to an erroneous operation during the ECO process. The system detects this breakpoint through the graph traversal algorithm and generates the following error report: "The scan_out signal of flip-flop FF_50 in Chain_0 is not connected to the scan_in signal of FF_51, resulting in a broken scan chain." The scan chain register count check ensures that the length of each scan chain meets the design requirements. The system counts the number of flip-flops in each scan chain and compares it with the reference netlist. For example, if Chain_0 in the reference netlist contains 128 flip-flops, but the pre-ECO netlist only has 126, the system will identify the two missing flip-flops and report their specific locations and names.

[0061] Furthermore, the system checks the balance of scan chains. In designs with multiple scan chains, to optimize test time, it is often desirable to keep the lengths of the individual scan chains as even as possible. If the length of a scan chain deviates from the average by more than a preset threshold (e.g., 5%), the system issues a warning and recommends rebalancing the scan chain distribution.

[0062] Checking the drive signals for clock and reset signals involves multiple aspects. For clock signals, the system checks: whether the clock terminal of each scan flip-flop is connected to the correct clock domain; whether the fan-out load of the clock signal is within the acceptable range; and whether the logic depth of the clock signal meets timing requirements. For reset signals, the system checks: whether the reset signal polarity is correct; whether the reset signal release timing meets requirements; and whether the reset signal coverage is complete.

[0063] The DFT repair module is connected to the DFT check module and is used to repair DFT structure and DFT DRC violations in the DFT pre ECO netlist according to the identified error type.

[0064] For scan chain break issues, the repair module employs the following strategy: first, identify the location and cause of the break; then, reestablish the correct connection relationship based on the connection information in the reference netlist; and finally, verify that the repaired connection meets timing requirements. For example, if the scan_out signal of FF_50 is detected to be disconnected, the system automatically adds a buffer or directly connects the Q output of FF_50 to the scan_in input of FF_51.

[0065] To address the issue of newly added registers not being inserted into the scan chain, the repair module uses an intelligent insertion algorithm: analyzing the location and function of the newly added registers; determining the scan chain to be inserted based on the clock domain and reset domain information; selecting the optimal insertion location while maintaining scan chain balance; and updating related connection relationships.

[0066] For example, suppose 64 new registers are added to the cache control module. They all use cpu_clk as the operating clock and async_reset as the reset signal. The repair module analyzes the eight existing scan chains and finds that Chain_2 and Chain_5 are relatively short. Therefore, it decides to insert 32 registers into Chain_2 and another 32 into Chain_5. During this insertion process, the system maintains the original scan order and ensures that all clock and reset connections are correct.

[0067] The DFT repair module performs repairs according to the inspection result, so that the DFT logic in the repaired netlist is consistent with the DFT logic in the DFT reference netlist.

[0068] During structural consistency verification, the system compares each DFT component of the repaired netlist with the reference netlist. For example, for a compressor module, the system verifies the consistency of the number and names of input ports, the number and names of output ports, the internal XOR logic connections, and the control signal connections.

[0069] Functional consistency verification ensures logical equivalence through formal verification methods. The system generates a series of test vectors and applies them to the reference netlist and the repaired netlist, comparing their output responses. If output inconsistencies are found under any test vector, the system reports a functional mismatch error and provides detailed debugging information.

[0070] The timing information of the repaired netlist is extracted, including parameters such as setup time, hold time, and propagation delay, and compared with the reference netlist. If the timing parameters are found to be outside the acceptable range, the system will automatically adjust the insertion of buffers or the structure of the clock tree.

[0071] The DFT ECO module is connected to the DFT repair module and is used to perform ECO operations after uplink and downlink based on the repaired netlist.

[0072] The DFT ECO module supports two operation modes: automatic ECO and ECO based on user instructions.

[0073] The output module is connected to the DFT ECO module and is used to generate a repaired DFT netlist and provide a comparison report.

[0074] The comparison report generated by the output module includes scan chain length comparison, statistics on the number of newly added / deleted registers, and DFT DRC check results.

[0075] Example 2 like Figure 2FIG. 1 is a flow chart of the DFT ECO method of the present invention, and the method includes the following steps: Step S1: receiving a DFT reference netlist input by a user as first input information, wherein the DFT reference netlist is a netlist with complete DFT logic and can be tested by an ATPG tool.

[0076] Step S1 includes multiple sub-processes: file format identification, syntax parsing, semantic analysis, and integrity verification. During the file format identification phase, the system supports a variety of mainstream netlist formats, including Verilog, SystemVerilog, and VHDL. The system automatically identifies the format type based on the file extension and header information and invokes the corresponding parser.

[0077] The parsing phase uses a recursive descent parser capable of handling complex syntactic structures. For example, for a Verilog netlist, the parser builds an abstract syntax tree (AST) containing all syntactic elements, including module definitions, port declarations, wire declarations, and instantiation statements. For netlists containing parameterized modules, the parser also handles parameter passing and module instantiation.

[0078] The semantic analysis phase performs type checking, name resolution, and scope analysis. The system creates a complete symbol table, recording all signal types, bit widths, scopes, and other information. For hierarchical designs, the system creates a hierarchical symbol table to support cross-hierarchical signal references.

[0079] Completeness verification is a key step in ensuring netlist quality. The system checks: whether all signals have clear driver sources; whether there are multiple drivers or driver conflicts; whether port connections are correct; and whether clock signal distribution is reasonable.

[0080] For example, suppose a user enters a reference netlist file named "cpu_core_with_dft.v," which is 50MB in size and contains one million gates. The system first checks the file for readability and formatting, then initiates a parallel parser for syntax analysis. During the semantic analysis phase, the system identifies the major design modules: the CPU core module, cache controller module, bus interface module, and so on, along with their DFT structure configurations.

[0081] Step S2: receiving a DFT pre ECO netlist to be ECO input by a user as second input information, wherein the DFT pre ECO netlist is a netlist of DFT logic that needs to be repaired.

[0082] The processing strategy for receiving user-entered DFT pre-ECO netlists for ECO needs to consider the special characteristics of pre-ECO netlists. These netlists often contain incomplete or erroneous DFT logic, necessitating the use of fault-tolerant parsing techniques. The system employs a multi-level fault-tolerance mechanism: syntax-level fault-tolerance handles syntax errors and incomplete statements; semantic-level fault-tolerance handles type mismatches and undefined signals; and structural-level fault-tolerance handles missing modules and connection errors.

[0083] Syntax-level fault tolerance employs an error recovery algorithm. When encountering a syntax error, the system attempts various recovery strategies: skipping the erroneous statement and continuing parsing; inserting potentially missing syntax elements; and inferring user intent based on context. For example, if an incomplete module instantiation statement is encountered, the system automatically completes the missing port connection based on the module definition.

[0084] Semantic-level fault tolerance involves type inference and signal reconstruction. When the system detects an undefined signal, it infers its type and bit width based on its usage context. For example, if a signal is used as a clock input, the system automatically marks it as a clock signal; if a signal is connected to the data inputs of multiple flip-flops, the system infers it as a data signal.

[0085] Structural-level fault tolerance processing is the most complex, involving module reconstruction and connection repair; the system maintains a module library that contains standard implementations of common DFT modules. When a DFT module is detected to be missing, the system will select a suitable replacement module from the module library.

[0086] Step S3: extracting DFT-related structures and logic signals from the DFT reference netlist.

[0087] The DFT-related structure includes a compression / decompression module and an on-chip clock management module, and the logic signal includes a controllable clock signal, a controllable reset signal and a scan enable signal.

[0088] Extracting DFT-related structures and logic signals using a pattern matching algorithm requires a large library of DFT structure templates, including: various types of scan trigger templates (D flip-flops, JK flip-flops, SR flip-flops, etc.); compressor templates with different configurations (8:1, 16:1, 32:1, etc.); different types of decompressor templates (LFSR, phase shifter, hybrid, etc.); and clock control logic templates (clock selector, clock gating, clock divider, etc.).

[0089] Each template contains a detailed structural description and matching rules. For example, for an 8:1 compressor template, the system will look for a structural pattern that contains 8 input ports, 1 output port, and 7 XOR gates inside.

[0090] The signal extraction process utilizes signal flow analysis. Starting from the identified DFT structure, the system traces the complete path of the relevant signal. For example, starting from the scan_enable signal, the system traces its path to each scan flip-flop, recording all logic gates and connections along the way.

[0091] For the compressor, the system needs to identify its compression ratio, compression algorithm, input and output port configuration, and other information. Common compression algorithms include simple XOR compression, weighted XOR compression, and parity check compression. The system analyzes the compressor's internal structure to determine the specific algorithm to use.

[0092] For example, for a 16:1 weighted XOR compressor, the system identifies 16 input ports (scan_out_0 to scan_out_15) and one output port (compressed_out). The internal structure consists of 15 XOR gates, each with different input weights. The system extracts the complete weight matrix to provide a reference for subsequent repair operations.

[0093] For the decompressor, the system needs to identify parameters such as its decompression ratio, seed value, feedback polynomial, etc. Taking the LFSR type decompressor as an example, the system will analyze its number of triggers, feedback connection method, output tap position, etc. For an 8-bit LFSR decompressor, the system will extract the feedback polynomial (such as ), initial seed value (such as 8'h5A), output tap configuration (such as output from the 1st, 3rd, 5th, 7th bit) and other parameters.

[0094] Extracting on-chip clock management modules requires analyzing clock domain partitioning and clock control logic. The system identifies all clock domains in the design, including functional clock domains (such as cpu_clk, bus_clk, and mem_clk); test clock domains (such as test_clk and scan_clk); and clock enable domains (such as various gated clocks). The system also analyzes clock switching logic, including clock selector configuration and clock enable signal control strategies.

[0095] Extracting logic signals involves signal classification and attribute analysis. Extracting controllable clock signals requires distinguishing between different types of clocks: master clock signals originate directly from the clock source; derived clock signals are generated through frequency division or multiplication; and gated clock signals are influenced by control signals. The system analyzes each clock signal's characteristics, including frequency, duty cycle, and phase relationship.

[0096] Extracting controllable reset signals requires analyzing the reset tree structure and reset strategy. The system will identify: global reset signals affect the entire design; local reset signals only affect specific modules; and conditional reset signals are triggered based on specific conditions. The complete path of the scan_enable signal from the top-level port to each scan flip-flop must be traced, including: the signal's fan-out structure (one-to-many distribution); the signal's logical processing (inversion, AND gate, OR gate, etc.); and the signal's timing relationship (relative timing with the clock signal). For example, in a complex SoC design, the scan_enable signal may be distributed to thousands of scan flip-flops via multi-level buffers. The system must establish a complete signal distribution tree, recording the delay and load information for each branch.

[0097] Step S4: performing a DFT DRC check on the DFT pre-ECO netlist according to the extracted DFT structure and logic signals to identify error types.

[0098] The DFT DRC check includes: DFT structure or logic signal connection check; check of the number of registers on the scan chain; check of drive signals such as clock and reset signals of the registers on the scan chain.

[0099] The system maintains over 500 DFT design rules, ranging from simple connection rules to complex timing constraints. For example, rule DFT_001 stipulates that "each scan flip-flop must have clear scan_in and scan_out connections"; rule DFT_075 stipulates that "the number of compressor inputs must match the number of scan chains"; and rule DFT_156 stipulates that "clock gating logic must be disabled in test mode."

[0100] The system represents the netlist as a directed graph, with nodes representing logic cells and edges representing signal connections. Using depth-first search (DFS) and breadth-first search (BFS) algorithms, the system detects: dangling nodes (nodes with no input or output connections); loops (connections that could cause combinational logic loops); unreachable nodes (nodes unreachable from the primary input); and redundant connections (unnecessary connections that do not affect functionality).

[0101] The corresponding error pattern library contains various common DFT error patterns and their characteristics. For example, the characteristic of a "scan chain break" error is that the scan_out signal of a flip-flop is not connected to the scan_in signal of the next flip-flop; the characteristic of a "clock domain error" is that the scan flip-flop uses the wrong clock signal; and the characteristic of a "reset logic error" is that the reset signal of the scan flip-flop is incorrectly connected.

[0102] Step S5: repairing DFT structure and DFT DRC violations in the DFT pre ECO netlist according to the inspection result.

[0103] The repair operation makes the DFT logic in the repaired netlist consistent with the DFT logic in the DFT reference netlist, and supports two operation modes: automatic ECO and user-instruction-based ECO.

[0104] Step S6: Perform ECO operations after uplink and downlink based on the repaired netlist.

[0105] Up and down chain ECO operation means that after the current design level is repaired, it needs to be propagated upward to the parent level and downward to the child level to ensure the consistency of the entire design hierarchy.

[0106] Upward propagation (uplinking) handles the impact of modifications at the current level on parent levels. For example, if a new DFT port is added at the module level, a corresponding port connection must be added at the chip level. The system analyzes the hierarchy, identifies the parent module that needs to be modified, and automatically generates the corresponding modification instructions.

[0107] The specific chain operation process is as follows: the port change analysis system analyzes the port changes of the current module, including adding ports, deleting ports, renaming ports, etc.; the parent module positioning system locates all parent modules that instantiate the current module in the design hierarchy; the connection update system updates the instantiation connection of the current module in the parent module to ensure the correctness of the port connection; the constraint propagation system propagates the timing constraints, area constraints, etc. of the current module to the parent module.

[0108] Downward propagation (downlinking) handles the impact of changes made at the current level on sub-levels. For example, if you change the clock distribution strategy, you need to ensure that all sub-modules use the correct clock signal. The system recursively analyzes all sub-modules and makes the appropriate changes.

[0109] The specific downlink operation process is as follows: the parameter transfer system passes the modified parameters to all sub-modules, including clock frequency, reset polarity, scan mode, etc.; the interface update system updates the interface connection with the sub-module to ensure the correctness of signal transmission; the constraint delivery system delivers the upper-level constraint requirements to the sub-module, including timing requirements, power consumption requirements, etc.; the consistency check system checks whether the modifications of all sub-modules are consistent and whether there are conflicts.

[0110] Step S7: Generate a repaired DFT netlist and provide a comparison report.

[0111] The report contains comparative information in multiple aspects: structure comparison shows added, deleted, and modified DFT structures; connection comparison shows changes in signal connections; performance comparison shows the performance difference before and after repair; and quality comparison shows the improvement in DRC check results.

[0112] The present invention is described by way of specific embodiments. It should be understood by those skilled in the art that various modifications and equivalent substitutions may be made to the present invention without departing from the scope of the present invention. In addition, various modifications may be made to the present invention for specific circumstances or materials without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed, but is intended to include all embodiments falling within the scope of the claims of the present invention.

Claims

1. A DFT ECO system, characterized in that: The system includes: a first input module, a second input module, a DFT structure extraction module, a DFT inspection module, a DFT repair module, a DFT ECO module, and an output module, wherein the first input module and the second input module are respectively connected to the DFT structure extraction module; The first input module is used to receive a DFT reference netlist input by a user as first input information, wherein the DFT reference netlist is a netlist with complete DFT logic and can be detected by an ATPG tool; The second input module is used to receive a DFT pre ECO netlist to be ECO input by a user as second input information, wherein the DFT pre ECO netlist is a netlist of DFT logic that needs to be repaired; The DFT structure extraction module is used to extract DFT related structures and logic signals from the DFT reference netlist; The DFT checking module is connected to the DFT structure extraction module and is used to perform DFT DRC checking on the DFT pre ECO netlist according to the extracted DFT structure and logic signals to identify error types; The DFT repair module is connected to the DFT check module and is used to repair DFT structure and DFT DRC violations in the DFTpre ECO netlist according to the identified error type; The DFT ECO module is connected to the DFT repair module and is used to perform ECO operations after uplink and downlink based on the repaired netlist; The output module is connected to the DFT ECO module and is used to generate a repaired DFT netlist and provide a comparison report.

2. A DFT ECO system according to claim 1, characterized in that: The DFT-related structure includes a compression / decompression module and an on-chip clock management module, and the logic signal includes a controllable clock signal, a controllable reset signal and a scan enable signal.

3. A DFT ECO system according to claim 2, characterized in that: The DFT inspection module performs DFTDRC inspection including: DFT structure or logic signal connection check; Check the number of registers on the scan chain; Check the drive signals of the clock and reset signals of the registers on the scan chain.

4. A DFT ECO system according to claim 3, characterized in that: The DFT repair module performs repairs according to the inspection result, so that the DFT logic in the repaired netlist is consistent with the DFT logic in the DFT reference netlist.

5. The DFT ECO system according to claim 4, characterized in that: The DFT ECO module supports two operation modes: automatic ECO and ECO based on user instructions.

6. The DFT ECO system according to claim 5, characterized in that: The comparison report generated by the output module includes scan chain length comparison, statistics on the number of newly added / deleted registers, and DFT DRC check results.

7. A DFT ECO method, implemented based on the system according to any one of claims 1 to 6, characterized in that: The method comprises the following steps: Step S1, receiving a DFT reference netlist input by a user as first input information, wherein the DFT reference netlist is a netlist with complete DFT logic and can be tested by an ATPG tool; Step S2, receiving a DFT pre-ECO netlist to be ECO input by a user as second input information, wherein the DFT pre-ECO netlist is a netlist of DFT logic that needs to be repaired; Step S3, extracting DFT-related structures and logic signals from the DFT reference netlist; Step S4, performing a DFT DRC check on the DFT pre-ECO netlist according to the extracted DFT structure and logic signals to identify error types; Step S5, repairing DFT structure and DFT DRC violations in the DFT pre ECO netlist according to the inspection results; Step S6, performing ECO operations after uplink and downlink based on the repaired netlist; Step S7: Generate a repaired DFT netlist and provide a comparison report.

8. The DFT ECO method according to claim 7, characterized in that: The DFT-related structure includes a compression / decompression module and an on-chip clock management module, and the logic signal includes a controllable clock signal, a controllable reset signal and a scan enable signal.

9. The DFT ECO method according to claim 8, characterized in that: The DFT DRC inspection content includes: DFT structure or logic signal connection check; Check the number of registers on the scan chain; Check the drive signals of the clock and reset signals of the registers on the scan chain.

10. The DFT ECO method according to claim 9, characterized in that: The repair operation makes the DFT logic in the repaired netlist consistent with the DFT logic in the DFT reference netlist, and supports two operation modes: automatic ECO and user-instruction-based ECO.

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