PROM programmer and control method

Abstract

The invention discloses a PROM (Programmable Read Only Memory) programmer and a control method. The PROM programmer comprises an upper computer application program and a PROM programming board, and can realize programming of an anti-fuse PROM. Through the matching and cooperation of the upper computer application program and the power supply module, the voltage of different programming stages and other function operations can be adjusted in real time, and an error address can be reprogrammed, so that the repeated programming of the programmed address is avoided, the programming success rate of the anti-fuse PROM is greatly improved, and the programming efficiency of the anti-fuse PROM is improved. Double verification of data can be realized through a four-segment programming algorithm under different voltage conditions and through two times of full-chip backward reading in the algorithm. The PROM programmer is comprehensive in verification function and high in programming success rate, and has important significance in improving the programming success rate and accuracy of the anti-fuse PROM.

Description

Technical Field

[0001] The invention relates to a PROM programmer and a control method, and belongs to the field of chip application verification. Background Art

[0002] PROMs are often used to store critical information, such as boot programs for aerospace electronics systems. Due to their specialized application, it's difficult to obtain or replicate programming methods for PROMs from abroad. Furthermore, since PROMs require dedicated programmers for programming, they require the development of their own programming methods and hardware components. Current PROM product research and design faces a lack of reliable programming methods, hindering their development and application. Summary of the Invention

[0003] The technical problem solved by the present invention is: in view of the problems in the current prior art such as the low success rate of the existing PROM programming method and the incomplete verification method, a PROM programmer and a control method are proposed.

[0004] The present invention solves the above technical problems by the following technical solutions:

[0005] A PROM programmer includes a host computer control module and a PROM programming board, wherein:

[0006] The host computer control module sends the data to be programmed and the starting address to the PROM programming board; sends a readback instruction to the PROM programming board, receives the programmed data sent back by the PROM programming board, compares it with the original data file, and if there is an error in the programmed data, records the address of the error data and sends a reprogramming instruction to the PROM programming board; stops sending instructions to the PROM programming board when there is no error in the reprogramming data sent back by the PROM programming board or the reprogramming number reaches the upper limit;

[0007] The PROM programming board receives the data to be programmed and the starting address sent by the host computer control module to perform full-chip programming; after the full-chip programming is completed, it receives the read-back instruction sent by the host computer control module and sends the programmed data back to the host computer control module; it receives the reprogramming instruction sent by the host computer control module, reprograms the programmed data if there is any error data, and sends it back to the host computer control module;

[0008] When error data appears in the programmed data received by the host computer control module, the error address where the error data appears in the programmed data is recorded, and the programming status is judged according to the number of error addresses. If the number of error addresses exceeds the error address number threshold, the host computer control module directly generates a programming failure flag and sends a stop command to the PROM programming board; if the number of error addresses does not exceed the error address number threshold, the host computer control module generates a reprogramming command and sends it to the PROM programming board or sends a stop command to the PROM programming board according to the result of the reprogramming number judgment.

[0009] The reprogramming number judgment result is a comparison result of the current reprogramming number and the programming number threshold; when the PROM programming board receives the reprogramming instruction, it reprograms the data after the previous programming. If the reprogramming number exceeds the programming number threshold, the host computer control module directly generates a programming failure flag and sends a stop instruction to the PROM programming board; when the number of error addresses does not exceed the error address number threshold and the reprogramming number exceeds the programming number threshold, the host computer control module generates a reprogramming instruction and sends it to the PROM programming board;

[0010] The host computer control module compares any reprogramming data with the original data file. If there is no error data, it generates a programming success mark and sends a stop command to the PROM programming board.

[0011] The host computer control module controls the power supply voltage of the PROM programming board through a voltage control signal; when completing the reprogramming stage and entering the first full-chip readback stage, the power supply voltage delivered to the PROM programming board is increased; when completing the first full-chip readback stage and entering the second full-chip readback stage, the power supply voltage delivered to the PROM programming board is reduced.

[0012] The programming modes of the PROM programming board include JTAG programming mode and FPGA configuration mode. Before the second full-chip readback, the programming mode of the PROM programming board remains in JTAG programming mode; during the second full-chip readback, the PROM programming board is converted from JTAG programming mode to FPGA configuration mode, and the upper computer control module reads back the programmed data according to the logic timing instructions, and compares the readback result with the original data file. If there is erroneous data, a programming failure flag is generated and the program is executed; otherwise, a programming success flag is generated.

[0013] During the process of reading back the programmed data according to the logic timing instructions, the host computer control module reads back the data from DQ[0] or DQ[0] to DQ[7] according to the serial and parallel settings of the logic timing instructions; during the second full-chip readback, the power supply voltage of the PROM programming board is lower than the power supply voltage after the first generation of the programming success mark, and is higher than the power supply voltage when the PROM programming board starts programming.

[0014] The host computer control module and the PROM programming board communicate using the USB protocol and communicate through USB signals; the signal or identifier generated by the host computer control module is converted into the corresponding JTAG signal or FPGA signal according to the programming mode of the PROM programming board after the USB protocol communication conversion; the programmed data signal generated by the PROM programming board is converted into the USB protocol communication and output to the host computer control module as the JTAG signal or FPGA signal.

[0015] A control method implemented according to a PROM programmer, comprising:

[0016] Check the pin connection status of the PROM programming board and enter the programming phase after passing the inspection;

[0017] The host computer control module sends the data to be programmed and the starting address to the PROM programming board;

[0018] The PROM programming board receives the data to be programmed and the starting address sent by the host computer control module for programming;

[0019] After the PROM programming board completes the first programming, the host computer control module sends a read-back instruction to the PROM programming board;

[0020] The PROM programming board sends the programmed data back to the host computer control module according to the read-back instruction sent by the host computer control module;

[0021] The host computer control module compares the programmed data with the original data file. If there is an error in the programmed data, it records the error address of the error data and sends a reprogramming instruction to the PROM programming board.

[0022] The PROM programming board receives the reprogramming instruction sent by the host computer control module, reprograms the programmed data with erroneous data and sends it back to the host computer control module;

[0023] The host computer control module reads back the reprogramming data sent back and compares it with the original data file. If there is still erroneous data, it will repeatedly record the erroneous address and send a reprogramming instruction to the PROM programming board until there is no erroneous data in the reprogramming data sent back by the PROM programming board.

[0024] After the reprogramming phase is completed, the voltage is increased and the first full chip readback is performed. The readback result is compared with the original data file. If there is erroneous data, a programming failure flag is generated; otherwise, a programming success flag is generated.

[0025] After completing the first full-chip readback, the PROM programming board switches from JTAG programming mode to FPGA configuration mode. The host computer control module performs a second full-chip readback of the programmed data according to the logic timing instructions, and compares the readback results with the original data file. If there is erroneous data, a programming failure flag is generated; otherwise, a programming success flag is generated.

[0026] Before sending the data to be programmed and the starting address to the PROM programming board, the host computer control module checks the pin connection status of the PROM programming board through a test data stream, wherein:

[0027] The host computer control module sends a test data stream and programming mode switching instructions to the PROM programming board. After the PROM programming board switches to FPGA programming mode, the host computer control module reads back data through the DQ port of the PROM programming board and compares it with the test data stream.

[0028] After the comparison is completed, a programming mode switching instruction is sent, and the PROM programming board switches to JTAG programming mode;

[0029] Repeat the DQ port data sending and data reading until the DQ ports of all PROM programming boards are traversed.

[0030] During the second full-chip readback process, according to the serial and parallel settings of each port on the PROM programming board, all DQ ports are traversed and the readback data with the same number of ports is collected and then compared with the original data file.

[0031] The advantages of the present invention compared with the prior art are:

[0032] (1) The present invention provides a PROM programmer and control method that can realize the programming and burning of anti-fuse PROM. Through the cooperation of the host computer application and the power module, the voltage of different programming stages and other functional operations can be adjusted in real time, and the wrong address can be reprogrammed, avoiding the repetitive programming of the programmed address, greatly improving the programming success rate of the anti-fuse PROM;

[0033] (2) The present invention adopts a double verification method to ensure the correctness of programming. When the PROM is in the JTAG programming mode, the host computer sends a readback instruction to the PROM, and reads the data back to the host computer for comparison with the specified file. After completing the data verification, the host computer sends an instruction to switch the working mode to the PROM, and switches the working mode of the PROM to the FPGA configuration mode. The host computer sends a serial-parallel indication signal and a readback instruction under the FPGA configuration mode to the PROM. According to the serial or parallel indication signal, the data is read back from the DQ[0] or DQ[0]~DQ[7] port of the PROM, respectively, and the data is read back to the host computer for comparison with the specified file. After all is completed, the verification result will be given on the program interface;

[0034] (3) The present invention uses a USB data cable for communication transmission between the host computer and the programmer hardware, which can improve the stability of programming. A communication protocol conversion module is used on the PROM programming board to convert USB signals and JTAG signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The functional block diagram of the PROM programmer provided by the present invention;

[0036] Figure 2 A schematic diagram of the programming algorithm of the PROM programmer provided by the present invention;

[0037] Figure 3 A schematic diagram of a dual data verification method for a PROM programmer provided by the present invention;

[0038] Figure 4 This is a schematic diagram of a method for the PROM programmer provided by the present invention to check the connectivity of the DQ pins of the PROM. DETAILED DESCRIPTION

[0039] A PROM programmer and control method, including a host computer application and a PROM programming board, can be used to program and burn antifuse PROMs. Through the collaboration of the host computer application and a power module, real-time adjustment of voltages for different programming stages and other functional operations can be achieved. Incorrect addresses can also be reprogrammed, avoiding repeated programming of already programmed addresses. This significantly improves the antifuse PROM programming success rate. The programmer utilizes a four-stage programming algorithm under different voltage conditions, and implements dual data verification through two full-chip readbacks within the algorithm. The PROM programmer has comprehensive verification capabilities and a high programming success rate, which is of great significance for improving the antifuse PROM programming success rate and accuracy.

[0040] The PROM programmer includes a host computer control module and a PROM programming board, including:

[0041] The host computer control module sends the data to be programmed and the starting address to the PROM programming board; sends a readback instruction to the PROM programming board, receives the programmed data sent back by the PROM programming board, compares it with the original data file, and if there is an error in the programmed data, records the address of the error data and sends a reprogramming instruction to the PROM programming board; stops sending instructions to the PROM programming board when there is no error in the reprogramming data sent back by the PROM programming board or the reprogramming number reaches the upper limit;

[0042] The PROM programming board receives the data to be programmed and the starting address sent by the host computer control module to perform full-chip programming; after the full-chip programming is completed, it receives the read-back instruction sent by the host computer control module and sends the programmed data back to the host computer control module; it receives the reprogramming instruction sent by the host computer control module, reprograms the programmed data if there is erroneous data, and sends it back to the host computer control module.

[0043] When error data appears in the programmed data received by the upper computer control module, the error address where the error data appears in the programmed data is recorded, and the programming status is judged according to the number of error addresses. If the number of error addresses exceeds the error address number threshold, the upper computer control module directly generates a programming failure flag and sends a stop command to the PROM programming board; if the number of error addresses does not exceed the error address number threshold, the upper computer control module generates a reprogramming command and sends it to the PROM programming board or sends a stop command to the PROM programming board based on the result of the reprogramming number judgment.

[0044] The reprogramming number judgment result is the comparison result of the current reprogramming number and the programming number threshold; when the PROM programming board receives the reprogramming instruction, it reprograms the data after the previous programming. If the reprogramming number exceeds the programming number threshold, the host computer control module directly generates a programming failure flag and sends a stop instruction to the PROM programming board; when the number of error addresses does not exceed the error address number threshold and the reprogramming number exceeds the programming number threshold, the host computer control module generates a reprogramming instruction and sends it to the PROM programming board;

[0045] The host computer control module compares any reprogramming data with the original data file. If there is no error data, it generates a programming success mark and sends a stop command to the PROM programming board.

[0046] The upper computer control module controls the power supply voltage of the PROM programming board through a voltage control signal; when the reprogramming phase is completed and the first full-chip readback phase is entered, the power supply voltage delivered to the PROM programming board is increased; when the first full-chip readback phase is completed and the second full-chip readback phase is entered, the power supply voltage delivered to the PROM programming board is reduced.

[0047] The programming modes of the PROM programming board include JTAG programming mode and FPGA configuration mode. Before the second full-chip readback, the programming mode of the PROM programming board remains in JTAG programming mode; during the second full-chip readback, the PROM programming board switches from JTAG programming mode to FPGA configuration mode, and the upper computer control module reads back the programmed data according to the logic timing instructions, and compares the readback result with the original data file. If there is erroneous data, a programming failure flag is generated and the program is executed; otherwise, a programming success flag is generated.

[0048] When the upper computer control module reads back the programmed data according to the logic timing instructions, the data is read back from DQ[0] or DQ[0]~DQ[7] according to the serial and parallel settings of the logic timing instructions; when the whole chip is read back for the second time, the power supply voltage of the PROM programming board is lower than the power supply voltage after the programming success mark is generated for the first time, and is higher than the power supply voltage when the PROM programming board starts programming.

[0049] The host computer control module and the PROM programming board communicate using the USB protocol and communicate through USB signals; the signals or identifiers generated by the host computer control module are converted to the USB protocol communication and then converted to corresponding JTAG signals or FPGA signals according to the programming mode of the PROM programming board; the programmed data signals generated by the PROM programming board are converted to the USB protocol communication and then output to the host computer control module as JTAG signals or FPGA signals.

[0050] The control method implemented by the PROM programmer includes the following steps:

[0051] Check the pin connection status of the PROM programming board and enter the programming phase after passing the inspection;

[0052] The host computer control module sends the data to be programmed and the starting address to the PROM programming board;

[0053] The PROM programming board receives the data to be programmed and the starting address sent by the host computer control module for programming;

[0054] After the PROM programming board completes the first programming, the host computer control module sends a read-back instruction to the PROM programming board;

[0055] The PROM programming board sends the programmed data back to the host computer control module according to the read-back instruction sent by the host computer control module;

[0056] The host computer control module compares the programmed data with the original data file. If there is an error in the programmed data, it records the error address of the error data and sends a reprogramming instruction to the PROM programming board.

[0057] The PROM programming board receives the reprogramming instruction sent by the host computer control module, reprograms the programmed data with erroneous data and sends it back to the host computer control module;

[0058] The host computer control module reads back the reprogramming data sent back and compares it with the original data file. If there is still erroneous data, it will repeatedly record the erroneous address and send a reprogramming instruction to the PROM programming board until there is no erroneous data in the reprogramming data sent back by the PROM programming board.

[0059] The PROM programming board is converted from JTAG programming mode to FPGA configuration mode. The host computer control module performs a second full-chip readback of the programmed data according to the logic timing instructions, and compares the readback result with the original data file. If there is erroneous data, a programming failure flag is generated; otherwise, a programming success flag is generated.

[0060] Before sending the data to be programmed and the starting address to the PROM programming board, the host computer control module checks the pin connection status of the PROM programming board through the test data stream, where:

[0061] The host computer control module sends a test data stream and programming mode switching instructions to the PROM programming board. After the PROM programming board switches to FPGA programming mode, the host computer control module reads back data through the DQ port of the PROM programming board and compares it with the test data stream.

[0062] After the comparison is completed, a programming mode switching instruction is sent, and the PROM programming board switches to JTAG programming mode;

[0063] Repeat the DQ port data sending and data reading until the DQ ports of all PROM programming boards are traversed.

[0064] During the second full-chip readback process, according to the serial and parallel settings of each port on the PROM programming board, all DQ ports are traversed and the readback data with the same number of ports is collected and then compared with the original data file.

[0065] The following is further described in conjunction with the accompanying drawings and preferred embodiments:

[0066] In the current embodiment, the dedicated PROM programmer includes a host computer application, a PROM programming board, and a PROM daughter board. The hardware integration design is as follows:

[0067] The PROM programming board includes FPGA, communication protocol conversion module, and power supply module;

[0068] The FPGA integrates IOB, CLB, BRAM and FLASH configuration memory units; IOB is used to configure and manage the electrical standards of different ports, CLB completes the combinational logic function, BRAM realizes data caching, and FLASH configuration memory unit is used to store and solidify the FPGA program to achieve power-on configuration; FPGA relies on the ISE development environment to communicate with the JTAG protocol and complete the communication between the host computer and the power module and PROM programmer daughter board.

[0069] The communication protocol conversion module receives the USB signal sent by the host computer, converts it into a JTAG protocol signal or other serial signal and sends it to the FPGA, and converts the feedback data of the FPGA into a USB protocol signal and sends it to the host computer application.

[0070] The power module generates the voltages required for each chip, powering the PROM programming board and PROM daughter board via analog switches. A power adapter powers the power module. The power module, with the LTM4644 as its core component, also powers the dedicated PROM programmer. Two power supply systems are provided: the first power module supplies the FPGA, while the second power module provides a separate power supply for the PROM being programmed. Each power supply system is independently powered and independent of the other, with separate power-up sequencing to meet the power-up timing requirements of both the FPGA and the PROM being programmed.

[0071] The host computer sends a voltage control signal, which is transmitted through the FPGA. The relay receives the control signal and performs strobing, switching the voltage supplied to the programmed PROM to achieve the switching of the PROM working voltage.

[0072] The host computer application sends instructions to the communication protocol conversion module based on user operations, such as device connectivity check, blank check, programming, data readback for verification, storage, and checksum calculation. The communication protocol conversion module receives feedback from the FPGA to verify whether the FPGA has executed the operation instructions sent by the host computer.

[0073] Data control, data transmission, PROM working mode and voltage selection are completed according to the dedicated PROM programmer FPGA program design.

[0074] The data control program mainly includes controlling the logic timing in the FPGA configuration mode, corresponding to the DQ port verification function of the host computer.

[0075] The data transfer program primarily transfers data and JTAG instructions between the host computer and the FPGA. When the PROM is in JTAG programming mode, JTAG instructions from the host computer are sent to the PROM via the data transfer program for corresponding operations. Programming data from the host computer and readback data from the PROM are also transmitted to the PROM and the host computer application, respectively, via the data transfer program according to the JTAG protocol.

[0076] The PROM operating mode and voltage selection program primarily switches the PROM's operating mode and operating voltage. Based on control commands from the host computer, the program switches the PROM's operating mode or sends voltage control signals to the power module to activate the relays and, in turn, switch the PROM's operating voltage.

[0077] In this embodiment, a four-stage programming algorithm is used, which is implemented as follows:

[0078] The first stage, full-chip programming, is when the PROM programmer operates at 2.8 V. The host computer application program sends the data to be programmed and the starting address to the programmer. After the FPGA transmits the data, the PROM receives the data and begins programming.

[0079] The second stage, reprogramming, involves the PROM programmer operating at 2.8V. The host computer application sends a readback command to the programmer, which performs a full chip readback, compares the data file, and records the addresses where errors occur. If there are too many error addresses, the program terminates prematurely, reports a programming failure, and skips the subsequent stages. Otherwise, the error addresses are reprogrammed. This step is repeated several times. If errors persist after reaching the maximum number of times, a programming failure is reported, and the subsequent stages are skipped.

[0080] The third stage is the first full-chip readback verification / JTAG readback verification. The PROM programmer operates at 3.6V. The host computer application sends a readback command to the programmer, which performs a full-chip readback. The program then compares the readback with the data file and records the total number of bytes with errors. If any errors are found, the program is reported as failed and the subsequent stages are skipped.

[0081] In the fourth phase, the second full-chip readback verification / DQ port readback verification phase, the PROM programmer's operating voltage is 3.3V. The host computer application sends an operating mode switch command to the programmer, switching it from JTAG programming mode to FPGA configuration mode. It then sends a logical timing command to read back the data. Based on the serial and parallel settings, the data is read back from the PROM's DQ[0] or DQ[0] to DQ[7] and compared with the data file. If there is an error, the programming fails; otherwise, the programming succeeds.

[0082] The power control module adjusts different voltages according to different operations of the PROM in the following ways:

[0083] When the host computer sends JTAG programming mode commands, it also sends voltage control commands to the power module. The power module adjusts the supply voltage to the PROM based on the control signals. Non-programming operations of the programmer all use 3.3V. Programming operations use different voltages depending on the stage: the first and second stages of programming use 2.8V, the third stage uses 3.6V, and the fourth stage uses 3.3V.

[0084] The double data verification of the programmed PROM is implemented as follows:

[0085] The programmer's verification is double verification, which reads the data in the PROM from two data channels by switching the working mode of the PROM.

[0086] First, the host computer sends a readback instruction in JTAG programming mode to the PROM, and the data is read back to the host computer application for data comparison with the specified file.

[0087] After completing data verification on the specified sub-chip, the host computer sends a command to switch the operating mode to the PROM, switching the PROM's operating mode to FPGA configuration mode. The host computer sends a serial-parallel indication signal and a readback command under FPGA configuration mode to the PROM. Based on the serial-parallel settings of the current sub-chip, the host computer reads back data from the PROM's DQ[0] or DQ[0]-DQ[7] ports. The data is then sent back to the host computer for comparison with the specified file. After both verifications are complete, the verification results are displayed on the program interface.

[0088] The device connectivity check operation checks the connection status of the PROM's DQ pins as follows:

[0089] The host computer sends specific test data to the PROM, followed by a mode-switch command, switching the PROM's operating mode to FPGA configuration mode. The host computer then reads back the data from the PROM's DQ pins and compares it with the sent test data. After comparison, it sends a mode-switch command, switching the PROM's operating mode to JTAG programming mode. This process repeats once, checking each of the PROM's four DQ pins twice. Upon completion, the program displays the results.

[0090] The present invention uses a communication protocol conversion module, and the host computer and the programmer use the USB protocol to communicate. The implementation method is as follows:

[0091] The host computer and the PROM programming board use USB signals for communication. The USB signals sent by the host computer are converted into JTAG signals or serial data and control signals through the communication protocol conversion module and input to the FPGA; the JTAG signals or other serial data inputs sent by the PROM received by the FPGA are converted into USB signals through the communication protocol conversion module and sent to the host computer.

[0092] The host computer application saves the operation process and operation results when programming the PROM, thereby recording and archiving the entire programming process.

[0093] Example 1:

[0094] like Figure 1 As shown, the entire programming process is as follows:

[0095] 1) Connect the cables. Use a USB cable to connect the host computer and the dedicated PROM programmer. Connect the power adapter to the dedicated PROM programmer.

[0096] 2) PROM placement: According to the pin 1 mark of the PROM to be programmed, correctly place the PROM to be programmed into the dedicated PROM programmer and tighten the socket to ensure good pin connectivity.

[0097] 3) Open the software. Open the programmer application software on the host computer.

[0098] 4) Power on. Turn on the dedicated PROM programmer. The indicator light will light up, indicating successful power-on.

[0099] 5) Device connectivity check. Click the "Device Connectivity Check" button to send the IDCODE check and pin connectivity check instructions. The host computer sends a USB protocol signal to the programmer. After receiving it, the communication protocol conversion module in the programmer converts it into a JTAG protocol signal or a serial control signal according to the current working mode of the PROM and sends it to the FPGA to perform corresponding operations. The programmed PROM returns the test results of the IDCODE and DQ pins according to the instructions and sends them to the FPGA. The inspection results are converted into USB signals by the communication protocol conversion module and sent to the host computer. Based on the results, the application determines the pin connectivity between the programmed PROM and the dedicated PROM programmer.

[0100] 6) Check for blank. Click the "Check Blank" button to send the "Check Blank" command, and the dedicated PROM programmer will perform a blank read test on the device to be programmed. First, read back the value of the PROM's BLANK REG register to determine whether it has been programmed. If it has been programmed, the subsequent stages will be skipped and the sub-chip will be directly reported as "not blank". If it has not been programmed, the program will continue to check whether the data stored in all address bits are all 0. If all are 0, the sub-chip will be reported as "blank", otherwise it will be reported as "not blank". Only when all four sub-chips of the PROM are "blank" can they be used for programming operations.

[0101] 7) Load File. Click the "Load File" button to load the target file address into the application's file address box. When the programmer performs operations such as programming and file verification that require reading the target file data, the application will read the target file data based on the address in the file address box.

[0102] 8) Programming. Click the "Program" button to send the corresponding instructions and relevant data to the PROM programmer in sequence according to the four-stage programming algorithm of this design. If programming is successful, "Programming Successful" will be displayed on the application interface, along with the serial and parallel settings of the current sub-chip and the data checksum. If programming fails, "Programming Failed" will be displayed on the application interface.

[0103] 9) Data Verification. Click the "Data Verification" button to perform data verification using the dual data verification method of this design. If the verification passes, "Verification Passed" will be displayed on the application interface; if the verification fails, "Verification Failed" will be displayed on the application interface, along with the number of error bytes for both verification methods.

[0104] 10) Calculate the checksum. Click the "Calculate Checksum" button and send the "Read Back" command. The application will calculate the checksum based on the readback data and display it on the application interface.

[0105] 11) Read back data. Click the "Read Back and Save" button and send the "Read Back" command. The application will save the read back data as a bin format file.

[0106] 12) View the usercode. Click the "View Configuration" button and send the "Read Usercode" command. The application will display the usercode of the sub-chip on the application interface and the serial and parallel settings.

[0107] like Figure 2 As shown, the dedicated PROM programmer uses a four-stage programming algorithm to program data.

[0108] In the first stage, the operating voltage of the PROM programmer is 2.8 V. The host computer application sends the data to be programmed and the first address to the programmer. After the FPGA transmits the data, the PROM receives the data and starts programming.

[0109] In the second stage, the PROM programmer operates at 2.8V. The host computer application sends a readback command to the programmer, which performs a full chip readback, compares it with the data file, and records the addresses where errors occur. If there are too many error addresses, the program terminates prematurely, reports a programming failure, and skips the subsequent stages. Otherwise, the error addresses are reprogrammed. This step is repeated several times. If errors persist after reaching the maximum number of times, a programming failure is reported, and the subsequent stages are skipped.

[0110] In the third stage, the PROM programmer operates at 3.6V. The host computer application sends a readback command to the programmer, which performs a full chip readback, compares it with the data file, and records the total number of bytes with errors. If any errors are found, the programming is reported as failed, and the subsequent stages are skipped.

[0111] In the fourth stage, the PROM programmer operates at 3.3V. The host computer application sends a mode switch command to the programmer, causing it to switch from JTAG programming mode to FPGA configuration mode. It then sends a logic timing command to read back data. Based on the serial-parallel settings, data is read back from DQ[0] or DQ[0] to DQ[7] of the PROM and compared with the data file. If there is an error, the programming fails; otherwise, it succeeds.

[0112] like Figure 3 As shown, the dedicated PROM programmer uses a double data verification method to perform data verification.

[0113] First, the host computer sends a readback instruction in JTAG programming mode to the PROM, and the data is read back to the host computer application for data comparison with the specified file.

[0114] After completing data verification on the specified sub-chip, the host computer sends a command to switch the operating mode to the PROM, switching the PROM's operating mode to FPGA configuration mode. The host computer sends a serial-parallel indication signal and a readback command under FPGA configuration mode to the PROM. Based on the serial-parallel setting of the current sub-chip, the host computer reads back data from the PROM's DQ[0] or DQ[0]-DQ[7] ports. The data is read back to the host computer and compared with the specified file.

[0115] After the two checks are completed, the verification results will be given in the program interface.

[0116] like Figure 4 As shown, a dedicated PROM programmer checks the connectivity of the DQ pins of the PROM.

[0117] When the PROM is in JTAG programming mode, the host computer application sends specific test data to the PROM, followed by a command to switch the operating mode to FPGA configuration mode. The host computer then reads back the data on the PROM's DQ pins and compares it with the sent test data. After comparison, it sends a command to switch the operating mode to JTAG programming mode. This step is repeated once, checking each of the PROM's four DQ pins twice. Once all checks are complete, the PROM's connectivity is determined based on the IDCODE results, and the results are displayed on the program interface.

[0118] In summary, the present invention provides a specialized PROM programmer with strong targeting, comprehensive verification capabilities, and a high programming success rate. It can program, burn, and perform other readback operations on an antifuse PROM read-only memory. This system utilizes an FPGA as its core, with peripheral components such as communication protocol conversion, power control, configuration, and host computer application software. This comprehensive programming system is of great significance for resolving antifuse PROM programming challenges and improving programming success rates.

[0119] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention.

[0120] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A PROM programmer, characterized in that: It includes host computer control module and PROM programming board, including: The host computer control module sends the data to be programmed and the starting address to the PROM programming board; sends a readback instruction to the PROM programming board, receives the programmed data sent back by the PROM programming board, compares it with the original data file, and if there is an error in the programmed data, records the address of the error data and sends a reprogramming instruction to the PROM programming board; stops sending instructions to the PROM programming board when there is no error in the reprogramming data sent back by the PROM programming board or the reprogramming number reaches the upper limit; The PROM programming board receives the data to be programmed and the starting address sent by the host computer control module to perform full-chip programming; after the full-chip programming is completed, it receives the read-back instruction sent by the host computer control module and sends the programmed data back to the host computer control module; it receives the reprogramming instruction sent by the host computer control module, reprograms the programmed data if there is erroneous data, and sends it back to the host computer control module.

2. A PROM programmer according to claim 1, characterized in that: When error data appears in the programmed data received by the host computer control module, the error address where the error data appears in the programmed data is recorded, and the programming status is judged according to the number of error addresses. If the number of error addresses exceeds the error address number threshold, the host computer control module directly generates a programming failure flag and sends a stop command to the PROM programming board; if the number of error addresses does not exceed the error address number threshold, the host computer control module generates a reprogramming command and sends it to the PROM programming board or sends a stop command to the PROM programming board according to the result of the reprogramming number judgment.

3. A PROM programmer according to claim 2, characterized in that: The reprogramming number judgment result is a comparison result of the current reprogramming number and the programming number threshold; when the PROM programming board receives the reprogramming instruction, it reprograms the data after the previous programming. If the reprogramming number exceeds the programming number threshold, the host computer control module directly generates a programming failure flag and sends a stop instruction to the PROM programming board; when the number of error addresses does not exceed the error address number threshold and the reprogramming number exceeds the programming number threshold, the host computer control module generates a reprogramming instruction and sends it to the PROM programming board; The host computer control module compares any reprogramming data with the original data file. If there is no error data, it generates a programming success mark and sends a stop command to the PROM programming board.

4. A PROM programmer according to claim 3, characterized in that: The host computer control module controls the power supply voltage of the PROM programming board through a voltage control signal; when completing the reprogramming stage and entering the first full-chip readback stage, the power supply voltage delivered to the PROM programming board is increased; when completing the first full-chip readback stage and entering the second full-chip readback stage, the power supply voltage delivered to the PROM programming board is reduced.

5. A PROM programmer according to claim 4, characterized in that: The programming modes of the PROM programming board include JTAG programming mode and FPGA configuration mode. Before the second full-chip readback, the programming mode of the PROM programming board remains in JTAG programming mode; during the second full-chip readback, the PROM programming board is converted from JTAG programming mode to FPGA configuration mode, and the upper computer control module reads back the programmed data according to the logic timing instructions, and compares the readback result with the original data file. If there is erroneous data, a programming failure flag is generated and the program is executed; otherwise, a programming success flag is generated.

6. A PROM programmer according to claim 5, characterized in that: During the process of reading back the programmed data according to the logic timing instructions, the host computer control module reads back the data from DQ[0] or DQ[0] to DQ[7] according to the serial and parallel settings of the logic timing instructions; during the second full-chip readback, the power supply voltage of the PROM programming board is lower than the power supply voltage after the first generation of the programming success mark, and is higher than the power supply voltage when the PROM programming board starts programming.

7. A PROM programmer according to claim 5, characterized in that: The host computer control module and the PROM programming board communicate using the USB protocol and communicate through USB signals; the signal or identifier generated by the host computer control module is converted into the corresponding JTAG signal or FPGA signal according to the programming mode of the PROM programming board after the USB protocol communication conversion; the programmed data signal generated by the PROM programming board is converted into the USB protocol communication and output to the host computer control module as the JTAG signal or FPGA signal.

8. A control method implemented by the PROM programmer according to claim 7, characterized in that include: Check the pin connection status of the PROM programming board and enter the programming phase after passing the inspection; The host computer control module sends the data to be programmed and the starting address to the PROM programming board; The PROM programming board receives the data to be programmed and the starting address sent by the host computer control module for programming; After the PROM programming board completes the first programming, the host computer control module sends a read-back instruction to the PROM programming board; The PROM programming board sends the programmed data back to the host computer control module according to the read-back instruction sent by the host computer control module; The host computer control module compares the programmed data with the original data file. If there is an error in the programmed data, it records the error address of the error data and sends a reprogramming instruction to the PROM programming board. The PROM programming board receives the reprogramming instruction sent by the host computer control module, reprograms the programmed data with erroneous data and sends it back to the host computer control module; The host computer control module reads back the reprogramming data sent back and compares it with the original data file. If there is still erroneous data, it will repeatedly record the erroneous address and send a reprogramming instruction to the PROM programming board until there is no erroneous data in the reprogramming data sent back by the PROM programming board. After the reprogramming phase is completed, the voltage is increased and the first full chip readback is performed. The readback result is compared with the original data file. If there is erroneous data, a programming failure flag is generated; otherwise, a programming success flag is generated. After completing the first full-chip readback, the PROM programming board switches from JTAG programming mode to FPGA configuration mode. The host computer control module performs a second full-chip readback of the programmed data according to the logic timing instructions, and compares the readback results with the original data file. If there is erroneous data, a programming failure flag is generated; otherwise, a programming success flag is generated.

9. The control method according to claim 8, characterized in that: Before sending the data to be programmed and the starting address to the PROM programming board, the host computer control module checks the pin connection status of the PROM programming board through a test data stream, wherein: The host computer control module sends a test data stream and programming mode switching instructions to the PROM programming board. After the PROM programming board switches to FPGA programming mode, the host computer control module reads back data through the DQ port of the PROM programming board and compares it with the test data stream. After the comparison is completed, a programming mode switching instruction is sent, and the PROM programming board switches to JTAG programming mode; Repeat the DQ port data sending and data reading until the DQ ports of all PROM programming boards are traversed.

10. The control method according to claim 8, characterized in that: During the second full-chip readback process, according to the serial and parallel settings of each port on the PROM programming board, all DQ ports are traversed and the readback data with the same number of ports is collected and then compared with the original data file.

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