LDPC (Low Density Parity Check) encoding and decoding system and method for high-density tape storage

Abstract

The invention discloses an LDPC (Low Density Parity Check) coding and decoding system and method for high-density tape storage, and the system comprises a main controller which is used for scheduling coding and decoding mode switching and module cooperative control; the storage and calculation integrated array is used for executing zero-carrying storage calculation; the ping-pong buffer framework is composed of an input buffer module Buffer A and an output buffer module Buffer B; the dynamic code length extension module is used for reconstructing a cascade link; the preprocessing module is used for converting the noisy code word into a log likelihood ratio (LLR) value; the hard decision module is used for converting the VN message into user data; the main controller is connected with all the modules through a control bus, and the dynamic code length extension module controls the power state and interconnection topology of the sub-arrays. According to the LDPC coding and decoding system and method based on the storage and calculation integrated array, zero-carrying calculation is achieved, iterative decoding is accelerated through a ping-pong buffer architecture, and the code length is flexibly configured through the dynamic code length extension module, the coding and decoding efficiency of high-density tape storage is improved, delay and energy consumption are reduced, meanwhile, multi-code-length self-adaption is supported, and high performance and flexibility are considered.

Description

Technical Field

[0001] The present invention relates to the technical field of magnetic tape storage encoding and decoding, and in particular to an LDPC encoding and decoding system and method for high-density magnetic tape storage. Background Art

[0002] As the core carrier of cold data storage, high-density tape storage technology has achieved significant breakthroughs in storage density, capacity, and cost efficiency in recent years. Taking the latest generation LTO-10 standard as an example, its single-cartridge native capacity reaches 45TB (112.5TB after compression), the track density exceeds 250kBPI (250,000 bits per inch), and the linear recording density is as high as 800kbpi (800,000 bits per inch). Enterprise-level tape libraries further increase sequential read and write speeds to 750MB / s (uncompressed) through multi-channel parallel read and write technology, supporting the cold data archiving needs of exabyte-level data centers. However, with the exponential growth of storage density, tape systems face the following key challenges:

[0003] 1. Very high bit error rate (BER) and long burst errors

[0004] The physical storage mechanism of magnetic tape makes it extremely sensitive to mechanical vibration, head wear, and environmental interference. Unstable contact between the head and the tape can cause magnetic field distortion in localized areas, leading to long burst errors (continuous errors exceeding 1000 bits in length). For example, in an area with uneven magnetic powder coating, a single head jitter can cause up to 2048 consecutive bits of errors, far exceeding the error correction limit of traditional error-correcting codes (such as RS codes). Laboratory tests have shown that the raw bit error rate (RawBER) of uncompressed tape can reach 1e-4 (i.e., one error per 10,000 bits) under typical operating conditions, but can deteriorate to 1e-3 in extreme environments (such as high humidity and strong magnetic field interference).

[0005] To meet the reliability requirements of enterprise-class storage (BER < 1e-20), error-correcting codes must strike a balance between coding gain and hardware efficiency. Taking RS codes as an example, RS (255, 239) codes can only correct 8-byte (64-bit) errors per codeword. However, in tape storage scenarios, a single codeword burst error can span 32 physical sectors (512 bytes per sector), rendering the RS code completely ineffective. Although LDPC codes can improve error correction capabilities through long code lengths (e.g., 8192 bits), their sparse matrix operations place stringent demands on the hardware architecture: in traditional ASIC solutions, a single encoding and decoding pass requires over 10^9 floating-point operations, resulting in an energy efficiency ratio of less than 5TOPS / W, making it difficult to meet the energy efficiency constraints of multi-channel tape controllers (power consumption < 10W).

[0006] 2. Dielectric aging effects and long-term reliability degradation

[0007] The design life of magnetic tapes is usually more than 30 years, but their magnetic media is subject to irreversible chemical and physical degradation during long-term storage:

[0008] Magnetic particle oxidation: Cobalt-based magnetic particles oxidize in a hot and humid environment to form non-magnetic oxides, resulting in a signal amplitude attenuation of >30% and a 6dB decrease in the signal-to-noise ratio (SNR).

[0009] Adhesive degradation: Polyester adhesive chains break under ultraviolet light or high temperature, causing the magnetic powder layer to fall off and form micron-sized voids, resulting in local signal loss.

[0010] Mechanical stress accumulation: Repeated winding and tension cause cracks in the magnetic layer, and the average annual defect density increases by 8%.

[0011] Research has shown that the bit error rate (BER) of magnetic tape increases exponentially with storage age. In accelerated aging experiments (85°C / 85% humidity), the BER of a certain brand of magnetic tape increased from an initial 1e-5 to 1e-3 after five years of storage, increasing the error correction requirements 100-fold. More critically, in the later stages of aging, the length of burst errors increases from 1000 bits to 5000 bits. Traditional fixed-redundancy coding schemes (such as RS codes), unable to dynamically adjust the bit rate and number of iterations, are forced to increase redundancy from 15% to 25%, resulting in a 40% loss in effective capacity.

[0012] 3. The triangular contradiction between energy efficiency, density and cost

[0013] Enterprise-class tape libraries must achieve ultra-high-density storage within a limited power budget (typically less than 100W / rack unit). This poses two challenges to the hardware efficiency of error correction codes:

[0014] The game between redundancy and storage density:

[0015] Traditional RS codes (redundancy of 15%-20%) significantly reduce effective capacity. For example, the native capacity of an LTO-9 tape is 18TB, but using RS (240, 224) codes reduces the effective capacity to 15.3TB (a 14.5% loss). In contrast, LDPC codes (e.g., n = 8192, R = 0.9) can reduce redundancy to 10%, but require hardware support for ultra-large-scale sparse matrix operations, resulting in a surge in chip area and power consumption.

[0016] Balance between energy efficiency and computational complexity:

[0017] Taking a typical LDPC (4096, 3277) code as an example, a single encoding pass requires 2.1×10^6 multiplication-addition operations, while decoding (10 iterations) requires 4.2×10^7 operations. In traditional ASIC solutions, data transfer accounts for as much as 80% of energy consumption, resulting in an overall energy efficiency of only 3.8 TOPS / W. If implemented using an FPGA, power consumption could exceed 25W, far exceeding the heat dissipation capacity of a tape drive.

[0018] Conflict between chip area and multi-channel expansion:

[0019] To achieve multi-channel parallel encoding and decoding (such as 32 channels), traditional solutions require stacking multiple ASIC chips, resulting in low area efficiency (<0.5Gb / mm 2 For example, a certain tape controller uses four 28nm ASIC chips to achieve 12.8Gbps throughput, with a total area of ​​160mm. 2 , the cost is extremely high. Summary of the Invention

[0020] The purpose of the present invention is to overcome the deficiencies of the prior art. To achieve the above purpose, an LDPC encoding and decoding system and method for high-density magnetic tape storage are adopted to solve the problems raised in the above background technology.

[0021] The first technical solution: an LDPC encoding and decoding system for high-density tape storage, including a main controller, a storage and computing array, a ping-pong buffer architecture, a dynamic code length extension module, a preprocessing module, and a hard decision module;

[0022] The main controller is used to schedule codec mode switching and module collaborative control;

[0023] The storage-computing integrated array includes SOT-MRAM storage units and a reconfigurable interconnection network. The SOT-MRAM units store a fixed QC-LDPC check matrix H. The storage-computing integrated array reuses the check matrix H to perform zero-transfer in-memory calculations.

[0024] The ping-pong buffer architecture consists of an input buffer module BufferA and an output buffer module BufferB, which alternately stores check node CN messages and variable node VN messages in decoding mode and combines information bits and check bits in encoding mode;

[0025] The dynamic code length extension module includes a code length analyzer, a power gating unit, and an interconnection network controller, which is used to dynamically activate / sleep subarrays and reconstruct cascade links according to the target code length;

[0026] The pre-processing module converts the noisy codewords read from the tape into log-likelihood ratio (LLR) values ​​and inputs the LLR values ​​into the input buffer module BufferA in the decoding mode;

[0027] The hard decision module converts the final VN message into binary user data in decoding mode;

[0028] The main controller is connected to each module via a control bus, the storage and computing integrated array is bidirectionally connected to the input buffer module BufferA and the output buffer module BufferB, and the dynamic code length extension module controls the power status and interconnection topology of the sub-array.

[0029] As a further solution of the present invention: the input buffer module BufferA receives and caches user data, and then inputs the data into the storage and computing integrated array after smoothing in the input buffer;

[0030] The storage and computing integrated array generates check bits in parallel based on the pre-stored check matrix H, and Buffer B combines the check bits with the information bits in Buffer A into a complete LDPC codeword and outputs it to the tape device.

[0031] As a further solution of the present invention: the integrated storage and computing array and ping-pong buffer architecture perform layered belief propagation BP iterative decoding, including:

[0032] CN update phase: VN messages are read from the input buffer module BufferA, the storage and computing array calculates the CN messages and writes them to the output buffer module BufferB;

[0033] VN update phase: CN messages are read from the output buffer module BufferB, the storage and computing array updates the VN messages and writes them into the input buffer module BufferA;

[0034] The CN update and VN update are executed cyclically until a preset iteration termination condition is met.

[0035] As a further solution of the present invention: the zero-transfer in-memory computing of the integrated storage and computing array includes:

[0036] During encoding, the pre-stored check matrix H is directly reused to perform row-column parallel multiplication and addition operations to generate check bits;

[0037] During decoding, the message update calculations of the CN nodes and VN nodes are performed in parallel based on the check matrix H to avoid data transfer between the storage and computing units.

[0038] As a further solution of the present invention: the workflow of the dynamic code length extension module includes the following steps:

[0039] Receive target code length N, and analyze the number of activated subarrays required M;

[0040] Activate M sub-arrays through power gating and put unused sub-arrays to sleep;

[0041] The activated sub-arrays are cascaded into continuous computing links through the interconnection network controller, and the input and output ports of the inactivated sub-arrays are disconnected.

[0042] As a further solution of the present invention, the main controller controls the data flow of the ping-pong buffer architecture through the selection signal SEL, including the following steps:

[0043] When SEL=1, the storage and computing integrated array reads the VN message from the input buffer module BufferA to update the CN, and writes the result to the output buffer module BufferB;

[0044] When SEL=0, the storage-computing integrated array reads the CN message from the output buffer module BufferB to update the VN, and writes the result into the input buffer module BufferA.

[0045] As a further solution of the present invention: the check matrix H remains fixed during the execution of the encoding and decoding task, and the storage and computing integrated array achieves zero data transfer through parallel computing.

[0046] The technical solution of the second aspect: a coding method applied to an LDPC coding and decoding system for high-density magnetic tape storage as described in any one of the above items, comprising the following steps:

[0047] S1. Pre-write the QC-LDPC check matrix H into the SOT-MRAM unit of the storage and computing integrated array;

[0048] S2: User data is cached and smoothed by the input buffer module BufferA and then input into the storage and computing integrated array;

[0049] S3, the storage and calculation integrated array reuses the pre-stored check matrix H to perform zero-transfer in-memory calculations, generates check bits and outputs them to the output buffer module BufferB;

[0050] S4. The output buffer module BufferB stores the generated check bits and combines them with the information bits cached in the input buffer module BufferA to form a complete LDPC codeword and write it into the tape device.

[0051] The technical solution of the third aspect: a decoding method applied to an LDPC encoding and decoding system for high-density magnetic tape storage as described in any one of the above, comprising the following steps:

[0052] Step 1: The preprocessing module converts the noisy codewords read from the tape into LLR values ​​and stores them into the input buffer module BufferA;

[0053] Step 2: Execute ping-pong buffer iterative calculation:

[0054] A. CN update phase: VN messages are read from the input buffer module BufferA, the storage and computing array calculates the CN messages and writes them to the output buffer module BufferB;

[0055] B. VN update phase: read CN message from output buffer module BufferB, update VN message in storage and computing array and write it into input buffer module BufferA;

[0056] C. Repeat A to B until the maximum number of iterations is met or the verification equation is established;

[0057] Step 3: The hard decision module converts the final VN message into user data output.

[0058] A fourth technical solution: A dynamic code length extension control method applied to an LDPC encoding and decoding system for high-density tape storage as described in any one of the above, comprising the following steps:

[0059] Receive the target code length N and analyze the number of subarrays to be activated M;

[0060] Compare the number of subarrays M with the number of currently activated subarrays, and activate or sleep the subarrays through power gating;

[0061] Reconstructing the interconnection network to cascade the M activated sub-arrays and disconnecting the ports of the inactivated sub-arrays;

[0062] Updates the status register and outputs the reconfiguration completion signal.

[0063] Compared with the prior art, the present invention has the following technical effects:

[0064] The above-mentioned technical solution is adopted, through a main controller, a storage-computing integrated array, a ping-pong buffer architecture, a dynamic code length extension module, a preprocessing module and a hard decision module; the storage-computing integrated array solidifies the check matrix H through SOT-MRAM units and realizes zero-transfer in-memory calculations, the ping-pong buffer architecture undertakes the data combination and iterative message alternating storage functions in the encoding and decoding mode, the dynamic code length extension module realizes code length adaptive configuration through sub-array activation / sleep and interconnection network reconstruction, the main controller coordinates the coordinated work of various modules, and the preprocessing module and hard decision module respectively complete LLR generation and final data decision output in the decoding mode. The storage-computing integrated architecture eliminates data transfer bottlenecks, the ping-pong buffer accelerates iterative convergence, and the dynamic code length extension realizes on-demand allocation of hardware resources, significantly improving encoding and decoding efficiency and energy efficiency, reducing latency, and supporting the flexible adaptation requirements of multiple code lengths for high-density tape storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings:

[0066] Figure 1 This is a schematic diagram of the architecture of the LDPC encoding and decoding system according to the embodiment disclosed in this application;

[0067] Figure 2 This is a flowchart of the encoding / decoding workflow of the embodiment disclosed in this application;

[0068] Figure 3 This is a flowchart of the ping-pong buffer iterative calculation process of the embodiment disclosed in this application;

[0069] Figure 4 This is a flowchart of the dynamic code length extension workflow of the embodiment disclosed in this application. DETAILED DESCRIPTION

[0070] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0071] Please refer to Figure 1 In an embodiment of the present invention, the technical solution of the first aspect provides an LDPC encoding and decoding system for high-density tape storage, including a main controller, a storage and computing integrated array, a ping-pong buffer architecture, a dynamic code length extension module, a preprocessing module, and a hard decision module;

[0072] Main controller, used to schedule codec mode switching and module collaborative control;

[0073] The integrated storage and computing array includes SOT-MRAM storage cells and a reconfigurable interconnect network. The SOT-MRAM cells store the QC-LDPC parity check matrix H, and the integrated storage and computing array reuses the parity check matrix H to perform zero-transfer in-memory calculations.

[0074] Ping-Pong buffer architecture, consisting of input buffer module BufferA and output buffer module BufferB, alternately storing check node CN messages and variable node VN messages in decoding mode, and combining information bits and check bits in encoding mode;

[0075] Dynamic code length extension module, including code length analyzer, power gating unit and interconnection network controller, used to dynamically activate / sleep subarrays and reconfigure cascade links according to target code length;

[0076] The preprocessing module converts the noisy codewords read from the tape into log-likelihood ratio (LLR) values ​​in the decoding mode and inputs them into the input buffer module BufferA;

[0077] Hard decision module, which converts the final VN message into binary user data in decoding mode;

[0078] Among them, the main controller connects each module through the control bus, the storage and computing integrated array is bidirectionally connected with the input buffer module BufferA and the output buffer module BufferB, and the dynamic code length extension module controls the power status and interconnection topology of the sub-array.

[0079] In this embodiment, the core architecture of the LDPC codec is developed around a storage and computing integrated array and a ping-pong buffer architecture, supplemented by a dynamic code length extension module, aiming to achieve high-performance, low-latency and flexible code length configuration encoding and decoding capabilities.

[0080] The entire system architecture, such as Figure 1 As shown, it is mainly composed of the following key modules:

[0081] The main controller serves as the core scheduling unit, coordinating the work of each module;

[0082] The pre-processing module (in decoding mode) is responsible for receiving tape read data and generating LLR values;

[0083] The input buffer module BufferA acts as a data cache and plays different roles in encoding and decoding modes;

[0084] Input buffers are used to smooth data flow;

[0085] The storage and computing integrated array is the core computing module, realizing H-matrix storage and zero-transfer in-memory computing;

[0086] The output buffer module BufferB and BufferA form a ping-pong buffer architecture, alternately storing iterative messages;

[0087] The output buffer module BufferB (in encoding mode) is used to output the encoded LDPC codeword;

[0088] The hard decision module (in decoding mode) makes the final decision and outputs the user data;

[0089] And the dynamic code length extension module realizes multi-code length adaptation.

[0090] These modules work together to complete LDPC encoding and decoding tasks for high-density tape storage. The core innovation of this architecture lies in the efficient encoding calculations achieved by the integrated storage and computing array, the accelerated decoding iterations achieved by the ping-pong buffer architecture, and the flexible code length configuration provided by the dynamic code length extension module. Together, these three elements support a high-performance, low-latency, and highly flexible LDPC codec.

[0091] In this embodiment, the input buffer module BufferA receives and caches user data, and then inputs the data into the storage and computing integrated array after smoothing by the input buffer;

[0092] The storage and computing integrated array generates check bits in parallel based on the pre-stored check matrix H. Buffer B combines the check bits with the information bits in Buffer A into a complete LDPC codeword and outputs it to the tape device.

[0093] In this embodiment, the integrated storage and computing array and ping-pong buffer architecture perform layered belief propagation BP iterative decoding, including:

[0094] CN update phase: VN messages are read from the input buffer module BufferA, the storage and computing array calculates the CN messages and writes them to the output buffer module BufferB;

[0095] VN update phase: CN messages are read from the output buffer module BufferB, the storage and computing array updates the VN messages and writes them into the input buffer module BufferA;

[0096] The CN update and VN update are executed cyclically until the preset iteration termination condition is met.

[0097] In this embodiment, the zero-transfer in-memory computing of the integrated storage and computing array includes:

[0098] During encoding, the pre-stored check matrix H is directly reused to perform row-column parallel multiplication and addition operations to generate check bits;

[0099] During decoding, the message update calculations of the CN nodes and VN nodes are performed in parallel based on the check matrix H to avoid data transfer between the storage and computing units.

[0100] In this embodiment, the workflow of the dynamic code length extension module includes the following steps:

[0101] Receive target code length N, and analyze the number of activated subarrays required M;

[0102] Activate M sub-arrays through power gating and put unused sub-arrays to sleep;

[0103] The activated sub-arrays are cascaded into continuous computing links through the interconnection network controller, and the input and output ports of the inactivated sub-arrays are disconnected.

[0104] In this embodiment, the main controller controls the data flow of the ping-pong buffer architecture through the selection signal SEL, including the following steps:

[0105] When SEL=1, the storage and computing integrated array reads the VN message from the input buffer module BufferA to update the CN, and writes the result to the output buffer module BufferB;

[0106] When SEL=0, the storage-computing integrated array reads the CN message from the output buffer module BufferB to update the VN, and writes the result into the input buffer module BufferA.

[0107] In this embodiment, the check matrix H remains fixed during the execution of the encoding and decoding task, and the storage and computing integrated array achieves zero data transfer through parallel computing.

[0108] The technical solution of the second aspect: a coding method applied to an LDPC coding and decoding system for high-density magnetic tape storage as described above, comprising the following steps:

[0109] S1. Pre-write the QC-LDPC check matrix H into the SOT-MRAM unit of the storage and computing integrated array;

[0110] S2: User data is cached and smoothed by the input buffer module BufferA and then input into the storage and computing integrated array;

[0111] S3, the storage and calculation integrated array reuses the pre-stored check matrix H to perform zero-transfer in-memory calculations, generates check bits and outputs them to the output buffer module BufferB;

[0112] S4. The output buffer module BufferB stores the generated check bits and combines them with the information bits cached in BufferA to form a complete LDPC codeword and writes it to the tape device.

[0113] In this embodiment, the encoding workflow is as follows:

[0114] like Figure 2 The encoding process is shown in the figure. Before the encoding process officially begins, the QC-LDPC parity check matrix H must be pre-written into the SOT-MRAM cells of the storage-computation array. This step is completed before the encoding operation begins. Loading the pre-designed parity check matrix into the storage-computation array ensures that the parity check matrix is ​​already in place in hardware during the subsequent encoding calculation process, laying the foundation for the zero-transfer calculation of the storage-computation array. Once the parity check matrix is ​​written, it remains fixed for the duration of the encoding task.

[0115] After the check matrix is ​​pre-written, the encoding process officially begins. The user's data to be stored is first sent to the input buffer module, BufferA, for preliminary caching, preparing the data for the subsequent encoding process. The input buffer then smoothes the data stream output by BufferA, ensuring that the data is input to the core storage and computing array in a stable and continuous state, avoiding rate mismatches during data transmission. Next, the storage and computing array begins executing the core encoding calculation task. It receives data from the input buffer, which represents the information bits to be encoded.

[0116] The design advantage is that the parity check matrix has been pre-written into the storage and computing integrated array, so the pre-written parity check matrix can be directly reused for in-memory calculations, and the parity check bits required for LDPC coding can be generated in parallel and efficiently. The core advantage of adopting a storage and computing integrated architecture and reusing pre-written parity check matrices is that it significantly reduces the frequent data handling operations in traditional encoders. Traditional encoders need to read the parity check matrix from the memory and then perform multiplication and addition operations. Data handling becomes a performance bottleneck and a major energy consumer. The present invention deeply integrates the computing unit and the storage unit through storage and computing integration and matrix pre-writing, eliminating the overhead of data transportation between the memory and the computing unit, thereby greatly improving the energy efficiency of the encoding and significantly reducing latency.

[0117] After encoding is complete, output buffer module BufferB receives the parity bits generated by the storage-computation array and combines them with the information bits previously cached in input buffer module BufferA to form a complete LDPC codeword, consisting of both information bits and parity bits. Finally, output buffer module BufferB outputs the completed LDPC codeword to the tape storage device, completing the encoding and writing process. The data is stored on the tape media in LDPC-encoded form.

[0118] The technical solution of the third aspect: a decoding method applied to an LDPC encoding and decoding system for high-density magnetic tape storage as described above, comprising the following steps:

[0119] Step 1: The preprocessing module converts the noisy codewords read from the tape into LLR values ​​and stores them into the input buffer module BufferA;

[0120] Step 2: Execute ping-pong buffer iterative calculation:

[0121] A. CN update phase: VN messages are read from the input buffer module BufferA, the storage and computing array calculates the CN messages and writes them to the output buffer module BufferB;

[0122] B. VN update phase: read CN message from output buffer module BufferB, update VN message in storage and computing array and write it into input buffer module BufferA;

[0123] C. Repeat A to B until the maximum number of iterations is met or the verification equation is established;

[0124] Step 3: The hard decision module converts the final VN message into user data output.

[0125] In this embodiment, the decoding workflow is as follows:

[0126] like Figure 2Figure 1 illustrates the decoding process. The decoding process begins when a tape storage device reads data from the tape media. Due to the physical characteristics of tape storage, the read LDPC codewords are often affected by noise and errors, resulting in reduced data quality compared to the original encoded data.

[0127] The read noisy codewords are first sent to the preprocessing module for preliminary processing. The main task of the preprocessing module is to receive these noisy LDPC codewords, perform necessary preprocessing operations on them, and generate log-likelihood ratio (LLR) values. The LLR value represents the probability information of each bit being 0 or 1, and is the initial soft information input for the subsequent iterative decoding algorithm. After generating the LLR value, the system enters the ping-pong buffer iterative calculation stage. The ping-pong buffer architecture (consisting of BufferA and BufferB) works in conjunction with the storage and computing array to execute the hierarchical BP (Belief Propagation) iterative decoding algorithm. During the iterative decoding process, VN messages and CN messages are alternately stored and updated between BufferA and BufferB, and the storage and computing array is responsible for executing the calculation of the CN node.

[0128] The ping-pong buffer architecture and mixed-precision acceleration are key points in the decoding process. Their core design advantage is the ability to achieve data reuse, thereby increasing decoding throughput. During the iteration process, traditional decoders need to frequently read VN messages and CN messages from the memory, and data handling also becomes a performance bottleneck. The ping-pong buffer architecture proposed in the present invention, by setting up dual-port BufferA and BufferB, and sophisticated pipeline control, allows VN messages and CN messages to be alternately stored and read between the two buffers, achieving efficient data reuse during the iteration process, significantly reducing data handling operations, and improving data access efficiency, thereby greatly increasing the throughput of the decoder.

[0129] The hard decision module receives the final VN message from the ping-pong buffer iteration and performs a hard decision on the soft information, converting the probability information into binary bits to recover the original user data. Finally, the hard decision module outputs the recovered user data, completing the decoding process. The user now has the original data read from the tape and decoded with error correction.

[0130] In the specific implementation steps, the ping-pong buffer iterative calculation workflow

[0131] The ping-pong buffer iterative calculation is a core component of the decoding process of the present invention. Its goal is to efficiently complete the decoding task of the LDPC code through iterative message passing and hardware acceleration mechanism. Through the alternating cycle execution of the two steps of CN update and VN update, as well as the ping-pong buffer mechanism of BufferA and BufferB, hardware acceleration of the layered BP iterative decoding algorithm is achieved. The ping-pong buffer architecture effectively realizes data multiplexing, reduces data handling, and improves data access efficiency, thereby significantly improving the throughput and decoding speed of the decoder. At the same time, by setting appropriate iteration termination conditions, a balance can be achieved between decoding performance and decoding delay.

[0132] Ping-pong buffer iterative calculation workflow, such as Figure 3 As shown. In step one: the check node (CN) update (BufferA->BufferB) phase, the direction of data flow is from BufferA to BufferB, and the storage and computing integrated array is responsible for the check node calculation. First, the selection signal SEL is set to 1, which explicitly instructs the system to obtain data input from BufferA. Subsequently, the system reads the variable node (VN) messages from BufferA in parallel. These messages represent the posterior probability information calculated in the previous VN update phase, or the initial LLR value at the first iteration. The read VN messages are input to the storage and computing integrated array, and the array reuses the pre-written check matrix to efficiently perform the calculation of the check node (CN). The advantage of the storage and computing integrated array lies in its in-memory computing capability, which can avoid the data handling bottleneck in the traditional architecture and significantly accelerate the calculation of the CN node. The calculated check node (CN) message is then written to the storage area of ​​BufferB to prepare data for the next variable node update phase.

[0133] Next, the system enters step two: the variable node (VN) update (BufferB->BufferA) phase. At this point, the data flow reverses direction, flowing from BufferB back to BufferA. The storage-computation array participates in the calculation again, this time responsible for updating the variable node messages. First, the selection signal SEL is set to 0, switching the data input source to BufferB. The system reads the check node (CN) messages from BufferB in parallel. These CN messages are the results just calculated in the CN update phase. The storage-computation array receives the CN messages read from BufferB and performs the variable node (VN) update operation. During the VN update phase, the array calculates the updated variable node messages, namely the posterior probabilities, based on the received CN messages and prior information. The calculated posterior probabilities (updated VN messages) are ultimately written to the storage area of ​​BufferA, overwriting the previously stored old VN messages, thus implementing a cyclic update of iterative messages. In this way, the updated VN messages prepare data for the next round of CN update phases.

[0134] After completing each VN update phase, the system needs to check the iteration termination conditions. Generally, the iteration termination conditions include reaching the preset maximum number of iterations (MaxIterations) or satisfying the check equation. If the maximum number of iterations is reached, or the check equation has been fully satisfied, even if the decoding result may not have fully converged, the system will determine that the iterative process can be terminated to control the decoding delay and computing resource consumption. If the iteration termination condition has not been met, the system will loop back to step one: CN update phase, start a new round of iterative calculations, and continue the alternating process of CN update and VN update, continuously optimizing VN messages and CN messages in order to obtain better decoding performance. If the iteration termination condition has been met, it means that the iterative decoding process has converged or reached the preset target, the iterative loop ends, and the system enters the final output stage.

[0135] When the iteration process completes, the system reads the final variable node (VN) messages from BufferA. These VN messages represent the best estimates obtained after multiple iterations of optimization and represent the decoder's soft decisions on the original information bits. The subsequent hard decision module makes hard decisions based on these final VN messages to recover the final user data, completing the entire ping-pong buffer iterative calculation process and delivering the decoding results to the subsequent data processing module.

[0136] A fourth technical solution: A dynamic code length extension control method for an LDPC encoding and decoding system for high-density tape storage, as applied to any of the above items, comprises the following steps:

[0137] Receive the target code length N and analyze the number of subarrays to be activated M;

[0138] Compare the number of subarrays M with the number of currently activated subarrays, and activate or sleep the subarrays through power gating;

[0139] Reconstructing the interconnection network to cascade the M activated sub-arrays and disconnecting the ports of the inactivated sub-arrays;

[0140] Updates the status register and outputs the reconfiguration completion signal.

[0141] In this embodiment, the dynamic code length extension workflow is as follows:

[0142] like Figure 4 The figure shows the workflow of the dynamic code length extension module. It begins by receiving a target code length command N from an external input. Upon receiving the command, the code length parser first parses the target code length N and calculates the number of subarrays M to be activated based on the code length. This calculation is typically performed by rounding up, for example, dividing the target code length by the data bit width processed by each subarray (e.g., 1024 bits) to obtain the required number of subarrays. The system then enters the subarray activation / sleep control phase.

[0143] At this stage, the system compares the calculated required number of subarrays, M, with the currently activated number of subarrays. If M is less than or equal to the currently activated number of subarrays, this means that the currently activated number of subarrays exceeds the actual demand. Therefore, the power gating unit will be triggered to turn off the power of (currently activated number - M) excess subarrays, putting them into a dormant state, thereby reducing power consumption. Conversely, if M is greater than the currently activated number of subarrays, this means that the currently activated number of subarrays is insufficient to support the target code length. In this case, the power gating unit will activate (M - currently activated number) dormant subarrays, increasing the activated hardware resources to meet demand. Regardless of whether activation or dormancy is performed, the power gating unit performs power management with a single subarray as the minimum control granularity, achieving refined power consumption control.

[0144] After subarray activation / sleep control is complete, the system updates the number of currently active subarrays to M, ensuring that the system status record is consistent with the actual hardware configuration. After the number of subarrays is adjusted, the interconnection network controller begins to configure the reconfigurable interconnect network based on the number of activated subarrays M, connecting the M activated subarrays into a cascaded computing chain. The cascade method connects the output port of the previous subarray to the input port of the next subarray, forming a data flow path. For inactive subarrays, the interconnection network controller disconnects their input and output ports from the cascade link, preventing them from participating in the current computing task.

[0145] Finally, the power gating unit further optimizes power consumption by completely shutting down the power to inactive subarrays, thus reducing static power consumption. The system updates the status register to record the current hardware configuration, including the number of active subarrays and the topology of the cascade links.

[0146] At this point, the dynamic code length extension reconfiguration process is complete, and the system issues a reconfiguration completion signal (Ready), indicating that the hardware is ready to perform encoding or decoding operations at the target code length. Through this process, the dynamic code length extension module achieves fast and seamless code length switching, efficient hardware resource reuse, and optimized power consumption, providing flexible and efficient code length adaptation for high-density tape storage systems.

[0147] Beneficial effects of this embodiment:

[0148] MRAM-based integrated storage and computing LDPC coding engine: Build an integrated storage and computing array based on SOT-MRAM, pre-write the QC-LDPC check matrix and reuse it in the analog domain multiplication and addition operations within the array to realize in-memory calculations during the encoding process.

[0149] Ping-pong buffer zero-transfer iterative LDPC decoding mechanism: Design a dual-port MRAM buffer (BufferA / B) and a crossbar switch network, combined with pipeline control, to implement ping-pong switching and zero-transfer iterative updates of VN and CN messages between buffers. Mixed-precision computing is used to optimize decoding performance.

[0150] Dynamic code length expansion mechanism: Build an interconnection network based on a switch matrix, cooperate with power gating units and code length adaptive controllers to achieve dynamic cascading and flexible configuration of MRAM sub-arrays, and support dynamic switching of code lengths ranging from 1K to 64K.

[0151] An overall solution for collaborative optimization of software and hardware: This invention is not a single technical improvement, but a comprehensive collaborative design and optimization from hardware architecture to encoding and decoding algorithms. It deeply integrates the storage and computing characteristics of MRAM and performs customized algorithm optimization for tape storage application scenarios to achieve deep integration of software and hardware.

[0152] Customized and optimized design for tape storage: From the hardware architecture to the algorithm level, this invention is tailored to the core requirements of tape storage systems: high throughput, low power consumption, and high reliability. For example, the integrated MRAM storage and computing architecture meets both high performance requirements and low power consumption. A method specifically designed to mitigate sudden errors is also designed to address the sudden error characteristics of tapes. A dynamic code length extension mechanism is also designed to accommodate multi-capacity tape storage applications.

[0153] Although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents, and all should be included within the scope of protection of the present invention.

Claims

1. An LDPC encoding and decoding system for high-density tape storage, characterized in that: It includes a main controller, a storage and computing array, a ping-pong buffer architecture, a dynamic code length extension module, a pre-processing module, and a hard decision module; The main controller is used to schedule codec mode switching and module collaborative control; The storage-computing integrated array includes SOT-MRAM storage units and a reconfigurable interconnection network. The SOT-MRAM units store a fixed QC-LDPC check matrix H. The storage-computing integrated array reuses the check matrix H to perform zero-transfer in-memory calculations. The ping-pong buffer architecture consists of an input buffer module BufferA and an output buffer module BufferB, which alternately stores check node CN messages and variable node VN messages in decoding mode and combines information bits and check bits in encoding mode; The dynamic code length extension module includes a code length analyzer, a power gating unit, and an interconnection network controller, which is used to dynamically activate / sleep subarrays and reconstruct cascade links according to the target code length; The pre-processing module converts the noisy codewords read from the tape into log-likelihood ratio (LLR) values ​​and inputs the LLR values ​​into the input buffer module BufferA in the decoding mode; The hard decision module converts the final VN message into binary user data in decoding mode; The main controller is connected to each module via a control bus, the storage and computing integrated array is bidirectionally connected to the input buffer module BufferA and the output buffer module BufferB, and the dynamic code length extension module controls the power status and interconnection topology of the sub-array.

2. The LDPC encoding and decoding system for high-density tape storage according to claim 1, characterized in that: The input buffer module BufferA receives and caches user data, and then inputs it into the storage and computing integrated array after smoothing in the input buffer; The storage and computing integrated array generates check bits in parallel based on the pre-stored check matrix H, and Buffer B combines the check bits with the information bits in Buffer A into a complete LDPC codeword and outputs it to the tape device.

3. The LDPC encoding and decoding system for high-density tape storage according to claim 1, characterized in that: The integrated storage and computing array and ping-pong buffer architecture perform layered belief propagation (BP) iterative decoding, including: CN update phase: VN messages are read from the input buffer module BufferA, the storage and computing array calculates the CN messages and writes them to the output buffer module BufferB; VN update phase: CN messages are read from the output buffer module BufferB, the storage and computing array updates the VN messages and writes them into the input buffer module BufferA; The CN update and VN update are executed cyclically until a preset iteration termination condition is met.

4. The LDPC encoding and decoding system for high-density tape storage according to claim 1, characterized in that: The zero-transfer in-memory computing of the integrated storage and computing array includes: During encoding, the pre-stored check matrix H is directly reused to perform row-column parallel multiplication and addition operations to generate check bits; During decoding, the message update calculations of the CN nodes and VN nodes are performed in parallel based on the check matrix H to avoid data transfer between the storage and computing units.

5. The LDPC encoding and decoding system for high-density tape storage according to claim 1, characterized in that: The workflow of the dynamic code length extension module includes the following steps: Receive target code length N, and analyze the number of activated subarrays required M; Activate M sub-arrays through power gating and put unused sub-arrays to sleep; The activated sub-arrays are cascaded into continuous computing links through the interconnection network controller, and the input and output ports of the inactivated sub-arrays are disconnected.

6. The LDPC encoding and decoding system for high-density tape storage according to claim 1, characterized in that: The main controller controls the data flow of the ping-pong buffer architecture through a selection signal SEL, including the following steps: When SEL=1, the storage and computing integrated array reads the VN message from the input buffer module BufferA to update the CN, and writes the result to the output buffer module BufferB; When SEL=0, the storage-computing integrated array reads the CN message from the output buffer module BufferB to update the VN, and writes the result into the input buffer module BufferA.

7. A coding method applied to an LDPC coding and decoding system for high-density magnetic tape storage according to any one of claims 1 to 6, characterized in that: The following steps are involved: S1. Pre-write the QC-LDPC check matrix H into the SOT-MRAM unit of the storage and computing integrated array; S2: User data is cached and smoothed by the input buffer module BufferA and then input into the storage and computing integrated array; S3, the storage and calculation integrated array reuses the pre-stored check matrix H to perform zero-transfer in-memory calculations, generates check bits and outputs them to the output buffer module BufferB; S4. The output buffer module BufferB stores the generated check bits and combines them with the information bits cached in the input buffer module BufferA to form a complete LDPC codeword and write it into the tape device.

8. The encoding method of the LDPC encoding and decoding system for high-density magnetic tape storage according to any one of claim 7, characterized in that: The check matrix H remains fixed during the execution of the encoding and decoding task, and the storage and computing integrated array achieves zero data transfer through parallel computing.

9. A decoding method applied to an LDPC encoding and decoding system for high-density magnetic tape storage according to any one of claims 1 to 6, characterized in that: The following steps are involved: Step 1: The preprocessing module converts the noisy codewords read from the tape into LLR values ​​and stores them into the input buffer module BufferA; Step 2: Execute ping-pong buffer iterative calculation: A. CN update phase: VN messages are read from the input buffer module BufferA, the storage and computing array calculates the CN messages and writes them to the output buffer module BufferB; B. VN update phase: read CN message from output buffer module BufferB, update VN message in storage and computing array and write it into input buffer module BufferA; C. Repeat A to B until the maximum number of iterations is met or the verification equation is established; Step 3: The hard decision module converts the final VN message into user data output.

10. A dynamic code length extension control method applied to an LDPC encoding and decoding system for high-density magnetic tape storage according to any one of claims 1 to 6, characterized in that: The following steps are involved: Receive the target code length N and analyze the number of subarrays to be activated M; Compare the number of subarrays M with the number of currently activated subarrays, and activate or sleep the subarrays through power gating; Reconstructing the interconnection network to cascade the M activated sub-arrays and disconnecting the ports of the inactivated sub-arrays; Updates the status register and outputs the reconfiguration completion signal.

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