Memory chip and preparation method thereof

Abstract

The invention provides a memory chip and a preparation method of the memory chip, the memory chip provided by the invention comprises a substrate, and a memory layer and a control layer which are arranged on the substrate, the memory layer and the control layer are arranged on different planes, and the projections of the memory layer and the control layer on the substrate are at least partially overlapped; the storage layer comprises a plurality of storage units, the control layer comprises a plurality of control units, and the control units are connected with the storage units and control the storage units to perform read-write operation; the storage layer comprises a magnetoresistive random access memory; the control layer comprises a transistor; and the substrate, the storage layer and the control layer form the same wafer. The memory chip has the characteristics of low power consumption, high speed and high reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a memory chip and a method for preparing the memory chip. Background Art

[0002] The traditional von Neumann architecture separates memory and computing units, making the functions of each computer component more clearly defined and relatively easy to design and implement. The designs of the memory and computing units can be optimized to address their respective characteristics, improving their respective performance. For example, the memory can focus on improving storage capacity and data read / write speeds, while the computing unit can focus on improving computational speed and processing power. The independence of the memory from the computing unit allows for flexible data sharing and transfer between different computing tasks. The computing unit can read and process different data from the memory as needed, and then store the processed data back in the memory for use in other computing tasks. This flexibility facilitates complex computing tasks and diverse applications. However, the relatively slow data transfer speed between the memory and the computing unit has become a bottleneck restricting overall computer performance. Frequent data transfer between the memory and the computing unit consumes significant energy. Summary of the Invention

[0003] The present invention mainly provides a memory chip and a method for preparing the memory chip. The memory chip has the characteristics of high reliability, low power consumption and high speed.

[0004] To solve the above technical problems, the first technical solution adopted by the present invention is to provide a memory chip, comprising:

[0005] substrate;

[0006] a storage layer and a control layer disposed on a substrate, wherein the storage layer and the control layer are disposed on different planes, and their projections on the substrate at least partially overlap;

[0007] The storage layer includes several storage units, the control layer includes several control units, the control units are connected to the storage units and control the storage units to perform read and write operations; the storage layer includes a magnetoresistive random access memory; the control layer includes transistors; the substrate, the storage layer and the control layer constitute the same wafer.

[0008] In one embodiment, the control layer includes at least one of a carbon nanotube transistor and a transistor based on a two-dimensional material.

[0009] Each of the control units comprises:

[0010] a read control unit for controlling data reading and a write control unit for controlling data writing, wherein the read control unit is a carbon nanotube transistor, and / or the write control unit is a carbon nanotube transistor; or

[0011] Each of the control units includes a read / write control unit for controlling data reading and writing, and the read / write control unit is a carbon nanotube transistor.

[0012] In one embodiment, the number of the storage layers is multiple;

[0013] The storage layer is arranged between the substrate and the control layer; or, the storage layer is arranged on a side of the control layer away from the substrate; or, part of the storage layer is arranged between the substrate and the control layer, and the remaining part of the storage layer is arranged on a side of the control layer away from the substrate; and / or

[0014] In one embodiment, the number of the control layers is multiple;

[0015] The control layer is arranged between the substrate and the storage layer; or, the control layer is arranged on the side of the storage layer away from the substrate; or, part of the control layer is arranged between the substrate and the storage layer, and the rest of the control layer is arranged on the side of the storage layer away from the substrate.

[0016] In one embodiment, n storage layers and m control layers constitute a storage component, the storage chip includes multiple storage components, and the multiple storage components are stacked in a direction perpendicular to the substrate, wherein n and m are positive integers.

[0017] In one embodiment, some of the control units in the control layer serve as slave control units, and the remaining control units in the control layer serve as master control units;

[0018] The master control unit and the slave control unit are respectively connected to the same storage unit, and the slave control unit is used to perform read and write operations on the storage unit instead of the master control unit.

[0019] In one embodiment, the read control unit includes a first carbon nanotube transistor, and the write control unit includes a second carbon nanotube transistor; the control layer includes a first control layer and a second control layer, and the second carbon nanotube transistor on the first control layer is connected in parallel with the second carbon nanotube transistor on the second control layer; and / or the first carbon nanotube transistor on the first control layer is connected in parallel with the first carbon nanotube transistor on the second control layer; or

[0020] The control unit includes at least two first carbon nanotube transistors and / or at least two second carbon nanotube transistors, the at least two first carbon nanotube transistors are connected in parallel; the at least two second carbon nanotube transistors are connected in parallel.

[0021] In one embodiment, the memory chip further includes a dielectric layer and a heat dissipation layer disposed between the control layer and the memory layer;

[0022] The heat dissipation layer includes carbon nanotubes, and the dielectric layer wraps the heat dissipation layer to isolate the heat dissipation layer from the control layer and the storage layer.

[0023] In one embodiment, the memory chip further includes: a sensing layer; the sensing layer is disposed on the substrate, on a different plane from the reservoir layer and the control layer, and their projections on the substrate at least partially overlap.

[0024] To solve the above technical problems, the second technical solution adopted by the present invention is to provide a method for preparing a memory chip, comprising:

[0025] providing a substrate;

[0026] A storage layer is prepared on the substrate, and a control layer is prepared on a side of the storage layer away from the substrate; or a control layer is prepared on the substrate, and a storage layer is prepared on a side of the control layer away from the substrate; wherein the storage layer includes a plurality of storage units, and the control layer includes a plurality of control units, and the control units are used to control the storage units to perform read and write operations; the substrate, the storage layer and the control layer constitute the same wafer, and the storage layer includes a magnetoresistive random access memory; and the control layer includes transistors.

[0027] The present invention has the following beneficial effects: Unlike the prior art, the memory chip provided by the present invention comprises: a substrate, and a storage layer and a control layer disposed on the substrate, wherein the storage layer and the control layer are disposed on different planes and their projections on the substrate at least partially overlap; the storage layer comprises a plurality of memory cells, and the control layer comprises a plurality of control units connected to the memory cells to control the memory cells to perform read and write operations; the storage layer comprises a magnetoresistive random access memory (MRAM); the control layer comprises transistors, and the substrate, storage layer, and control layer form a single wafer. This memory chip is characterized by high reliability, low power consumption, and high speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 is a structural diagram of the first embodiment of the memory chip provided by the present application;

[0030] Figure 2 yes Figure 1 Schematic diagram of the structure of the memory chip;

[0031] Figure 3 is an equivalent circuit diagram of the control unit and storage unit of the memory chip provided by this application;

[0032] Figure 4 is a structural diagram of a second embodiment of the memory chip provided by this application;

[0033] Figure 5 is a schematic structural diagram of a third embodiment of the memory chip provided by the present application;

[0034] Figure 6 is a schematic structural diagram of a fourth embodiment of a memory chip provided by the present application;

[0035] Figure 7 is a schematic structural diagram of a fifth embodiment of the memory chip provided by the present application;

[0036] Figure 8 is a schematic structural diagram of a sixth embodiment of the memory chip provided by the present application;

[0037] Figure 9 is a schematic structural diagram of a seventh embodiment of the memory chip provided by the present application;

[0038] Figure 10 is a schematic structural diagram of an eighth embodiment of the memory chip provided by the present application;

[0039] Figure 11 This is a flow chart of an embodiment of a method for manufacturing a memory chip of the present application. DETAILED DESCRIPTION

[0040] The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0041] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0042] The term "and / or" in this document simply describes a relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the related objects are in an "or" relationship. Furthermore, "many" in this document means two or more than two.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0044] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0045] The traditional von Neumann architecture separates memory and computing units. The relatively slow data transfer speed between the memory and computing units has become a bottleneck restricting overall computer performance. Frequent data transfer between the memory and computing units consumes a significant amount of energy.

[0046] Monolithic 3D integration can overcome the shortcomings of the von Neumann architecture. Specifically, monolithic 3D integration vertically stacks and integrates devices or circuit layers with different functions on a single chip. Interlayer dielectrics and interconnecting signal vias enable electrical connections and signal transmission between layers, thus achieving chip integration in three dimensions and effectively improving integration density and system performance. By vertically stacking multiple layers of devices, this architecture allows for the integration of more functional modules within the same chip area, contributing to system miniaturization and multifunctionality, while also improving integration density. This shortens the signal transmission distance between different functional modules, reduces signal latency, and improves data transmission speed and overall system efficiency. Furthermore, the tight integration between layers helps reduce signal interference, improving system stability and reliability. The shortened signal transmission distance reduces energy loss during signal transmission, thereby helping to reduce overall chip power consumption.

[0047] However, in monolithic 3D integration, the fabrication processes for different functional layers need to be compatible with each other, especially to achieve the integration of various active and passive devices under low thermal budget conditions. For example, silicon-based technology for CMOS back-end integration is limited by low thermal loads (<400°C), so it is necessary to develop materials and device fabrication technologies suitable for low-temperature processes.

[0048] During AI model training, training parameters need to be repeatedly stored in a cache. The cache currently used is static random access memory (SRAM). SRAM is composed of six transistors, has high static power consumption, and is volatile storage, requiring repeated power-on refresh and resulting in high leakage current. However, SRAM has fast read and write speeds (experimental data shows a read and write speed of less than 10ns) and a high erase and write endurance (experimental data shows an erase and write endurance of more than 1e16), making this device a necessity. However, because the processing temperature of SRAM is too high, the lower device will be damaged by the high temperature when the upper device is manufactured. Currently, emerging low-temperature storage types mainly include ReRAM (resistive random access memory) and MRAM (magnetic random access memory). The working principle of ReRAM is based on the property that certain materials undergo a reversible change in resistance under the action of an electric field. Typically, these materials contain some conductive filaments or conductive channels. When a forward voltage is applied, conductive filaments form within the material, reducing resistance to a low-resistance state, representing a logical "1." When a reverse voltage is applied, the conductive filaments partially break or disappear, increasing resistance to a high-resistance state, representing a logical "0." By controlling the magnitude and direction of the voltage, the resistance state of the memory cell can be altered, enabling data writing and erasing. Its advantage is the significant difference in resistance between 0 and 1, making it suitable for multi-valued brain-like computing; however, its endurance is extremely low. Magnetoresistive random access memory (MRAM), also known as magnetic memory, is a non-volatile magnetic random access memory that uses electron spin to store information. The relative orientation of the magnetization of two ferromagnetic layers in a magnetic tunnel junction (MTJ) represents binary data "0" and "1." When the magnetization directions of the two ferromagnetic layers are parallel, the MTJ exhibits a low-resistance state, representing a "0"; when they are antiparallel, it exhibits a high-resistance state, representing a "1." This type of magnetic memory preserves data without requiring a power source and protects against data loss after a power outage, enhancing data security and reliability. It boasts high-speed read and write capabilities similar to static random access memory (SRAM), enabling rapid data read and write operations to meet the demands of high-speed computing. It boasts a high level of integration comparable to dynamic random access memory (DRAM), enabling it to store large amounts of data within a limited space. It consumes very little power in standby mode, and with technological advancements, new writing technologies are significantly reducing power consumption during data writing. Furthermore, MRAM (magnetic memory) has an infinite erase and write endurance.

[0049] In addition, the transistors in the traditional control wafer 20 are generally silicon-based transistors, which face dual challenges in practical applications: on the one hand, the Si-Si chemical bond binding energy is low (327kJ / mol), which easily causes structural failure under strong radiation environment; on the other hand, its manufacturing process requires high-temperature process, resulting in poor compatibility with three-dimensional heterogeneous integration process. In contrast, new semiconductor devices represented by carbon nanotubes and two-dimensional materials have shown significant advantages. This type of material not only has stronger chemical bond binding energy (such as CC bond up to 607kJ / mol), but its nanometer-scale thickness more effectively shortens the action path of high-energy particles and significantly improves radiation tolerance. In terms of manufacturing process, carbon nanotube transistors can be processed at low temperature through solution deposition, which is highly compatible with chip back-end processes. At the same time, its high on-state current density characteristics are particularly suitable for driving transistor scenarios. Two-dimensional material transistors have similar advantages. Therefore, the control unit of this application includes at least one of carbon nanotube transistors and transistors based on two-dimensional materials, which not only breaks through the performance limitations of traditional silicon-based devices, but also solves the technical bottleneck of complex integration processes.

[0050] In view of this, the present application provides a memory chip, which includes: a substrate and a storage layer and a control layer arranged on the substrate, wherein the storage layer and the control layer are arranged on different planes, and their projections on the substrate at least partially overlap. The storage layer includes a plurality of storage units, and the control layer includes a plurality of control units, and the control unit is used to control the storage units to perform read and write operations; the substrate, storage layer and control layer constitute the same wafer, and the storage layer includes a magnetoresistive random access memory; the control layer includes transistors. With such a design, the resulting memory chip has the characteristics of high reliability, low power consumption and high speed.

[0051] Furthermore, the preparation temperature of the transistor and the preparation temperature of the magnetoresistive random access memory are both lower than the preset temperature, and they can both be prepared at a low temperature lower than the preset temperature, meeting the process requirements and making the product more reliable. In a specific embodiment, the control layer includes: at least one of a carbon nanotube transistor and a transistor based on a two-dimensional material. It should be noted that a carbon nanotube transistor refers to a transistor using a carbon nanotube material as a channel, and a transistor based on a two-dimensional material refers to a transistor using a two-dimensional material as a channel, and the two-dimensional material is, for example, at least one of molybdenum disulfide (MoS2) and tungsten diselenide (WSe2). The magnetoresistive random access memory may, for example, include at least one of a spin-orbit torque magnetoresistive random access memory (SOT-MRAM) and a spin transfer torque magnetoresistive random access memory (STT-MRAM). This application is explained by taking the magnetoresistive random access memory as SOT-MRAM and the control layer including a carbon nanotube transistor as an example.

[0052] This application uses monolithic three-dimensional integration technology to prepare a magnetoresistive random access memory and a control unit that controls the reading and writing of the magnetoresistive random access memory on the same wafer. The transistors in the control unit are at least one of carbon nanotube transistors and transistors based on two-dimensional materials. This memory chip can overcome the process temperature requirements (it can be prepared under low-temperature processes) and has a read and write speed of less than 10ns and an endurance of more than 1e12 times, which can be applied to large AI model training scenarios. Compared with existing architectures, it has the advantages of low latency, low power consumption, large bandwidth, and high reliability.

[0053] In order to enable those skilled in the art to better understand the technical solution of the present invention, a memory chip provided by the present invention is described in further detail below with reference to the accompanying drawings and specific implementation methods.

[0054] See Figure 1 , Figure 1 This is a structural diagram of a first embodiment of the memory chip of the present application, which specifically includes: a substrate 40 and a storage layer 10 and a control layer 20 arranged on the substrate 40.

[0055] Specifically, substrate 40 is a basic material used to support and construct various semiconductor structures. Substrate 40 generally includes a silicon substrate, a silicon carbide substrate, a sapphire substrate, and a gallium arsenide substrate. In the memory chip of the present application, substrate 40 is a silicon substrate.

[0056] Specifically, the storage layer 10 and the control layer 20 are disposed on different planes, and their projections on the substrate 40 at least partially overlap. In this embodiment, the projections of the storage layer 10 and the control layer 20 on the substrate 40 completely overlap.

[0057] Specific, combined Figure 2 The storage layer 10 includes a magnetoresistive random access memory, which includes a plurality of storage cells 11, and the plurality of storage cells 11 are arranged in an array. The storage cell 11 is a magnetic tunnel junction (SOT-MTJ, also known as a spin-orbit moment magnetic tunnel junction), which is composed of two magnetic layers and a tunneling layer in the middle. One of the magnetic layers is a fixed magnetic axis layer (also called a reference layer), and its magnetization direction is fixed; the other layer is a free magnetic axis layer (also called a storage layer), and its magnetization direction can be changed under the action of an external magnetic field or spin transfer torque or spin-orbit torque to store different data. When the magnetization directions of the free magnetic axis layer and the fixed magnetic axis layer are parallel, the SOT-MTJ is in a low resistance state, representing a logic "1"; when they are anti-parallel, it is in a high resistance state, representing a logic "0".

[0058] It can be understood that the storage layer 10 also includes peripheral circuits, such as word lines, bit lines, data lines, and programming lines. The word line is used to select the row where the storage cell is located. When a word line is activated, all storage cells on the row are selected for read and write operations. The bit line is connected to the free magnetic axis layer of the storage cell and is used to transmit data. During a read operation, the resistance state of the storage cell is detected by the bit line to determine the stored data; during a write operation, the bit line is used to provide a write current. The data line is connected to the fixed magnetic axis layer of the storage cell and cooperates with the bit line to complete the reading and writing of data. For example, during writing, the data line and the bit line work together to cause current to flow through the MTJ, generating a magnetic field to change the magnetization direction of the free magnetic axis layer. The programming line is used to provide a programming current. When the switching device is turned on, the programming current flows through the data line, and the generated magnetic field changes the magnetic axis direction of the free magnetic axis layer, thereby achieving data writing.

[0059] The control layer 20 includes several control units 21, which are connected to the storage unit 11 and control the storage unit 11 to perform read and write operations. The control unit 21 includes a carbon nanotube transistor. Specifically, this embodiment is described by taking the storage layer 10 including SOT-MRAM as an example. Figure 3 Each control unit 21 includes a read control unit for controlling data reading and a write control unit for controlling data writing. The read control unit is a carbon nanotube transistor and / or the write control unit is a carbon nanotube transistor. In one specific embodiment, the read control unit includes a first carbon nanotube transistor Read Tx, and the write control unit includes a second carbon nanotube transistor Write Tx. The first carbon nanotube transistor Read Tx and the second carbon nanotube transistor Write Tx have a control terminal connected to a word line WL, a first access terminal connected to a bit line BL, and a second access terminal connected to a corresponding memory cell 11. The control terminal of the second carbon nanotube transistor Write Tx is connected to a word line WL, a first access terminal connected to a bit line BL, and a second access terminal connected to a corresponding memory cell 11. Specifically, the first carbon nanotube transistor Read Tx and the second carbon nanotube transistor Write Tx are used to control the gating and read and write operations of the memory cells. For example, during the reading and writing process, a specific memory cell is selected by controlling the on and off of the transistor, and current is passed through the MTJ to read or write data.

[0060] It can be understood that the second carbon nanotube transistor Write Tx is used to control the storage unit 11 to write data, and the first carbon nanotube transistor Read Tx is used to control the storage unit 11 to read data. In one embodiment, only the transistor that controls data writing can be set to a carbon nanotube transistor, that is, the transistor that controls data writing in the control unit is the second carbon nanotube transistor. In another embodiment, only the transistor that controls data reading can be set to a carbon nanotube transistor, that is, the transistor that controls data reading in the control unit is the first carbon nanotube transistor. Of course, in order to simplify the process, the transistor that controls data writing and the transistor that controls data reading can both be set to carbon nanotube transistors, that is, the transistor that controls data writing in the control unit is the second carbon nanotube transistor, and the transistor that controls data reading in the control unit is the first carbon nanotube transistor.

[0061] In another embodiment of the present application, a storage layer including a spin transfer torque magnetoresistive random access memory (STT-MRAM) is used as an example for illustration. STT-MRAM is a two-terminal device that can be controlled by only one transistor. In this embodiment, each control unit includes a read / write control unit for controlling data reading and writing, and the read / write control unit is a carbon nanotube transistor. The transistor is configured as a carbon nanotube transistor, and read / write control is performed through the carbon nanotube transistor.

[0062] In the embodiment of the present application, the substrate 40, the storage layer 10 and the control layer 20 constitute the same wafer. For example, the storage layer 10 and the control layer 20 are disposed on different metal layers of the same wafer.

[0063] For further information, see Figure 1 The memory chip of the present application also includes a dielectric layer 30, which is disposed between the memory layer 10 and the control layer 20. The dielectric layer 30 is used to isolate the memory layer 10 and the control layer 20, preventing short circuits and ensuring that current flows along the designed path. It also avoids electrical interference between different components. Furthermore, the dielectric layer 30 of the present application is also provided with a signal hole 31. The control unit 21 is electrically connected to the memory unit 11 through the signal hole 31 in the dielectric layer 30 for signal transmission, thereby achieving chip integration in three dimensions, effectively improving integration density and system performance.

[0064] In this embodiment, both the storage layer 10 and the control layer 20 are single-layer structures, and the storage layer 10 is disposed between the control layer 20 and the substrate 40. The structure of the entire memory chip, from bottom to top, includes the substrate 40, the storage layer 10, the dielectric layer 30, and the control layer 20. In another embodiment, the control layer 20 may be disposed between the storage layer 10 and the substrate 40. The structure of the entire memory chip, from bottom to top, includes the substrate 40, the control layer 20, the dielectric layer 30, and the storage layer 10.

[0065] In another embodiment of the present application, in order to expand the storage space, the number of storage layers 10 is multiple. The multiple storage layers 10 are arranged between the substrate 40 and the control layer 20, such as Figure 4 As shown, Figure 4 The embodiment shown is similar to the above Figure 1 Compared to the embodiment shown, the difference is that the storage layer 10 in this embodiment is two layers. In other embodiments, the storage layer 10 can also be three or four layers, and the specific embodiment is not limited. It is understood that in this embodiment, a dielectric layer 30 is provided between the storage layers 10 and the storage layer 10, and between the storage layer 10 and the control layer 20. For interconnection, the dielectric layer 30 is also provided with a signal hole 31.

[0066] It should be noted that in this application, the same control layer 20 controls the read and write operations of two storage layers 10. Therefore, it is necessary to rationally arrange the signal holes so that the control unit 21 in the control layer 20 is interconnected with the storage unit 11 in the closest storage layer 10. It is also necessary to interconnect the control unit 21 in the control layer 20 with the storage unit 11 in the storage layer 10 that is farther away across layers. In this way, when reading and writing, a specific storage unit can be selected for access based on the read and write address. Alternatively, a gating structure can be set on the path connecting the control unit 21 and the storage unit 11. According to the read and write address, the gating structure is selectively turned on, thereby selecting a specific storage unit for access based on the read and write address. The gating structure can be, for example, a switch element or a multiplexer.

[0067] Furthermore, part of the storage layer 10 in this embodiment can be used as redundant storage. When the primary storage is damaged, the redundant storage replaces the primary storage.

[0068] In another embodiment, the storage layer 10 is disposed on a side of the control layer 20 away from the substrate 40. Assuming that the storage layer 10 is two layers, the overall structure of the memory chip includes, from bottom to top, the substrate 40, the control layer 20, the dielectric layer 30, the storage layer 10, the dielectric layer 30, and the storage layer 10.

[0069] In another embodiment, part of the storage layer 10 is disposed between the substrate 40 and the control layer 20, and the remaining part of the storage layer 10 is disposed on the side of the control layer 20 away from the substrate 40. Figure 5 , Figure 5 Also take the 2-layer storage layer 10 as an example to explain, Figure 5 The embodiment shown is similar to the above Figure 4 Compared with the embodiment shown in FIG, the difference is that in this embodiment, the control layer 20 is arranged between the two storage layers 10. In the layout of this embodiment, the control unit 21 in the control layer 20 and the storage unit 11 do not need to be connected across layers. Figure 4In the embodiment shown, the interconnection distance between the control layer 20 and the storage layer 10 is closer, the data access speed is faster, and the power consumption is lower.

[0070] Figure 1 、 Figure 4 and Figure 5 In the illustrated embodiment, n storage layers 10 and one control layer 20 are regarded as a storage component. In the same wafer, multiple storage components can be stacked and interconnected, and the details are not repeated here.

[0071] In the above embodiment, in order for the control unit 21 to drive the memory cell 11, the driving current density of the transistors of the control unit 21 (e.g., the first carbon nanotube transistor and the second carbon nanotube transistor) must meet a certain standard. If the driving current density is insufficient, then the reading and writing of the memory cell 11 will not be sufficient.

[0072] Based on this, the present application further provides a control unit 21 including at least two first carbon nanotube transistors and / or at least two second carbon nanotube transistors, wherein the at least two first carbon nanotube transistors are connected in parallel; and the at least two second carbon nanotube transistors are connected in parallel. Connecting the at least two carbon nanotube transistors in parallel increases the driving current density.

[0073] In another embodiment of the present application, in order to reduce wiring complexity, the number of control layers 20 is further set to multiple. In one embodiment, see Figure 6 At least two control layers 20 are provided between the substrate 40 and the storage layer 10. Figure 1 Compared to the embodiment shown, the difference is that the control layer 20 in this embodiment is two layers. In other embodiments, the control layer 20 can be three, four, or other layers, and the specific embodiment is not limited thereto. It will be appreciated that in this embodiment, a dielectric layer 30 is provided between the control layer 20 and the storage layer 10. Similarly, for interconnection, a signal hole 31 is provided in the dielectric layer 30.

[0074] It should be noted that, to provide a higher drive current density, the present application arranges for control units 21 on different control layers 20 to be connected in parallel. Specifically, assuming that the at least two control layers 20 in this embodiment include a first control layer and a second control layer, the second carbon nanotube transistor on the first control layer is connected in parallel with the second carbon nanotube transistor on the second control layer; and / or the first carbon nanotube transistor on the first control layer is connected in parallel with the first carbon nanotube transistor on the second control layer. Furthermore, to effectively utilize wiring space, two second carbon nanotube transistors in corresponding positions perpendicular to the substrate can be connected in parallel, and two first carbon nanotube transistors in corresponding positions perpendicular to the substrate can be connected in parallel. The two parallel second carbon nanotube transistors jointly drive a memory cell for a write operation, and the two parallel first carbon nanotube transistors jointly drive a memory cell for a read operation. In another embodiment, the control layer 20 is disposed on the side of the memory layer 10 away from the substrate 40. Thus, the overall structure of the memory chip comprises, from bottom to top, the substrate 40, the memory layer 10, the dielectric layer 30, the control layer 20, the dielectric layer 30, and the control layer 20.

[0075] In another embodiment of the present application, part of the control layer is disposed between the substrate and the storage layer, while the remaining part of the control layer is disposed on the side of the storage layer away from the substrate. Again, using two control layers 20 as an example, in this embodiment, one control layer 20 is located between the substrate 40 and the storage layer 10, while the other control layer 20 is disposed on the side of the storage layer 10 away from the substrate 40. Thus, the overall structure of the memory chip, from bottom to top, includes, in order: substrate 40, control layer 20, dielectric layer 30, storage layer 10, dielectric layer 30, and control layer 20.

[0076] In the above embodiment, one storage layer 10 and n control layers 20 are regarded as one storage component. In the same wafer, multiple storage components can be stacked and interconnected, and the details are not repeated here.

[0077] Furthermore, taking the above embodiment as an example, n storage layers 10 and m control layers 20 form a storage component 50, then the memory chip includes multiple storage components 50, and the multiple storage components 50 are stacked in a direction perpendicular to the substrate 40, where n and m are positive integers. In one embodiment, the multiple storage components 50 are stacked and arranged in a direction perpendicular to the substrate 40, such as Figure 8 As shown, this can not only expand the storage space of the memory chip, but also reduce the area of ​​the memory chip. In another embodiment, multiple storage components 50 can also be arranged on the same plane and laid flat on the substrate 40, such as Figure 7 As shown, this can not only expand the storage space of the memory chip, but also reduce the thickness of the memory chip.

[0078] Furthermore, in one embodiment of the present application, the control units 21 in part of the control layer 20 serve as slave control units, and the control units 21 in the remaining control layers 20 serve as master control units; the master control unit and the slave control unit are respectively connected to the same storage unit 11, and the slave control unit is used to perform read and write operations on the storage unit 11 on behalf of the master control unit. For example, the control layer 20 is set to have three layers, including a first control layer, a second control layer, and a third control layer. Among them, the control units 21 in corresponding positions in the three control layers 20 are connected in parallel, specifically, the second carbon nanotube transistor on the first control layer, the second carbon nanotube transistor on the second control layer, and the second carbon nanotube transistor on the third control layer are connected in parallel; and / or the first carbon nanotube transistor on the first control layer, the first carbon nanotube transistor on the second control layer, and the first carbon nanotube transistor on the third control layer are connected in parallel. In this case, at least one of the three transistors connected in parallel serves as a slave transistor, and when the master transistor is unavailable, the slave transistor replaces the master transistor. It is understood that a switch element can be provided on the path between the slave transistor and the master transistor. When the master transistor is available, the slave transistor is disconnected from the control path (the path for controlling the reading and writing of the storage unit) through the switch element. When the master transistor is unavailable, the slave transistor is electrically connected to the control path (the path for controlling the reading and writing of the storage unit) through the switch element. Of course, the control layer of the slave control unit can also be provided in multiple layers, depending on specific needs and is not limited to this.

[0079] Furthermore, the memory chip of the present application expands the space and control of the memory chip in the longitudinal direction (perpendicular to the substrate), making the memory chip a multi-layer structure. Under this structure, the memory chip will generate a lot of heat, so the heat dissipation of the memory chip is a problem that needs to be solved. Based on this, see Figure 9 The memory chip of the present application further provides a heat dissipation layer 32 between the control layer 20 and the storage layer 10. Specifically, the heat dissipation layer 32 includes carbon nanotubes. In order to prevent the heat dissipation layer 32 from affecting the electrical effect between the control layer 20 and the storage layer 10, the heat dissipation layer 32 is wrapped with a dielectric layer 30 to isolate the heat dissipation layer 32 from the control layer 20 and the storage layer 10. Furthermore, the dielectric layer 30 also needs to separate the signal hole 31 from the heat dissipation layer 32. In one embodiment, the carbon nanotubes can form a mesh heat dissipation layer 32, and the signal hole 31 is located in the grid of the mesh heat dissipation layer 32. In one embodiment, the carbon nanotubes can be directly laid in strips to form the heat dissipation layer 32.

[0080] It is understandable that if the heat dissipation layer 32 is made of other insulating materials, the heat dissipation layer 32 may also be in contact with the control layer 20 or the storage layer 10 as long as the electrical effect between the control layer 20 and the storage layer 10 is not affected.

[0081] In the memory chip of this embodiment, the heat dissipation layer 32 is provided between the memory layer 10 and the control layer 20 for exemplary purposes only. If multiple memory layers 10 are present, a heat dissipation layer 32 may also be provided between adjacent memory layers 10. Similarly, if multiple control layers 20 are present, a heat dissipation layer 32 may also be provided between adjacent control layers 20.

[0082] For further information, see Figure 10 The storage chip of the present application further includes a sensing layer 60 , which is disposed on the substrate 40 , on a different plane from the reservoir layer 10 and the control layer 20 , and whose projections on the substrate 40 at least partially overlap.

[0083] In one embodiment, the sensing layer 60 may be disposed on a side of the control layer 20 away from the storage layer 10. In other embodiments, the sensing layer 60 may also be disposed on a side of the storage layer 10 away from the control layer 20, which is not specifically limited.

[0084] It should be noted that the sensing layer 60 is a sensor device with a processing temperature lower than 400 degrees, such as a CNTFET biosensor device, a two-dimensional material optical signal sensor device, etc.

[0085] The memory chip of this embodiment can realize sensing, storage, and computing in one, and can be applied in fields such as artificial intelligence and the Internet of Things.

[0086] The memory chip of the present application integrates the control layer and the storage layer into a monolithic three-dimensional structure, and the storage layer is a magnetoresistive random access memory, and the control layer is at least one of a carbon nanotube transistor and a transistor based on two-dimensional materials. All of them can be prepared in a low-temperature environment, making the product highly reliable.

[0087] See also Figure 11 , Figure 11 This is a flow chart of an embodiment of a method for preparing a memory chip of the present application, which specifically includes:

[0088] Step S111: providing a substrate.

[0089] A substrate is a fundamental material used to support and construct various semiconductor structures. Substrates typically include silicon substrates, silicon carbide substrates, sapphire substrates, and gallium arsenide substrates. In the memory chip described in this application, the substrate is a silicon substrate.

[0090] Step S112: preparing a storage layer on the substrate and preparing a control layer on a side of the storage layer away from the substrate; or preparing a control layer on the substrate and preparing a storage layer on a side of the control layer away from the substrate.

[0091] Among them, the storage layer includes several storage units, the control layer includes several control units, the control unit is used to control the storage unit to perform read and write operations, the substrate, storage layer and control layer constitute the same wafer, and the storage layer includes a magnetoresistive random access memory; the control layer includes transistors, specifically, the control layer includes at least one of carbon nanotube transistors and transistors based on two-dimensional materials.

[0092] In one embodiment of the present application, a storage layer is disposed between a substrate and a control layer. After providing a substrate, the storage layer is formed on the substrate, and then the control layer is formed on a side of the storage layer away from the substrate. It is understood that before forming the control layer, a dielectric layer may be further formed on a side of the storage layer away from the substrate.

[0093] In another embodiment of the present application, the control layer is disposed between the substrate and the storage layer. After providing the substrate, the control layer is formed on the substrate, and then the storage layer is formed on the side of the control layer away from the substrate. It is understood that before forming the storage layer, a dielectric layer may be further formed on the side of the control layer away from the substrate.

[0094] Furthermore, after the control layer and the storage layer are prepared, the prepared wafer is further cut to obtain a plurality of crystal grains, and the obtained crystal grains are packaged to obtain a plurality of chips.

[0095] The preparation method of the memory chip of the present application integrates the control layer and the storage layer into a monolithic three-dimensional integration, and the storage layer is a magnetoresistive random access memory, and the control layer is at least one of a carbon nanotube transistor and a transistor based on two-dimensional materials. All of them can be prepared in a low-temperature environment, so that the product has the characteristics of high reliability.

[0096] The above are merely embodiments of the present invention and are not intended to limit the scope of patent protection of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention's description and drawings, or directly or indirectly applied in other related technical fields, are also included in the scope of patent protection of the present invention.

Claims

1. A memory chip, characterized in that: include: substrate; a storage layer and a control layer disposed on the substrate, wherein the storage layer and the control layer are disposed on different planes, and their projections on the substrate at least partially overlap; The storage layer includes a plurality of storage units, the control layer includes a plurality of control units, the control units are connected to the storage units and control the storage units to perform read and write operations; the storage layer includes a magnetoresistive random access memory; the control layer includes transistors; The substrate, the storage layer and the control layer constitute a same wafer.

2. The memory chip according to claim 1, wherein: The control layer includes at least one of a carbon nanotube transistor and a transistor based on a two-dimensional material.

3. The memory chip according to claim 2, wherein: Each of the control units includes: a read control unit for controlling data reading and a write control unit for controlling data writing, the read control unit is a carbon nanotube transistor, and / or the write control unit is a carbon nanotube transistor; or Each of the control units includes a read / write control unit for controlling data reading and writing, and the read / write control unit is a carbon nanotube transistor.

4. The memory chip according to claim 1, wherein: There are multiple storage layers; The storage layer is arranged between the substrate and the control layer; or, the storage layer is arranged on a side of the control layer away from the substrate; or, part of the storage layer is arranged between the substrate and the control layer, and the remaining part of the storage layer is arranged on a side of the control layer away from the substrate; and / or There are multiple control layers; The control layer is arranged between the substrate and the storage layer; or, the control layer is arranged on the side of the storage layer away from the substrate; or, part of the control layer is arranged between the substrate and the storage layer, and the rest of the control layer is arranged on the side of the storage layer away from the substrate.

5. The memory chip according to any one of claims 1 to 4, wherein: The n storage layers and the m control layers constitute a storage component. The storage chip includes a plurality of the storage components, and the plurality of storage components are stacked in a direction perpendicular to the substrate, wherein n and m are positive integers.

6. The memory chip according to claim 4, wherein: The control units in some of the control layers serve as slave control units, and the control units in the remaining control layers serve as master control units; The master control unit and the slave control unit are respectively connected to the same storage unit, and the slave control unit is used to perform read and write operations on the storage unit instead of the master control unit.

7. The memory chip according to claim 3, wherein: The read control unit includes a first carbon nanotube transistor, and the write control unit includes a second carbon nanotube transistor; the control layer includes a first control layer and a second control layer, the second carbon nanotube transistor on the first control layer is connected in parallel with the second carbon nanotube transistor on the second control layer; and / or the first carbon nanotube transistor on the first control layer is connected in parallel with the first carbon nanotube transistor on the second control layer; or The control unit includes at least two first carbon nanotube transistors and / or at least two second carbon nanotube transistors, the at least two first carbon nanotube transistors are connected in parallel; the at least two second carbon nanotube transistors are connected in parallel.

8. The memory chip according to claim 1, wherein: The memory chip further includes a dielectric layer and a heat dissipation layer disposed between the control layer and the memory layer; The heat dissipation layer includes carbon nanotubes, and the dielectric layer wraps the heat dissipation layer to isolate the heat dissipation layer from the control layer and the storage layer.

9. The memory chip according to claim 1, wherein: The memory chip further includes: a sensing layer; the sensing layer is arranged on the substrate, on a different plane from the reservoir layer and the control layer, and their projections on the substrate at least partially overlap.

10. A method for preparing a memory chip, characterized in that: include: providing a substrate; forming a storage layer on the substrate, and forming a control layer on a side of the storage layer away from the substrate; Alternatively, a control layer is prepared on the substrate, and a storage layer is prepared on a side of the control layer away from the substrate; wherein the storage layer includes a plurality of storage units, and the control layer includes a plurality of control units, and the control units are used to control the storage units to perform read and write operations; the substrate, the storage layer and the control layer constitute the same wafer, and the storage layer includes a magnetoresistive random access memory; and the control layer includes transistors.

Images