Back contact battery, preparation method thereof and photovoltaic module

Abstract

The embodiment of the invention provides a back contact cell and a preparation method thereof, and a photovoltaic module, and relates to the field of solar cells, the back contact cell comprises a silicon substrate, the back surface of the silicon substrate comprises a first region, a second region and a spacer region, the first region comprises a first sub-region and a second sub-region, and the spacer region comprises a second sub-region and a third sub-region; the spacer region comprises a first spacer sub-region adjacent to the first region and a second spacer sub-region adjacent to the second region; the first carrier collection layer has a first conduction type, is arranged on the back surface of the silicon substrate and is positioned in the first region and the first spacer region; the amorphous semiconductor layer is arranged on the first carrier collection layer and is positioned in the second sub-region and the first spacer sub-region; the second carrier collection layer has an opposite second conduction type, is arranged on the back surface of the silicon substrate, is positioned in the second region, the spacer region and the second sub-region, and is positioned on the amorphous semiconductor layer in the second sub-region and the first spacer region; and the first electrode is arranged in the first sub-region and is positioned on one side, far away from the silicon substrate, of the first carrier collection layer. The back contact battery has excellent electrical properties.

Description

Technical Field

[0001] The present disclosure relates to a back-contact cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] Solar cells are semiconductor devices that convert light into electricity. Back-contact solar cells are high-efficiency cells with electrodes located on the back of the cell. This improves cell efficiency because the front surface is free of metal grid lines. Back-contact (IBC) solar cells are widely used in the photovoltaic industry due to their numerous advantages, including no front-side light blocking and significantly improved short-circuit current and open-circuit voltage.

[0003] Selective passivation contact technology has obvious selectivity for the passage of specific carriers, allowing one type of carrier to pass effectively while having a shielding effect on the other carrier, greatly reducing the recombination of the two carriers and effectively improving the photoelectric conversion efficiency of solar cell devices.

[0004] Currently, there are two typical types of selective passivated contact solar cells: one is the tunnel oxide passivated contact solar cell ("Tunnel Oxide Passivated Contact", TOPCon), and the other is the heterojunction solar cell ("Hetero-Junction with Intrinsic Thin-layer", HIT). The TBC ("Tunnel Oxide Back Contact") or HBC ("Hetero-Junction Back Contact") technology, which combines the back contact cell technology IBC with TOPCon or HJT technology, further reduces the recombination of the metal on the back of the IBC. Although the current cells have many advantages as they gradually develop, further improving the photoelectric conversion efficiency of the back contact solar cell and thus improving the electrical performance remains an important goal. Summary of the Invention

[0005] The present disclosure provides a back-contact cell and a preparation method thereof, and a photovoltaic module, which can improve the electrical performance of the back-contact cell.

[0006] A first aspect of the present disclosure provides a back-contact battery, comprising:

[0007] The silicon substrate has a back surface comprising a first region, a second region and a spacer region, wherein the adjacent first region and second region are separated by the spacer region, the first region comprises a first sub-region and a second sub-region, and the spacer region comprises a first spacer sub-region adjacent to the first region and a second spacer sub-region adjacent to the second region;

[0008] A first carrier collection layer having a first conductivity type, the first carrier collection layer being disposed on the back side of the silicon substrate and located in the first region and the first spacer region;

[0009] an amorphous semiconductor layer, provided on a surface of the first carrier collection layer away from the silicon substrate, and located in the second sub-region and the first spacer sub-region;

[0010] a second carrier collection layer having a second conductivity type opposite to the first conductivity type, the second carrier collection layer being disposed on the back side of the silicon substrate and located in the second region, the spacer region, and the second sub-region, wherein the second sub-region and the first spacer sub-region are located on a surface of the amorphous semiconductor layer away from the silicon substrate; and

[0011] The first electrode is arranged in the first sub-region and is located on a side of the first carrier collection layer away from the silicon substrate.

[0012] In some embodiments, a second sub-region is disposed on both sides of the first sub-region.

[0013] In some embodiments, the percentage of the width of the first sub-region to the width of the first region ranges from 2% to 70%.

[0014] In some embodiments, the first carrier collection layer comprises:

[0015] a tunneling layer disposed on the back side of the silicon substrate and located in the first region and the first spacer region; and

[0016] A doped polysilicon layer is provided on a surface of the tunneling layer away from the silicon substrate;

[0017] The amorphous semiconductor layer is arranged on a surface of the doped polysilicon layer away from the silicon substrate, and the first electrode is arranged on a side of the doped polysilicon layer away from the silicon substrate.

[0018] In some embodiments, the thickness of the tunneling layer ranges from 0.5 nm to 3.0 nm; and / or

[0019] The thickness of the doped polysilicon layer ranges from 20 nm to 200 nm.

[0020] In some embodiments, the second carrier collection layer comprises:

[0021] An intrinsic silicon-containing layer is provided on the back side of the silicon substrate and is located in the second region, the spacer region, and the second sub-region; and

[0022] The doped silicon-containing layer is provided on a surface of the intrinsic silicon-containing layer away from the silicon substrate and is located at least in the second region and the second sub-region;

[0023] The back contact cell further includes a second electrode, which is located on a side of the doped silicon-containing layer away from the silicon substrate.

[0024] In some embodiments, the thickness of the amorphous semiconductor layer is greater than the thickness of the intrinsic silicon-containing layer;

[0025] Preferably, the thickness of the amorphous semiconductor layer is in the range of 10 nm to 40 nm, and / or the thickness of the intrinsic silicon-containing layer is in the range of 1 nm to 10 nm;

[0026] Preferably, the amorphous semiconductor layer is an intrinsic silicon-containing layer.

[0027] In some embodiments, the back contact cell further includes a conductive layer, the conductive layer covering the second carrier collection layer and the first carrier collection layer located in the first sub-region;

[0028] An isolation groove is formed in the spacing region of the conductive layer. The isolation groove at least penetrates the conductive layer, and the depth of the isolation groove is configured to retain at least a portion of the thickness of the second carrier collection layer.

[0029] In some embodiments, the width of the isolation trench ranges from 5 um to 250 um.

[0030] In some embodiments, the back surface of the silicon substrate has a first distance from the front surface in the first region and the first spacer region, and the back surface of the silicon substrate has a second distance from the front surface in the second region, the first distance is greater than the second distance, and the height difference between the first distance and the second distance does not exceed a preset height;

[0031] Preferably, the preset height ranges from 0.1um to 4um.

[0032] In some embodiments, the back surface of the silicon substrate is connected between the second region and the first spacer region via a transition surface.

[0033] In some embodiments, the back contact cell further comprises a passivation layer and / or an anti-reflection layer disposed on the front side of the silicon substrate.

[0034] A second aspect of the present disclosure provides a photovoltaic module comprising the back-contact cell of the above embodiment.

[0035] A third aspect of the present disclosure provides a method for preparing a back-contact battery, comprising:

[0036] S1. Providing a silicon substrate, wherein the back side of the silicon substrate comprises a first region, a second region, and a spacer region, wherein adjacent first and second regions are separated by the spacer region, the first region comprises a first sub-region and a second sub-region, and the spacer region comprises a first spacer sub-region adjacent to the first region and a second spacer sub-region adjacent to the second region;

[0037] S2, forming a first carrier collection layer and an amorphous semiconductor layer having a first conductivity type in the first region and the first spacer region on the back side of the silicon substrate;

[0038] S3, forming a second carrier collection layer having a second conductivity type on the entire back side of the silicon substrate, where the second conductivity type is opposite to the first conductivity type;

[0039] S4, removing the second carrier collection layer and the amorphous semiconductor layer in the first sub-region on the back side of the silicon substrate;

[0040] S5. Form a first electrode on a side of the first sub-region of the first carrier collection layer away from the silicon substrate.

[0041] In some embodiments, the first carrier collection layer further includes a tunneling layer and a doped polysilicon layer, and S2 includes:

[0042] S21, sequentially disposing a tunneling layer, a doped polysilicon layer, an amorphous semiconductor layer, and a mask layer on the entire back surface of the silicon substrate;

[0043] S22, removing the tunneling layer, the doped polysilicon layer, the amorphous semiconductor layer, and the mask layer in the second region and the second spacer region by laser;

[0044] S23 , removing the mask layer in the first spacer region and the first region.

[0045] In some embodiments, the second carrier collection layer includes: an intrinsic silicon-containing layer and a doped silicon-containing layer, and S3 includes:

[0046] S31, after laser removal of all layer structures on the back side of the silicon substrate in the second area and the second spacer area, continue to remove a portion of the thickness of the back side of the silicon substrate in the second area, and form a textured surface in the second area;

[0047] S32. Forming an intrinsic silicon-containing layer and a doped silicon-containing layer in sequence on the back side of the silicon substrate.

[0048] 16. In some embodiments, further comprising:

[0049] S6, forming a textured surface on the front side of the silicon substrate;

[0050] S7. Form a passivation layer and / or an anti-reflection layer on the front surface of the silicon substrate.

[0051] In some embodiments, the preparation method further comprises:

[0052] S8, forming a conductive layer on the back side of the silicon substrate;

[0053] S9. An isolation trench is formed in the spacing region on the conductive layer. The isolation trench at least penetrates the conductive layer, and the depth of the isolation trench is configured to retain at least a portion of the thickness of the second carrier collection layer.

[0054] In the back contact battery of the embodiment of the present disclosure, an amorphous semiconductor layer is provided between the first carrier collection layer and the second carrier collection layer in the spacing region, which can effectively separate the first carrier collection layer and the second carrier collection layer to prevent leakage.

[0055] The disclosed embodiments also have the following further beneficial effects: During the fabrication of back-contact cells, the provision of an amorphous semiconductor layer provides a high laser absorption coefficient, much higher than that of crystalline silicon. During the cell fabrication process, when removing excess film layers through a laser process, the amorphous semiconductor layer acts as a mask and efficiently absorbs the laser energy, thereby reducing the power of the laser opening and minimizing damage to the underlying film layers. Furthermore, the height difference between the first and second regions can be reduced, which can shorten the carrier transmission path and effectively reduce metal slurry waste, thereby lowering manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0057] Figure 1 A schematic structural diagram of a back-contact battery provided in one embodiment of the present disclosure.

[0058] Figure 2 A schematic structural diagram of a silicon substrate provided in one embodiment of the present disclosure.

[0059] Figure 3 This is a structural diagram of an embodiment of the present disclosure in which a tunneling layer, a doped polysilicon layer, an amorphous semiconductor layer and a mask layer are sequentially provided on the back side of a silicon substrate.

[0060] Figure 4 This is a schematic structural diagram of removing the mask layer, intrinsic silicon-containing layer, doped polysilicon layer and tunneling layer from the second region according to an embodiment of the present disclosure.

[0061] Figure 5 This is a schematic structural diagram of forming a textured surface on the front side of a silicon substrate according to an embodiment of the present disclosure, and further removing damaged portions in a second area on the back side to form a textured surface.

[0062] Figure 6 This is a structural schematic diagram of an embodiment of the present disclosure in which an intrinsic silicon-containing layer and a doped silicon-containing layer are sequentially formed on the back side of a silicon substrate, and a passivation layer and an anti-reflection layer are sequentially formed on the front side.

[0063] Figure 7Schematic diagram of the structure of a doped silicon-containing layer, an intrinsic silicon-containing layer and an amorphous semiconductor layer in a first sub-region in a first region on the back side of a silicon substrate according to an embodiment of the present disclosure.

[0064] Figure 8 Schematic diagram of a structure in which a conductive layer is formed on the back side of a silicon substrate according to an embodiment of the present disclosure.

[0065] Figure 9 This is a structural diagram of an isolation trench provided in a spacing region according to an embodiment of the present disclosure.

[0066] Figure 10 A schematic diagram of a structure in which a first electrode and a second electrode are provided in accordance with an embodiment of the present disclosure.

[0067] Figure 11 A schematic flow chart of a method for preparing a back-contact battery according to an embodiment of the present disclosure.

[0068] Description of reference numerals:

[0069] 1. Silicon substrate; 2. Tunneling layer; 3. Doped polysilicon layer; 4. Amorphous semiconductor layer; 5. Mask layer; 6. Intrinsic silicon-containing layer; 7. Doped silicon-containing layer; 8. Passivation layer; 9. Anti-reflection layer; 10. Conductive layer; 11. Isolation trench; 12. First electrode; 13. Second electrode; 14. Transition surface; A. First region; A1. First sub-region; A2. Second sub-region; B. Second region; C. Spacer region; C1. First spacer sub-region; C2. Second spacer sub-region. DETAILED DESCRIPTION

[0070] The following detailed description of the embodiments of the present disclosure is provided in conjunction with the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of the present disclosure, but are not intended to limit the scope of the present disclosure, that is, the present disclosure is not limited to the described embodiments.

[0071] Back-contact solar cells move the front electrode to the back of the cell, eliminating grid lines on the front, thus eliminating light obstruction. Consequently, back-contact solar cells have higher conversion efficiency. An existing back-contact solar cell primarily comprises a silicon substrate, the back of which includes an N region, a P region, and a spacer region, with adjacent N and P regions separated by the spacer region; a first carrier collection layer located above the N region and the spacer region, and a second carrier collection layer located above the P region and the spacer region. The first and second carrier collection layers have opposite conductivity types. In the spacer region, the second carrier collection layer overlies the first carrier collection layer. The second carrier collection layer comprises an intrinsic silicon-containing layer and a doped silicon-containing layer disposed on the intrinsic silicon-containing layer.

[0072] Through research, the inventors discovered that in existing HBC batteries, the intrinsic silicon-containing layer in the second carrier-collecting layer primarily serves as tunneling passivation. Its thickness is relatively thin, and the first and second carrier-collecting layers in the spacer region are separated only by this thin intrinsic silicon-containing layer. While the intrinsic silicon-containing layer provides a certain degree of insulation, carriers of opposite conductivity types in the first and second carrier-collecting layers can still pass through the intrinsic silicon-containing layer and recombine, causing leakage in the spacer region perpendicular to the silicon substrate surface.

[0073] In addition, the manufacturing process of the above-mentioned solar cell includes two laser film opening processes: after forming a first carrier collection layer on the entire back side of the silicon substrate, the first carrier collection layer located in the P region is removed by the first laser, and then a second carrier collection layer is formed on the entire back side of the silicon substrate, and then the second carrier collection layer located in at least part of the N region is removed by the second laser.

[0074] However, due to the high penetrability of laser, the first laser will cause significant damage to the silicon substrate and the first carrier collection layer adjacent to the P region when removing the first carrier collection layer in the P region; moreover, when the second laser removes the second carrier collection layer in at least part of the N region, it will also cause significant damage to the first carrier collection layer in the N region, the silicon substrate and the adjacent second carrier collection layer.

[0075] Therefore, if the performance of back-contact cells is to be improved, it is necessary to reduce the impact of laser on the carrier collection layer and the silicon substrate. Therefore, reasonable design of the film structure and preparation process is crucial to the formation of high-performance back-contact cells.

[0076] Based on the above ideas, the present disclosure provides a back contact battery, hereinafter referred to as "battery", such as Figure 1 As shown, in some embodiments, the back contact cell includes:

[0077] A silicon substrate 1, wherein the back side includes a first region A, a second region B, and a spacer region C. The adjacent first region A and second region B are separated by the spacer region C. The first region A includes a first sub-region A1 and a second sub-region A2. The spacer region C includes a first spacer sub-region C1 adjacent to the first region A and a second spacer sub-region C2 adjacent to the second region B.

[0078] A first carrier collection layer having a first conductivity type, the first carrier collection layer being disposed on the back side of the silicon substrate 1 and located in the first region A and the first spacer region C1;

[0079] The amorphous semiconductor layer 4 is provided on the surface of the first carrier collection layer away from the silicon substrate 1 and is located in the second sub-region A2 and the first spacer sub-region C1;

[0080] a second carrier collection layer having a second conductivity type opposite to the first conductivity type, the second carrier collection layer being disposed on the back side of the silicon substrate 1 and being located in the second region B, the spacer region C, and the second sub-region A2, wherein the second sub-region A2 and the first spacer sub-region C1 are located on the surface of the amorphous semiconductor layer 4 away from the silicon substrate 1; and

[0081] The first electrode 12 is provided in the first sub-region A1 and is located on a side of the first carrier collection layer away from the silicon substrate 1 .

[0082] The silicon substrate 1 can be N-type or P-type, for example, an N-type silicon wafer, such as a phosphorus-doped single-crystal silicon wafer. Optionally, the front surface of the silicon substrate 1 has a textured surface to reduce light reflection and increase light absorption, thereby improving the photovoltaic conversion efficiency of the battery.

[0083] like Figure 1 As shown, the first region A, the second region B, and the spacer region C are not physical components, but rather are regions demarcated on the back side of the silicon substrate 1. At least one first region A and at least one second region B may be provided. When multiple first regions A and multiple second regions B are provided, the multiple first regions A and multiple second regions B may be alternately provided, for example, along a predetermined direction, which may be the length or width of the silicon substrate 1.

[0084] The first region A includes a first sub-region A1 and a second sub-region A2 adjacent to each other along a predetermined direction. The first sub-region A1 is used to provide the first electrode 12, and the second sub-region A2 can be located on one or both sides of the first sub-region A1. The spacer region C includes a first spacer sub-region C1 and a second spacer sub-region C2 adjacent to each other along a predetermined direction. The first spacer sub-region C1 is adjacent to the first region A, and the second spacer sub-region C2 is adjacent to the second region B. The silicon substrate 1 can be located in the first spacer sub-region C1 and the second spacer sub-region C2 on the same plane or at different heights.

[0085] Furthermore, the terms “first,” “second,” etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

[0086] The first carrier collection layer is provided on the back side of the silicon substrate 1 and is located in the first region A and the first spacer region C1 . The back side of the silicon substrate 1 is located in the first region A and the first spacer region C1 in the same plane.

[0087] The amorphous semiconductor layer 4 is provided on the surface of the first carrier collection layer away from the silicon substrate 1, and is located in the second sub-region A2 and the first spacer sub-region C1, but is not provided in the first sub-region A1. The amorphous semiconductor layer 4 can be provided as an amorphous intrinsic semiconductor layer (undoped) or an amorphous doped semiconductor layer. When an amorphous doped semiconductor layer is used, its doping type is consistent with the doping type of the first carrier collection layer. After doping, the amorphous semiconductor layer 4 has a better light absorption effect and can better reduce damage to the underlying first carrier collection layer and the silicon substrate 1. It is understandable that the doping concentration of the amorphous doped intrinsic semiconductor layer can be set within an appropriate range, on the one hand, to improve the light absorption effect, and on the other hand, not to affect its isolation effect. The amorphous semiconductor layer 4 can be a single layer with the same properties of a thin film layer such as amorphous silicon, silicon oxide or silicon carbide, or a multilayer with different properties, or a stacked or mixed silicon-containing thin film of several types, preferably an amorphous silicon-containing layer.

[0088] The second carrier collection layer is disposed on the back side of the silicon substrate 1 and is located in the second region B, the spacer region C, and the second sub-region A2. It is not disposed in the first sub-region A1. The second carrier collection layer is disposed in the second region B, which is in contact with the back side of the silicon substrate 1. The second carrier collection layer is located in the second sub-region A2 and the first spacer sub-region C1 on the surface of the amorphous semiconductor layer 4 that is away from the silicon substrate 1. In other words, the second carrier collection layer covers the amorphous semiconductor layer 4.

[0089] For example, the first carrier collection layer may be of N-type, and the second carrier collection layer may be of P-type, or vice versa. The first conductivity type is the same as the conductivity type of the silicon substrate 1 .

[0090] The back-contact cell includes a first electrode 12 and a second electrode 13. The first electrode 12 is provided in the first sub-region A1 and is located on the side of the first carrier collection layer away from the silicon substrate 1. The second electrode 13 is provided in the second region B and is located on the side of the second carrier collection layer away from the silicon substrate 1. For example, the first electrode 12 and the second electrode 13 can be one or more stacks of silver electrodes, silver alloy electrodes, copper electrodes, copper alloy electrodes, and nickel / copper / silver multilayer electrodes.

[0091] The battery provided in this embodiment is provided with an amorphous semiconductor layer 4, which has a high absorption coefficient for laser, much higher than that of crystalline silicon. During the battery preparation process, when the excess film layer is removed by a laser process, by covering the amorphous semiconductor layer 4, not only can a mask effect be achieved, but also the laser energy can be efficiently absorbed by the layer, thereby reducing the power of the laser film opening and reducing the damage to the underlying film layer during the laser film opening, mainly reducing the damage to the underlying film layer caused by heat diffusion.

[0092] Specifically, the amorphous semiconductor layer 4 acts as a protective layer, reducing damage to the silicon substrate 1 during the first laser processing of the second region B, and reducing damage to the underlying first carrier collection layer and silicon substrate 1 during the second laser processing of the first sub-region A1. This improves the efficiency of the cell in converting light energy into electrical energy, reduces the impact of damage on the passivation performance of the subsequent passivation layer, and enhances the cell's passivation effectiveness. Consequently, the cell can have superior electrical performance.

[0093] Moreover, because the power parameters of the laser will inevitably fluctuate greatly during the processing, when the power parameters are high, it can prevent major damage to the first carrier collection layer and the silicon substrate 1. When the power parameters are low, the amorphous semiconductor layer 4 has a strong light absorption ability, which can also meet the removal requirements of the film layer. This can broaden the process window of laser film opening, reduce the strictness of control over laser processing parameters, and thus reduce the processing difficulty.

[0094] Furthermore, after the initial laser processing, minimal damage is inflicted on the silicon substrate 1. Therefore, when subsequently removing the film layer on the surface of the second region B to expose the surface of the silicon substrate 1, a thicker layer does not need to be removed to repair the laser damage. This reduces the height difference between the first region A and the second region B, shortening the carrier transmission path, facilitating carrier transport and improving energy conversion efficiency. Furthermore, when removing the damaged layer through chemical etching, the chemical solution corrodes the cross-section, so a thinner layer removed minimizes corrosion, lowering the probability of carrier recombination at the surface and improving the battery's fill factor (FF) and open-circuit voltage (Voc). Furthermore, during passivation, excellent passivation and mechanical properties are achieved at the transition between the first region A and the second region B. For example, defects in the junction cross-section are reduced, passivation layer coverage is uniform, and stress concentration is reduced, thereby improving the overall passivation effect, stabilizing the fabrication process, and increasing battery yield. Furthermore, when forming electrodes through screen printing, less slurry flows into lower-height recessed areas, effectively reducing metal slurry waste and thus lowering manufacturing costs.

[0095] In some embodiments, as Figure 1 As shown, second sub-regions A2 are provided on both sides of first sub-region A1. For example, first sub-region A1 is located in the middle of second sub-region A2. This structure can simultaneously minimize damage to the film layers and silicon substrate 1 in adjacent spacer regions C and second region B during secondary laser removal of the second carrier collection layer and amorphous semiconductor layer 4 of first sub-region A1.

[0096] In some embodiments, the width of the first sub-region A1 accounts for a percentage of 2% to 70% of the width of the first region A. For example, the percentage of the width can be 2%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, etc., without limitation thereto.

[0097] This embodiment, by limiting the width range of the first sub-region A1, can prevent the large width of the first sub-region A1 from significantly affecting the film layer and silicon substrate 1 in the surrounding area during laser processing, and can also prevent the small width of the first sub-region A1 from affecting the current transmission to the first electrode 12. Therefore, by setting the first sub-region A1 within this width range, it can reduce the damage caused by laser removal of the second carrier collection layer and amorphous semiconductor layer 4 of the first sub-region A1, while ensuring current transmission capacity.

[0098] In some embodiments, the first carrier collection layer comprises:

[0099] a tunneling layer 2 disposed on the back side of the silicon substrate 1 and located between the first region A and the first spacer region C1; and

[0100] The doped polysilicon layer 3 is provided on the surface of the tunneling layer 2 away from the silicon substrate 1;

[0101] The amorphous semiconductor layer 4 is disposed on a surface of the doped polysilicon layer 3 away from the silicon substrate 1 , and the first electrode 12 is disposed on a side of the doped polysilicon layer 3 away from the silicon substrate 1 .

[0102] The tunneling layer 2 is an ultrathin dielectric layer that, through the quantum tunneling effect, allows carriers of one conductivity type (e.g., electrons) to efficiently pass through while simultaneously preventing the recombination loss of carriers of the opposite conductivity type (e.g., holes), thereby providing tunneling passivation. For example, silicon oxide, silicon nitride, or aluminum oxide can be used. The doped polysilicon layer 3 has a first conductivity type and can, for example, be an N-type doped polysilicon layer.

[0103] The thickness of the tunneling layer 2 may range from 0.5 nm to 3.0 nm, for example, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3.0 nm, etc.

[0104] The thickness of the doped polysilicon layer 3 can range from 20nm to 200nm, for example, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm and 200nm.

[0105] In some embodiments, the second carrier collection layer comprises:

[0106] An intrinsic silicon-containing layer 6 is provided on the back side of the silicon substrate 1 and is located in the second region B, the spacer region C and the second sub-region A2; and

[0107] The doped silicon-containing layer 7 is provided on the surface of the intrinsic silicon-containing layer 6 away from the silicon substrate 1 and is located at least in the second region B and the second sub-region A2;

[0108] The back contact cell further includes a second electrode 13 , which is provided on a side of the doped silicon-containing layer 7 away from the silicon substrate 1 .

[0109] For example, the amorphous semiconductor layer 4, the intrinsic silicon-containing layer 6 and the doped silicon-containing layer 7 can be a single layer with the same properties or a multilayer with different properties or a stacked or mixed silicon-containing film of microcrystalline, nano, amorphous silicon, silicon oxide or silicon carbide.

[0110] The intrinsic silicon-containing layer 6 also acts as a tunneling passivation layer. The intrinsic low-crystallization silicon-containing layer has very low crystallinity and is almost completely amorphous. The intrinsic silicon-containing layer 6 contains not only silicon but also other elements (such as oxygen, carbon, or nitrogen). This helps improve the battery's bandgap matching, reduce interface band offset, and promote carrier separation. The mixed elements can saturate silicon dangling bonds, reducing passivation failure at high temperatures. Furthermore, it reduces parasitic absorption and anti-reflection effects, and lowers stress to prevent film cracking or delamination. Therefore, the use of the intrinsic silicon-containing layer 6 simultaneously addresses passivation, conductivity, optics, and reliability issues, making it a key design feature for breakthrough heterojunction battery performance. Compared to the use of an intrinsic amorphous silicon layer, the intrinsic amorphous silicon layer contains only pure amorphous silicon, which has a bandgap significantly different from that of crystalline silicon, resulting in band discontinuity at the interface.

[0111] The doped silicon-containing layer 7 contains both amorphous silicon and microcrystalline silicon. Since microcrystalline silicon has a higher carrier mobility and forms a conductive grid that can provide a low-resistance path, it has better conductivity, is conducive to carrier conduction, and can improve the working efficiency of the battery. Compared with the use of doped amorphous silicon, the resistivity of doped amorphous silicon is higher, which is not conducive to the conduction of carriers. In addition, the doped silicon-containing layer 7 also has a wider spectral transmittance, and the transition of microcrystalline silicon can reduce the transition stress at the interface connection, thereby improving the reliability of long-term use. Moreover, the hydrogen in amorphous silicon can passivate interface defects, while microcrystalline silicon provides a conductive channel, achieving synergistic optimization of passivation and conductivity.

[0112] The doped polysilicon layer 3 and the doped silicon-containing layer 7 have opposite conductivity types. For example, the doped polysilicon layer 3 is an N-type doped polysilicon layer, such as doped with elements such as phosphorus, and the doped silicon-containing layer 7 is a P-type doped silicon-containing layer, such as doped with elements such as boron.

[0113] In some embodiments, the thickness of the amorphous semiconductor layer 4 may be greater than the thickness of the intrinsic silicon-containing layer 6. Preferably, the thickness of the amorphous semiconductor layer 4 may range from 10 nm to 40 nm, and the thickness of the intrinsic silicon-containing layer 6 may range from 1 nm to 10 nm. Preferably, the amorphous semiconductor layer 4 is an intrinsic silicon-containing layer.

[0114] Among them, such as Figure 3 and Figure 4The amorphous semiconductor layer 4 is prepared before forming the mask layer 5, and the intrinsic silicon-containing layer 6 adopts a conventional thickness (ie, has a tunneling passivation effect) and does not affect the normal transmission of carriers in the second region B (such as holes in the P region).

[0115] In this embodiment, an amorphous semiconductor layer 4 and an intrinsic silicon-containing layer 6 are provided on the back side of the silicon substrate 1 in the first spacer region C1, and the amorphous semiconductor layer 4 and the intrinsic silicon-containing layer 6 are stacked in the thickness direction. The intrinsic silicon-containing layer 6 is a layer structure conventionally set in a battery. By stacking the amorphous semiconductor layer 4 on the surface of the doped polycrystalline silicon layer 3 away from the silicon substrate 1, the thickness of the film layer with insulating properties in the first spacer region C1 is thickened, which can effectively reduce the leakage risk of the battery, increase the reliability performance of the battery, and improve the stability of the process, which is conducive to large-scale production.

[0116] On this basis, the thickness of the amorphous semiconductor layer 4 can be greater than the thickness of the intrinsic silicon-containing layer 6, which can not only prevent the intrinsic silicon-containing layer 6 from affecting the normal transmission of carriers in the second region B, for example, the second region B is a P region and does not affect the normal transmission of holes, but also greatly increase the thickness of the film layer with insulating properties in the first spacer region C1, which can effectively reduce the risk of battery leakage and increase the reliability performance of the battery.

[0117] In some embodiments, the back contact cell further includes a conductive layer 10 , which covers the second carrier collection layer and the first carrier collection layer located in the first sub-area A1 ;

[0118] The conductive layer 10 defines an isolation trench 11 in the spacing region C. The isolation trench 11 at least penetrates the conductive layer 10 , and the depth of the isolation trench 11 is configured to retain at least a portion of the thickness of the second carrier collection layer.

[0119] For example, the conductive layer 10 is a multilayer, stacked layer, or mixture of one or more doped metal oxides or nitrides. The metal oxide may be indium oxide, tin oxide, zinc oxide, cadmium oxide, or titanium nitride; the metal nitride may be titanium nitride, and the doping element may be indium, tin, calcium, aluminum, cadmium, zinc, cerium, or fluorine.

[0120] like Figure 1 As shown, in the spacing region C, the regions where the isolation trench 11 is provided are the first spacing region C1 and the second spacing region C2 , or the isolation trench 11 may also be provided at a partial width of the spacing region C.

[0121] For example, the width of the isolation trench 11 ranges from 5 μm to 250 μm. Setting the width of the isolation trench 11 within this range not only improves isolation reliability, prevents short circuit risks, avoids leakage, and prevents breakdown, but also reduces waste of light-receiving area, thereby achieving a balance between isolation reliability and photoelectric conversion performance.

[0122] The isolation trench 11 may remove only the conductive layer 10, or remove the conductive layer 10 and a partial thickness of the doped silicon-containing layer 7, or remove the conductive layer 10 and the entire thickness of the doped silicon-containing layer 7, or remove the conductive layer 10, the doped silicon-containing layer 7 and a partial thickness of the intrinsic silicon-containing layer 6.

[0123] This embodiment provides an isolation trench 11, the depth of which at least penetrates the conductive layer 10, to completely cut off the conductive path between the first and second carrier collection layers, preventing a short circuit between the first and second electrodes 12, 13. The greater the depth of the isolation trench 11, the better the isolation effect. Furthermore, retaining a portion or all of the thickness of the second carrier collection layer prevents damage to the silicon substrate 1 in this area.

[0124] When the conductive layer 10 is set, the first electrode 12 is set in the conductive layer 10 of the first sub-area A1 and is in ohmic contact with the conductive layer 10 of the first sub-area A1; the second electrode 13 is set in the conductive layer 10 of the second area B and is in ohmic contact with the conductive layer 10 of the second area B.

[0125] In some embodiments, the back surface of the silicon substrate 1 has a first distance from the front surface in the first region A and the first spacer region C1, and the back surface of the silicon substrate 1 has a second distance from the front surface in the second region B. The first distance is greater than the second distance, and the height difference between the first distance and the second distance does not exceed a predetermined height. Preferably, the predetermined height ranges from 0.1 μm to 4 μm.

[0126] In some embodiments, as Figure 5 As shown, the back side of the silicon substrate 1 is connected between the second region B and the first spacer region C1 via a transition surface 14 .

[0127] Since there is a height difference between the second region B and the first spacer region C1 on the back side of the silicon substrate 1, the connection through the transition surface 14 can relieve the stress at the connection between the second region B and the first spacer region C1, prevent the sharp boundary from causing defects and causing the defect position to become a carrier recombination center, thereby improving the photoelectric conversion efficiency of the battery.

[0128] In some embodiments, the back contact cell further includes a passivation layer 8 and / or an anti-reflection layer 9 disposed on the front surface of the silicon substrate 1. The passivation layer 8 or the anti-reflection layer 9 can improve the passivation performance of the cell and reduce or avoid the impact of defects generated during the cell preparation process.

[0129] For example, the passivation layer 8 is an intrinsic silicon-containing film or a stack of an intrinsic silicon-containing film and a doped silicon-containing film. The conductivity type of the doped silicon-containing film is the same as that of the silicon substrate 1. The intrinsic silicon-containing film can be a silicon-containing film of one or more stacks of microcrystalline, nanocrystalline, amorphous silicon, silicon oxide or silicon carbide film layers, with a thickness of 1nm to 15nm; the doped silicon-containing film can be a silicon-containing film of one or more stacks of microcrystalline, nanocrystalline, amorphous silicon, silicon oxide or silicon carbide film layers, with a thickness of 0nm to 30nm. Alternatively, the passivation layer 8 is silicon oxide SiO x , alumina AlO x , potassium oxide GaO x , titanium oxide TiO x A single layer film or a stacked layer film of several kinds, with a thickness of 1 nm to 15 nm.

[0130] For example, the anti-reflection layer 9 is silicon nitride SiN x , silicon oxynitride SiN x O 1-x , silicon oxide SiO x 、Magnesium fluoride MgF x , lithium fluoride LiF, a single layer film or a stacked layer film of several kinds thereof, with a thickness of 1nm to 300nm.

[0131] In some specific embodiments, such as Figure 1 As shown, the first region A on the back side of the silicon substrate 1 includes a first sub-region A1 and a second sub-region A2, with the second sub-region A2 located on either side of the first sub-region A1. On the back side of the silicon substrate 1, a tunneling layer 2, a doped polysilicon layer 3, a conductive layer 10, and a first electrode 12 are sequentially provided in the first sub-region A1 away from the silicon substrate 1. In the second sub-region A2, a tunneling layer 2, a doped polysilicon layer 3, an amorphous semiconductor layer 4, an intrinsic silicon-containing layer 6, a doped silicon-containing layer 7, and a conductive layer 10 are sequentially provided in the direction away from the silicon substrate 1.

[0132] The second region B on the back side of the silicon substrate 1 is provided with an intrinsic silicon-containing layer 6 , a doped silicon-containing layer 7 , a conductive layer 10 and a second electrode 13 in sequence in a direction away from the silicon substrate 1 .

[0133] The first isolation sub-region C1 on the back side of the silicon substrate 1 is provided with a tunneling layer 2, a doped polysilicon layer 3, an amorphous semiconductor layer 4, an intrinsic silicon-containing layer 6, and a doped silicon-containing layer 7 in the order of distance away from the silicon substrate 1. The second isolation sub-region C2 on the back side of the silicon substrate 1 is inclined, and the intrinsic silicon-containing layer 6 and the doped silicon-containing layer 7 are provided in the order of distance away from the inclined surface.

[0134] This type of battery is a combination of TBC and HBC. The first area A is prepared at high temperature and the second area B is prepared at low temperature.

[0135] Next, a photovoltaic module includes the back-contact cell of the above embodiment. Exemplarily, the photovoltaic module includes a laminate and a frame assembled on the edge of the laminate, wherein the laminate includes a cover plate, an adhesive film, a back-contact cell, an adhesive film, and a back plate stacked in sequence.

[0136] Since the amorphous semiconductor layer 4 is provided in the battery, the thickness of the insulating film layer in the spacer region is increased, effectively preventing leakage in the spacer region. In addition, the amorphous semiconductor layer 4 has a high absorption coefficient for lasers, which is much higher than that of crystalline silicon. During the battery preparation process, when the excess film layer is removed by the laser process, by covering the amorphous semiconductor layer 4, not only can a masking effect be achieved, but the laser energy can also be efficiently absorbed by the layer, thereby reducing the power of the laser film opening and reducing the damage to the underlying film layer during the laser film opening. In addition, the height difference between the first area A and the second area B is small, which is conducive to carrier transmission and reduces the probability of carrier surface recombination, thereby improving the fill factor and open circuit voltage of the battery. When forming the electrode by screen printing, the waste of metal paste can be effectively reduced. As a result, the battery can have better electrical performance and reduce manufacturing costs. This can also improve the efficiency of photovoltaic modules in converting light energy into electrical energy and improve overall performance.

[0137] Finally, the embodiments of the present disclosure provide a method for preparing a back contact battery. In some embodiments, as Figure 11 As shown, the preparation method comprises:

[0138] S1. Provide a silicon substrate 1. The back side of the silicon substrate 1 includes a first region A, a second region B, and a spacer region C. The adjacent first region A and second region B are separated by the spacer region C. The first region A includes a first sub-region A1 and a second sub-region A2. The spacer region C includes a first spacer sub-region C1 adjacent to the first region A and a second spacer sub-region C2 adjacent to the second region B.

[0139] S2, forming a first carrier collection layer and an amorphous semiconductor layer 4 having a first conductivity type on the first region A and the first spacer region C1 on the back side of the silicon substrate 1;

[0140] S3, forming a second carrier collection layer having a second conductivity type on the entire back side of the silicon substrate 1, where the second conductivity type is opposite to the first conductivity type;

[0141] S4, removing the second carrier collection layer and the amorphous semiconductor layer 4 in the first sub-region A1 on the back side of the silicon substrate 1;

[0142] S5 . Form a first electrode 12 on a side of the first sub-region A1 of the first carrier collection layer away from the silicon substrate 1 .

[0143] Specifically, steps S1 to S5 are executed sequentially.

[0144] In step S1, Figure 2 As shown, the silicon substrate 1 includes a front surface and a back surface. The back surface includes a first region A, a second region B, and a spacer region C. Adjacent first regions A and second regions B are separated by the spacer region C. When multiple first regions A and multiple second regions B are provided, the first regions A and second regions B are alternately provided, and the spacer region C is provided between adjacent first regions A and second regions B. The first sub-region A1 and the second sub-region A2 are adjacently provided, and the first spacer sub-region C1 and the second spacer sub-region C2 are adjacently provided.

[0145] In step S2, a first carrier collection layer and an amorphous semiconductor layer 4 are formed on the first region A and the first spacer region C1 on the back side of the silicon substrate 1. Specifically, a tunneling layer 2, a doped polysilicon layer 3 and an amorphous semiconductor layer 4 are sequentially arranged in a direction away from the silicon substrate 1 to form a structure as shown in FIG. Figure 5 The film structure shown.

[0146] In step S3, a second carrier collection layer is formed on the entire back side of the silicon substrate 1. Specifically, an intrinsic silicon-containing layer 6 and a doped silicon-containing layer 7 are sequentially provided in a direction away from the silicon substrate 1. In the second region B and the second spacer region C2, the second carrier collection layer directly covers the surface of the silicon substrate 1. In the first region A and the first spacer region C1, the second carrier collection layer covers the amorphous semiconductor layer 4, forming a structure as shown in FIG. Figure 6 The structure shown.

[0147] In step S4, the second carrier collection layer and the amorphous semiconductor layer 4 in the first sub-region A1 on the back of the silicon substrate 1 can be removed by etching, cleaning or laser. Specifically, the intrinsic silicon-containing layer 6, the doped silicon-containing layer 7 and the amorphous semiconductor layer 4 in the first sub-region A1 are removed to expose the first carrier collection layer. Specifically, the first carrier collection layer includes a tunneling layer 2 and a doped polysilicon layer 3. After removing the intrinsic silicon-containing layer 6, the doped silicon-containing layer 7 and the amorphous semiconductor layer 4 in the first sub-region A1, the doped polysilicon layer 3 is exposed. Thus, a structure as shown in FIG. Figure 7 The structure shown.

[0148] In step S5 , a first electrode 12 is formed on a side of the first carrier collection layer of the first sub-area A1 away from the silicon substrate 1 ; this step may also include forming a second electrode 13 on a side of the second carrier collection layer of the second area B away from the silicon substrate 1 .

[0149] The preparation method of this embodiment sets an amorphous semiconductor layer 4 on the surface of the first carrier collection layer, which has a high absorption coefficient for lasers, much higher than that of crystalline silicon. During the battery preparation process, when removing excess film layers through a laser process, by covering the amorphous semiconductor layer 4, not only can a masking effect be achieved, but the laser energy can also be efficiently absorbed by the layer, thereby reducing the power of the laser film opening and reducing the damage to the underlying film layer during the laser film opening, mainly by reducing the damage to the underlying film layer caused by thermal diffusion. In this way, the efficiency of the battery in converting light energy into electrical energy can be improved, and the impact of damage on the passivation performance of the subsequent passivation layer can be reduced, thereby improving the passivation effect of the battery. As a result, the battery can have better electrical performance.

[0150] Moreover, because the power parameters of the laser will inevitably fluctuate greatly during the processing, when the power parameters are high, it can prevent major damage to the first carrier collection layer and the silicon substrate 1. When the power parameters are low, the amorphous semiconductor layer 4 has a strong light absorption ability, which can also meet the removal requirements of the film layer. This can broaden the process window of laser film opening, reduce the strictness of control over laser processing parameters, and thus reduce the processing difficulty.

[0151] Furthermore, after the initial laser processing, minimal damage is inflicted on the silicon substrate 1. Therefore, when subsequently removing the film layer on the surface of the second region B to expose the surface of the silicon substrate 1, a thicker layer does not need to be removed to repair the laser damage. This reduces the height difference between the first region A and the second region B, shortening the carrier transmission path, facilitating carrier transport and improving energy conversion efficiency. Furthermore, when removing the damaged layer through chemical etching, the chemical solution corrodes the cross-section, so a thinner layer removed minimizes corrosion, lowering the probability of carrier recombination at the surface and improving the battery's fill factor (FF) and open-circuit voltage (Voc). Furthermore, during passivation, excellent passivation and mechanical properties are achieved at the transition between the first region A and the second region B. For example, defects in the junction cross-section are reduced, passivation layer coverage is uniform, and stress concentration is reduced, thereby improving the overall passivation effect, stabilizing the fabrication process, and increasing battery yield. Furthermore, when forming electrodes through screen printing, less slurry flows into lower-height recessed areas, effectively reducing metal slurry waste and thus lowering manufacturing costs.

[0152] In some embodiments, the first carrier collection layer further includes a tunneling layer 2 and a doped polysilicon layer 3, and S2 includes:

[0153] S21, sequentially disposing a tunneling layer 2, a doped polysilicon layer 3, an amorphous semiconductor layer 4 and a mask layer 5 on the entire back surface of the silicon substrate 1;

[0154] S22, removing the tunneling layer 2, the doped polysilicon layer 3, the amorphous semiconductor layer 4 and the mask layer 5 in the second region B and the second spacer region C2 by laser;

[0155] S23 , removing the mask layer 5 of the first spacer region C1 and the first region A.

[0156] Among them, steps S21 to S23 are executed sequentially.

[0157] In step S21, a tunneling layer 2, a doped polysilicon layer 3, an amorphous semiconductor layer 4 and a mask layer 5 are sequentially provided on the entire back side of the silicon substrate 1 along the surface away from the silicon substrate to form Figure 3 The structure shown. For example, the mask layer 5 is a silicon nitride, oxide layer, or a stacked or mixed thin film. The main function of the mask layer 5 is to protect the doped polysilicon layer 3 during the subsequent cleaning and texturing of the silicon substrate 1 to prevent the doped polysilicon layer 3 from being corroded.

[0158] In step S22, the tunneling layer 2, the doped polysilicon layer 3, the amorphous semiconductor layer 4 and the mask layer 5 of the second region B and the second spacer region C2 are removed by the first laser to form Figure 4 The structure shown.

[0159] In step S23, the mask layer 5 of the first spacer region C1 and the first region A can be removed by cleaning with an acid solution, for example, to form Figure 5 The film structure shown.

[0160] Prior art typically uses silicon nitride (SiNx) as a mask. However, SiNx is difficult to open and exhibits low parasitic light absorption, requiring higher laser energy. Furthermore, SiNx deposition quality is generally poor at the edges of the silicon substrate 1, or dust is deposited onto the surface of the silicon substrate 1 during deposition, resulting in poor masking effectiveness.

[0161] The embodiment of the present disclosure adds an amorphous semiconductor layer 4 between the mask layer 5 and the doped polysilicon 3, which has a higher absorption coefficient for laser, much higher than that of crystalline silicon. During the battery preparation process, when the excess film layer is removed by laser technology, by covering the amorphous semiconductor layer 4, it can not only play a mask effect, but also make the laser energy efficiently absorbed by the layer, thereby reducing the power of laser film opening. The laser only needs to open the amorphous semiconductor layer 4, and the mask layer 5 covering it can be removed at the same time as the amorphous silicon semiconductor layer 4 is removed.

[0162] Moreover, this preparation method adds an amorphous semiconductor layer 4 under the mask layer 5, which is equivalent to adding another film layer with blocking ability, and can also play a certain masking effect, reducing the velvet problem at the edge of the silicon substrate 1 during velvet preparation. Therefore, the reliability of the mask can be improved, the wet process is more stable, and can be applied to large-scale industrialization.

[0163] In some embodiments, the second carrier collection layer includes: an intrinsic silicon-containing layer 6 and a doped silicon-containing layer 7, and S3 includes:

[0164] S31, after laser removal of all layer structures on the back surface of the silicon substrate 1 in the second region B and the second spacer region C2, continue to remove a portion of the thickness of the back surface of the silicon substrate 1 in the second region B, and form a textured surface in the second region B;

[0165] S32 , forming an intrinsic silicon-containing layer 6 and a doped silicon-containing layer 7 in sequence on the back side of the silicon substrate 1 .

[0166] Among them, steps S31~S32 are executed sequentially.

[0167] In step S31, after step S22, the thickness of the second region B on the back of the silicon substrate 1 is further removed by alkaline solution, and a textured surface is formed in the second region B. While the textured surface is formed in the second region B on the back of the silicon substrate 1, a textured surface can also be formed on the front of the silicon substrate 1, and the mask layer 5 can be removed by hydrofluoric acid or the like. Since there is a height difference between the second region B on the back of the silicon substrate 1 and the first spacer region C1, an inclined transition surface is formed between the second region B and the first spacer region C1, forming Figure 5 The structure shown.

[0168] In step S32, a vapor deposition device can be used to sequentially form an intrinsic silicon-containing layer 6 and a doped silicon-containing layer 7 on the back of the silicon substrate 1. The intrinsic silicon-containing layer 6 and the doped silicon-containing layer 7 cover the second area B and extend to cover the spacer area C and the first area A, forming Figure 6 The structure shown.

[0169] This embodiment takes into account that when the film layer of the second region B is removed by a single laser in step S22, although the amorphous semiconductor layer 4 can well protect the silicon substrate 1, it may still cause certain damage to the silicon substrate 1 in the second region B. By continuing to remove part of the thickness of the back side of the silicon substrate 1 in the second region B in step S31, the laser damage can be eliminated to the greatest extent, and a textured surface can be formed in the first region B at the same time.

[0170] In some embodiments, the preparation method further comprises:

[0171] S6, forming a textured surface on the front side of the silicon substrate 1;

[0172] S7 . Form a passivation layer 8 and / or an anti-reflection layer 9 on the front surface of the silicon substrate 1 .

[0173] Among them, steps S6 and S7 are performed sequentially.

[0174] In step S6, the front surface of the silicon substrate 1 can be formed into a textured surface by using an alkaline solution, such as Figure 5 As shown. Steps S6 and S7 are executed before S5. Steps S6 and S31 can be completed in the same step or in different steps, and the execution order is not limited. The execution order of steps S7 and S32 is not limited.

[0175] Specifically, a passivation layer 8 is first formed on the front surface of the silicon substrate 1 after texturing, and then an anti-reflection layer 9 is formed on the passivation layer 8 to form a Figure 6 The structure shown.

[0176] In this embodiment, the passivation layer 8 or the anti-reflection layer 9 can improve the passivation performance of the battery, thereby reducing or avoiding the impact of defects generated during the preparation process of the battery.

[0177] In some embodiments, the preparation method of the present disclosure further includes:

[0178] S8, forming a conductive layer 10 on the back side of the silicon substrate 1;

[0179] S9. An isolation trench 11 is formed in the spacer region C on the conductive layer 10. The isolation trench 11 at least penetrates the conductive layer 10, and the depth of the isolation trench 11 is configured to retain at least a portion of the thickness of the second carrier collection layer.

[0180] Steps S8 and S9 are executed before step S5. The execution order of steps S8 and S9 and steps S6 and S7 is not limited.

[0181] The isolation trench 11 may remove only the conductive layer 10, or remove the conductive layer 10 and a partial thickness of the doped silicon-containing layer 7, or remove the conductive layer 10 and the entire thickness of the doped silicon-containing layer 7, or remove the conductive layer 10, the doped silicon-containing layer 7 and a partial thickness of the intrinsic silicon-containing layer 6.

[0182] This embodiment provides an isolation trench 11, the depth of which at least penetrates the conductive layer 10, to completely cut off the metal conductive path between the first and second carrier collection layers, preventing a short circuit between the first and second electrodes 12 and 13. The greater the depth of the isolation trench 11, the better the isolation effect. Furthermore, retaining a portion or all of the thickness of the second carrier collection layer prevents loss of carrier collection capacity in the area where the isolation trench 11 is located, and avoids exposing the silicon substrate 1 in this area and causing leakage.

[0183] A specific example is given below to illustrate the preparation method of the battery disclosed herein.

[0184] (1) Provide Figure 2 The silicon substrate 1 shown is, for example, an N-type silicon substrate 1, and the back side of the silicon substrate 1 includes a first region A, a second region B and a spacer region C. The adjacent first region A and second region B are separated by the spacer region C. The first region A includes a first sub-region A1 and a second sub-region A2. The spacer region C includes: a first spacer sub-region C1 adjacent to the first region A and a second spacer sub-region C2 adjacent to the second region B.

[0185] (2) A tunneling layer 2, a doped polysilicon layer 3, an amorphous semiconductor layer 4 and a mask layer 5 are sequentially provided on the entire back side of the silicon substrate 1. For example, the mask layer 5 is a silicon nitride film. Figure 3 The structure shown.

[0186] (3) The tunneling layer 2, doped polysilicon layer 3, amorphous semiconductor layer 4 and mask layer 5 of the second region B and the second spacer region C2 are removed by laser to form Figure 4 The structure shown.

[0187] (4) The silicon substrate 1 is polished and textured to form a textured surface on the front and back second regions B of the silicon substrate 1, and then the mask layer 5 located in the first region A and the first spacer region C1 on the back of the silicon substrate 1 is removed to form Figure 5 Due to the protection of the mask layer 5, the film structure of the first area A will not be damaged when the second area B on the front and back sides of the silicon substrate 1 is textured.

[0188] (5) A passivation layer 8 and an anti-reflection layer 9 are sequentially formed on the front surface of the silicon substrate 1, and an intrinsic silicon-containing layer 6 and a doped silicon-containing layer 7 are sequentially formed on the entire back surface of the silicon substrate 1 to form Figure 6 The structure shown.

[0189] (6) The amorphous semiconductor layer 4, the intrinsic silicon-containing layer 6 and the doped silicon-containing layer 7 on the back side of the silicon substrate 1 in the first sub-region A1 are removed to expose the doped polysilicon layer 3, forming Figure 7 The structure shown.

[0190] (7) A conductive layer 10 is formed on the entire back surface of the silicon substrate 1 to form Figure 8 The structure shown.

[0191] (8) An isolation groove 11 is formed in the spacer region C on the conductive layer 10. The isolation groove 11 at least penetrates the conductive layer 10, and the depth of the isolation groove 11 is configured to retain at least a portion of the thickness of the second carrier collection layer, forming Figure 9 The structure shown.

[0192] (9) A first electrode 12 and a second electrode 13 are respectively formed on the first sub-area A1 and the second sub-area B on the back of the silicon substrate 1 to form Figure 10 The structure shown.

[0193] In step (5), the order of forming the film layer on the front surface of the silicon substrate 1 and forming the film layer on the back surface of the silicon substrate 1 can be adjusted, but the passivation layer 8 is formed before the anti-reflection layer 9, and the intrinsic silicon-containing layer 6 is formed before the doped silicon-containing layer 7.

[0194] While the present disclosure has been described with reference to preferred embodiments, various modifications may be made thereto and equivalent components may be substituted without departing from the scope of the present disclosure. In particular, the various technical features described in the various embodiments may be combined in any manner, provided no structural conflicts exist. The present disclosure is not limited to the specific embodiments disclosed herein, but encompasses all technical solutions within the scope of the claims.

Claims

1. A back contact battery, characterized in that: include: A silicon substrate (1), the back side of which comprises a first region (A), a second region (B) and a spacer region (C), wherein the adjacent first region (A) and the second region (B) are separated by the spacer region (C), the first region (A) comprises a first sub-region (A1) and a second sub-region (A2), and the spacer region (C) comprises a first spacer sub-region (C1) adjacent to the first region (A) and a second spacer sub-region (C2) adjacent to the second region (B); a first carrier collection layer having a first conductivity type, the first carrier collection layer being arranged on the back side of the silicon substrate (1) and located in the first region (A) and the first spacer region (C1); an amorphous semiconductor layer (4), provided on a surface of the first carrier collection layer away from the silicon substrate (1), and located between the second sub-region (A2) and the first spacer sub-region (C1); a second carrier collection layer having a second conductivity type opposite to the first conductivity type, the second carrier collection layer being arranged on the back side of the silicon substrate (1) and being located in the second region (B), the spacer region (C) and the second sub-region (A2), wherein the second sub-region (A2) and the first spacer sub-region (C1) are located on the surface of the amorphous semiconductor layer (4) away from the silicon substrate (1); and A first electrode (12) is provided in the first sub-region (A1) and is located on a side of the first carrier collection layer away from the silicon substrate (1).

2. The back contact battery according to claim 1, characterized in that The second sub-area (A2) is provided on both sides of the first sub-area (A1).

3. The back contact battery according to claim 1, characterized in that The percentage of the width of the first sub-region (A1) to the width of the first region (A) is in a range of 2% to 70%.

4. The back contact cell according to claim 1, wherein The first carrier collection layer comprises: a tunneling layer (2), provided on the back side of the silicon substrate (1) and located in the first region (A) and the first spacer region (C1); and a doped polysilicon layer (3) provided on a surface of the tunneling layer (2) away from the silicon substrate (1); The amorphous semiconductor layer (4) is provided on a surface of the doped polysilicon layer (3) away from the silicon substrate (1), and the first electrode (12) is provided on a side of the doped polysilicon layer (3) away from the silicon substrate (1).

5. The back contact battery according to claim 4, wherein The thickness of the tunneling layer (2) is in the range of 0.5 nm to 3.0 nm; and / or The thickness of the doped polysilicon layer (3) ranges from 20 nm to 200 nm.

6. The back contact cell according to claim 1, wherein The second carrier collection layer comprises: an intrinsic silicon-containing layer (6), provided on the back side of the silicon substrate (1) and located in the second region (B), the spacer region (C) and the second sub-region (A2); and a doped silicon-containing layer (7), provided on a surface of the intrinsic silicon-containing layer (6) away from the silicon substrate (1), and located at least in the second region (B) and the second sub-region (A2); The back contact cell further comprises a second electrode (13), and the second electrode (13) is provided on a side of the doped silicon-containing layer (7) away from the silicon substrate (1).

7. The back contact battery according to claim 6, characterized in that The thickness of the amorphous semiconductor layer (4) is greater than the thickness of the intrinsic silicon-containing layer (6); Preferably, the thickness of the amorphous semiconductor layer (4) is in the range of 10 nm to 40 nm, and / or the thickness of the intrinsic silicon-containing layer (6) is in the range of 1 nm to 10 nm; Preferably, the amorphous semiconductor layer (4) is an intrinsic silicon-containing layer.

8. The back contact battery according to any one of claims 1 to 7, characterized in that: It also includes a conductive layer (10), wherein the conductive layer (10) covers the second carrier collection layer and the first carrier collection layer located in the first sub-area (A1); The conductive layer (10) has an isolation groove (11) in the spacer region (C), the isolation groove (11) at least penetrates the conductive layer (10), and the depth of the isolation groove (11) is configured to retain at least a portion of the thickness of the second carrier collection layer.

9. The back contact battery according to claim 8, characterized in that The width of the isolation groove (11) ranges from 5um to 250um.

10. The back contact battery according to any one of claims 1 to 7, characterized in that: The back surface of the silicon substrate (1) has a first distance from the front surface in the first area (A) and the first spacer area (C1), and the back surface of the silicon substrate (1) has a second distance from the front surface in the second area (B), the first distance is greater than the second distance, and the height difference between the first distance and the second distance does not exceed a preset height; Preferably, the preset height ranges from 0.1um to 4um.

11. The back contact battery according to claim 10, characterized in that The back side of the silicon substrate (1) is connected between the second region (B) and the first spacer region (C1) via a transition surface (14).

12. The back contact battery according to any one of claims 1 to 7, characterized in that: It also includes a passivation layer (8) and / or an anti-reflection layer (9) provided on the front side of the silicon substrate (1).

13. A photovoltaic module, characterized in that: A back contact battery comprising the back contact battery according to any one of claims 1 to 12.

14. A method for preparing a back contact battery, characterized in that: include: S1. Providing a silicon substrate (1), wherein the back surface of the silicon substrate (1) comprises a first region (A), a second region (B), and a spacer region (C), wherein the adjacent first region (A) and the second region (B) are separated by the spacer region (C), wherein the first region (A) comprises a first sub-region (A1) and a second sub-region (A2), and the spacer region (C) comprises a first spacer sub-region (C1) adjacent to the first region (A) and a second spacer sub-region (C2) adjacent to the second region (B); S2, forming a first carrier collection layer and an amorphous semiconductor layer (4) having a first conductivity type in the first region (A) and the first spacer region (C1) on the back side of the silicon substrate (1); S3, forming a second carrier collection layer having a second conductivity type on the entire back side of the silicon substrate (1), wherein the second conductivity type is opposite to the first conductivity type; S4, removing the second carrier collection layer and the amorphous semiconductor layer (4) on the back side of the silicon substrate (1) in the first sub-region (A1); S5. Forming a first electrode (12) on a side of the first sub-region (A1) of the first carrier collection layer away from the silicon substrate (1).

15. The preparation method according to claim 14, characterized in that The first carrier collection layer further includes a tunneling layer (2) and a doped polysilicon layer (3), and S2 includes: S21, sequentially arranging the tunneling layer (2), the doped polysilicon layer (3), the amorphous semiconductor layer (4), and the mask layer (5) on the entire back surface of the silicon substrate (1); S22, removing the tunneling layer (2), the doped polysilicon layer (3), the amorphous semiconductor layer (4), and the mask layer (5) in the second region (B) and the second spacer region (C2) by laser; S23, removing the mask layer (5) of the first spacer region (C1) and the first region (A).

16. The preparation method according to claim 14, characterized in that The second carrier collection layer comprises: an intrinsic silicon-containing layer (6) and a doped silicon-containing layer (7), and the S3 comprises: S31, after laser removal of all layer structures on the back side of the silicon substrate (1) in the second area (B) and the second spacer area (C2), continue to remove a portion of the thickness of the back side of the silicon substrate (1) in the second area (B), and form a textured surface in the second area (B); S32, sequentially forming the intrinsic silicon-containing layer (6) and the doped silicon-containing layer (7) on the back side of the silicon substrate (1).

17. The preparation method according to any one of claims 14 to 16, characterized in that Also includes: S6, forming a textured surface on the front side of the silicon substrate (1); S7. Forming a passivation layer (8) and / or an anti-reflection layer (9) on the front surface of the silicon substrate (1).

18. The preparation method according to any one of claims 14 to 16, characterized in that Also includes: S8, forming a conductive layer (10) on the back side of the silicon substrate (1); S9. An isolation groove (11) is formed in the spacer region (C) on the conductive layer (10), wherein the isolation groove (11) at least penetrates the conductive layer (10), and the depth of the isolation groove (11) is configured to retain at least a portion of the thickness of the second carrier collection layer.

Images