TOPCon battery and preparation method thereof

Abstract

The invention provides a TOPCon cell and a preparation method thereof, and relates to the technical field of solar cells, and the TOPCon cell comprises a silicon substrate; and a back intrinsic amorphous silicon layer and a P-type amorphous silicon layer are sequentially laminated on the back of the silicon substrate. A back intrinsic amorphous silicon layer (a-Si: H (I)) and a P-type amorphous silicon layer (a-Si: H (p)) are used as a back passivation structure, and the method has the following advantages that (1) passivation is realized by adopting an amorphous silicon (a-Si) film, the interface defect state density of the amorphous silicon layer is effectively reduced through hydrogen passivation, and the surface recombination rate is obviously lower than that of an existing tunneling oxide layer and polycrystalline silicon composite structure; and (2) the wide band gap characteristic (about 1.7-1.8 eV) of the amorphous silicon can more effectively inhibit carrier recombination.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a TOPCon cell and a preparation method thereof. Background Art

[0002] In the field of photovoltaic technology, TOPCon cells, as a high-efficiency solar cell, have attracted widespread attention due to their excellent passivation effect and high conversion efficiency. The back structure design of TOPCon cells generally adopts a combination of a tunneling oxide layer and a p-type polysilicon (p-poly) layer to achieve effective carrier transport and passivation. However, in existing technologies, the doping concentration of the p-poly layer is limited by the solid solubility of the element boron, resulting in poor passivation quality and contact resistance.

[0003] At present, the manufacturing process of TOPCon batteries mainly uses the low-pressure chemical vapor deposition (LPCVD) method to first form the intrinsic layer, and then doping is achieved through the boron diffusion process. Although this process has met the needs of battery manufacturing to a certain extent, it also has many technical bottlenecks. First, the deposition rate of the LPCVD method is slow, and the uniformity of the boron diffusion process is difficult to control, resulting in uneven distribution of the thickness of the Poly layer. When the Poly layer is too thin, the oxide layer is prone to burn-through during the silver paste sintering process, which in turn causes quality problems such as poor EL or contact failure. Secondly, the high-temperature treatment process required for the boron diffusion process will generate thermal stress on the battery cell, causing the substrate to warp, thereby increasing the fragmentation rate in the process and reducing the product yield. In addition, the process route of first intrinsic doping and then boron diffusion will lead to an increase in the defect state density of the P-Poly layer, increase the probability of carrier recombination, and ultimately affect the conversion efficiency of the battery.

[0004] Given the aforementioned technical deficiencies, existing processes face significant challenges in improving the conversion efficiency and yield of TOPCon cells. Therefore, developing new TOPCon cell structures and process preparation methods to overcome existing technical bottlenecks has become an important direction for the development of TOPCon cell technology.

[0005] In view of this, the present invention is proposed. Summary of the Invention

[0006] One of the objectives of the present invention is to provide a TOPCon battery to at least solve one of the technical problems existing in the prior art.

[0007] A second object of the present invention is to provide a method for preparing a TOPCon battery.

[0008] In order to achieve the above-mentioned purpose of the present invention, the following technical solutions are adopted:

[0009] In a first aspect, the present invention provides a TOPCon cell, comprising a silicon substrate; a back side intrinsic amorphous silicon layer and a P-type amorphous silicon layer are sequentially stacked on the back side of the silicon substrate.

[0010] Furthermore, a TCO film layer is provided on a side of the P-type amorphous silicon layer away from the intrinsic amorphous silicon layer.

[0011] Furthermore, the metal area on the front surface of the silicon substrate is sequentially stacked with a tunneling oxide layer, a phosphorus-doped polysilicon layer, a passivation layer and an anti-reflection layer; the non-metal area on the front surface of the silicon substrate is sequentially stacked with a passivation layer and an anti-reflection layer;

[0012] Preferably, the material of the passivation layer includes aluminum oxide; and the material of the anti-reflection layer includes silicon nitride.

[0013] In a second aspect, the present invention provides a method for preparing a TOPCon cell, comprising the following steps: sequentially laminating a back intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the back side of a silicon substrate.

[0014] Furthermore, a PECVD deposition process is used to prepare a back intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the back of the silicon wafer; the thickness of the back intrinsic amorphous silicon layer is 5-20 nm; the thickness of the P-type amorphous silicon layer is 5-20 nm; the deposition temperature is 180-250° C.; the deposition time is 10-30 min; the pressure is 50-500 Pa; the required gases include SiH, H, and BH; the gas flow ratio of SiH, H, and BH is 1-3:10-50:0.1-0.3; the doping concentration is 1E19-5E20 / cm 3 ;

[0015] Preferably, a TCO film layer is prepared on the P-type amorphous silicon layer;

[0016] Preferably, the thickness of the TCO film layer is 60-200 nm;

[0017] Preferably, before preparing the TCO film layer, plasma cleaning is used to activate the silicon wafer surface;

[0018] Preferably, the plasma comprises argon or oxygen; the power is 100-300 W; and the treatment time is 5-15 minutes.

[0019] Furthermore, before preparing the back structure on the silicon substrate, the method for preparing the TOPCon cell further includes the following steps:

[0020] (a) A tunneling oxide layer and a front intrinsic amorphous silicon layer are sequentially stacked on the front surface of a silicon substrate; phosphorus diffusion is then performed to dope phosphorus into the front intrinsic amorphous silicon layer to form a phosphorus-doped polysilicon layer, while a PSG layer is formed on the surface of the phosphorus-doped polysilicon layer;

[0021] (b) removing the PSG layer in the non-gate line area on the front side of the silicon wafer; then removing the PSG layer that was plated; then removing the phosphorus-doped polysilicon layer, tunnel oxide layer, and the phosphorus-doped polysilicon layer and tunnel oxide layer in the non-gate line area on the front side of the silicon substrate, and texturing the non-gate line area on the front side of the silicon substrate; then removing the PSG layer in the gate line area on the front side of the silicon substrate;

[0022] (c) A passivation layer and an anti-reflection layer are sequentially stacked on the front side of the silicon wafer.

[0023] Furthermore, in step (a), a tunnel oxide layer and a front intrinsic amorphous silicon layer are formed on the front surface of the silicon substrate using an LPCVD deposition process;

[0024] Preferably, the thickness of the tunnel oxide layer is 1.2-2.5 nm; the gas used for preparation is O2; the gas flow rate of O2 is 15000-30000 sccm; the deposition time is 100-400 s; and the deposition temperature is 450-700° C.;

[0025] Preferably, the thickness of the PSG layer is 50-90 nm; the thickness of the phosphorus-doped polysilicon layer is 60-200 nm; the gases used for deposition are POCl3 and O2; the POCl3 gas flow rate is 300-2000 sccm; and the O2 gas flow rate is 20000-30000 sccm.

[0026] Furthermore, in step (b), the PSG layer in the non-gate line area on the front side of the silicon wafer is removed by laser patterning;

[0027] Preferably, the laser power is 20%-50%; the laser scanning speed is 30000-50000 mm / s;

[0028] Preferably, a one-step chain cleaning process is used to remove the plated PSG layer;

[0029] Preferably, the reagent used in the one-step chain cleaning process includes HF solution; the concentration of the HF solution is 5%-9%;

[0030] Preferably, a groove texturing process is used to remove the phosphorus-doped polysilicon layer, the tunnel oxide layer and the plated phosphorus-doped polysilicon layer and the tunnel oxide layer in the non-gate line area on the front surface, and texturing is performed on the non-gate line area on the front surface of the silicon substrate;

[0031] Preferably, the components of the reagents used in the tank texturing process include 3%-6% NaOH, 0.3%-2.5% additives and 3%-12% H2O2 by mass percentage; the processing temperature of the tank texturing process is 50-80°C; and the process time is 300-600s;

[0032] Preferably, a secondary chain cleaning is used to remove the PSG layer in the gate line area on the front side of the silicon substrate;

[0033] Preferably, the reagent used in the secondary chain cleaning process includes HF solution; the concentration of the HF solution is 5%-9%.

[0034] Furthermore, in step (c), the passivation layer is prepared by atomic layer deposition;

[0035] Preferably, the thickness of the passivation layer is 3-5 nm; the deposition temperature is 200-350° C.; the deposition time is 30-60 min; the gases required for depositing the passivation layer include TMA and water; the gas flow ratio of TMA to water is 1:3-1:4;

[0036] Preferably, the anti-reflection layer is prepared by a PECVD deposition process; the thickness of the anti-reflection layer is 70-130 nm; the deposition temperature is 400-600°C; the time is 40-80 min; the gases required for depositing the anti-reflection layer include N3H, SiH4 and N2O, and the gas flow ratio of N3H, SiH4 and N2O is 1-3:5-15:3-12.

[0037] Furthermore, after step (c) and before step (b), a three-way chain cleaning process is used to remove the passivation layer and the anti-reflection layer coated on the back and edge of the silicon wafer;

[0038] Preferably, the reagent used in the three-chain cleaning process includes HF solution; the concentration of the HF solution is 5%-9%;

[0039] Preferably, after three chain cleanings, the back of the silicon wafer is polished using tank cleaning; the polishing process uses NaOH solution with a concentration of 2%-6%; the polishing temperature is 55-75° C.; and the polishing time is 300-500 seconds.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] The TOPCon cell provided by the present invention has a back intrinsic amorphous silicon layer (a-Si:H(I)) and a p-type amorphous silicon layer (a-Si:H(p)) arranged on the back of the silicon substrate in sequence from the inside to the outside. The back intrinsic amorphous silicon layer (a-Si:H(I)) + p-type amorphous silicon layer (a-Si:H(p)) forms a back passivation structure, which has the following advantages: (1) passivation is achieved by using an amorphous silicon (a-Si) thin film, and the amorphous silicon layer effectively reduces the interface defect state density through hydrogen passivation, and the surface recombination rate is significantly lower than that of the existing tunneling oxide layer + polycrystalline silicon composite structure. (2) The wide bandgap characteristics of amorphous silicon (about 1.7-1.8 eV) can more effectively suppress carrier recombination, and the open circuit voltage (Voc) of the cell is about 5-10 mV higher than that of the existing passivation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 This is a schematic structural diagram of the TOPCon battery provided by the present invention;

[0044] Figure 2 This is a flow chart of the preparation process of the TOPCon battery provided by the present invention.

[0045] Icon: 100-tunneling oxide layer; 200-phosphorus-doped polysilicon layer; 300-AlOx film layer; 400-SiNx film layer; 500-back intrinsic amorphous silicon layer; 600-P-type amorphous silicon layer; 700-TCO film layer; 800-positive electrode; 900-back electrode; 1000-silicon substrate. DETAILED DESCRIPTION

[0046] Unless otherwise defined herein, scientific and technical terms used in conjunction with the present invention shall have the meanings commonly understood by those of ordinary skill in the art. The meaning and scope of the terms should be clear; however, in the event of any potential ambiguity, the definitions provided herein take precedence over any dictionary or external definitions. In this application, the use of "or" means "and / or" unless otherwise stated. In addition, the use of the term "including" and other forms is non-limiting.

[0047] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0048] A first aspect of the present invention provides a TOPCon cell, which comprises a silicon substrate; a back side intrinsic amorphous silicon layer and a P-type amorphous silicon layer are sequentially stacked on the back side of the silicon substrate.

[0049] In some preferred embodiments, a TCO film layer is provided on a side of the P-type amorphous silicon layer away from the intrinsic amorphous silicon layer.

[0050] In some preferred embodiments, the metal area on the front surface of the silicon substrate is sequentially stacked with a tunneling oxide layer, a phosphorus-doped polysilicon layer, a passivation layer, and an anti-reflection layer, and the non-metal area on the front surface of the silicon substrate is sequentially stacked with a passivation layer and an anti-reflection layer;

[0051] Preferably, the material of the passivation layer includes aluminum oxide, and the material of the anti-reflection layer includes silicon nitride.

[0052] A second aspect of the present invention provides a method for preparing a TOPCon battery, comprising the following steps:

[0053] (a) A tunneling oxide layer and a front intrinsic amorphous silicon layer are sequentially stacked on the front surface of a silicon substrate, followed by phosphorus diffusion to dope phosphorus into the front intrinsic amorphous silicon layer to form a phosphorus-doped polysilicon layer. Simultaneously, a PSG layer is formed on the surface of the phosphorus-doped polysilicon layer.

[0054] (b) removing the PSG layer in the non-gate line area on the front side of the silicon wafer, then removing the PSG layer that was plated around, then removing the phosphorus-doped polysilicon layer, tunneling oxide layer and the phosphorus-doped polysilicon layer, tunneling oxide layer in the non-gate line area on the front side of the silicon substrate, and texturing the non-gate line area on the front side of the silicon substrate, then removing the PSG layer in the gate line area on the front side of the silicon substrate;

[0055] (c) sequentially stacking a passivation layer and an anti-reflection layer on the front side of the silicon wafer;

[0056] (d) sequentially stacking a back intrinsic amorphous silicon layer, a P-type amorphous silicon layer, and a TCO film layer on the back side of the silicon wafer;

[0057] (e) Electrodes are printed on the front and back of the silicon wafer.

[0058] Preferably, the present invention provides an N-type silicon substrate, and performs double-sided polishing on the silicon substrate; the polishing process uses NaOH solution with a concentration percentage of 2%-6%, for example, it can be 2%, 4%, 6%, etc.; the temperature is 55-75°C, for example, it can be 55°C, 65°C, 75°C, etc.; the time is 300-500s, for example, it can be 300s, 400s, 500s, etc.

[0059] In some preferred embodiments, a tunneling oxide layer and a front intrinsic amorphous silicon layer are formed on the front surface of the silicon substrate using an LPCVD deposition process;

[0060] Preferably, the thickness of the tunnel oxide layer is 1.2-2.5 nm, for example, 1.2 nm, 1.5 nm, 2 nm, 2.5 nm, etc.; the gas used for preparation is O2, and the gas flow rate is 15000-30000 sccm, for example, 15000 sccm, 22500 sccm, 30000 sccm, etc.; the deposition time is 100-400 s, for example, 100 s, 250 s, 400 s, etc., and the deposition temperature is 450-700 ° C, for example, 450 ° C, 575 ° C, 700 ° C, etc.;

[0061] Preferably, the thickness of the PSG layer is 50-90nm, for example, it can be 50nm, 70nm, 90nm, etc.; the thickness of the phosphorus-doped polysilicon layer is 60-200nm, for example, it can be 60nm, 130nm, 200nm, etc.; the gases used for deposition are POCl3 and O2, and the POCl3 gas flow rate is 300-2000sccm, for example, it can be 300sccm, 1150sccm, 2000sccm, etc.; the O2 gas flow rate is 20000-30000sccm, for example, it can be 20000sccm, 25000sccm, 30000sccm, etc.

[0062] In some preferred embodiments, in step (b), laser patterning is used to remove the PSG layer in the non-gate line area on the front side of the silicon wafer;

[0063] Preferably, the laser power is 20%-50%, for example, 20%, 35%, 50%, etc.; the laser scanning speed is 30,000-50,000 mm / s, for example, 30,000 mm / s, 40,000 mm / s, 50,000 mm / s, etc.

[0064] In some preferred embodiments, a one-time chain cleaning process is used to remove the wrapped PSG layer;

[0065] Preferably, the reagent used in the one-step chain cleaning process includes HF solution with a concentration of 5%-9%, for example, 5%, 7%, 9%, etc.;

[0066] Preferably, a groove texturing process is used to remove the phosphorus-doped polysilicon layer, the tunnel oxide layer and the plated phosphorus-doped polysilicon layer and the tunnel oxide layer in the non-gate line area on the front surface, and texturing is performed on the non-gate line area on the front surface of the silicon substrate;

[0067] Preferably, the components of the reagent used in the tank texturing process include 3%-6% NaOH, 0.3%-2.5% additives and 3%-12% H2O2 by mass percentage. The processing temperature of the tank texturing process is 50-80°C, for example, 50°C, 65°C, 80°C, etc.; the process time is 300-600s, for example, 300s, 450s, 600s, etc.;

[0068] Preferably, a secondary chain cleaning is used to remove the PSG layer in the gate line area on the front side of the silicon substrate;

[0069] Preferably, the reagent used in the secondary chain cleaning process includes HF solution with a concentration of 5%-9%, for example, 5%, 7%, 9%, etc.

[0070] In some preferred embodiments, in step (c), the passivation layer is prepared by atomic layer deposition;

[0071] Preferably, the thickness of the passivation layer is 3-5 nm, for example, 3 nm, 4 nm, 5 nm, etc.; the deposition temperature is 200-350° C., for example, 200° C., 275° C., 350° C., etc.; the deposition time is 30-60 min, for example, 30 min, 45 min, 60 min, etc.; the gases required for depositing the passivation layer include TMA and water, and the gas flow ratio of TMA to water is 1:3-1:4;

[0072] Preferably, the anti-reflection layer is prepared by a PECVD deposition process; the thickness of the anti-reflection layer is 70-130 nm, for example, 70 nm, 100 nm, 130 nm, etc.; the deposition temperature is 400-600° C., for example, 400° C., 500° C., 600° C., etc.; the deposition time is 40-80 min, for example, 40 min, 60 min, 80 min, etc.; the gases required for depositing the anti-reflection layer include N3H, SiH4, and N2O, and the gas flow ratio of N3H, SiH4, and N2O is 1-3:5-15:3-12;

[0073] Here, "1-3" can be, for example, 1, 2, 3, etc.;

[0074] "5-15" can be, for example, 5, 10, 15, etc.;

[0075] "3-12" can be, for example, 3, 7.5, 12, etc.

[0076] In some preferred embodiments, after step (c) and before step (b), a three-way chain cleaning process is used to remove the passivation layer and the anti-reflection layer coated on the back and edge of the silicon wafer;

[0077] Preferably, the reagent used in the three-chain cleaning process includes HF solution with a concentration of 5%-9%, for example, 5%, 7%, 9%, etc.;

[0078] Preferably, after three chain cleanings, the back of the silicon wafer is polished by tank cleaning. The polishing process uses NaOH solution with a concentration of 2%-6%. The polishing temperature is 55-75°C, for example, 55°C, 65°C, 75°C, etc.; the time is 300-500s, for example, 300s, 400s, 500s, etc.

[0079] In some preferred embodiments, in step (d), a PECVD deposition process is used to prepare a back intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the back side of the silicon wafer.

[0080] In the present invention, intrinsic amorphous silicon and P-type amorphous silicon are prepared by the PECVD method, the passivation and contact of the P-type amorphous silicon layer are improved, and the efficiency of the solar cell is increased.

[0081] Preferably, the thickness of the back intrinsic amorphous silicon layer is 5-20 nm, for example, 5 nm, 12.5 nm, 20 nm, etc.; the thickness of the P-type amorphous silicon layer is 5-20 nm, for example, 5 nm, 12.5 nm, 20 nm, etc.; the deposition temperature is 180-250 ° C, for example, 180 ° C, 215 ° C, 250 ° C, etc.; the deposition time is 10-30 min, for example, 10 min, 20 min, 30 min, etc.; the pressure is 50-500 Pa, for example, 50 Pa, 275 Pa, 500 Pa, etc.; the required gases include SiH, H and BH, and the gas flow ratio of SiH, H and BH is 1-3:10-50:0.1-0.3; the doping concentration is 1E19-5E20 / cm 3 ;

[0082] Here, "1-3" can be, for example, 1, 2, 3, etc.;

[0083] "10-50" can be, for example, 10, 30, 50, etc.;

[0084] “0.1-0.3” can be, for example, 0.1, 0.2, 0.3, etc.

[0085] In this invention, the passivation structure consists of a back-side intrinsic amorphous silicon layer and a P-type amorphous silicon layer. The process temperature of the passivation structure is ≤200°C. In contrast, the existing tunneling oxide layer and P-poly layer structure requires high-temperature boron diffusion (>950°C) to form the P-Poly layer. This high-temperature process can easily cause thermal damage to the silicon wafer and lattice defects, affecting yield and long-term reliability. This invention uses a low-temperature process to produce the P-type emitter, reducing high-temperature damage to the silicon wafer and improving product yield.

[0086] Preferably, in step (d), the thickness of the TCO film layer is 60-200 nm, for example, 60 nm, 130 nm, 200 nm, etc.;

[0087] Preferably, before preparing the TCO film layer, plasma cleaning is used to activate the silicon wafer surface;

[0088] Preferably, the plasma includes argon or oxygen, and the power is 100-300 W, for example, 100 W, 200 W, 300 W, etc.; the processing time is 5-15 minutes, for example, 5 minutes, 10 minutes, 15 minutes, etc.

[0089] Among the optional solutions of the present invention, it is more preferred that Figure 1 and Figure 2 As shown, the preparation method of the double-sided TOPCon battery includes the following steps:

[0090] Step 1: providing an N-type silicon substrate 1000 and performing double-sided polishing on the silicon substrate 1000; the polishing process uses a NaOH solution with a concentration of 2%-6%, a temperature of 55-75° C., and a time of 300-500 seconds;

[0091] Step 2: A tunneling oxide layer 100 and a front intrinsic amorphous silicon layer are formed on the front surface of the silicon substrate 1000 using an LPCVD deposition process; the thickness of the tunneling layer is 1.2-2.5 nm, the gas introduced is O2, the gas flow rate is 15000-30000 sccm, the deposition time is 100-400 s, and the deposition temperature is 450-700°C; the gas used to prepare the intrinsic amorphous silicon layer is SiH, the gas flow rate is 800-2500 sccm, the deposition time is 1000-3000 s, the deposition temperature is 450-700°C, and the thickness is 60-200 nm;

[0092] Step 3: Phosphorus diffusion: Phosphorus is doped into the front intrinsic amorphous silicon of the silicon wafer using a phosphorus diffusion process to form a phosphorus-doped polysilicon layer 200 (N-Poly-Si layer) and a PSG layer. The thickness of the PSG layer is 50-90 nm, and the thickness of the N-Poly-Si layer is 60-200 nm. The deposition gas used is POCl3 at a flow rate of 300-2000 sccm, and O2 at a flow rate of 20,000-30,000 sccm.

[0093] Step 4: Use laser patterning to remove the PSG layer in the non-gate line area on the front side of the silicon wafer, with the laser power at 20-50% and the laser scanning speed at 30,000-50,000 mm / s;

[0094] Step 5: After the treatment in step 4, a chain cleaning process is used to remove the PSG layer by using an HF solution with a concentration of 5-9%;

[0095] Afterwards, a trench texturing process is used to remove the phosphorus-doped polysilicon layer 200, the tunnel oxide layer 100, and the plated phosphorus-doped polysilicon layer 200 and the tunnel oxide layer 100 in the non-gate line area on the front side, and texturing is performed on the non-gate line area on the front side of the silicon substrate 1000. The components of the reagent used in the trench texturing process include 3%-6% NaOH, 0.3%-2.5% additives, and 3%-12% H2O2 by mass percentage. The processing temperature of the trench texturing process is 50-80°C, and the process time is 300-600s.

[0096] Afterwards, a chain cleaning process is used to remove the PSG layer in the front gate line region of the silicon substrate 1000. The reagent used is an HF solution with a concentration of 5%-9%.

[0097] Step 6: Forming an AlOx film 300 (aluminum oxide passivation film layer). The treated silicon wafer is deposited on the front side of the silicon wafer using atomic layer deposition. The thickness of the AlOx film 300 is 3-5 nm, the deposition temperature is 200-350° C., and the deposition time is 30-60 min. The AlOx film requires a TMA gas and water flow ratio of 1:3-1:4.

[0098] Step 7: Forming a SiNx film layer 400 (silicon nitride anti-reflective film layer). The treated silicon wafer is deposited on the front side of the silicon wafer using a PECVD deposition process. The thickness of the SiNx film 400 is 70-130 nm, the deposition temperature is 400-600° C., and the deposition time is 40-80 min. The flow ratio of N3H, SiH4, and N2O required for the SiNx film is (1-3): (5-15): (3-12).

[0099] Step 8: Remove the edge and back windings, and use a chain cleaning process to remove AlOx+SiNx on the back and edge of the silicon wafer; the chain polishing process uses an HF solution with a concentration of 5-9%;

[0100] Step 9: backside polishing: backside polishing is performed using a tank cleaning process, wherein the polishing process uses a NaOH solution with a concentration of 2%-6%, a temperature of 55-75° C., and a time of 300-500 seconds;

[0101] Step 10: Prepare a back intrinsic amorphous silicon layer 500 (a-Si:H(I)) + a P-type amorphous silicon (a-Si:H(p)) layer on the back of the silicon wafer by stacking them in sequence using a PECVD deposition process. The back intrinsic amorphous silicon layer has a thickness of 5-20 nm. The gas used for preparation is SiH, the gas flow rate is 600-1000 sccm, the deposition time is 500-1500 s, and the deposition temperature is 450-700°C. The P-type amorphous silicon layer 600 has a thickness of 5-20 nm, the deposition temperature is 180-250°C, the deposition time is 10-30 min, the pressure is 50-500 Pa, and the required gas SiH:H:BH=(1-3):(10-50):(0.1-0.3); the doping concentration is 1E19-5E20 / cm 3 .

[0102] Step 11: Prepare a TCO film layer 700 on the P-type amorphous silicon layer 600. Before preparing the TCO film layer 700, plasma cleaning is used to activate the surface, usually using argon or oxygen plasma with a power of 100-300W and a processing time of 5-15 minutes. Then, the TCO film layer 700 is prepared with a sputtering power of 30-60%, a deposition time of 2-10 minutes, and a film thickness of 60-200nm.

[0103] Step 12: After the silicon wafer is processed in step 11, a positive electrode 800 (eg, a silver electrode) is printed on the front side, and a back electrode 900 (eg, a silver electrode) is printed on the back side, and then sintering is performed.

[0104] The present invention is further described below by way of examples. Unless otherwise specified, the materials in the examples were prepared according to existing methods or directly purchased from the market.

[0105] The texturing additives used in the following examples and comparative examples are:

[0106] Manufacturer: Changzhou Shichuang Energy, Model: ST20 (V02A).

[0107] Example 1

[0108] This embodiment provides a TOPCon battery, the preparation method of which includes the following steps:

[0109] Step 1: providing an N-type silicon substrate and performing double-sided polishing on the silicon substrate; the polishing process uses a NaOH solution with a concentration of 4%, a temperature of 65° C., and a time of 400 seconds;

[0110] Step 2: A tunneling oxide layer and a front intrinsic amorphous silicon layer are formed on the front side of the silicon substrate using an LPCVD deposition process; the tunneling layer has a thickness of 1.8 nm, the gas introduced is O2, the gas flow rate is 20,000 sccm, the deposition time is 250 s, and the deposition temperature is 575°C; the intrinsic amorphous silicon layer has a thickness of 150 nm, the gas introduced is SiH, the gas flow rate is 1500 sccm, the deposition time is 1000 s, and the deposition temperature is 600°C;

[0111] Step 3: Phosphorus diffusion: Phosphorus is doped into the front intrinsic amorphous silicon of the silicon wafer using a phosphorus diffusion process to form a phosphorus-doped polysilicon layer (N-Poly-Si layer) and a PSG layer; the PSG layer is 70nm thick, and the N-Poly-Si layer is 130nm thick. The deposition gases used are POCl3 at a flow rate of 1150sccm and O2 at a flow rate of 25000ccm.

[0112] Step 4: Use laser patterning to remove the PSG layer in the non-gate line area on the front side of the silicon wafer, with the laser power at 35% and the laser scanning speed at 40,000 mm / s;

[0113] Step 5: After the treatment in step 4, a chain cleaning process is used to remove the plated PSG layer, specifically using an HF solution with a concentration of 7%;

[0114] Afterwards, a trench texturing process is used to remove the phosphorus-doped polysilicon layer, the tunneling oxide layer, and the plated phosphorus-doped polysilicon layer and the tunneling oxide layer in the non-gate line area on the front side, and texturing is performed on the non-gate line area on the front side of the silicon substrate. The reagent components used in the trench texturing process include 45% NaOH, 1.4% additives, and 7.5% H2O2 by mass percentage. The processing temperature of the trench texturing process is 65°C, and the process time is 450s.

[0115] Afterwards, a chain cleaning process is used to remove the PSG layer in the gate line region on the front side of the silicon substrate. The reagent used is an HF solution with a concentration of 7%.

[0116] Step 6: Forming an AlOx (aluminum oxide layer): Atomic layer deposition (ALD) is used to deposit an AlOx film on the front of the treated silicon wafer. The AlOx film has a thickness of 4 nm and is deposited at a temperature of 275° C. for 45 minutes. The AlOx film requires a TMA to water flow ratio of 1:3.5.

[0117] Step 7: Forming a SiNx (silicon nitride layer): A SiNx layer is deposited on the front of the treated silicon wafer using a PECVD deposition process. The SiNx film thickness is 100 nm, the deposition temperature is 500°C, and the deposition time is 60 minutes. The flow ratio of N3H, SiH4, and N2O required for the SiNx film is 2:10:7.5.

[0118] Step 8: Remove the edge and back windings, and use a chain cleaning process to remove AlOx+SiNx on the back and edge of the silicon wafer; the chain polishing process uses an HF solution with a concentration of 7%;

[0119] Step 9, backside polishing: backside polishing is performed using a tank cleaning process, wherein the polishing process uses a NaOH solution with a concentration of 4%, a temperature of 65° C., and a time of 400 s;

[0120] Step 10: Prepare a back intrinsic amorphous silicon layer (a-Si:H(I)) + a P-type amorphous silicon (a-Si:H(p)) layer on the back of the silicon wafer by stacking them in sequence using a PECVD deposition process. The back intrinsic amorphous silicon layer has a thickness of 12.5 nm. The gas introduced is SiH, the gas flow rate is 1000 sccm, the deposition time is 1200 s, and the deposition temperature is 550 ° C. The thickness of the P-type amorphous silicon layer is 12.5 nm, the deposition temperature is 215 ° C, the deposition time is 20 min, the pressure is 275 Pa, the required gas SiH:H:BH=2:30:0.2; the doping concentration is 6.2E19 / cm 3 .

[0121] Step 11: Prepare a TCO film layer on the P-type amorphous silicon layer. Before preparing the TCO film layer, plasma cleaning is used to activate the surface. Usually, oxygen plasma is used with a power of 200 W and a treatment time of 10 minutes. Then, a TCO film layer with a thickness of 130 nm is prepared. The process parameters are: sputtering power 45% and deposition time 6 minutes.

[0122] Step 12: After the processing in step 11, the positive electrode is printed on the front side of the silicon wafer, the back electrode is printed on the back side, and then sintering is performed.

[0123] Example 2

[0124] This embodiment provides a TOPCon battery, and the preparation steps thereof differ from those of Example 1 in that:

[0125] In step 10, the thickness of the back intrinsic amorphous silicon layer is 5nm, the gas introduced is SiH gas flow rate 600sccm, the deposition time is 550s, and the deposition temperature is 470℃; the thickness of the P-type amorphous silicon layer is 20nm, the deposition temperature is 180℃, the deposition time is 30min, the pressure is 50Pa, the required gas SiH:H:BH=1:50:0.1; the doping concentration is 2.1E19 / cm 3 ;

[0126] The remaining steps are consistent with those in Example 1.

[0127] Example 3

[0128] This embodiment provides a TOPCon battery, and the preparation steps thereof differ from those of Example 1 in that:

[0129] In step 10, the thickness of the back intrinsic amorphous silicon layer is 20nm, the gas introduced is SiH gas flow rate 1000sccm, the deposition time is 1300s, and the deposition temperature is 680℃; the thickness of the P-type amorphous silicon layer is 5nm, the deposition temperature is 250℃, the deposition time is 10min, the pressure is 500Pa, the required gas SiH:H:BH=3:10:0.3; the doping concentration is 4.8E20 / cm 3 ;

[0130] The remaining steps are consistent with those in Example 1.

[0131] Example 4

[0132] This embodiment provides a TOPCon battery, and the preparation steps thereof differ from those of Example 1 in that:

[0133] In step 2, a tunneling oxide layer and a front intrinsic amorphous silicon layer are formed on the front side of the silicon substrate by an LPCVD deposition process. The intrinsic amorphous silicon layer has a thickness of 60 nm, the gas introduced is SiH gas with a flow rate of 1000 sccm, the deposition time is 1050 s, and the deposition temperature is 500°C; the tunneling layer has a thickness of 1.2 nm, the gas introduced is O2, the gas flow rate is 16000 sccm, the deposition time is 100 s, and the deposition temperature is 700°C;

[0134] In step 3, the thickness of the PSG layer is 50 nm, the thickness of the N-Poly-Si layer is 60 nm, and the deposition gas used is POCl3 with a flow rate of 300 sccm and O2 with a flow rate of 30,000 sccm;

[0135] In step 5, the components of the reagents used in the tank texturing process include 3% NaOH, 2.5% additives and 3% H2O2 by mass percentage, the processing temperature of the tank texturing process is 50° C., and the process time is 600 s;

[0136] In step 6, the thickness of the AlOx film is 3 nm, the deposition temperature is 350° C., and the deposition time is 30 min. The flow ratio of TMA and water required for the AlOx film is 1:4.

[0137] In step 7, the thickness of the SiNx film layer is 70 nm, the deposition temperature is 600° C., and the deposition time is 40 min. The flow ratio of N3H, SiH4, and N2O required for the SiNx film is 1:15:3.

[0138] Step 11: A TCO film is formed on the P-type amorphous silicon layer. Before forming the TCO film, the surface is activated by plasma cleaning, typically using argon plasma with a power of 100 W and a treatment time of 15 minutes. Then, a TCO film with a thickness of 60 nm is formed using the following process parameters: sputtering power of 30% and deposition time of 2 minutes.

[0139] The remaining steps are consistent with those in Example 1.

[0140] Example 5

[0141] This embodiment provides a TOPCon battery, and the preparation steps thereof differ from those of Example 1 in that:

[0142] In step 2, a tunneling oxide layer and a front intrinsic amorphous silicon layer are formed on the front side of the silicon substrate using an LPCVD deposition process; the tunneling layer thickness is 2.5 nm, the inlet gas is O2, the gas flow rate is 28000 sccm, the deposition time is 400 s, and the deposition temperature is 450°C; the intrinsic amorphous silicon layer thickness is 200 nm, the inlet gas is SiH gas flow rate 1000 sccm, the deposition time is 1300 s, and the deposition temperature is 680°C;

[0143] In step 3, the thickness of the PSG layer is 90 nm, the thickness of the N-Poly-Si layer is 200 nm, and the deposition gas used is POCl3 with a flow rate of 2000 sccm and O2 with a flow rate of 20000 sccm;

[0144] In step 5, the components of the reagent used in the tank texturing process include 6% NaOH, 0.3% additives and 12% H2O2 by mass percentage, the processing temperature of the tank texturing process is 80°C, and the process time is 300s;

[0145] In step 6, the thickness of the AlOx film is 5 nm, the deposition temperature is 200° C., and the deposition time is 60 min. The flow ratio of TMA and water required for the AlOx film is 1:3.

[0146] In step 7, the thickness of the SiNx film layer is 130 nm, the deposition temperature is 400° C., and the deposition time is 80 min. The flow ratio of N3H, SiH4, and N2O required for the SiNx film is 3:5:12.

[0147] Step 11: A TCO film is formed on the P-type amorphous silicon layer. Before forming the TCO film, the surface is activated by plasma cleaning, typically using argon plasma with a power of 300 W and a treatment time of 5 minutes. Then, a TCO film with a thickness of 200 nm is formed. The process parameters are: sputtering power of 60% and deposition time of 10 minutes.

[0148] The remaining steps are consistent with those in Example 1.

[0149] Example 6

[0150] This embodiment provides a TOPCon cell, and the preparation steps thereof differ from those of Example 1 in that: in step 10, the thickness of the back intrinsic amorphous silicon layer is 4 nm, the flow rate of SiH gas is 520 sccm, the deposition time is 610 s, and the deposition temperature is 450°C; the thickness of the P-type amorphous silicon layer is 4 nm, the deposition temperature is 300°C, the deposition time is 8 min, and the doping concentration is 2E19 / cm 3 ;

[0151] The remaining steps are consistent with those in Example 1.

[0152] Example 7

[0153] This embodiment provides a TOPCon cell, the preparation steps of which differ from those of Example 1 in that: in step 10, the thickness of the back intrinsic amorphous silicon layer is 21 nm, the flow rate of SiH2 gas is 1500 sccm, the deposition time is 1800 s, and the deposition temperature is 550°C; the thickness of the P-type amorphous silicon layer is 21 nm, the deposition temperature is 300°C, the deposition time is 20 min, the required gas ratio is SiH2:H2:BH2=5:50:0.3, and the doping concentration is 4E20 / cm3. 3 ;

[0154] The remaining steps are consistent with those in Example 1.

[0155] Example 8

[0156] This embodiment provides a TOPCon cell, the preparation steps of which differ from those of Example 1 in that: in step 11, plasma cleaning is not performed to activate the silicon wafer surface before forming the TCO film layer; the remaining steps are consistent with those of Example 1.

[0157] Comparative Example 1

[0158] This comparative example provides a TOPCon battery, the preparation steps of which are different from those of Example 1. In step 10, a tunneling oxide layer (SiO2) + a P-type amorphous silicon (a-Si:H(p)) layer is sequentially stacked on the back of the silicon wafer using a PECVD deposition process. The thickness of the back tunneling oxide layer is 1.5 nm, the deposition temperature is 450°C, the deposition time is 170 s, and the gas flow rate N2O required for deposition is 9800 sccm; the thickness of the P-type amorphous silicon layer is 125 nm, the deposition temperature is 450°C, the deposition time is 30 min, and the required gas SiH:H:BH=15:55:0.4; the doping concentration is 6E20 / cm 3 .

[0159] Do not proceed to step 11;

[0160] The remaining steps are consistent with those in Example 1.

[0161] Test Case

[0162] Test samples: The TOPCon batteries prepared in Examples 1-8 and Comparative Example 1 were used as samples for testing.

[0163] Test method: Use IV tester to test the performance of the battery cell;

[0164] UOC (open circuit voltage) and FF (fill factor) were tested using a halm tester;

[0165] It should be noted that the passivation effect is characterized by UOC (open circuit voltage), and a good passivation effect means a good passivation effect, and a high UOC;

[0166] The contact performance is characterized by FF (fill factor), and poor contact performance means a low fill factor.

[0167] The test results are shown in Table 1.

[0168] Table 1

[0169]

[0170]

[0171] It can be seen from the data in Table 1 that compared with Comparative Example 1 (traditional back passivation structure: tunneling oxide layer + P-type amorphous silicon), Example 1 of the present invention adopts a back intrinsic amorphous silicon layer (a-Si:H(I)) + P-type amorphous silicon layer (a-Si:H(p)) as a back passivation structure, and its battery efficiency yield is the best; It can be seen from the result data of Examples 1 and Examples 6-7 that the battery efficiency yield of the battery is better when the parameters within the preferred range of the present invention are used to prepare the back intrinsic amorphous silicon layer and the P-type amorphous silicon layer; It can be seen from the result data of Examples 1 and 8 that the battery of the product without plasma cleaning to activate the silicon wafer surface is better. The efficiency and yield are poor. This is because without plasma cleaning, contaminants or oxide layers may remain on the silicon wafer surface. These substances will hinder the good contact between the TCO film layer and the P-type amorphous silicon layer. The increased contact resistance will lead to a decrease in current transmission efficiency, thereby reducing the fill factor (FF), and ultimately affecting the overall conversion efficiency of the battery. At the same time, the TCO film layer needs to be tightly bonded to the P-type amorphous silicon layer to achieve efficient charge transfer. If the silicon wafer surface is not activated, the TCO film layer may have insufficient adhesion, which may cause the TCO film layer to peel off or crack in subsequent processes, further reducing the battery yield.

[0172] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A TOPCon battery, characterized in that: The invention comprises a silicon substrate; a back intrinsic amorphous silicon layer and a P-type amorphous silicon layer are sequentially stacked on the back of the silicon substrate.

2. The TOPCon battery according to claim 1, characterized in that A TCO film layer is provided on a side of the P-type amorphous silicon layer away from the intrinsic amorphous silicon layer.

3. The TOPCon battery according to claim 1, characterized in that The metal area on the front side of the silicon substrate is sequentially stacked with a tunneling oxide layer, a phosphorus-doped polysilicon layer, a passivation layer and an anti-reflection layer; the non-metal area on the front side of the silicon substrate is sequentially stacked with a passivation layer and an anti-reflection layer; Preferably, the material of the passivation layer includes aluminum oxide; and the material of the anti-reflection layer includes silicon nitride.

4. A method for preparing a TOPCon battery according to any one of claims 1 to 3, characterized in that: The following steps are involved: A back intrinsic amorphous silicon layer and a P-type amorphous silicon layer are sequentially stacked on the back side of the silicon substrate.

5. The preparation method according to claim 4, characterized in that A PECVD deposition process is used to prepare a back intrinsic amorphous silicon layer and a P-type amorphous silicon layer on the back of a silicon wafer; the thickness of the back intrinsic amorphous silicon layer is 5-20 nm; the thickness of the P-type amorphous silicon layer is 5-20 nm; the deposition temperature is 180-250° C.; the deposition time is 10-30 min; the pressure is 50-500 Pa; the required gases include SiH, H, and BH; the gas flow ratio of SiH, H, and BH is 1-3:10-50:0.1-0.3; the doping concentration is 1E19-5E20 / cm 3 ; Preferably, a TCO film layer is prepared on the P-type amorphous silicon layer; Preferably, the thickness of the TCO film layer is 60-200 nm; Preferably, before preparing the TCO film layer, plasma cleaning is used to activate the silicon wafer surface; Preferably, the plasma comprises argon or oxygen; the power is 100-300 W; and the treatment time is 5-15 minutes.

6. The preparation method according to claim 4, characterized in that Before preparing the back structure on the silicon substrate, the preparation method of the TOPCon cell further includes the following steps: (a) A tunneling oxide layer and a front intrinsic amorphous silicon layer are sequentially stacked on the front surface of a silicon substrate; phosphorus diffusion is then performed to dope phosphorus into the front intrinsic amorphous silicon layer to form a phosphorus-doped polysilicon layer, while a PSG layer is formed on the surface of the phosphorus-doped polysilicon layer; (b) removing the PSG layer in the non-gate line area on the front side of the silicon wafer; then removing the PSG layer that was plated; then removing the phosphorus-doped polysilicon layer, tunnel oxide layer, and the phosphorus-doped polysilicon layer and tunnel oxide layer in the non-gate line area on the front side of the silicon substrate, and texturing the non-gate line area on the front side of the silicon substrate; then removing the PSG layer in the gate line area on the front side of the silicon substrate; (c) A passivation layer and an anti-reflection layer are sequentially stacked on the front side of the silicon wafer.

7. The preparation method according to claim 6, characterized in that In step (a), a tunnel oxide layer and a front intrinsic amorphous silicon layer are formed on the front surface of the silicon substrate using an LPCVD deposition process; Preferably, the thickness of the tunnel oxide layer is 1.2-2.5 nm; the gas used for preparation is O2; the gas flow rate of O2 is 15000-30000 sccm; the deposition time is 100-400 s; and the deposition temperature is 450-700° C.; Preferably, the thickness of the PSG layer is 50-90 nm; the thickness of the phosphorus-doped polysilicon layer is 60-200 nm; the gases used for deposition are POCl3 and O2; the POCl3 gas flow rate is 300-2000 sccm; and the O2 gas flow rate is 20000-30000 sccm.

8. The preparation method according to claim 6, characterized in that In step (b), laser patterning is used to remove the PSG layer in the non-gate line area on the front side of the silicon wafer; Preferably, the laser power is 20%-50%; the laser scanning speed is 30000-50000 mm / s; Preferably, a one-step chain cleaning process is used to remove the plated PSG layer; Preferably, the reagent used in the one-step chain cleaning process includes HF solution; the concentration of the HF solution is 5%-9%; Preferably, a groove texturing process is used to remove the phosphorus-doped polysilicon layer, the tunnel oxide layer and the plated phosphorus-doped polysilicon layer and the tunnel oxide layer in the non-gate line area on the front surface, and texturing is performed on the non-gate line area on the front surface of the silicon substrate; Preferably, the components of the reagents used in the tank texturing process include 3%-6% NaOH, 0.3%-2.5% additives and 3%-12% H2O2 by mass percentage; the processing temperature of the tank texturing process is 50-80°C; and the process time is 300-600s; Preferably, a secondary chain cleaning is used to remove the PSG layer in the gate line area on the front side of the silicon substrate; Preferably, the reagent used in the secondary chain cleaning process includes HF solution; the concentration of the HF solution is 5%-9%.

9. The preparation method according to claim 6, characterized in that In step (c), a passivation layer is prepared by atomic layer deposition; Preferably, the thickness of the passivation layer is 3-5 nm; the deposition temperature is 200-350° C.; the deposition time is 30-60 min; the gases required for depositing the passivation layer include TMA and water; the gas flow ratio of TMA to water is 1:3-1:4; Preferably, the anti-reflection layer is prepared by a PECVD deposition process; the thickness of the anti-reflection layer is 70-130 nm; the deposition temperature is 400-600°C; the time is 40-80 min; the gases required for depositing the anti-reflection layer include N3H, SiH4 and N2O, and the gas flow ratio of N3H, SiH4 and N2O is 1-3:5-15:3-12.

10. The preparation method according to claim 6, characterized in that After step (c) and before step (b), a three-way chain cleaning process is used to remove the passivation layer and the anti-reflection layer coated on the back and edge of the silicon wafer; Preferably, the reagent used in the three-chain cleaning process includes HF solution; the concentration of the HF solution is 5%-9%; Preferably, after three chain cleanings, the back of the silicon wafer is polished using tank cleaning; the polishing process uses NaOH solution with a concentration of 2%-6%; the polishing temperature is 55-75° C.; and the polishing time is 300-500 seconds.

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