Calculation circuit, data processing method, storage medium and electronic equipment

Abstract

The invention discloses a calculation circuit, a data processing method, a storage medium and electronic equipment. Wherein the calculation circuit comprises an instruction processing sub-circuit, and the instruction processing sub-circuit is used for obtaining atomic instructions and caching the atomic instructions corresponding to the same target operation address in the same target queue; the calculation sub-circuit is used for obtaining original data, corresponding to the target operation address, in the memory, calculation types indicated by the atomic instructions in the target queue and sorting attributes of the atomic instructions in the target queue; generating target calculation result data based on the original data, the calculation type and the sorting attribute; and updating the original data corresponding to the target operation address into the target calculation result data. According to the embodiment of the invention, the execution efficiency of the atomic instruction can be improved.

Description

Technical Field

[0001] The present disclosure relates to chip technology, and in particular to a computing circuit, a data processing method, a storage medium, and an electronic device. Background Art

[0002] Atomic instructions are special instructions provided by computer architecture to ensure the indivisibility of an operation, that is, the operation is either completely executed or not executed at all.

[0003] It should be noted that if there are multiple atomic instructions that need to be executed, the multiple atomic instructions are usually executed in a serial manner, so the execution efficiency is low. How to improve the execution efficiency of atomic instructions is a technical issue worthy of attention for technical personnel in this field. Summary of the Invention

[0004] In order to solve the above technical problems, the present disclosure provides a computing circuit, a data processing method, a storage medium and an electronic device.

[0005] According to one aspect of an embodiment of the present disclosure, there is provided a computing circuit, including:

[0006] an instruction processing subcircuit, the instruction processing subcircuit being used to obtain atomic instructions and cache the atomic instructions corresponding to the same target operation address in the same target queue;

[0007] A calculation subcircuit, wherein the calculation subcircuit is used to obtain the original data corresponding to the target operation address in the memory, the calculation type indicated by each of the atomic instructions in the target queue, and the sorting attribute of each of the atomic instructions in the target queue; generate target calculation result data based on the original data, the calculation type and the sorting attribute; and update the original data corresponding to the target operation address to the target calculation result data.

[0008] According to another aspect of an embodiment of the present disclosure, a data processing method is provided, including:

[0009] Get atomic instructions;

[0010] caching the atomic instructions corresponding to the same target operation address in the same target queue;

[0011] Obtaining original data corresponding to the target operation address in a memory, a calculation type indicated by each of the atomic instructions in the target queue, and an ordering attribute of each of the atomic instructions in the target queue;

[0012] Generate target calculation result data based on the original data, the calculation type and the sorting attribute;

[0013] The original data corresponding to the target operation address is updated to the target calculation result data.

[0014] According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is executed by a processor to perform the above-mentioned data processing method.

[0015] According to another aspect of the embodiments of the present disclosure, an electronic device is provided, the electronic device including:

[0016] processor;

[0017] a memory for storing instructions executable by the processor;

[0018] The processor is used to read the executable instructions from the memory and execute the instructions to implement the above data processing method.

[0019] According to another aspect of the embodiments of the present disclosure, a computer program product is provided. When instructions in the computer program product are executed by a processor, the above-mentioned data processing method is performed.

[0020] Based on the computing circuit, data processing method, storage medium, electronic device and program product provided by the above-mentioned embodiments of the present disclosure, the instruction processing subcircuit can cache the obtained atomic instructions according to the caching rules that the atomic instructions corresponding to the same target operation address are cached in the same target queue. Through a read operation, the computing subcircuit can obtain the original data corresponding to the target operation address in the memory. Based on the original data, the calculation type indicated by each atomic instruction in the target queue, and the sorting attributes of each atomic instruction in the target queue, the computing subcircuit can perform calculations of the calculation type indicated by each atomic instruction in the target queue in sequence on the basis of the original data to generate target calculation result data. Through a write operation, the computing subcircuit can update the data stored in the address space corresponding to the target operation address in the memory from the original data to the target calculation result data, thereby completing the execution of each atomic instruction in the target queue. It can be seen that in the embodiments of the present disclosure, when caching atomic instructions according to the above-mentioned caching rules, the original data in the memory can be obtained through a read operation, and then several modification operations can be continuously performed for each atomic instruction in the target queue to obtain the target calculation result data. After that, the original data in the memory can be updated to the target calculation result data through a write operation, and the execution of each atomic instruction in the target queue can be completed. There is no need to perform read operations, modification operations, and write operations for each atomic instruction in sequence, which can greatly reduce the number of read operations and write operations, thereby effectively improving the execution efficiency of atomic instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is one of the structural diagrams of a computing circuit provided by some exemplary embodiments of the present disclosure.

[0022] Figure 2 This is one of the structural schematic diagrams of a computing sub-circuit in a computing circuit provided by some exemplary embodiments of the present disclosure.

[0023] Figure 3 This is the second structural diagram of the computing circuit provided by some exemplary embodiments of the present disclosure.

[0024] Figure 4 This is the second structural schematic diagram of a computing sub-circuit in a computing circuit provided by some exemplary embodiments of the present disclosure.

[0025] Figure 5 This is the third structural diagram of the computing circuit provided by some exemplary embodiments of the present disclosure.

[0026] Figure 6 It is one of the flowcharts of the data processing method provided by some exemplary embodiments of the present disclosure.

[0027] Figure 7 This is the second flowchart of the data processing method provided by some exemplary embodiments of the present disclosure.

[0028] Figure 8 This is the third flowchart of the data processing method provided by some exemplary embodiments of the present disclosure.

[0029] Figure 9 This is the fourth flowchart of the data processing method provided by some exemplary embodiments of the present disclosure.

[0030] Figure 10 This is the fifth flowchart of the data processing method provided by some exemplary embodiments of the present disclosure.

[0031] Figure 11 This is the sixth flowchart of the data processing method provided by some exemplary embodiments of the present disclosure.

[0032] Figure 12 This is the seventh flow chart of the data processing method provided by some exemplary embodiments of the present disclosure.

[0033] Figure 13 This is the eighth flowchart of the data processing method provided by some exemplary embodiments of the present disclosure.

[0034] Figure 14 is a schematic structural diagram of an electronic device provided by some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0035] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0036] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0037] Application Overview

[0038] Currently, the application of chips is becoming more and more extensive. For example, in the field of driving technology, the application of smart driving chips and smart cockpit chips is becoming more and more widespread.

[0039] Generally speaking, a chip may include computing circuits that can be used to execute atomic instructions. Atomic instructions are usually executed in three steps: read, modify, and write. That is, the computing circuit can first read data from memory, then calculate the read data, and then write the calculated data to memory.

[0040] In the process of implementing the present disclosure, the inventors found that if there are multiple atomic instructions that need to be executed, the multiple atomic instructions are usually executed in a serial manner, that is, first for the first atomic instruction, the read operation, the change operation, and the write operation are executed in sequence, and then for the second atomic instruction, the read operation, the change operation, and the write operation are executed in sequence, and then for the third atomic instruction, the read operation, the change operation, and the write operation are executed in sequence, and so on, until the read operation, the change operation, and the write operation are executed in sequence for the last atomic instruction. Since multiple atomic instructions are executed in a serial manner, the execution efficiency is low and it is difficult to meet actual needs. Therefore, it is necessary to take some measures to improve the execution efficiency of atomic instructions.

[0041] Exemplary Systems

[0042] In the embodiment of the present disclosure, several atomic instructions corresponding to the same operation address can be determined. Next, the original data corresponding to the operation address can be read from the memory through a read operation, and then, based on the original data, several modification operations can be continuously performed to generate the target calculation result data, and then a write operation is performed to update the original data in the memory to the target calculation result data. At this point, these atomic instructions are all executed. Obviously, in the embodiment of the present disclosure, there is no need to perform read operations, modification operations, and write operations in sequence for each atomic instruction, which can greatly reduce the number of executions of read operations and the number of executions of write operations, thereby effectively improving the execution efficiency of atomic instructions.

[0043] Example Circuit

[0044] Figure 1 Schematic diagram of a computing circuit provided by some exemplary embodiments of the present disclosure. Figure 1 As shown, the calculation circuit may include:

[0045] The instruction processing subcircuit 20 is used to obtain atomic instructions and cache atomic instructions corresponding to the same target operation address in the same target queue;

[0046] The calculation subcircuit 30 is used to obtain the original data corresponding to the target operation address in the memory 40, the calculation type indicated by each atomic instruction in the target queue, and the sorting attribute of each atomic instruction in the target queue; based on the original data, the calculation type and the sorting attribute, generate the target calculation result data; and update the original data corresponding to the target operation address to the target calculation result data.

[0047] Optionally, the instruction processing subcircuit 20 may be a circuit for acquiring and caching atomic instructions. The instruction processing subcircuit 20 may receive atomic instructions from a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (DSP), or the like. The number of atomic instructions received by the instruction processing subcircuit 20 may be multiple, for example, M; wherein M may be an integer greater than or equal to 2. Each of the M atomic instructions may carry an operation address, and the operation address carried by any atomic instruction may be understood as the address indicated by the atomic instruction to be operated, and the operation address carried by any atomic instruction may be used as the operation address corresponding to the atomic instruction. The instruction processing subcircuit 20 may include a first cache space, and the instruction processing subcircuit 20 may cache the M atomic instructions in a queue manner in the first cache space based on the operation addresses corresponding to the M atomic instructions, so that the atomic instructions corresponding to the same target operation address are cached in the same target queue.

[0048] In an optional example, the M atomic instructions are 10 atomic instructions, namely atomic instruction D1, atomic instruction D2, atomic instruction D3, ..., atomic instruction D9, and atomic instruction D10; wherein, the operation addresses corresponding to atomic instructions D1 to D3 are all operation address A1, the operation addresses corresponding to atomic instructions D4 to D6 are all operation address A2, and the operation addresses corresponding to atomic instructions D7 to D10 are all operation address A3. Obviously, atomic instructions D1 to D3 correspond to the same operation address (i.e., operation address A1), atomic instructions D4 to D6 correspond to the same operation address (i.e., operation address A2), and atomic instructions D7 to D10 correspond to the same operation address (i.e., operation address A3). Then, the instruction processing subcircuit 20 can cache atomic instructions D1 to D3 in the same queue, for example, in queue C1; the instruction processing subcircuit 20 can also cache atomic instructions D4 to D6 in the same queue, for example, in queue C2; ​​the instruction processing subcircuit 20 can also cache atomic instructions D7 to D10 in the same queue, for example, in queue C3. Operation address A1, operation address A2, and operation address A3 can each serve as a target operation address, and queue C1, queue C2, and queue C3 can each serve as a target queue; wherein, operation address A1 corresponds to queue C1; operation address A2 corresponds to queue C2; ​​and operation address A3 corresponds to queue C3.

[0049] As can be seen from the above example, the number of target operation addresses and target queues can be multiple. For ease of understanding, the following mainly introduces the related processing of a single target operation address and the corresponding target queue.

[0050] Alternatively, the memory 40 may be a circuit for storing data, and may include but is not limited to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR), a Static Random Access Memory (SRAM), a register group, and the like.

[0051] Optionally, the calculation subcircuit 30 may be a circuit for executing atomic instructions. In the embodiments of the present disclosure, an architecture in which the memory 40 is separated from the calculation subcircuit 30 may be adopted. The calculation subcircuit 30 may be electrically connected to the instruction processing subcircuit 20, and the calculation subcircuit 30 may also be electrically connected to the memory 40. The calculation subcircuit 30 may obtain at least the following three items for executing each atomic instruction in the target queue: (a) the original data corresponding to the target operation address in the memory 40; (b) the calculation type indicated by each atomic instruction in the target queue; and (c) the sorting attribute of each atomic instruction in the target queue.

[0052] In some optional embodiments of the present disclosure, the instruction processing subcircuit 20 can read the memory 40 to obtain the data located at the target operation address in the memory 40, and the data can be used as the original data corresponding to the target operation address. The original data may include but is not limited to image data, feature map data, etc. As an example, the computing circuit can be designed in an intelligent driving chip, and a camera can be provided on a vehicle equipped with the intelligent driving chip; wherein the image data included in the original data may be at least part of the image data in the environmental image data captured by the camera; the feature map data included in the original data may be at least part of the feature map data obtained after performing a predetermined operation on the environmental image data captured by the camera. Here, the predetermined operation may include but is not limited to tensor operations, vector operations, etc. Tensor operations may include convolution operations, such as two-dimensional convolution operations, three-dimensional convolution operations, etc. Vector operations may include point-to-point element-by-element operations, such as point-to-point element-by-element multiplication operations, point-to-point element-by-element addition operations, etc.

[0053] In some optional embodiments of the present disclosure, each of the M atomic instructions may carry a calculation type, and the calculation subcircuit 30 may determine the calculation type carried by any atomic instruction as the calculation type indicated by the atomic instruction. The calculation type may include, but is not limited to, atomic addition / subtraction type, atomic increment / decrement type, atomic multiplication type, atomic maximum / minimum type, etc.

[0054] In some optional embodiments of the present disclosure, the atomic instructions in the target queue may be added to the target queue sequentially, and the calculation subcircuit 30 may determine the sorting attributes of the atomic instructions in the target queue based on the order in which the atomic instructions in the target queue are added. For example, for the first atomic instruction added to the target queue, the calculation subcircuit 30 may determine that the sorting attribute of the atomic instruction is the head of the queue attribute, that is, the atomic instruction serves as the head element of the target queue. For another example, for the last (i.e., the last) atomic instruction added to the target queue, the calculation subcircuit 30 may determine that the sorting attribute of the atomic instruction is the tail of the queue attribute, that is, the atomic instruction serves as the tail element of the target queue. For another example, for an atomic instruction that is neither the first nor the last (i.e., neither the first nor the last) added to the target queue, the calculation subcircuit 30 may determine that the sorting attribute of the atomic instruction is the in-queue attribute, that is, the atomic instruction serves as the in-queue element of the target queue.

[0055] In some optional embodiments of the present disclosure, based on the original data, the calculation type indicated by each atomic instruction in the target queue, and the sorting attributes of each atomic instruction in the target queue, the calculation subcircuit 30 can, on the basis of the original data, sequentially perform calculations of the calculation type indicated by each atomic instruction in the target queue to generate target calculation result data. In this way, the target calculation result data can also be understood as the calculation result data that can be obtained after continuously executing several operations on each atomic instruction in the target queue based on the original data. The calculation subcircuit 30 can write the target calculation result data into the address space corresponding to the target operation address in the memory 40 to update the data stored in the address space corresponding to the target operation address from the original data to the target calculation result data.

[0056] In an embodiment of the present disclosure, the instruction processing subcircuit 20 can cache the obtained atomic instructions according to the caching rules that the atomic instructions corresponding to the same target operation address are cached in the same target queue. Through a read operation, the calculation subcircuit 30 can obtain the original data corresponding to the target operation address in the memory 40. Based on the original data, the calculation type indicated by each atomic instruction in the target queue, and the sorting attribute of each atomic instruction in the target queue, the calculation subcircuit 30 can, on the basis of the original data, perform calculations of the calculation type indicated by each atomic instruction in the target queue in sequence to generate target calculation result data. Through a write operation, the calculation subcircuit 30 can update the data stored in the address space corresponding to the target operation address in the memory 40 from the original data to the target calculation result data, thereby completing the execution of each atomic instruction in the target queue. It can be seen that in the embodiments of the present disclosure, when caching atomic instructions according to the above-mentioned cache rules, the original data in the memory 40 can be obtained through a read operation, and then several modification operations are continuously performed for each atomic instruction in the target queue to obtain the target calculation result data. After that, the original data in the memory 40 is updated to the target calculation result data through a write operation, and the execution of each atomic instruction in the target queue can be completed. There is no need to perform read operations, modification operations, and write operations for each atomic instruction in sequence, which can greatly reduce the number of executions of read operations and the number of executions of write operations, thereby effectively improving the execution efficiency of atomic instructions.

[0057] In some optional examples, the calculation subcircuit 30 is configured to generate target calculation result data based on the original data, the calculation type, and the sorting attribute, and may include:

[0058] The calculation subcircuit 30 is used to calculate the original data based on the corresponding calculation type for the atomic instructions with the queue head attribute in the target queue, generate reference calculation result data and cache it;

[0059] The calculation subcircuit 30 is used to calculate the latest cached reference calculation result data based on the corresponding calculation type for the atomic instructions with the queue attribute in the target queue, generate new reference calculation result data and cache it;

[0060] The calculation sub-circuit 30 is used to calculate the latest cached reference calculation result data based on the corresponding calculation type for the atomic instruction with the tail attribute in the target queue to generate target calculation result data.

[0061] Optionally, for an atomic instruction whose sorting attribute in the target queue is a head-of-the-line attribute, the calculation subcircuit 30 may perform calculations on the original data based on the calculation type indicated by the atomic instruction to generate reference calculation result data. For example, if the calculation type indicated by the atomic instruction is an atomic addition type, the calculation subcircuit 30 may perform an atomic addition type calculation on the original data to generate reference calculation result data. For another example, if the calculation type indicated by the atomic instruction is an atomic multiplication type, the calculation subcircuit 30 may perform an atomic multiplication type calculation on the original data to generate reference calculation result data. The calculation subcircuit 30 may include a second cache space, and the calculation subcircuit 30 may cache the reference calculation result data in the second cache space.

[0062] Optionally, for an atomic instruction in the target queue whose sorting attribute is a queue attribute, the calculation sub-circuit 30 may calculate the reference calculation result data most recently cached in the second cache space based on the calculation type indicated by the atomic instruction to generate new reference calculation result data, and cache the new reference calculation result data in the second cache space. In this way, the reference calculation result data most recently cached in the second cache space mentioned in this paragraph may be the reference calculation result data generated after calculating the original data in the previous paragraph, or may be the new reference calculation result data generated after calculating the already generated reference calculation result data.

[0063] Optionally, for an atomic instruction whose sorting attribute in the target queue is the tail attribute, the calculation subcircuit 30 can calculate the reference calculation result data most recently cached in the second cache space based on the calculation type indicated by the atomic instruction to generate new reference calculation result data, which can be used as the target calculation result data.

[0064] In an example, the queue C3 mentioned above is used as the target queue, and the target queue includes four atomic instructions: atomic instruction D7, atomic instruction D8, atomic instruction D9, and atomic instruction D10. In the target queue, atomic instruction D7 can be located at the head of the queue, atomic instruction D10 can be located at the tail of the queue, atomic instruction D8 and atomic instruction D9 can be located between the head and the tail of the queue, and atomic instruction D8 and atomic instruction D7 can be adjacent. The calculation type indicated by atomic instruction D7 can be calculation type R1; the calculation type indicated by atomic instruction D8 can be calculation type R2; the calculation type indicated by atomic instruction D9 can be calculation type R3; the calculation type indicated by atomic instruction D10 can be calculation type R4.

[0065] The calculation subcircuit 30 may perform four consecutive operations on each atomic instruction in the target queue based on the original data. For example, the calculation subcircuit 30 may first perform the operation on the atomic instruction D7, then perform the operation on the atomic instruction D8, then perform the operation on the atomic instruction D9, and finally perform the operation on the atomic instruction D10.

[0066] Since the atomic instruction D7 is at the head of the team, that is, the sorting attribute of the atomic instruction D7 is the head of the team attribute, when performing this operation on the atomic instruction D7, the calculation subcircuit 30 can calculate the original data based on the calculation type R1 to generate reference calculation result data S1 and cache it.

[0067] Since the atomic instruction D8 is in the queue, that is, the sorting attribute of the atomic instruction D8 is the queue attribute, and since the latest cached reference calculation result data is the reference calculation result data S1, when executing this operation on the atomic instruction D8, the calculation sub-circuit 30 can calculate the reference calculation result data S1 based on the calculation type R2 to generate the reference calculation result data S2 and cache it.

[0068] Since the atomic instruction D9 is in the queue, that is, the sorting attribute of the atomic instruction D9 is the queue attribute, and since the latest cached reference calculation result data is the reference calculation result data S2, when executing this operation on the atomic instruction D9, the calculation subcircuit 30 can calculate the reference calculation result data S2 based on the calculation type R3 to generate the reference calculation result data S3 and cache it.

[0069] Since the atomic instruction D10 is at the end of the queue, that is, the sorting attribute of the atomic instruction D10 is the end of the queue attribute, and since the latest cached reference calculation result data is the reference calculation result data S3, when performing this operation on the atomic instruction D10, the calculation sub-circuit 30 can calculate the reference calculation result data S3 based on the calculation type R4 to generate the target calculation result data.

[0070] In an embodiment of the present disclosure, based on the original data, the calculation type indicated by each atomic instruction in the target queue, and the sorting attributes of each atomic instruction in the target queue, the calculation subcircuit 30 can continuously perform several modification operations, wherein the object targeted by the first modification operation can be the original data, and the object targeted by the non-first modification operation can be the latest cached reference calculation result data, and the target calculation result data can be generated through the last (i.e., the last) modification operation. By updating the original data corresponding to the target operation address to the target calculation result data, the execution of each atomic instruction in the target queue can be completed, so there is no need to perform read operations, modification operations, and write operations in sequence for each atomic instruction, which can greatly reduce the number of executions of read operations and write operations, thereby effectively improving the execution efficiency of atomic instructions.

[0071] In some embodiments, the target queue may include only one atomic instruction, and this atomic instruction is located both at the head and the tail of the target queue. Accordingly, the sorting attributes of this atomic instruction include both the head attribute and the tail attribute. Then, the calculation subcircuit 30 can directly calculate the original data based on the calculation type indicated by this atomic instruction to generate the target calculation result data.

[0072] In some optional examples, such as Figure 2 As shown, the calculation sub-circuit 30 may include:

[0073] Register 301, register 301 is used to cache reference calculation result data;

[0074] The operator 303 and the selector 305 are configured to include a first mode and a second mode; the selector 305 is used to turn on the first bus between the memory 40 and the operator 303 in the first mode, and the operator 303 is used to calculate the original data obtained from the first bus; the selector 305 is used to turn on the second bus between the register 301 and the operator 303 in the second mode, and the operator 303 is used to calculate the latest cached reference calculation result data obtained from the second bus.

[0075] Optionally, the register 301 may be a circuit for temporarily storing data, instructions, etc.

[0076] Optionally, the operator 303 may be a circuit for performing atomic calculations, such as an arithmetic logic unit (ALU). Thus, the operator 303 may be used to perform various arithmetic and logical operations.

[0077] Alternatively, the selector 305 may be a multiple-input single-output selector. Figure 2As shown, selector 305 may include a first input terminal P1, a second input terminal P2, and an output terminal P3. The first input terminal P1 may be electrically connected to memory 40 via bus 52; the second input terminal P2 may be electrically connected to register 301 via bus 54; and the output terminal P3 may be electrically connected to operator 303 via bus 56. The first bus between memory 40 and operator 303 may include bus 52 and bus 56. The second bus between register 301 and operator 303 may include bus 54 and bus 56. In a first mode of selector 305, the first input terminal P1 and output terminal P3 may be in a connected state, while the second input terminal P2 and output terminal P3 may be in a disconnected state. Thus, the first bus between memory 40 and operator 303 may be conductive, while the second bus between register 301 and operator 303 may be disconnected. In the second mode of the selector 305, the first input terminal P1 and the output terminal P3 can be in a disconnected state, and the second input terminal P2 and the output terminal P3 can be in a connected state. In this way, the first bus between the memory 40 and the operator 303 can be disconnected, and the second bus between the register 301 and the operator 303 can be connected.

[0078] Continuing the example above where the target queue includes four atomic instructions, namely, atomic instruction D7, atomic instruction D8, atomic instruction D9, and atomic instruction D10, and the calculation types indicated by atomic instruction D7, atomic instruction D8, atomic instruction D9, and atomic instruction D10 are respectively calculation type R1, calculation type R2, calculation type R3, and calculation type R4, the calculation sub-circuit 30 can first place the selector 305 in the first mode. At this time, the first bus between the memory 40 and the operator 303 is turned on, then the original data in the selector 305 can pass through the first mode in sequence. Figure 2The bus 52, selector 305, and bus 56 are supplied to the operator 303. The operator 303 can calculate the original data based on the calculation type R1 indicated by the atomic instruction D7 to generate reference calculation result data S1, and cache the reference calculation result data S1 into the register 301. Next, the calculation sub-circuit 30 can place the selector 305 in the second mode. At this time, the second bus between the register 301 and the operator 303 is turned on, and the reference calculation result data S1 cached in the register 301 can be supplied to the operator 303 through the bus 54, the selector 305, and the bus 56 in sequence. The operator 303 can calculate the reference calculation result data S1 based on the calculation type R2 indicated by the atomic instruction D8 to generate reference calculation result data S2, and cache the reference calculation result data S2 in the register 301, so that the reference calculation result data S1 in the register 301 is replaced by the reference calculation result data S2. In addition, the register 301 can also cache indication information for indicating the most recent mode of the selector 305 (specifically the second mode). Since the atomic instruction D9 is not at the head of the target queue, the calculation sub-circuit 30 can still place the selector 305 in the second mode according to the indication information cached in the register 301. At this time, the reference calculation result data S2 cached in the register 301 can be supplied to the operator 303 through the bus 54, the selector 305, and the bus 56 in sequence. The operator 303 can calculate the reference calculation result data S2 based on the calculation type R3 indicated by the atomic instruction D9 to generate reference calculation result data S3, and cache the reference calculation result data S3 in the register 301, so that the reference calculation result data S2 in the register 301 is replaced by the reference calculation result data S3. Since the atomic instruction D10 is not at the head of the target queue, the calculation sub-circuit 30 can then, based on the indication information cached in the register 301, still place the selector 305 in the second mode. The reference calculation result data S3 cached in the register 301 can be sequentially supplied to the operator 303 via the bus 54, the selector 305, and the bus 56. The operator 303 can calculate the reference calculation result data S3 based on the calculation type R4 indicated by the atomic instruction D10 to generate the target calculation result data. Optionally, the operator 303 can cache the target calculation result data in the register 301, so that the reference calculation result data S3 in the register 301 is replaced by the target calculation result data.

[0079] In an embodiment of the present disclosure, the calculation subcircuit 30 can continuously perform several modification operations. By controlling the mode of the selector 305, the original data can be supplied to the operator 303 for calculation for the first modification operation, and the latest cached reference calculation result data can be supplied to the operator 303 for calculation for non-first modification operations, thereby effectively supporting the continuous execution of several modification operations through a set of hardware structures.

[0080] In some optional examples, the instruction processing subcircuit 20 may further be configured to determine an atomic instruction to be dequeued from the target queue, remove the atomic instruction from the target queue, output a computation type and a corresponding sorting attribute corresponding to the atomic instruction, and, in response to the sorting attribute of the atomic instruction being a head-of-queue attribute, send a first read request for a target operation address to the memory 40, so that the memory 40 outputs original data corresponding to the target operation address in response to the first read request.

[0081] The calculation subcircuit 30 is used to obtain the original data corresponding to the target operation address in the memory 40, the calculation type indicated by each atomic instruction in the target queue, and the sorting attribute of each atomic instruction in the target queue, which may include:

[0082] The calculation sub-circuit 30 is used to obtain the original data output by the memory 40 , the calculation type output by the instruction processing sub-circuit 20 , and the sorting attribute output by the instruction processing sub-circuit 20 .

[0083] Optionally, the instruction processing subcircuit 20 may determine the actual number of atomic instructions currently cached in the first cache space, and based on the determined actual number, determine whether the instruction processing subcircuit 20 meets a preset instruction dequeue condition. The preset instruction dequeue condition may include, but is not limited to, the first cache space being full, the occupied ratio of the first cache space exceeding a preset ratio, etc.

[0084] If the instruction processing subcircuit 20 meets the preset instruction dequeue condition, the instruction processing subcircuit 20 can determine the atomic instruction to be dequeued in the target queue. The atomic instruction to be dequeued in the target queue can be understood as the atomic instruction to be executed. For example, the atomic instruction can be the atomic instruction with the earliest addition time among the atomic instructions in the target queue. Here, the instruction processing subcircuit 20 can remove the atomic instruction from the target queue and send it to the target queue through the bus between the instruction processing subcircuit 20 and the calculation subcircuit 30 (for example, Figure 3 In this way, the calculation sub-circuit 30 receives the corresponding calculation type and the corresponding sorting attribute through the bus 62. In addition, if the sorting attribute of the atomic instruction is the head of queue attribute, the instruction processing sub-circuit 20 can also receive the corresponding calculation type and the corresponding sorting attribute through the bus between the instruction processing sub-circuit 20 and the memory 40 (for example, Figure 3The computing sub-circuit 30 can transmit a first read request for the target operation address to the memory 40 through the bus 64 in the example. The memory 40 can respond to the first read request by outputting corresponding read data, which can be used as the original data corresponding to the target operation address. Figure 3 bus 66 in the memory) to obtain the original data output by the memory 40.

[0085] In an embodiment of the present disclosure, by determining the atomic instruction to be dequeued in the target queue, moving the atomic instruction out of the target queue, and outputting the corresponding calculation type and the corresponding sorting attribute, and when the sorting attribute of the atomic instruction is the head of the queue attribute, by sending a read request, triggering the memory 40 to output the original data, the calculation sub-circuit 30 can obtain the input data (such as original data, calculation type and sorting attribute) required to continuously perform several operations, so that the calculation sub-circuit 30 can continuously perform several operations based on this.

[0086] In some optional examples, the calculation sub-circuit 30 is configured to update the original data corresponding to the target operation address to the target calculation result data, which may include:

[0087] The calculation sub-circuit 30 is used to send a write request for a target operation address to the memory 40, where the write request carries target calculation result data;

[0088] The memory 40 is used to update the original data of the target operation address to the target calculation result data in response to the write request; the memory 40 is also used to output a write success notification in response to the write request;

[0089] The instruction processing subcircuit 20 is used to count the removal status of the atomic instructions in the target queue and the reception status of the write success notification; based on the removal status and the reception status, determine the number of instructions being executed by the calculation subcircuit 30;

[0090] The calculation circuit is configured such that the maximum number of atomic instructions that the instruction processing subcircuit 20 allows to be cached is greater than or equal to a predetermined maximum number of instructions being executed by the calculation subcircuit 30 .

[0091] Optionally, after generating the target calculation result data, the calculation sub-circuit 30 may store the target calculation result data via a bus (eg, Figure 3 68 in the memory 40), sends a write request for the target operation address to the memory 40. Since the write request carries the target calculation result data, after the memory 40 receives the write request through the bus 68, the memory 40 can respond to the write request and update the data stored in the address space corresponding to the target operation address in the memory 40 from the original data to the target calculation result data. In addition, when the update is completed, the memory 40 can also send a write request to the memory 40 through the bus (for example, Figure 3 The bus 70 in the instruction processing sub-circuit outputs the write success notification, so that the write success notification can be transmitted to the instruction processing sub-circuit 20.

[0092] Optionally, the instruction processing subcircuit 20 can count the removal status of atomic instructions in the target queue and the reception status of write success notifications. The removal status of atomic instructions in the target queue can, for example, be used to represent the number of atomic instructions removed from the target queue and the removal time. The reception status of write success notifications can, for example, be used to represent the number of received write success notifications and the reception time. The instruction processing subcircuit 20 can determine the number of instructions being executed by the calculation subcircuit 30 based on the removal status and the reception status. The number of instructions being executed by the calculation subcircuit 30 can be understood as the number of atomic instructions that the calculation subcircuit 30 is currently executing but has not yet completed. Here, the instruction processing subcircuit 20 can be provided with a counter. The initial count value of the counter can be zero. Each time an atomic instruction in the target queue is removed from the target queue, the counter can be incremented by 1 based on the existing count value. Each time the instruction processing subcircuit 20 receives a write success notification, the counter can be decremented by 1 based on the existing count value. In this way, the current count value of the counter can be used as the number of instructions being executed by the calculation subcircuit 30 determined based on the removal status and the reception status.

[0093] Optionally, the instruction processing subcircuit 20 may be pre-configured with a predetermined maximum number of instructions being executed by the calculation subcircuit 30 , which may be represented by K. K may be, for example, 20, 30, 40, 50, etc., which are not listed here one by one.

[0094] Optionally, the maximum number of atomic instructions that the instruction processing subcircuit 20 is allowed to cache can be expressed as N max Then, if the actual number of atomic instructions cached in the first cache area of ​​the instruction processing sub-circuit 20 is N max , the instruction processing sub-circuit 20 may no longer continue to receive and cache new atomic instructions, and wait until the actual number of atomic instructions cached in the first cache area of ​​the instruction processing sub-circuit 20 is less than N through the coordinated work of the instruction processing sub-circuit 20 and the calculation sub-circuit 30. max , the instruction processing sub-circuit 20 can start receiving and caching new atomic instructions.

[0095] In the embodiment of the present disclosure, the instruction processing sub-circuit 20 can cache the latest received N instructions according to the cache rule that the atomic instructions corresponding to the same target operation address are cached in the same target queue. max The instruction processing sub-circuit 20 can remove the atomic instruction, and the calculation sub-circuit 30 can perform the operation for the removed atomic instruction. maxIf the number of atomic instructions supplied to the computing subcircuit 30 is greater than or equal to K, the instruction processing subcircuit 20 is able to fully supply the atomic instructions required to perform the operation. For any two atomic instructions supplied to the computing subcircuit 30, if the two atomic instructions correspond to the same target operation address, the two atomic instructions are either removed from the same target queue or separated by at least N. max Atomic instructions. If these two atomic instructions are removed from the same target queue, since the calculation sub-circuit 30 can continuously execute several write operations for each atomic instruction in the target queue and then execute a write operation, it will not happen that the data is read again from the target operation address before the target calculation result data is written back, thereby ensuring the atomicity of the atomic instruction execution. If the two atomic instructions are separated by at least N max Atomic instructions, since the maximum number of atomic instructions allowed to be cached by the instruction processing sub-circuit 20 is N max , only in the existing N max When the execution of atomic instructions is completed, the instruction processing sub-circuit 20 will cache the new N max Atomic instructions, which means that based on the N completed max The target calculation result data obtained by the atomic instruction has been written into the memory 40, so there will be no situation where data is read again from the target operation address before the target calculation result data is written back, thereby ensuring the atomicity of the atomic instruction execution.

[0096] In some optional examples, the instruction processing subcircuit 20 may further be used to determine a numerical relationship between the actual number of atomic instructions currently cached by the instruction processing subcircuit 20 and the number of instructions being executed or a predetermined maximum value, and / or determine an attribute of the presence of target information for indicating the end of instruction transmission in the atomic instructions currently cached by the instruction processing subcircuit 20;

[0097] The instruction processing subcircuit 20 is further configured to determine the atomic instructions to be dequeued from the target queue, which may include:

[0098] The instruction processing subcircuit 20 is configured to determine an atomic instruction to be dequeued in the target queue in response to determining that the instruction processing subcircuit 20 meets a preset instruction dequeue condition based on a numerical relationship and / or an existence attribute.

[0099] Optionally, the actual number of atomic instructions currently cached by the instruction processing subcircuit 20 can be obtained by counting the atomic instructions currently cached by the instruction processing subcircuit 20. The actual number of atomic instructions currently cached by the instruction processing subcircuit 20 can be expressed as N 实际The numerical value of the number of instructions being executed by the calculation subcircuit 30 can be expressed as R. The predetermined maximum value can be expressed as K. The numerical relationship between the actual number of atomic instructions currently cached by the instruction processing subcircuit 20 and the numerical value of the number of instructions being executed can be understood as N 实际 The relationship between the actual number of atomic instructions currently cached by the instruction processing sub-circuit 20 and the predetermined maximum value can be understood as N 实际 The size relationship between K.

[0100] Optionally, the existence attribute of the target information for indicating the end of instruction transmission in the atomic instruction currently cached by the instruction processing sub-circuit 20 can be used to indicate whether the target information exists in the atomic instruction currently cached by the instruction processing sub-circuit 20.

[0101] In the embodiment of the present disclosure, the instruction processing subcircuit 20 can determine whether the instruction processing subcircuit 20 meets the preset instruction dequeue condition based on the numerical relationship and / or the existence attribute. For example, if the numerical relationship is used to represent N 实际 Greater than R, or represents N 实际 Is greater than K, indicating that the first cache space of the instruction processing subcircuit 20 caches many atomic instructions that need to be executed, then it can be determined that the instruction processing subcircuit 20 meets the preset instruction dequeue condition. For another example, if there is an attribute used to characterize that there is target information in the atomic instructions currently cached by the instruction processing subcircuit 20, then no new atomic instructions will be added to the target queue before all atomic instructions in the target queue are removed, then it can be determined that the instruction processing subcircuit 20 meets the preset instruction dequeue condition. For another example, if the numerical relationship is used to characterize N 实际 If the value is greater than K and the attribute exists to indicate that the target information exists in the atomic instruction currently cached by the instruction processing sub-circuit 20, it can be determined that the instruction processing sub-circuit 20 meets the preset instruction dequeue condition. If the instruction processing sub-circuit 20 meets the preset instruction dequeue condition, the instruction processing sub-circuit 20 can determine the atomic instruction to be dequeued in the target queue. For example, the atomic instruction with the earliest addition time in the target queue can be determined as the atomic instruction to be dequeued.

[0102] In the embodiments of the present disclosure, reference numerical relationships and / or existence attributes can be used to efficiently and reliably identify situations where the instruction processing subcircuit 20 meets the preset instruction dequeue conditions, so as to determine the atomic instructions to be dequeued in the target queue on this basis, remove the atomic instructions, and output the calculation type and sorting attributes. On this basis, several operations can be performed continuously for each atomic instruction in the target queue.

[0103] In some optional examples, the calculation subcircuit 30 is configured to generate target calculation result data based on the original data, the calculation type, and the sorting attribute, and may include:

[0104] The calculation subcircuit 30 is used to obtain the additional input data to be involved in the calculation indicated by each atomic instruction in the target queue; and generate target calculation result data based on the original data, calculation type, sorting attribute and additional input data.

[0105] Optionally, for any atomic instruction in the target queue, the atomic instruction may indicate additional input data to be calculated, and the additional input data may include but is not limited to addends for atomic addition calculations, subtrahends for atomic subtraction calculations, multipliers for atomic multiplication calculations, etc.

[0106] In some optional embodiments of the present disclosure, the instruction processing subcircuit 20 is configured to, for each atomic instruction in the target queue, output the additional input data carried by the atomic instruction in response to the atomic instruction carrying the additional input data; in response to the atomic instruction carrying the additional address, send a second read request for the additional address to the memory 40, and the memory 40 is configured to output the additional input data located at the additional address in the memory 40 in response to the second read request;

[0107] The calculation subcircuit 30 is used to obtain the additional input data to be calculated indicated by each atomic instruction in the target queue, which may include:

[0108] The calculation sub-circuit 30 is used to obtain additional input data output by the instruction processing sub-circuit 20 or the memory 40 .

[0109] Optionally, for any atomic instruction in the target queue, the instruction processing subcircuit 20 can determine whether the atomic instruction carries additional input data. If the atomic instruction carries additional input data, the additional input data can be directly extracted from the atomic instruction and transmitted through the bus (e.g. Figure 3 The additional input data is output to the calculation sub-circuit 30. If the atomic instruction does not carry the additional input data but carries an additional address (which is used to indicate the address space where the additional input data is located), the instruction processing sub-circuit 20 may send a second read request for the additional address to the memory 40. The memory 40 may output the corresponding read data in response to the second read request. The read data may serve as the additional input data. The additional input data may be transmitted through the bus (e.g. Figure 3 The bus 66 shown is output to the calculation subcircuit 30. In this way, no matter whether the atomic instruction carries additional input data or additional addresses, the calculation subcircuit 30 can efficiently and quickly obtain the additional input data for subsequent calculations.

[0110] Optionally, the calculation subcircuit 30 can generate target calculation result data based on the original data, calculation type, sorting attribute and additional input data. Continuing the example above where the target queue includes four atomic instructions, namely, atomic instruction D7, atomic instruction D8, atomic instruction D9 and atomic instruction D10, and the calculation types indicated by atomic instruction D7, atomic instruction D8, atomic instruction D9 and atomic instruction D10 are respectively calculation type R1, calculation type R2, calculation type R3 and calculation type R4, assuming that calculation type R1 is an atomic addition type, calculation type R2 is an atomic addition type, calculation type R3 is an atomic multiplication type and calculation type R4 is an atomic multiplication type, and the additional input data corresponding to atomic instruction D7, atomic instruction D8, atomic instruction D9 and atomic instruction D10 are respectively additional input data Z1, additional input data Z2, additional input data Z3 and additional input data Z4, the operator 303 can add the additional input data Z1 to the original data to generate reference calculation result data S1. Next, the operator 303 may multiply the additional input data Z2 by the reference calculation result data S1 to generate reference calculation result data S2. Thereafter, the operator 303 may multiply the additional input data Z3 by the reference calculation result data S2 to generate reference calculation result data S3. Furthermore, the operator 303 may multiply the additional input data Z4 by the reference calculation result data S3 to generate target calculation result data.

[0111] In an optional example, the original data or reference calculation result data transmitted by the selector 305 to the operator 303 can be expressed as Figure 4 The first input in , additional input data can be expressed as Figure 4 The operator 303 obtains the first input and the second input via the corresponding bus, and the operator 303 can calculate the first input and the second input, and finally generate target calculation result data.

[0112] In an embodiment of the present disclosure, the calculation subcircuit 30 can obtain the additional input data to be involved in the calculation indicated by each atomic instruction in the target queue for use in generating target calculation result data. In this way, the embodiment of the present disclosure can better support calculation types that require two inputs (such as the first input and the second input mentioned above).

[0113] In some optional examples, such as Figure 5 As shown, the instruction processing sub-circuit 20 may include:

[0114] The decoder 202 is configured to decode each newly received atomic instruction in response to receiving the newly received atomic instruction and obtain an operation address of the newly received atomic instruction;

[0115] Comparator 204, which is used to compare the operation address of the newly received atomic instruction with the target operation addresses corresponding to the existing target queues to obtain a comparison result;

[0116] The instruction processing unit 206 is used to cache the newly received atomic instruction in the existing target queue in response to the comparison result indicating that the operation address of the newly received atomic instruction matches the target operation address corresponding to the existing target queue; create a new target queue in response to the comparison result indicating that the operation address of the newly received atomic instruction does not match the target operation addresses corresponding to the existing target queues, and cache the newly received atomic instruction in the new target queue.

[0117] Alternatively, decoder 202 may be a hardware unit for decoding atomic instructions. Comparator 204 may be hardware for comparing different inputs. Instruction processing unit 206 may be hardware for performing corresponding processing operations based on the comparison result of comparator 204. Comparator 204 may be electrically connected to decoder 202, and instruction processing unit 206 may be electrically connected to comparator 204.

[0118] In an embodiment of the present disclosure, whenever the instruction processing subcircuit 20 receives a new atomic instruction, the decoder 20 can decode the newly received atomic instruction to separate the operation address from the newly received atomic instruction, that is, obtain the operation address of the newly received atomic instruction. The decoder 202 can send the operation address of the newly received atomic instruction to the comparator 204. The comparator 204 can also obtain the target operation addresses corresponding to each existing target queue. The comparator 204 can compare the operation address of the newly received atomic instruction with the target operation addresses corresponding to each existing target queue to obtain a comparison result; wherein the comparison result is used to indicate whether the operation address of the newly received atomic instruction is the same as the target operation address corresponding to an existing target queue. If the comparison result indicates that the operation address of the newly received atomic instruction is the same as the target operation address corresponding to an existing target queue, indicating that the operation address of the newly received atomic instruction matches the target operation address corresponding to the existing target queue, then the newly received atomic instruction can be added to the existing target queue. In this case, the newly received atomic instruction can be placed at the end of the target queue. If the comparison result indicates that the operation address of the newly received atomic instruction is different from the target operation address corresponding to any existing target queue, indicating that the operation address of the newly received atomic instruction does not match the target operation address corresponding to each existing target queue, then the instruction processing unit 206 can create a new target queue in the first cache space, and the newly received atomic instruction can be placed at the head of the new target queue. In this way, when the atomic instructions in the target queue are subsequently executed, the atomic instruction that enters the target queue first will be removed and executed first, and the atomic instruction that enters the target queue later will be removed and executed later, which is conducive to ensuring the correctness of the execution order of these atomic instructions.

[0119] In the embodiment of the present disclosure, through the coordinated work of the decoder 202, the comparator 204 and the instruction processing unit 206, the atomic instructions can be cached according to the caching rule that the atomic instructions with the same operation address are cached in the same target queue. On this basis, several modification operations can be executed continuously for each atomic instruction in the target queue. In this way, the execution of each atomic instruction in the target queue can be completed based on one read operation, several modification operations and one write operation, thereby effectively improving the execution efficiency of the atomic instructions.

[0120] For some optional examples, see Figure 5If, in combination with the numerical relationship and existence attributes described above, it is identified that the instruction processing subcircuit 20 meets the preset instruction dequeue conditions, the instruction processing subcircuit 20 can start from the oldest target queue and send a read request to the memory 40, and send it in order from the head element to the tail element. After the sending is successful, the corresponding atomic instruction can be dequeued. After each read request is sent, if the instruction processing subcircuit 20 still meets the preset dequeue conditions, the next read request is sent. While sending the read request, the calculation type and corresponding sorting attribute indicated by the corresponding atomic instruction can also be transmitted to the calculation subcircuit 30. The calculation subcircuit 30 can obtain the read data output by the memory 40 in response to the read request (which may include the first input and the second input described above). The calculation subcircuit 30 can perform multiple calculations continuously based on the first input, the calculation type, the sorting attribute, and the second input to generate the target calculation result data. Finally, the calculation subcircuit 30 can write the target calculation result data back to the memory 40.

[0121] In summary, in the embodiment of the present disclosure, by caching the atomic instructions corresponding to the same target operation address in the same target queue according to the caching rule, the atomic instructions are cached, so that multiple atomic instructions for the same target operation address can be executed continuously, and only need to access the memory 40 twice (once for reading and once for writing), thereby greatly improving the execution efficiency of the atomic instructions. In addition, in the embodiment of the present disclosure, by configuring the calculation circuit so that the maximum number of atomic instructions allowed to be cached by the instruction processing subcircuit 20 is greater than or equal to the predetermined maximum number of instructions in execution of the calculation subcircuit 30, it is beneficial to ensure the atomicity of the atomic instructions during execution.

[0122] Exemplary Methods

[0123] Figure 6 It is a flowchart of a data processing method provided by some exemplary embodiments of the present disclosure. Figure 6 The method shown may include:

[0124] Step 610, obtaining an atomic instruction;

[0125] Step 620 , caching the atomic instructions corresponding to the same target operation address in the same target queue;

[0126] Step 630 , obtaining the original data corresponding to the target operation address in the memory, the calculation type indicated by each atomic instruction in the target queue, and the sorting attribute of each atomic instruction in the target queue;

[0127] Step 640: Generate target calculation result data based on the original data, calculation type, and sorting attributes;

[0128] Step 650: Update the original data corresponding to the target operation address to the target calculation result data.

[0129] In some optional examples, such as Figure 7 As shown, step 640 may include:

[0130] Step 6402: For the atomic instructions in the target queue whose sorting attribute is the head attribute, calculate the original data based on the corresponding calculation type, generate reference calculation result data, and cache it;

[0131] Step 6404: For the atomic instructions in the target queue whose sorting attribute is the queue attribute, based on the corresponding calculation type, calculate the latest cached reference calculation result data, generate new reference calculation result data, and cache it;

[0132] Step 6406 , for the atomic instructions in the target queue whose sorting attribute is the tail attribute, based on the corresponding calculation type, the latest cached reference calculation result data is calculated to generate target calculation result data.

[0133] In some optional examples, such as Figure 8 As shown, the method provided by the embodiment of the present disclosure may further include:

[0134] Step 810, caching reference calculation result data via registers;

[0135] Step 820 , in the first mode of the selector, conducting the first bus between the memory and the operator through the selector so that the operator performs calculations on the original data obtained from the first bus;

[0136] Step 830 : In the second mode of the selector, the second bus between the register and the operator is turned on through the selector, so that the operator calculates the latest cached reference calculation result data obtained from the second bus.

[0137] In some optional examples, such as Figure 9 As shown, the method provided by the embodiment of the present disclosure may further include:

[0138] Step 910, determining the atomic instruction to be dequeued in the target queue, and removing the atomic instruction from the target queue;

[0139] Step 920: Outputting the calculation type and the corresponding sorting attribute corresponding to the atomic instruction through the instruction processing subcircuit;

[0140] Step 930 : In response to the order attribute of the atomic instruction being a head-of-line attribute, sending a first read request for the target operation address to the memory, so that the memory outputs original data corresponding to the target operation address in response to the first read request.

[0141] Step 630 may include:

[0142] Step 6301: Obtain the original data output by the memory, the calculation type output by the instruction processing sub-circuit, and the sorting attribute output by the instruction processing sub-circuit.

[0143] In some optional examples, such as Figure 10 As shown, step 650 may include:

[0144] Step 6501: Send a write request for a target operation address to a memory, where the write request carries target calculation result data, so that the memory updates the original data of the target operation address with the target calculation result data in response to the write request, and outputs a write success notification in response to the write request.

[0145] like Figure 10 As shown, the method provided by the embodiment of the present disclosure may further include:

[0146] Step 1010, counting the removal status of atomic instructions in the target queue and the reception status of write success notifications;

[0147] Step 1020: Determine the number of instructions being executed by the computing subcircuit based on the removal status and the receiving status; wherein the computing circuit is configured such that the maximum number of atomic instructions allowed to be cached by the instruction processing subcircuit is greater than or equal to a predetermined maximum value of the number of instructions being executed by the computing subcircuit.

[0148] In some optional examples, such as Figure 11 As shown, the method provided by the embodiment of the present disclosure may further include:

[0149] Step 1110, determining a numerical relationship between the actual number of atomic instructions currently cached by the instruction processing subcircuit and the number of instructions being executed or a predetermined maximum value, and / or determining the presence attribute of target information for indicating the end of instruction transmission in the atomic instructions currently cached by the instruction processing subcircuit;

[0150] Step 910 may include:

[0151] Step 9101 , in response to determining that the instruction processing subcircuit meets a preset instruction dequeue condition based on a numerical relationship and / or an existence attribute, determine an atomic instruction to be dequeued in a target queue.

[0152] In some optional examples, such as Figure 12 As shown, step 640 may include:

[0153] Step 6407: Obtain additional input data to be calculated indicated by each atomic instruction in the target queue;

[0154] Step 6409: Generate target calculation result data based on the original data, calculation type, sorting attributes and additional input data.

[0155] In some optional examples, step 6407 may include:

[0156] For each atomic instruction in the target queue, in response to the atomic instruction carrying additional input data, outputting the additional input data carried by the atomic instruction through the instruction processing subcircuit; in response to the atomic instruction carrying an additional address, sending a second read request for the additional address to the memory, so that the memory outputs the additional input data located at the additional address in the memory in response to the second read request;

[0157] Step 6407 may include:

[0158] Get additional input data from the instruction processing subcircuit or memory output.

[0159] In some optional examples, such as Figure 13 As shown, the method provided by the embodiment of the present disclosure may further include:

[0160] Step 1310 , in response to each newly received atomic instruction, decoding the newly received atomic instruction to obtain an operation address of the newly received atomic instruction;

[0161] Step 1320 , comparing the operation address of the newly received atomic instruction with the target operation addresses corresponding to the existing target queues to obtain a comparison result;

[0162] Step 1330 , in response to the comparison result indicating that the operation address of the newly received atomic instruction matches the target operation address corresponding to the existing target queue, caching the newly received atomic instruction in the existing target queue;

[0163] Step 1340 , in response to the comparison result indicating that the operation address of the newly received atomic instruction does not match the target operation addresses corresponding to the existing target queues, a new target queue is created and the newly received atomic instruction is cached in the new target queue.

[0164] In the method disclosed herein, various optional embodiments, optional implementations, and optional examples disclosed in the exemplary system section above may be flexibly selected and combined as needed to achieve corresponding functions and effects, and are not listed one by one in this disclosure.

[0165] The beneficial technical effects corresponding to the exemplary embodiment of this method can be found in the corresponding beneficial technical effects of the above exemplary system part, which will not be repeated here.

[0166] Exemplary electronic devices

[0167] Figure 14 14 shows a block diagram of an electronic device according to an embodiment of the present disclosure. The electronic device 1400 includes one or more processors 1410 and a memory 1420 .

[0168] The processor 1410 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1400 to perform desired functions.

[0169] The memory 1420 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1410 may execute the one or more computer program instructions to implement the methods of the various embodiments of the present disclosure described above and / or other desired functions.

[0170] In one example, the electronic device 1400 may further include an input device 1430 and an output device 1440 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0171] The input device 1430 may also include, for example, a keyboard, a mouse, and the like.

[0172] The output device 1440 can output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and its connected remote output device, etc.

[0173] Of course, to simplify, Figure 14 Only some of the components related to the present disclosure in the electronic device 1400 are shown, and components such as buses, input / output interfaces, etc. are omitted. In addition, the electronic device 1400 may further include any other appropriate components according to specific application scenarios.

[0174] Exemplary computer program products and computer-readable storage media

[0175] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions that, when executed by a processor, enable the processor to perform the steps of the method according to various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section of this specification.

[0176] The computer program product may be written in any combination of one or more programming languages ​​to implement the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as C or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a stand-alone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0177] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, causes the processor to execute the steps of the method according to various embodiments of the present disclosure described in the above “Exemplary Method” section of this specification.

[0178] The computer-readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can, for example, include but is not limited to a system, device or component of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0179] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, the advantages, strengths, and effects mentioned in this disclosure are merely illustrative and non-limiting, and should not be construed as necessarily possessed by each embodiment of the present disclosure. The specific details disclosed above are provided for illustrative purposes and to facilitate understanding, and are not intended to be limiting. The above details do not limit the present disclosure to necessarily being implemented using the above specific details.

[0180] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A computing circuit comprising: an instruction processing subcircuit, the instruction processing subcircuit being used to obtain atomic instructions and cache the atomic instructions corresponding to the same target operation address in the same target queue; a calculation subcircuit, the calculation subcircuit being configured to obtain original data corresponding to the target operation address in a memory, a calculation type indicated by each of the atomic instructions in the target queue, and an ordering attribute of each of the atomic instructions in the target queue; Based on the original data, the calculation type and the sorting attribute, target calculation result data is generated; and the original data corresponding to the target operation address is updated to the target calculation result data.

2. The calculation circuit according to claim 1, wherein: The calculation subcircuit is configured to generate target calculation result data based on the original data, the calculation type, and the sorting attribute, including: The calculation subcircuit is configured to calculate the original data based on the corresponding calculation type for the atomic instruction whose sorting attribute is the head of queue in the target queue, generate reference calculation result data, and cache the reference calculation result data; The calculation subcircuit is configured to calculate, for the atomic instruction in the target queue whose sorting attribute is the queue attribute, the latest cached reference calculation result data based on the corresponding calculation type, generate new reference calculation result data, and cache the new reference calculation result data; The calculation subcircuit is used to calculate the reference calculation result data in the latest cache based on the corresponding calculation type for the atomic instruction whose sorting attribute in the target queue is the tail attribute, and generate the target calculation result data.

3. The calculation circuit according to claim 2, wherein: The calculation subcircuit comprises: a register, the register being used to cache the reference calculation result data; An operator and a selector, the selector being configured to include a first mode and a second mode; the selector being used to conduct a first bus between the memory and the operator in the first mode, and the operator being used to calculate the original data obtained from the first bus; the selector being used to conduct a second bus between the register and the operator in the second mode, and the operator being used to calculate the latest cached reference calculation result data obtained from the second bus.

4. The calculation circuit according to claim 1, wherein: The instruction processing subcircuit is further configured to determine the atomic instruction to be dequeued from the target queue, remove the atomic instruction from the target queue, output the calculation type and the corresponding sorting attribute corresponding to the atomic instruction, and in response to the sorting attribute of the atomic instruction being a head-of-queue attribute, send a first read request for the target operation address to the memory, so that the memory outputs the original data corresponding to the target operation address in response to the first read request. The calculation subcircuit is used to obtain original data corresponding to the target operation address in the memory, the calculation type indicated by each atomic instruction in the target queue, and the sorting attribute of each atomic instruction in the target queue, including: The calculation sub-circuit is used to obtain the original data output by the memory, the calculation type output by the instruction processing sub-circuit, and the sorting attribute output by the instruction processing sub-circuit.

5. The calculation circuit according to claim 4, wherein: The calculation sub-circuit is configured to update the original data corresponding to the target operation address to the target calculation result data, including: The calculation sub-circuit is used to send a write request for the target operation address to the memory, where the write request carries the target calculation result data; The memory is used to update the original data of the target operation address to the target calculation result data in response to the write request; the memory is also used to output a write success notification in response to the write request; The instruction processing subcircuit is used to count the removal status of the atomic instructions in the target queue and the reception status of the write success notification; based on the removal status and the reception status, determine the number of instructions being executed by the calculation subcircuit; The computing circuit is configured such that the maximum number of atomic instructions that the instruction processing subcircuit is allowed to cache is greater than or equal to a predetermined maximum number of instructions being executed by the computing subcircuit.

6. The calculation circuit according to claim 5, wherein: The instruction processing subcircuit is further configured to determine a numerical relationship between an actual number of the atomic instructions currently cached by the instruction processing subcircuit and the number of instructions being executed or the predetermined maximum value, and / or determine an attribute of the presence of target information for indicating the end of instruction transmission in the atomic instruction currently cached by the instruction processing subcircuit; The instruction processing subcircuit is further configured to determine the atomic instruction to be dequeued from the target queue, including: The instruction processing subcircuit is configured to determine the atomic instruction to be dequeued in the target queue in response to determining that the instruction processing subcircuit meets a preset instruction dequeue condition based on the numerical relationship and / or the existence attribute.

7. The calculation circuit according to claim 1, wherein: The calculation subcircuit is configured to generate target calculation result data based on the original data, the calculation type, and the sorting attribute, including: The calculation subcircuit is used to obtain the additional input data to be involved in the calculation indicated by each atomic instruction in the target queue; and generate the target calculation result data based on the original data, the calculation type, the sorting attribute and the additional input data.

8. The calculation circuit according to claim 7, wherein: The instruction processing subcircuit is configured to, for each atomic instruction in the target queue, output the additional input data carried by the atomic instruction in response to the atomic instruction carrying the additional input data; in response to the atomic instruction carrying the additional address, send a second read request for the additional address to the memory, and the memory is configured to output the additional input data located at the additional address in the memory in response to the second read request; The calculation subcircuit is used to obtain additional input data to be calculated as indicated by each atomic instruction in the target queue, including: The calculation sub-circuit is used to obtain the additional input data output by the instruction processing sub-circuit or the memory.

9. The computing circuit according to any one of claims 1 to 8, wherein: The instruction processing subcircuit includes: a decoder, the decoder being configured to decode the newly received atomic instruction in response to each newly received atomic instruction, and obtain an operation address of the newly received atomic instruction; a comparator, configured to compare an operation address of the newly received atomic instruction with the target operation addresses corresponding to the existing target queues to obtain a comparison result; An instruction processing unit, the instruction processing unit is used to cache the newly received atomic instruction in the existing target queue in response to the comparison result indicating that the operation address of the newly received atomic instruction matches the target operation address corresponding to the existing target queue; in response to the comparison result indicating that the operation address of the newly received atomic instruction does not match the target operation addresses corresponding to each of the existing target queues, create a new target queue and cache the newly received atomic instruction in the new target queue.

10. A data processing method comprising: Get atomic instructions; caching the atomic instructions corresponding to the same target operation address in the same target queue; Obtaining original data corresponding to the target operation address in a memory, a calculation type indicated by each of the atomic instructions in the target queue, and an ordering attribute of each of the atomic instructions in the target queue; Generate target calculation result data based on the original data, the calculation type and the sorting attribute; The original data corresponding to the target operation address is updated to the target calculation result data. 11 . A computer-readable storage medium storing a computer program, wherein the computer program is executed by a processor to perform the data processing method according to claim 10 .

12. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the data processing method according to claim 10.

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