DMA communication device for converged computing architecture and its working method

Abstract

This invention discloses a DMA communication device and its operating method for a converged computing architecture. The DMA communication device includes a DMA transaction processing module and a protocol conversion module. When the network protocol processing component initiates a DMA read / write request, the DMA transaction processing module parses the relevant DMA read / write request, processes the DMA read / write request, receives DMA read request response data, and handles interrupt requests. The protocol conversion module converts read / write requests between the DMA interface and the AXI interface and maps response states. This invention aims to achieve efficient protocol conversion between the AXI and DMA interfaces, avoid DMA read request starvation caused by resource contention, ensure the consistency of DMA data access, improve the performance of accelerators in high-performance computing and artificial intelligence applications, reduce transmission latency, and increase data transmission bandwidth and energy efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer communication technology, and more specifically to a DMA communication device and its working method for a computer-network converged computing architecture. Background Technology

[0002] To address the explosive growth in computing power and diverse integration requirements of high-performance computing (HPC) and artificial intelligence (AI) applications, traditional CPU+GPU heterogeneous computing architectures, which use the PCIe bus for interconnection between CPU, GPU, and network interface card (NIC), face limitations in data transmission bandwidth and energy efficiency. Against this backdrop, heterogeneous computing architectures that integrate computing and network components, employing on-chip heterogeneous integration or multi-chip integration, have become a significant development trend. These integrated computing architectures utilize AXI interfaces to achieve on-chip integration between computing and network components, reducing transmission latency and improving data transmission bandwidth and energy efficiency. DMA (Direct Memory Access) allows certain hardware subsystems to directly access system memory without CPU control. In HPC and AI applications, this can be used for GPUs to directly access system memory without CPU control, potentially improving GPU performance. Therefore, how to implement DMA communication technology in integrated computing architectures has become a critical technical problem that urgently needs to be solved. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a DMA communication device and its working method for a computing-network converged computing architecture, which addresses the above-mentioned problems in the prior art. The present invention aims to achieve efficient protocol conversion between AXI interface and DMA interface, avoid the problem of DMA read request starvation caused by resource contention, ensure the consistency of DMA data access, so as to improve the performance of accelerators in high-performance computing and artificial intelligence applications, reduce transmission latency and improve data transmission bandwidth and energy efficiency.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] A DMA communication device for a converged computing architecture includes two interconnected modules: a DMA transaction processing module and a protocol conversion module. The protocol conversion module is connected to the computing unit and memory of an on-chip network (NoC) via an AXI interface. The DMA transaction processing module is connected to a network protocol processing unit. When the network protocol processing unit initiates a DMA read / write request, the DMA transaction processing module parses the relevant DMA read / write request, processes the DMA read / write request, receives DMA read request response data, and handles interrupt requests. The protocol conversion module converts read / write requests between the DMA interface and the AXI interface and maps response states. The protocol conversion module includes a read... The system comprises a request FIFO, a request conversion unit, a data FIFO, a data conversion unit, and a state conversion unit. The read request FIFO is used to cache DMA read request information received by the protocol conversion module, ensuring the smooth execution of continuous read request operations. The request conversion unit parses DMA read / write requests, converts them into AXI read / write requests, and performs conversions on the request address and data length. The data FIFO is responsible for caching DMA write request data and DMA read response data. The data conversion unit achieves cross-protocol data consistency through endianness conversion. The state conversion unit is responsible for converting AXI response signals into the transaction processing status of DMA read / write requests, where the transaction processing status includes success or failure.

[0006] Optionally, the DMA transaction processing module includes a DMA write request processing module and a DMA read request processing module for processing DMA write requests and DMA read requests from the network protocol processing unit. The DMA write request processing module is used to cache DMA write requests initiated by the network protocol processing unit, parse the target address and data length of the request, and transmit the target address, data length, and write data to the protocol conversion module. The DMA read request processing module receives requests from each read request source in parallel through a request queue that corresponds one-to-one with the read request source. At the same time, the DMA read request processing module arbitrates the read requests based on available credit and whether there is a read-write conflict, and transmits the response data of the read request to the corresponding read request source after receiving the response data. The DMA transaction processing module adopts an interrupt line approach, triggering an interrupt after the DMA data transmission is completed, notifying the CPU to release memory access rights, thereby realizing alternating memory access between the CPU and DMA and reducing resource contention.

[0007] Optionally, the DMA write request processing module comprises a DMA write request FIFO, a DMA write data FIFO, a DMA write control unit, and an interrupt request unit. The DMA write request FIFO is used to buffer write requests initiated by the network protocol processing unit, and the DMA write data FIFO is used to buffer write data from write requests initiated by the network protocol processing unit. When the DMA write control unit detects a write request channel ready signal, it reads the write request and write data from the DMA write request FIFO and DMA write data FIFO respectively, parses the target address and data length of the request, and transmits the address, data length, and write data to the protocol conversion module. After the data transmission is completed, the DMA write control unit marks the write request as successfully sent and triggers the interrupt request unit to perform interrupt request and clearing operations through an interrupt enable signal. The DMA read request processing module includes a DMA read request FIFO allocated to each read request source, a read request arbitration unit, and a DMA read control unit. The DMA read request FIFO is used to cache read requests initiated by the network protocol processing component. The read request arbitration unit is used to determine whether each read request FIFO has the processing conditions based on available credits and whether there is a read-write conflict, and to poll and arbitrate the FIFOs that meet the conditions to determine the DMA read requests to be processed. When the DMA read control unit detects a read request channel ready signal, it receives and parses the DMA read request determined by the read arbitration unit, and transmits the corresponding DMA read request information to the protocol conversion module, while receiving its response data. After feeding back the response data to the corresponding read request source, the DMA transaction processing module performs credit reclamation and resource release operations.

[0008] Optionally, the DMA write control unit has a built-in write request receive counter and a write request send counter to control the execution order between DMA read requests and DMA write requests. The value of the write request receive counter, wreq_count, is used to record the number of write requests initiated by the network protocol processing unit. This counter increments whenever the DMA write control unit receives a new write request. The value of the write request send counter, wsent_count, represents the number of write requests that have completed data transmission. This counter increments after each write request is sent to the protocol conversion module. When the DMA read request processing module receives a new read request, it increments the current value of the write request receive counter, wreq_count. After `unt` is merged with the read request, it is stored in the corresponding DMA read request FIFO. During the arbitration phase, the read request arbitration unit compares the value of the write request receive counter `wreq_count` carried in the read request with the value of the write request send counter `wsent_count` of the current DMA write control unit to determine whether there are any pending write requests before the read request: if the value of the write request send counter `wsent_count` is greater than or equal to the value of the write request receive counter `wreq_count`, it means that all write requests received before the read request have been sent to the protocol conversion module, and there is no read / write conflict, so the read request can be processed; otherwise, the read request is not processed for the time being.

[0009] Optionally, when the read request arbitration unit is used to determine whether each read request FIFO has the conditions for processing based on available credits and whether there is a read-write conflict, the criteria for determining whether each read request FIFO has the conditions for processing include: (1) the read request FIFO of the request source is not empty and there are unprocessed read requests; (2) the reserved credits of the request source have not been exhausted or the total credit resources used have not reached the system limit; (3) there is no situation where "write first, read later" is incorrectly processed as "read first, write later".

[0010] Optionally, the protocol conversion module's operational state transition includes four stages: initial state IDLE, address resolution state ADDR_PARSE, data transmission state DATA_XFER, and response adaptation state RESP_ADAPT. After power-on reset, the protocol conversion module is in the initial state IDLE, waiting for a DMA request signal. When a DMA read / write request enable signal is detected, the module enters the address resolution state ADDR_PARSE to complete the AXI request conversion. In the address resolution state ADDR_PARSE, the DMA request conversion unit caches DMA read request information and converts the DMA read / write request into an AXI read / write request. Simultaneously, it generates AXI address information, calculates the AXI bit width and Burst, and generates a byte valid signal. After the conversion is completed, the module enters the data transmission state DATA_XFER. The protocol conversion module implements DMA data conversion and transmission. In the data transmission state DATA_XFER, the DMA data conversion unit buffers DMA request data and performs endianness conversion based on the request type: for write requests, the protocol conversion module waits for the DMA write data to be valid, stores the DMA write request data in the data FIFO, performs endianness conversion, and sends it to the AXI interface; for read requests, the protocol conversion module waits for the AXI read data feedback to be valid, performs endianness conversion, and stores it in the data FIFO. After transmission is complete, the protocol conversion module enters the response adaptation state RESP_ADAPT to report the processing status of the DMA request. In the response adaptation state RESP_ADAPT, the protocol conversion module generates an AXI response request signal, parses the DMA processing result, and feeds it back to the DMA transaction processing module, then returns to the initial state IDLE.

[0011] In addition, the present invention also provides a computing-network converged computing chip, comprising a computing unit, an on-chip network NoC, a DMA communication device, and a network protocol processing unit connected in sequence, wherein the DMA communication device is the DMA communication device for the computing-network converged computing architecture.

[0012] Furthermore, this invention also provides a method for operating the aforementioned DMA communication device for a converged computing architecture, comprising a request conversion unit performing DMA request conversion: including AXI transaction request generation, address information conversion, AXI Burst length calculation, and write byte valid signal generation; when the network protocol processing unit initiates a DMA transaction request, if it is a read request, the request conversion unit caches the read request in a read request FIFO and then converts it into an AXI read request sequentially; if it is a write request, the request conversion unit performs the conversion directly; then the request conversion unit sends the converted AXI read / write request to the processor, while simultaneously performing address information conversion; during address information conversion, the request conversion unit maps the DMA request address to an AXI physical address and generates a write byte valid signal for the write request, wherein the AXI interface data width is 256 bits, the offset of the DMA write request address is represented by ADDR[4:0], and the request conversion unit determines and generates the corresponding byte valid signal based on whether the address is aligned: for the case of address alignment, if the total data length If the data length is less than or equal to 32 bytes, a single-cycle byte valid signal is generated based on the data length; if it exceeds 32 bytes, the first few cycles in Burst mode are all valid, and the last cycle generates a corresponding byte valid signal based on the remaining data length; however, for cases of address misalignment, if the total data length... If the value is less than or equal to 32-ADDR[4:0], then a single-byte valid signal is generated by combining the address offset and the data length; if the total data length is... If the data exceeds 32-ADDR[4:0], the first clock cycle generates a partial byte valid signal based on the address offset, the middle clock cycles are all valid, and the last clock cycle generates a corresponding byte valid signal based on the remaining data length. When calculating the AXI Burst length, the request conversion unit calculates the AXI Burst length based on the data length requested by the DMA, and its calculation function expression is:

[0013]

[0014] in, The length of the AXI Burst. Total data length Offset of the write request address for DMA. This is the floor operator.

[0015] Optionally, the system also includes a data conversion unit to perform DMA data conversion: upon receiving a DMA data enable signal, the data conversion unit buffers the DMA write request data into the data FIFO and initiates an AXI write data request. Simultaneously, the data conversion unit performs endianness conversion and uses a counter to count the amount of data transmitted to ensure data transmission accuracy. If the length of the data to be transmitted is less than the data bus width, the data conversion unit sets the last data signal to be valid, notifying the processor that data transmission has ended. During DMA read request processing, upon receiving an AXI read response data enable signal, the data conversion unit performs endianness conversion on the response data and buffers the converted DMA response data into the data FIFO. If the length of the data to be transmitted is less than the data bus width, the data conversion unit sets the last data signal to be valid, notifying the network protocol processing unit that data transmission has ended.

[0016] Optionally, it also includes a state transition unit performing DMA state transitions: during the write request processing, after the write data request is responded to, the state transition unit waits for the data transmission to complete, and then converts the AXI write request response to a DMA transaction processing state. During the read request processing, when the AXI read data feedback ends, the AXI response request is parsed as a DMA transaction processing state, and the transaction processing state includes success or failure.

[0017] Compared with existing technologies, the present invention mainly achieves the following beneficial effects: In a converged computing architecture, the network protocol processing unit accesses storage space through DMA requests. Based on this architecture, the device of the present invention can complete the DMA communication conversion and processing between the network protocol processing unit and the computing unit, realizing efficient DMA communication between the computing unit and the network unit. The device of the present invention completes efficient protocol conversion between the AXI interface and the DMA interface through the decoupling design of address, data, and response channels. Simultaneously, the device of the present invention reserves a certain amount of credit for each DMA read request and avoids the DMA read request starvation problem caused by resource contention through a fair round-robin scheduling strategy. The device of the present invention ensures the consistency of DMA data access by controlling the execution order between DMA read requests and DMA write requests. The device of the present invention can improve the performance of the computing unit in high-performance computing and artificial intelligence applications, reduce transmission latency, and improve data transmission bandwidth and energy efficiency. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the DMA communication device in an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the DMA transaction processing module in an embodiment of the present invention.

[0020] Figure 3This is a schematic diagram illustrating the principle of the three conversion functions of the protocol conversion module in this embodiment of the invention. Detailed Implementation

[0021] In a converged computing architecture, the network protocol processing unit accesses storage space via DMA requests. Based on this architecture, this invention proposes an AXI interface DMA communication device to complete DMA communication conversion and processing between the network protocol processing unit and the computing unit. To enable those skilled in the art to better understand the technical solution of this invention, the technical solution of this invention will be further described in detail below with reference to the accompanying drawings of the embodiments of this invention.

[0022] like Figure 1 As shown, this embodiment provides a DMA communication device for a converged computing architecture, including two interconnected modules: a DMA transaction processing module and a protocol conversion module. The protocol conversion module is connected to computing components (such as general-purpose computing components, accelerated computing components, etc.) and memory connected to the on-chip network NoC via an AXI interface. The DMA transaction processing module is connected to a network protocol processing component. When the network protocol processing component initiates a DMA read / write request, the DMA transaction processing module is used to parse the relevant DMA read / write request, process the DMA read / write request, receive DMA read request response data, and process interrupt requests. The protocol conversion module is used to convert read / write requests between the DMA interface and the AXI interface and to map the response status.

[0023] like Figure 1 As shown, the DMA transaction processing module in this embodiment includes a DMA write request processing module and a DMA read request processing module to process DMA write requests and DMA read requests from the network protocol processing unit. The DMA write request processing module is used to cache DMA write requests initiated by the network protocol processing unit, parse the target address and data length of the request, and transmit the target address, data length, and write data to the protocol conversion module. The DMA read request processing module receives requests from each read request source in parallel through a request queue that corresponds one-to-one with the read request source. At the same time, the DMA read request processing module arbitrates the read requests based on available credit and whether there is a read-write conflict, and transmits the response data of the read request to the corresponding read request source after receiving the response data. The DMA transaction processing module adopts an interrupt line approach, triggering an interrupt after the DMA data transmission is completed, notifying the CPU to release memory access rights, thereby realizing alternating memory access between the CPU and DMA and reducing resource contention.

[0024] like Figure 1As shown, the protocol conversion module in this embodiment includes a read request FIFO, a request conversion unit, a data FIFO, a data conversion unit, and a state conversion unit. The read request FIFO is used to cache DMA read request information received by the protocol conversion module, ensuring the smooth execution of continuous read request operations. The request conversion unit parses DMA read / write requests, converts them into AXI read / write requests, and performs conversion on the request address and data length. The data FIFO is responsible for caching DMA write request data and DMA read response data. The data conversion unit achieves cross-protocol data consistency through big / little endian conversion. The state conversion unit is responsible for converting the AXI response signal into the transaction processing status of the DMA read / write request, which includes success or failure.

[0025] like Figure 2 As shown, the DMA write request processing module in this embodiment consists of a DMA write request FIFO, a DMA write data FIFO, a DMA write control unit, and an interrupt request unit. The DMA write request FIFO is used to buffer write requests initiated by the network protocol processing unit, and the DMA write data FIFO is used to buffer write data from write requests initiated by the network protocol processing unit. When the DMA write control unit detects a write request channel ready signal, it reads the write request and write data from the DMA write request FIFO and the DMA write data FIFO, respectively, parses the target address and data length of the request, and transmits the address, data length, and write data to the protocol conversion module. After the data transmission is completed, the DMA write control unit marks that the write request has been successfully sent and triggers the interrupt request unit to perform interrupt request and clearing operations through an interrupt enable signal.

[0026] like Figure 2 As shown, the DMA read request processing module in this embodiment includes a DMA read request FIFO allocated to each read request source, a read request arbitration unit, and a DMA read control unit. The DMA read request FIFO is used to cache read requests initiated by the network protocol processing component. The read request arbitration unit is used to determine whether each read request FIFO has the processing conditions based on available credits and whether there is a read-write conflict, and to poll and arbitrate the FIFOs that meet the conditions to determine the DMA read requests to be processed. When the DMA read control unit detects a read request channel ready signal, it receives and parses the DMA read request determined by the read arbitration unit, and transmits the corresponding DMA read request information to the protocol conversion module, while receiving its response data. After feeding back the response data to the corresponding read request source, the DMA transaction processing module performs credit reclamation and resource release operations.

[0027] In this embodiment, the DMA write request FIFO and DMA write data FIFO are used to cache write requests initiated by the network protocol processing unit and the corresponding write data, respectively. Specifically, when the DMA transaction processing module receives the DMA write request enable signal from the network protocol processing unit, it increments the write request receive counter value wreq_count, stores the write request in the DMA write request FIFO, assigns a unique number to each write request, and returns a request acknowledgment signal. After receiving the DMA write data enable signal from the network protocol processing unit, it stores the data in the DMA write data FIFO and returns a receive acknowledgment signal. By controlling the execution order between DMA read requests and DMA write requests, the DMA transaction processing module prevents "write-then-read" from being mistakenly processed as "read-then-write," ensuring the consistency of read and write accesses. To ensure consistency between read and write accesses, the DMA write control unit in this embodiment incorporates a write request receive counter and a write request send counter to control the execution order between DMA read and write requests. The write request receive counter, wreq_count, records the number of write requests initiated by the network protocol processing unit; this counter increments whenever the DMA write control unit receives a new write request. The write request send counter, wsent_count, represents the number of write requests that have completed data transmission; this counter increments after each write request is sent to the protocol conversion module. When the DMA read request processing module receives a new read request, it increments the current write request receive counter value wreq_count by the value of the new read request. After merging, the requests are stored in the corresponding DMA read request FIFO. During the arbitration phase, the read request arbitration unit compares the value of the write request receive counter wreq_count carried in the read request with the value of the write request send counter wsent_count of the current DMA write control unit to determine whether there are any pending write requests before the read request: if the value of the write request send counter wsent_count is greater than or equal to the value of the write request receive counter wreq_count (i.e., wsent_count ≥ wreq_count), it means that all write requests received before the read request have been sent to the protocol conversion module, and there is no read / write conflict, so the read request can be processed; otherwise, the read request is not processed for the time being.

[0028] In this embodiment, the DMA write control unit is responsible for managing the processing of DMA write requests. Its control logic is as follows: When the DMA write request channel of the protocol conversion module is ready and there are pending requests in the DMA write request FIFO, the DMA write control unit sends a read enable signal to the DMA write request FIFO, reads a write request, and parses the write data address and data length. It then sends the parsing result to the protocol conversion module and triggers the DMA write request enable signal, and then performs data transmission. The DMA write control unit sends a read enable signal to the DMA write data FIFO, reads the requested write data, and sends it to the protocol conversion module, simultaneously triggering the DMA write data enable signal. After transmission is complete, the DMA write control unit triggers the DMA write data completion signal, increments the write request sending counter to mark that the current write request has been successfully sent to the protocol conversion module, and prepares to process the next write request. If an interrupt request is parsed during request processing, the DMA transaction processing module sends an interrupt enable signal to the interrupt request unit to trigger interrupt handling, and simultaneously suspends the processing of the current write request. DMA write request processing continues after the interrupt handling is completed.

[0029] In this embodiment, the interrupt request unit is responsible for interrupt request and clearing operations. When the interrupt request unit detects the interrupt enable signal of the DMA read control unit, it sends an interrupt request signal to the processor through the interrupt line, and at the same time suspends the current DMA transaction processing to ensure data consistency; after the interrupt processing is completed, the DMA transaction request processing flow is resumed through the status flag clearing mechanism.

[0030] In this embodiment, the DMA read request FIFO buffers read requests initiated by the network protocol processing unit. Specifically, the DMA transaction processing module allocates an independent DMA read request FIFO for each read request source of the network protocol processing unit, ensuring that each DMA read request FIFO corresponds one-to-one with the read request source. When the DMA transaction processing module receives the DMA read request enable signal from the network protocol processing unit, it obtains the value wreq_count of the write request receive counter in the current write request processing module, concatenates it with the read request to form a single data entry, stores it in the corresponding DMA read request FIFO according to its source, assigns a unique number to the read request, and returns a read request response signal to the network protocol processing unit.

[0031] In this embodiment, the read request arbitration unit is responsible for polling and arbitrating the DMA read request FIFO of each read request source. This unit independently maintains credit for each DMA read request source and reserves a certain amount of credit value to prevent a single request source from excessively occupying system resources. The arbitration logic takes the larger value between the actual used credit and the reserved credit of each request source as its effective used credit; and determines whether the credit resources have been exhausted based on the sum of the effective used credits of all request sources and a preset threshold. The read request arbitration unit is used to determine whether each read request FIFO has the conditions for processing based on the available credit and whether there is a read-write conflict. The criteria for determining whether each read request FIFO has the conditions for processing include: (1) the read request FIFO of the request source is not empty and there are unprocessed read requests; (2) the reserved credit of the request source has not been exhausted or the total used credit resources have not reached the system limit; (3) there is no situation where "write first, read later" is incorrectly processed as "read first, write later". Subsequently, the read request arbitration unit uses a polling strategy to read requests from the qualified read request FIFOs and hands them over to the DMA read control unit for processing. During the request processing, the DMA transaction processing module updates credit usage in real time.

[0032] In this embodiment, the DMA read control unit is responsible for coordinating the processing of DMA read requests and receiving response data. During the DMA read request processing phase, when the DMA read request channel ready signal of the protocol conversion module is detected, the DMA read control unit reads the pending read request from the read request arbitration unit and reduces the credit of the corresponding request source. Subsequently, the DMA read control unit parses the target address and data length information in the read request, stores the parsed request in the response request queue, and sends the DMA read request ID, DMA read data address, and DMA read data length to the protocol conversion module, while simultaneously triggering the DMA read request enable signal to complete the submission of the DMA read request. Upon receiving the read response enable signal returned by the protocol conversion module, the DMA read control unit enters the response data receiving process. First, the read control unit determines whether the receive buffer space of the request source corresponding to the read response ID is sufficient to accommodate the current response data. When the request source's receive buffer space is sufficient to accommodate the response data, the DMA read control unit sends a DMA read data enable signal to the protocol conversion module and receives the response data; otherwise, it pauses data reception. After data reception is complete, the response data reception completion signal and the response data enable signal are set to valid, and the response data is forwarded to the corresponding request source. Finally, the DMA read control unit releases the credit resources occupied by the read request, marks the read transaction as complete, and prepares to process subsequent requests.

[0033] like Figure 3 As shown, the protocol conversion module of the DMA communication device in this embodiment mainly implements three functions: DMA request conversion, DMA data conversion, and DMA state conversion. Figure 3As shown, the DMA request conversion unit performs DMA request conversion, which is responsible for caching DMA read request information, converting DMA read / write requests into AXI read / write requests, and sending them to the processor via the AXI bus. Simultaneously, it parses DMA address information to generate corresponding AXI address information, parses the DMA data length to calculate the AXI bit width and Burst parameter, and generates a write request byte valid signal. The DMA data conversion unit performs DMA data conversion, which is responsible for caching DMA request data, converting DMA data to AXI data through Big / Little Endian format conversion, and converting between the DMA data enable signal and the AXI data valid signal. The DMA state conversion unit performs DMA state conversion, which is used to monitor the processing progress of DMA requests, generate corresponding AXI response requests, and, after the AXI response handshake signal is parsed and converted into a DMA transaction processing state, feeds it back to the network protocol processing unit. In this embodiment, the protocol conversion module's working state transition includes four stages: initial state IDLE, address resolution state ADDR_PARSE, data transmission state DATA_XFER, and response adaptation state RESP_ADAPT. After power-on reset, the protocol conversion module is in the initial state IDLE, waiting for the DMA request signal. Upon detecting a DMA read / write request enable signal, the module enters the address resolution state (ADDR_PARSE) to complete the AXI request conversion. In ADDR_PARSE, the DMA request conversion unit caches DMA read request information and converts the DMA read / write request into an AXI read / write request. Simultaneously, it generates AXI address information, calculates the AXI bit width and Burst, and generates a byte validity signal. After conversion, the module enters the data transfer state (DATA_XFER) to implement DMA data conversion and transmission. In DATA_XFER, the DMA data conversion unit caches DMA request data and performs endianness conversion based on the request type: for write requests, the protocol conversion module waits for the DMA write data to be valid, stores the DMA write request data in a data FIFO, performs endianness conversion, and sends it to the AXI interface; for read requests, the protocol conversion module waits for valid AXI read data feedback, performs endianness conversion, and stores it in the data FIFO. After transmission, the protocol conversion module enters the response adaptation state (RESP_ADAPT) to provide feedback on the DMA request processing status. In the response adaptation state RESP_ADAPT, the protocol conversion module generates an AXI response request signal, parses the DMA processing result and feeds it back to the DMA transaction processing module, and then returns to the initial state IDLE.

[0034] In summary, the DMA communication device of this embodiment includes a DMA transaction processing module and a protocol conversion module. When the network protocol processing unit initiates a DMA read / write request, the DMA transaction processing module parses the relevant DMA read / write request, processes the DMA read / write request, receives the DMA read request response data, and handles interrupt requests. The protocol conversion module converts read / write requests between the DMA interface and the AXI interface and maps the response status. This DMA communication device can achieve efficient protocol conversion between the AXI interface and the DMA interface, avoiding DMA read request starvation caused by resource contention, ensuring the consistency of DMA data access, thereby improving the performance of the accelerator in high-performance computing and artificial intelligence applications, reducing transmission latency, and increasing data transmission bandwidth and energy efficiency.

[0035] In addition, this embodiment also provides a computing-network converged computing chip, including a computing unit, an on-chip network NoC, a DMA communication device, and a network protocol processing unit connected in sequence, wherein the DMA communication device is the DMA communication device used for the computing-network converged computing architecture.

[0036] Furthermore, this embodiment also provides a working method for the DMA communication device for the aforementioned computing-network converged computing architecture, including a request conversion unit performing DMA request conversion (converting DMA read / write requests into AXI read / write requests): including AXI transaction request generation, address information conversion, AXI Burst length calculation, and write byte valid signal generation; when the network protocol processing unit initiates a DMA transaction request, if it is a read request, the request conversion unit caches the read request in the read request FIFO and then converts it into an AXI read request sequentially; if it is a write request, the request conversion unit performs the conversion directly; then the request conversion unit sends the converted AXI read / write request to the processor, and performs address information conversion operation simultaneously; during the address information conversion, the request conversion unit maps the DMA request address to the AXI physical address, and generates a write byte valid signal for the write request, the AXI interface data width is 256 bits (i.e., 32 bytes), the offset of the DMA write request address is represented by ADDR[4:0], and the request conversion unit determines and generates the corresponding byte valid signal based on whether the address is aligned: for the case of address alignment, if the total data length If the data length is less than or equal to 32 bytes, a single-cycle byte valid signal is generated based on the data length; if it exceeds 32 bytes, the first few cycles in Burst mode are all valid, and the last cycle generates a corresponding byte valid signal based on the remaining data length; however, for cases of address misalignment, if the total data length... Less than or equal to 32-ADDR[4:0], that is: Then, the address offset and data length are combined to generate a single-byte valid signal; if the total data length If the data exceeds 32-ADDR[4:0], the first clock cycle generates a partial byte valid signal based on the address offset, the middle clock cycles are all valid, and the last clock cycle generates a corresponding byte valid signal based on the remaining data length. When calculating the AXI Burst length, the request conversion unit calculates the AXI Burst length based on the data length requested by the DMA, and its calculation function expression is:

[0037]

[0038] in, The length of the AXI Burst. Total data length Offset of the write request address for DMA. This is the floor function operator. Furthermore, in this embodiment, each AXI request carries a unique number (ID) to ensure the independence of multiple request operations. Upon receiving the response signal for the AXI request, DMA data conversion is performed, and the DMA read / write transaction request is responded to via the system bus.

[0039] The method in this embodiment also includes a data conversion unit performing DMA data conversion: upon receiving a DMA data enable signal, the data conversion unit buffers the DMA write request data into a data FIFO and initiates an AXI write data request. Simultaneously, the data conversion unit performs endianness conversion and uses a counter to count the amount of data transmitted to ensure data transmission accuracy. If the length of the data to be transmitted is less than the data bus width, the data conversion unit sets the last data signal to be valid, notifying the processor that data transmission has ended. During DMA read request processing, upon receiving an AXI read response data enable signal, the data conversion unit performs endianness conversion on the response data and buffers the converted DMA response data into a data FIFO. If the length of the data to be transmitted is less than the data bus width, the data conversion unit sets the last data signal to be valid, notifying the network protocol processing unit that data transmission has ended.

[0040] The method in this embodiment also includes a state transition unit performing DMA state transition: after the write data request is responded to during the write request processing, the state transition unit waits for the data transmission to complete, and then converts the AXI write request response to the DMA transaction processing state. During the read request processing, at the same time as the AXI read data feedback ends, the AXI response request is parsed as the DMA transaction processing state, which includes success or failure.

[0041] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A DMA communication device for a converged computing architecture, characterized in that, The system comprises two interconnected modules: a DMA transaction processing module and a protocol conversion module. The protocol conversion module is connected to the computing unit and memory on the on-chip network NoC via an AXI interface. The DMA transaction processing module is connected to the network protocol processing unit. When the network protocol processing unit initiates a DMA read / write request, the DMA transaction processing module parses the relevant DMA read / write request, processes the DMA read / write request, receives DMA read request response data, and handles interrupt requests. The protocol conversion module converts read / write requests between the DMA interface and the AXI interface and maps response states. The protocol conversion module includes a read request FIFO, a request conversion unit, a data FIFO, a data conversion unit, and a state conversion unit. The read request FIFO buffers the DMA read request information received by the protocol conversion module, ensuring the smooth execution of continuous read request operations. The request conversion unit parses the DMA read / write request, converts it into an AXI read / write request, and performs conversion of the request address and data length. The data FIFO buffers DMA write request data and DMA read response data. The data conversion unit achieves cross-protocol data consistency through endianness conversion. The state conversion unit is responsible for converting AXI response signals into DMA read / write request transaction states, including success or failure. The DMA transaction processing module includes a DMA write request processing module and a DMA read request processing module to process DMA write and read requests from the network protocol processing unit. The DMA write request processing module caches DMA write requests initiated by the network protocol processing unit, parses the target address and data length of the request, and transmits the target address, data length, and write data to the protocol conversion module. The DMA read request processing module receives requests from each read request source in parallel through a request queue that corresponds one-to-one with the read request source. Simultaneously, the DMA read request processing module arbitrates read requests based on available credit and the existence of read / write conflicts, and after receiving the response data for the read request, transmits it to the corresponding read request source. The DMA transaction processing module uses an interrupt line to trigger an interrupt after the DMA data transmission is completed, notifying the CPU to release memory access rights, thereby achieving alternating memory access between the CPU and DMA and reducing resource contention.

2. The DMA communication device for a converged computing architecture according to claim 1, characterized in that, The DMA write request processing module consists of a DMA write request FIFO, a DMA write data FIFO, a DMA write control unit, and an interrupt request unit. The DMA write request FIFO is used to buffer write requests initiated by the network protocol processing unit, and the DMA write data FIFO is used to buffer write data from write requests initiated by the network protocol processing unit. When the DMA write control unit detects a write request channel ready signal, it reads the write request and write data from the DMA write request FIFO and the DMA write data FIFO respectively, parses the target address and data length of the request, and transmits the address, data length, and write data to the protocol conversion module. After data transmission is completed, the DMA write control unit marks the write request as successfully sent and triggers the interrupt request unit to perform interrupt request and clearing operations through the interrupt enable signal; the DMA read request processing module includes a DMA read request FIFO allocated to each read request source, a read request arbitration unit, and a DMA read control unit. The DMA read request FIFO is used to buffer read requests initiated by the network protocol processing component. The read request arbitration unit is used to determine whether each read request FIFO has the processing conditions based on available credit and whether there is a read-write conflict, and to poll and arbitrate the read request FIFOs that meet the conditions to determine the DMA read requests to be processed. When the DMA read control unit detects the read request channel ready signal, it receives and parses the DMA read request determined by the read arbitration unit, transmits the corresponding DMA read request information to the protocol conversion module, and receives its response data. After sending the response data back to the corresponding read request source, the DMA transaction processing module performs credit reclamation and resource release operations.

3. The DMA communication device for a converged computing architecture according to claim 2, characterized in that, The DMA write control unit has built-in write request receive counter and write request send counter to control the execution order between DMA read requests and DMA write requests. The value of the write request receive counter, wreq_count, is used to record the number of write requests initiated by the network protocol processing unit. This counter increments whenever the DMA write control unit receives a new write request. The value of the write request send counter, wsent_count, represents the number of write requests that have completed data transmission. This counter increments after each write request is sent to the protocol conversion module. When the DMA read request processing module receives a new read request, it merges the current write request receive counter value, wreq_count, with the read request value and stores the result in the corresponding DMA read request FIFO. During the arbitration phase, the read request arbitration unit compares the value of the write request receive counter wreq_count carried in the read request with the value of the write request send counter wsent_count of the current DMA write control unit to determine whether there are any pending write requests before the read request: if the value of the write request send counter wsent_count is greater than or equal to the value of the write request receive counter wreq_count, it means that all write requests received before the read request have been sent to the protocol conversion module, and there is no read-write conflict, so the read request can be processed; otherwise, the read request is not processed for the time being.

4. The DMA communication device for a converged computing architecture according to claim 3, characterized in that, The read request arbitration unit is used to determine whether each read request FIFO has the conditions for processing based on available credits and whether there is a read-write conflict. The criteria for determining whether each read request FIFO has the conditions for processing include: (1) the read request FIFO of the request source is not empty and there are unprocessed read requests; (2) the reserved credits of the request source have not been exhausted or the total credit resources used have not reached the system limit; (3) there is no situation where "write first, read later" is incorrectly processed as "read first, write later".

5. The DMA communication device for a converged computing architecture according to claim 1, characterized in that, The protocol conversion module's operational state transition comprises four stages: initial state (IDLE), address resolution state (ADDR_PARSE), data transmission state (DATA_XFER), and response adaptation state (RESP_ADAPT). After power-on reset, the protocol conversion module is in the initial state (IDLE), waiting for a DMA request signal. Upon detecting a DMA read / write request enable signal, the module enters the address resolution state (ADDR_PARSE) to complete the AXI request conversion. In the address resolution state (ADDR_PARSE), the DMA request conversion unit caches DMA read request information and converts the DMA read / write request into an AXI read / write request. Simultaneously, it generates AXI address information, calculates the AXI bit width and Burst, and generates a byte valid signal. After conversion, the module enters the data transmission state (DATA_XFER) to implement... The DMA data conversion and transmission process is as follows: In the data transmission state DATA_XFER, the DMA data conversion unit buffers the DMA request data and performs endianness conversion based on the request type: If it is a write request, the protocol conversion module waits for the DMA write data to be valid, stores the DMA write request data in the data FIFO, performs endianness conversion, and sends it to the AXI interface; if it is a read request, the protocol conversion module waits for the AXI read data feedback to be valid, performs endianness conversion, and stores it in the data FIFO; after the transmission is completed, the protocol conversion module enters the response adaptation state RESP_ADAPT to provide feedback on the processing status of the DMA request; in the response adaptation state RESP_ADAPT, the protocol conversion module generates an AXI response request signal, parses the DMA processing result, and feeds it back to the DMA transaction processing module, then returns to the initial state IDLE.

6. A converged computing chip, comprising a computing unit, an on-chip network (NoC), a DMA communication device, and a network protocol processing unit connected in sequence, characterized in that, The DMA communication device is the DMA communication device for computing-network converged computing architecture as described in any one of claims 1 to 5.

7. A method for operating a DMA communication device, characterized in that, The DMA communication device is the DMA communication device for a converged computing architecture as described in any one of claims 1 to 5. The working method includes a request conversion unit performing DMA request conversion: including AXI transaction request generation, address information conversion, AXI Burst length calculation, and write byte valid signal generation. When the network protocol processing unit initiates a DMA transaction request, if it is a read request, the request conversion unit caches the read request in a read request FIFO and then converts it into an AXI read request in sequence; if it is a write request, the request conversion unit performs the conversion directly. Then, the request conversion unit sends the converted AXI read / write request to the CPU and performs address information conversion operation simultaneously. During address information conversion, the request conversion unit maps the DMA request address to the AXI physical address and generates a write byte valid signal for the write request. The AXI interface data width is 256 bits, and the offset of the DMA write request address is represented by ADDR[4:0]. The request conversion unit determines and generates the corresponding byte valid signal based on whether the address is aligned. For the case of address alignment, if the total data length... If the data length is less than or equal to 32 bytes, a single-cycle byte valid signal is generated based on the data length; if it exceeds 32 bytes, the first few cycles in Burst mode are all valid, and the last cycle generates a corresponding byte valid signal based on the remaining data length; however, for cases of address misalignment, if the total data length... If the value is less than or equal to 32-ADDR[4:0], then a single-byte valid signal is generated by combining the address offset and the data length; if the total data length is... If the data exceeds 32-ADDR[4:0], the first clock cycle generates a partial byte valid signal based on the address offset, the middle clock cycles are all valid, and the last clock cycle generates a corresponding byte valid signal based on the remaining data length. When calculating the AXI Burst length, the request conversion unit calculates the AXI Burst length based on the data length requested by the DMA, and its calculation function expression is: in, The length of the AXI Burst. Total data length Offset of the write request address for DMA. This is the floor operator.

8. The method of operating the DMA communication device according to claim 7, characterized in that, It also includes a data conversion unit performing DMA data conversion: upon receiving a DMA data enable signal, the data conversion unit buffers the DMA write request data into the data FIFO and initiates an AXI write data request. Simultaneously, the data conversion unit performs endianness conversion and uses a counter to count the amount of data transmitted to ensure data transmission accuracy. If the length of the data to be transmitted is less than the data bus width, the data conversion unit sets the last data signal to be valid, notifying the CPU that data transmission has ended. During DMA read request processing, upon receiving an AXI read response data enable signal, the data conversion unit performs endianness conversion on the response data and buffers the converted DMA response data into the data FIFO. If the length of the data to be transmitted is less than the data bus width, the data conversion unit sets the last data signal to be valid, notifying the network protocol processing unit that data transmission has ended.

9. The method of operating the DMA communication device according to claim 8, characterized in that, It also includes a state transition unit performing DMA state transitions: during write request processing, after the write data request is answered, the state transition unit waits for the data transmission to complete, and then converts the AXI write request response into a DMA transaction processing state. During read request processing, at the same time as the AXI read data feedback ends, the AXI response request is parsed into a DMA transaction processing state, which includes success or failure.

Images