Circuits, methods, and systems for equalizing voltages of memory cells

Abstract

The invention relates to circuits, methods and systems for equalizing voltages of series connected memory cells (BTs). The circuit corresponds to a trapezoidal network, in which horizontal switches (SH) form crosspieces of the ladder, a storage unit (BT) is arranged between each crosspiece on a first vertical bar of the ladder, and a vertical switch (SV) is arranged between each crosspiece on a second vertical bar of the ladder. By switching the horizontal switch (SH) and the vertical switch (SV), a single memory cell (BT) can be connected with the equalization source (SY) such that the equalization source adjusts the voltage of the connected memory cell (BT), thereby equalizing the voltage of the memory cells (BT) in the series circuit.

Description

Technical Field

[0001] The present invention relates to circuits, methods and systems for equalizing voltages of memory cells. Background Art

[0002] To operate electric boat drives, electrical energy is typically stored in electrochemical battery cells. These battery cells are typically combined and connected in various configurations to achieve not only the desired electrical performance parameters, such as the desired terminal voltage and capacitance of the current storage device, but also to take into account structural requirements via a corresponding form factor. Other parameters for designing and constructing the current storage device include environmental conditions, such as the available charging infrastructure or the typical ambient temperature.

[0003] In battery technology, a distinction is made between different structural storage units. The basic unit is always a battery cell—a distinction is made between cylindrical cells, prismatic cells, and pouch cells. A battery module can be a series and / or parallel connection of battery cells, wherein a battery module typically includes, in addition to the mechanical structure and contacting of the battery cells, also sensor systems for monitoring the battery cells. A battery can be a series and / or parallel connection of battery modules and, in addition to the mechanical structure, also include temperature control and contacting. A battery pack can include a plurality of batteries connected in series and / or in parallel.

[0004] In battery modules used in the maritime sector, efforts are generally made to select the number of battery cells so that the characteristic voltage value corresponds to a protective low voltage range. The protective low voltage is a voltage that is low enough to prevent a user from receiving an electric shock if accidentally touched.

[0005] When using lithium-ion cells, a typical battery module consists of 6 cells for a 24V battery or 12 cells for a 48V battery. When using lithium iron phosphate cells, due to the lower cell voltage, 7 cells are usually used for a 24V battery and 14 cells for a 48V battery.

[0006] The same current flows through the battery cells connected in series in a module. Since the battery cells have different internal resistances and capacitances, despite the same current flow during charging and discharging, different terminal voltages (current not equal to zero) and subsequently different open-circuit voltages occur both dynamically (current greater than or less than zero) and then statically (current equal to zero).

[0007] If the internal resistance of the battery cells exhibits a temperature dependency, different heating of the individual battery cells can also lead to different states of charge of these battery cells or to different battery cell voltages.

[0008] Voltage differences between battery cells cannot be detected based on the external voltage of the battery module, as the battery module only outputs the total voltage of all connected battery cells. Therefore, reliable and efficient operation of the battery module requires voltage synchronization of the battery cells. With reliable voltage synchronization of the battery cells, the battery module can be charged to a multiple of the battery cell charge cut-off voltage corresponding to the number of battery cells connected in series, or discharged to a similar multiple of the battery cell discharge cut-off voltage, without damaging the individual battery cells.

[0009] If, on the other hand, synchronous operation of the battery cells' voltages is not ensured, individual battery cells can be overcharged or deeply discharged, depending on the operating mode, while the battery module voltage remains constant, while other battery cells remain within the permissible voltage range.

[0010] At least the battery cell voltages must be monitored for consistency within a permissible tolerance range to prevent damage to the battery cells. This task is typically undertaken by a battery management system (BMS) located in the corresponding battery. High-performance BMSs compensate for the different voltages of the battery cells within a battery module connected in series using active or passive balancing. However, it should be taken into account that with passive balancing, for example by connecting a resistor in parallel to one or more battery cells with excessive voltage, only very low discharge powers can be achieved due to space limitations, so the balancing process can potentially take several days.

[0011] In contrast, active balancing, which can extract energy from individual battery cells using clock circuits and supply it to other battery cells, is very cost-intensive and involves space disadvantages.

[0012] In batteries, the equalization of the cell voltages is normally organized across modules, so that even at a battery voltage of approximately 400 V (96 cells connected in series or 8 modules with 12 cells each), all battery cells move within a narrow tolerance of the cell voltage.

[0013] However, for achieving a system power of several hundred kilowatts, a voltage of 400 V is not optimal. For example, efforts are made to double the system voltage, for example by connecting two 400 V batteries in series.

[0014] In this case, balancing between the battery cells of different batteries cannot be achieved by a corresponding internal BMS provided in the battery. Therefore, there is a need for balancing at the system level or for a universal circuit for balancing the voltages of the storage cells. Summary of the Invention

[0015] Based on the known prior art, the object of the present invention is to provide an improved circuit for equalizing the voltage of memory cells, as well as a corresponding method and a corresponding system.

[0016] This object is achieved by a circuit for equalizing the voltage of a storage cell having the features of the invention. Advantageous developments are apparent from the description and the drawings.

[0017] Correspondingly, a circuit for equalizing voltages of memory cells is proposed, the circuit comprising N memory cells BT(1), ..., BT(N), where N is a natural number greater than or equal to 2, where 1<=i<=N, and each memory cell BT(i) having a first electrode and a second electrode. The N memory cells are connected in series such that the second electrode of the i-th memory cell BT(i) is connected to the first electrode of the i+1-th memory cell BT(i+1).

[0018] The circuit further includes N+1 horizontal switches SH(1), ..., SH(N+1) and N vertical switches SV(1), ..., SV(N). The first electrode of the i-th storage cell BT(i) is detachably connected to the vertical switch SV(i) via the first horizontal switch SH(i). The second electrode of the i-th storage cell BT(i) is detachably connected to the vertical switch SV(i) via the second horizontal switch SH(i+1). The first horizontal switch SH(i) and the second horizontal switch SH(i+1) are detachably connected via the vertical switch SV(i).

[0019] The circuit further includes a balancing source having a first terminal and a second terminal. The first terminal of the balancing source is detachably connected to the first terminal of the first storage unit BT(1) via a first horizontal switch SH(1). The second terminal of the balancing source is detachably connected to the second terminal of the last storage unit BT(N) via a last horizontal switch SH(N+1).

[0020] The i-th storage unit BT(i) is connected to the balanced source by closing the horizontal switches SH(i) and SH(i+1), and by closing all the vertical switches SV(1),...,SV(i-1),SV(i+1),...,SV(N).

[0021] The voltage of the i-th memory cell BT(i) is thereby adjusted, thereby equalizing the voltages of the memory cells BT(1), . . . , BT(N).

[0022] In other words, the circuit proposed here can be understood as a type of ladder network, wherein the horizontal switches form the rungs of the ladder and a storage unit is respectively arranged between the rungs on the first vertical rod of the ladder and a vertical switch is respectively arranged between the rungs on the second vertical rod.

[0023] The first rod is connected to an electrical consumer, such as an electric motor or a heating device, via the first pole of the first storage cell and the last pole of the last storage cell. Since the storage cells are connected in series, the voltages of the individual storage cells are added.

[0024] By operating the horizontal switch, a specific pole of the storage unit can be connected to the opposite vertical rod of the ladder. Finally, the specific pole of the storage unit can be connected to the equalization source via the vertical switch.

[0025] For example, a 1600 Vdc network can be generated by connecting four 400 Vdc storage cells in series. Thus, a scalable circuit for equalizing the voltages of the storage cells can be provided, particularly for local current storage cells in which a different number of storage cells is provided depending on the storage requirements.

[0026] In the present invention, the first pole may be a positive pole of a storage unit or a balancing source and the second pole may be a negative pole of the storage unit or the balancing source.

[0027] Switches SV(1), ..., SV(N), SH(1), ..., SH(N) may be bidirectionally interruptible.

[0028] A switch that, in the off state, allows no current flow in both directions is bidirectionally disconnectable.

[0029] In this way, an undesired current flow from the balancing source to the storage cell or from the storage cell to the balancing source can be effectively suppressed.

[0030] At least one of the switches SV(1), ..., SV(N), SH(1), ..., SH(N) may be a mechanical switch. In this case, bidirectional disconnectability is also ensured by mechanical separation of the ladder.

[0031] At least one of the switches SV( 1 ), . . . , SV(N), SH( 1 ), . . . , SH(N) may be an anti-series arrangement of two transistors, in particular MOSFETs.

[0032] In power transistors, a parasitic diode is created between the source and drain terminals due to its structural design, which allows current to flow in the conduction direction of the parasitic diode even in the off state. In reverse-conducting IGBTs (Insulated-Gate Bipolar Transistor – Bipolar transistor), this diode is inserted as an additional "die" between the emitter and collector terminals. If two such power transistors are connected in anti-series, the diodes also have an anti-parallel conduction direction. In this case, current flow is effectively suppressed in the off state. By connecting the gate terminals simultaneously, the two transistors are connected simultaneously, allowing current to flow.

[0033] The aforementioned object is also achieved by a simplified circuit for equalizing the voltage of storage cells having the features of the invention. Advantageous developments of the method are apparent from the present description and the accompanying drawings.

[0034] Accordingly, a simplified circuit for equalizing the voltage of storage cells is proposed, which includes K first storage cells BT(1,1), ..., BT(K,1) and K second storage cells BT(1,2), ..., BT(K,2). For all j=1, ..., K, the following applies:

[0035] Each of the memory cells BT(j, 1) and BT(j, 2) has a first electrode and a second electrode. The first memory cell BT(j, 1) and the second memory cell BT(j, 2) are connected in series in pairs, such that the second electrode of the first memory cell BT(j, 1) is connected to the first electrode of the second memory cell BT(j, 2). The paired series-connected memory cells BT(j, 1) and BT(j, 2) form a 2S-KP network.

[0036] Furthermore, the circuit includes K first vertical switches SV(1,1), ..., SV(K,1) and K second vertical switches SV(1,2), ..., SV(K,2), as well as a first diode and a second diode. Here, for all j=1, ..., K, the following applies:

[0037] The first electrode of the first storage unit BT(j, 1) is connected to the cathode of the first diode. The anode of the first diode is detachably connected to the second electrode of the first storage unit BT(j, 1) via the first vertical switch SV(j, 1). The second electrode of the second storage unit BT(j, 2) is connected to the anode of the second diode. The cathode of the second diode is detachably connected to the first electrode of the second storage unit BT(j, 2) via the second vertical switch SV(j, 2).

[0038] Furthermore, the circuit includes a balancing source having a first pole and a second pole, wherein the first pole of the balancing source is connected to the anode of the first diode and wherein the second pole of the balancing source is connected to the cathode of the second diode, wherein the first pole is the positive pole of the storage unit and the balancing source and the second pole is the negative pole of the storage unit and the balancing source.

[0039] For all j=1, ..., K, the second storage cell BT(j,2) is connected to the equalization source (SY) by closing the first vertical switch SV(j,1), or the first storage cell BT(j,1) is connected to the equalization source (SY) by closing the second vertical switch SV(j,2). This adjusts the voltage of the second storage cell BT(j,2) or the first storage cell BT(j,1), thereby equalizing the voltages of the storage cells.

[0040] For the case K=1, a particularly simple circuit results, wherein the indices are then reduced from BT(1,1) and BT(1,2) to BT(1) and BT(2).

[0041] In the present case, the current direction is predetermined by the arrangement of the diodes and the balancing source. In particular, this makes it possible to dispense with horizontal switches. The voltage of the individual storage cells is adjusted solely via a single vertical switch.

[0042] If the battery cell BT(j,k) acts as a sink and the balancing source acts as a source, the vertical switch of the simplified circuit can be unidirectionally interruptible.

[0043] The first diode and the second diode predetermine the direction of the current in the circuit, so that the switch only has to limit the current flow in one direction, thereby further simplifying the circuit.

[0044] However, if the balanced source is to operate as a sink, the vertical switch must be bidirectionally interruptible.

[0045] At least one of the vertical switches may be a mechanical switch, which can cut off current in both directions and thus reliably cut off current flow in one direction.

[0046] At least one of the vertical switches can be a transistor, in particular a MOSFET. MOSFETs are unidirectionally switchable, just like IGBTs with anti-parallel diodes. This allows a single transistor to replace the vertical switch in a simplified circuit. This simplifies the circuit and, in particular, makes it mechanically more stable, since only one circuit of the switch can be implemented.

[0047] In both conventional and simplified circuits, each storage unit can be a battery, a battery module, or a battery cell.

[0048] The storage cell may be based on or contain iron phosphate. The storage cell may be based on or contain lithium ions. However, the storage cell may also include a solid electrolyte.

[0049] Each storage cell may have a voltage of 400 Vdc. In particular, an 800 Vdc system may be provided by using two 400 Vdc storage cells.

[0050] The balancing source can be supplied potential-free from the series circuit of the storage cells. Thus, the entire series and parallel circuit or the entire battery pack can supply energy to the balancing source.

[0051] The balancing source can be fed from one of the storage cells of the series circuit or from an external energy source, in particular from a power grid. For example, the balancing source can be fed from the storage cell with the highest voltage.

[0052] The above-mentioned object is also achieved by a method for equalizing the voltage of a storage cell having the features of the invention. Advantageous developments of the method are apparent from the present description and the accompanying drawings.

[0053] Accordingly, a method for equalizing the voltages of storage cells is proposed. The method involves one of the aforementioned circuits or simplified circuits. In a first method step, at least one storage cell to be regulated is determined by a management system. In a second method step, the storage cell to be regulated is connected to an equalization source. This adjusts the voltage of the at least one storage cell to be regulated, thereby equalizing the voltages of the storage cells.

[0054] The management system is configured to measure the voltages of various storage cells. By comparing the measured voltages, the storage cell whose voltage must be adjusted can be determined. The management system is also configured to switch corresponding switches in the circuit so that the storage cell to be adjusted is connected to the equalization source.

[0055] The memory cell to be adjusted may be the memory cell with the highest voltage or the lowest voltage.

[0056] This allows for voltage equalization by adjusting the storage cells with extreme voltage values, thereby achieving a more uniform voltage distribution overall and thus voltage equalization.

[0057] For example, the second method step can also consist in adjusting the voltage of the storage cell having the lowest voltage and subsequently adjusting the voltage of the storage cell having the highest voltage, or vice versa.

[0058] The voltage level of the equalization source can be adapted to the voltage of the storage cell to be regulated.

[0059] For example, the voltage of the balancing source can be adapted to the charge cutoff voltage of the smallest cell to be balanced, ie the battery voltage, module voltage or cell voltage. The method can be implemented in such a way that voltage balancing can be adjusted in any desired charge state of the series circuit of storage cells.

[0060] The voltage of the memory cell may be adjusted via the CCCV method.

[0061] In the CCCV method, in a first phase, the voltage of the memory cell is adjusted via a constant current (“constant current”, CC). In a further phase, the voltage of the memory cell is adjusted via a constant voltage (“constant voltage”, CV).

[0062] After completing the voltage equalization of at least one storage cell to be regulated, the storage cell can be disconnected from the equalization source, thereby interrupting the voltage regulation. In particular, the voltage change can also be monitored by the management system to compare the expected voltage of the storage cell with the actual voltage.

[0063] The balancing source may have a balancing current regulating device which is configured to regulate the balancing current to zero before one of the switches is opened. This prevents current flow before the switch is opened.

[0064] For example, the equalization of the voltages of the storage cells can be terminated when the relative voltage difference of the storage cells is less than 10%, in particular less than 1%.

[0065] The relative voltage difference can be characterized in particular by the quotient of the maximum voltage and the minimum voltage. However, it is also possible to determine the relative voltage difference based on the median voltage or the average voltage.

[0066] The above-mentioned object is also achieved by a system for equalizing the voltage of storage cells having the features of the invention. Advantageous developments of the method are apparent from the present description and the accompanying drawings.

[0067] Accordingly, a system for equalizing voltages across storage cells is provided. The system includes at least two storage cells, a voltage equalization source, and at least one management system. The storage cells are connected in series, wherein the storage cells are detachably connected to the voltage equalization source. According to the present invention, the storage cells are detachably connected to the voltage equalization source via one of the aforementioned circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Advantageous further embodiments of the present invention are explained in detail by the following description of the drawings. Here, the following is shown:

[0069] Figure 1A 、 Figure 1B A circuit diagram showing a circuit according to the present invention;

[0070] Figure 2 A circuit diagram showing the arrangement of MOSFETs;

[0071] Figure 3 A circuit diagram showing a simplified circuit according to the present invention in a 2S-1P configuration;

[0072] Figure 4 a circuit diagram showing a simplified circuit according to the present invention in a 2S-KP configuration; and

[0073] Figure 5 A further circuit diagram shows a simplified circuit according to the invention in a 2S-KP configuration. DETAILED DESCRIPTION

[0074] In the following, preferred embodiments are described with reference to the accompanying drawings. In the different drawings, identical, similar or identically acting elements are provided with the same reference numerals, and a repeated description of the elements is partially omitted in order to avoid redundancy.

[0075] Figure 1A A first aspect of the proposed circuit is shown. One embodiment of a circuit for equalizing the voltages of storage cells is shown, which are in the form of batteries BT(1) to BT(N), where N is greater than or equal to 2. Each of the batteries BT(1) to BT(N) shown has a first pole and a second pole, where, for example, the first pole is a positive pole (+) and the second pole is a negative pole (-).

[0076] Batteries BT(1), ..., BT(N) are connected in series so that the second terminal (negative terminal) of the i-th battery BT(i) is connected to the first terminal (positive terminal) of the i+1-th battery BT(i+1). For example, the negative terminal (-) of the first battery BT1 is connected to the positive terminal (+) of the second battery BT2.

[0077] The series circuit of batteries BT(1), ..., BT(N) which together form a battery pack or battery system can be connected, for example, to an electric motor M. Alternatively to the electric motor M, other electrical consumers, such as a heating device, can also be connected. Alternatively to the electrical consumers, an energy source, such as a charging device, can also be connected.

[0078] However, the circuit proposed here can be operated independently of the connected electrical consumers.

[0079] The circuit includes N+1 horizontal switches SH(1), ..., SH(N+1) and N vertical switches SV(1), ..., SV(N). The first electrode of the i-th battery BT(i) can be detachably connected to the vertical switch SV(i) via the first horizontal switch SH(i). The second electrode of the i-th battery BT(i) can be detachably connected to the vertical switch SV(i) via the second horizontal switch SH(i+1). The first horizontal switch SH(i) and the second horizontal switch SH(i+1) can be detachably connected to each other via the vertical switch SV(i).

[0080] Overall, this results in a ladder-shaped arrangement, wherein the rungs of the ladder are horizontal switches SV(1), ..., SV(N+1). On the first vertical leg of the ladder, between the rungs, there are batteries BT(1), ..., BT(N). On the second vertical leg of the ladder, between the rungs, there are vertical switches SV(1), ..., SV(N).

[0081] In order to achieve balancing of the battery cells of the batteries BT(1), ..., BT(N), a balancing source SY is provided. A first terminal of the balancing source SY is detachably connected to a first terminal of the first storage unit BT(1) via a first horizontal switch SH(1). A second terminal of the balancing source SY is detachably connected to a second terminal of the Nth storage unit BT(N) via a last horizontal switch SH(N+1).

[0082] To charge or discharge a specific battery BT(i), the corresponding battery BT(i) is connected to the balancing source SY. To do this, the horizontal switches SH(i) and SH(i+1) are closed, as well as all vertical switches SV(1), ..., SV(i-1), SV(i+1), ..., SV(N).

[0083] exist Figure 1B How to charge the battery BT(2) is shown as an example. For example, the battery BT(2) has the highest voltage or the lowest voltage of all batteries and must be charged or discharged accordingly in order to change the voltage and thus balance the battery system.

[0084] In order to change the voltage BT(2) of the storage cell, the adjacent horizontal switches SH(2) and SH(3) must be closed. Similarly, the vertical switches SV(1), SV(3), ..., SV(N) must be closed. This ensures that the current from the balancing source SY flows exclusively through the battery BT(2). With the aid of adjusted voltage values ​​of SY, in particular higher voltage values, multiple batteries can also be recharged or discharged simultaneously. Thus, only one battery or a maximum of N batteries can be recharged or discharged together. However, only batteries that are directly connected to one another in direct sequence, i.e., without switches, can be recharged together.

[0085] Generally speaking, it is possible to Figure 1A For the topology, in order to change the voltage of the i-th battery BT(i), it is necessary to close the horizontal switches SH(i) and SH(i+1) and all vertical switches except the switch SV(i).

[0086] If the battery BT needs to be able to be charged and discharged individually, it is advantageous if all horizontal and vertical switches are bidirectionally disconnectable. For example, mechanical switches are bidirectionally disconnectable.

[0087] When using power semiconductors instead of mechanical switches, an anti-series circuit may be necessary to ensure bidirectional disconnection. If a MOSFET is used as the power semiconductor, it may have a parasitic anti-parallel diode, for example, which prevents disconnection in the diode's forward direction. Consequently, the MOSFET is not bidirectionally disconnectable, but only unidirectionally.

[0088] Figure 2 A possible equivalent circuit for a bidirectionally disconnectable switch based on a first MOSFET Q1 and a second MOSFET Q2 is shown. Here, the source terminals S and base terminals B of the two MOSFETs are connected to each other. This prevents a current from flowing from the source terminal S to the drain terminal D. Current flow is therefore only possible when current is supplied to the gate terminal G. The following circuit has the same effect, in which the drains of the MOSFETs are connected to each other and the sources of the MOSFETs form the connection points for the connected circuits.

[0089] exist Figure 3 A circuit for equalizing the voltages of the two storage cells BT1 and BT2 is shown in FIG. The circuit is derived from the simplified circuit described above for the case K=1.

[0090] If it is assumed that only the voltage of the battery with the lowest energy needs to be increased, the circuit of FIG. 1 can be significantly simplified.

[0091] A simplified circuit for equalizing voltages of memory cells includes a first memory cell BT (1) and a second memory cell BT (2), wherein each of the two memory cells BT (1) and BT (2) has a first electrode (+) and a second electrode (-). The first memory cell BT (1) and the second memory cell BT (2) are connected in series such that the second electrode of the first memory cell BT (1) is connected to the first electrode of the second memory cell BT (2).

[0092] Furthermore, the simplified circuit includes a first vertical switch SV(1) and a second vertical switch SV(2), and a first diode D1 and a second diode D2.

[0093] A first electrode of the first storage cell BT(1) is connected to a cathode of a first diode D1, wherein an anode of the first diode D1 is detachably connected to a second electrode of the first storage cell BT(1) via a first vertical switch SV(1).

[0094] The second electrode of the second storage unit BT(2) is connected to the anode of the second diode D2, wherein the cathode of the second diode D2 is detachably connected to the first electrode of the second battery BT(2) via the second vertical switch SV(2).

[0095] The first electrode of the balancing source SY is connected to the anode of the first diode D1 and the second electrode of the balancing source SY is connected to the cathode of the second diode D2. The first electrode is the positive electrode of the battery BT and the balancing source SY and the second electrode is the negative electrode of the battery BT and the balancing source SY.

[0096] First, as can be compared to FIG1 , the horizontal switches SH(1) and SH(N+1) in the outermost rung of the ladder circuit can be replaced by the first diode D1 and the second diode D2. If only unidirectionally blocked vertical switches are implemented, the circuit is limited to charging one or more cells of the battery via the balancing source SY. Discharging one or more cells via the balancing source SY is not possible in this manner.

[0097] The first diode D1 and the second diode D2 are arranged in a forward direction with respect to the balancing source SY. At the same time, the first diode D1 is arranged in a reverse direction with respect to the first battery BT(1), and the second diode D2 is arranged in a reverse direction with respect to the second battery BT(2).

[0098] By replacing the switches with diodes, the control complexity of the circuit can be reduced.

[0099] Since only two batteries are installed and the current direction of the balancing source SY is predetermined, it is possible to completely omit the horizontal switch SH compared to FIG. 1 .

[0100] Figure 3 The recharging of the battery BT (2) is also schematically shown, which can be achieved by closing the switch SV (1). If the battery BT1 needs to be recharged, SV (1) must be opened and SV (2) must be closed.

[0101] Figure 4The general case of a simplified circuit for a 2S-KP configuration is shown. The simplified circuit for equalizing the voltage of a battery BT includes K first batteries BT(1,1), ..., BT(K,1) and K second batteries BT(1,2), ..., BT(K,2). For all j = 1, ..., K, each of the batteries BT(j,1) and BT(j,2) has a first electrode and a second electrode. The first battery BT(j,1) and the second battery BT(j,2) are connected in series in pairs, such that the second electrode of the first battery BT(j,1) is connected to the first electrode of the second battery BT(j,2). The paired series-connected batteries BT form a 2S-KP network.

[0102] The circuit also includes K first vertical switches SV(1,1), ..., SV(K,1) and K second vertical switches SV(1,2), ..., SV(K,2), as well as a first diode D1 and a second diode D2. For all j = 1, ..., K, the first electrode of the first battery BT(j,1) is connected to the cathode of the first diode. The anode of the first diode is detachably connected to the second electrode of the first battery BT(j,1) via the first vertical switch SV(j,1). The second electrode of the second battery BT(j,2) is connected to the anode of the second diode. The cathode of the second diode is detachably connected to the first electrode of the second battery BT(j,2) via the second vertical switch SV(j,2).

[0103] Furthermore, the circuit includes a balancing source SY having a first pole and a second pole, wherein the first pole of the balancing source SY is connected to the anode of the first diode, and wherein the second pole of the balancing source SY is connected to the cathode of the second diode, wherein the first pole is the positive pole of the storage unit and the balancing source SY and the second pole is the negative pole of the storage unit and the balancing source SY.

[0104] For all j=1, ..., K, the second battery BT(j,2) is connected to the balancing source (SY) by closing the first vertical switch SV(j,1), or the first battery BT(j,1) is connected to the balancing source SY by closing the second vertical switch SV(j,2). This adjusts the voltage of the second battery BT(j,2) or the first battery BT(j,1), thereby balancing the voltages of the batteries BT.

[0105] K two-stage battery branches with associated switching half-bridges can be managed with the aid of a balancing source SY and two diodes D1 , D2 .

[0106] To this end, K two-stage battery branches BT(j, 1) and BT(j, 2) are connected in parallel. Similarly, the corresponding branches of the series-connected vertical switches SV(j, 1) and SV(j, 2) are connected in parallel. Finally, the parallel-connected battery branches and vertical switch branches are connected to the first and second diodes and the balancing source SY in the manner and method described above.

[0107] Figure 5 Show Figure 4 An equivalent circuit in which the switch of the circuit is replaced by a unidirectionally interruptible switch Q. Because the switch must interrupt current in only one direction, it is feasible to use any switch that can block voltage in one direction. For example, a MOSFET can be used as a replacement for the switch.

[0108] The circuit shown can be used to perform a method for balancing (not shown). The management system can be configured to measure the voltages of individual cells and determine the cell to be regulated. Finally, the cell to be regulated can be connected to a balancing source SY via a switch controlled by the management system, allowing the voltage of the cell to be regulated to be regulated. If the voltage of the cell to be regulated is within a predetermined tolerance range, the cell to be regulated can be disconnected from the balancing source SY. After voltage regulation, for example, the difference between the cell with the highest voltage and the cell with the lowest voltage is smaller, thereby balancing the cell voltages.

[0109] As far as applicable, all individual features shown in the exemplary embodiments may be combined with one another and / or interchanged without departing from the scope of the present invention.

[0110] Reference Signs List

[0111] BT storage unit

[0112] D diode

[0113] Q MOSFET / Power Transistor

[0114] SY equalization source

[0115] SH level switch

[0116] SV vertical switch

Claims

1. A circuit for equalizing the voltage of a memory cell, The circuit comprises N storage units BT(1), ..., BT(N), Where N is greater than or equal to 2, Each memory cell BT(i) has a first electrode and a second electrode. The N memory cells are connected in series so that the second electrode of the i-th memory cell BT(i) is connected to the first electrode of the i+1-th memory cell BT(i+1), The circuit further comprises N+1 horizontal switches SH(1), ..., SH(N+1) and N vertical switches SV(1), ..., SV(N), The first electrode of the i-th storage unit BT(i) is detachably connected to the vertical switch SV(i) via the first horizontal switch SH(i). The second electrode of the i-th storage unit BT(i) is detachably connected to the vertical switch SV(i) via the second horizontal switch SH(i+1). The first horizontal switch SH(i) and the second horizontal switch SH(i+1) are connected via The vertical switches SV(i) are detachably connected to each other, The circuit further includes a balancing source (SY) having a first pole and a second pole, wherein the first electrode of the equalizing source (SY) is detachably connected to the first electrode of the first storage unit BT(1) via the first horizontal switch SH(1), The second electrode of the balancing source (SY) is detachably connected to the second electrode of the Nth storage unit BT(N) via the last horizontal switch SH(N+1), wherein The i-th storage unit BT(i) is connected to the equalization source (SY) by closing the horizontal switches SH(i) and SH(i+1), and by closing all vertical switches SV(1) to SV(i-1) and SV(i+1) to SV(N), The voltage of the i-th memory cell BT(i) is thereby adjusted, thereby balancing the voltages of the memory cells BT(1), ..., BT(N).

2. The circuit according to claim 1, wherein: The switches SV(1), ..., SV(N), SH(1), ..., SH(N) are bidirectionally interruptible.

3. The circuit according to claim 1 or 2, characterized in that At least one switch SV(1), ..., SV(N), SH(1), ..., SH(N) is a mechanical switch or At least one switch SV( 1 ), . . . , SV(N), SH( 1 ), . . . , SH(N) is an anti-series arrangement of two transistors, in particular MOSFETs.

4. A circuit for equalizing the voltage of a memory cell (BT), The circuit comprises K first memory cells BT(1,1), ..., BT(K,1) and K second memory cells BT(1,2), ..., BT(K,2), wherein for all j=1, ..., K: Each first memory cell BT(j,1) and each second memory cell BT(j,2) has a first pole and a second pole, The first storage unit BT(j, 1) and the second storage unit BT(j, 2) are connected in series in pairs, so that the second electrode of the first storage unit BT(j, 1) is connected to the first electrode of the second storage unit BT(j, 2). The memory cells BT(j,1) and BT(j,2) connected in series in pairs form a 2S-KP network. The circuit further comprises K first vertical switches SV(1,1), ..., SV(K,1) and K second vertical switches SV(1,2), ..., SV(K,2), and a first diode (D1) and a second diode (D2), wherein for all j=1, ..., K: The first electrode of the first storage unit BT(j,1) is connected to the cathode of the first diode (D1), The anode of the first diode (D1) is detachably connected to the second electrode of the first storage unit BT(j,1) via the first vertical switch SV(j,1). The second electrode of the second storage unit BT(j,2) is connected to the anode of the second diode (D2). The cathode of the second diode (D2) is detachably connected to the first electrode of the second storage unit BT(j,2) via the second vertical switch SV(j,2). The circuit further includes a balancing source (SY) having a first pole and a second pole, wherein the first electrode of the balancing source (SY) is connected to the anode of the first diode (D1) and The second electrode of the balancing source (SY) is connected to the cathode of the second diode (D2), The first electrode is the positive electrode of the storage unit (BT) and the balancing source (SY) and the second electrode is the negative electrode of the storage unit (BT) and the balancing source (SY), wherein For all j=1,…,K: Connecting the second storage unit BT(j,2) to the equalization source (SY) by closing the first vertical switch SV(j,1), or By closing the second vertical switch SV(j,2), the first storage unit BT(j,1) is connected to the equalization source (SY), Thus, the voltage of the second storage unit BT(j, 2) or the first storage unit BT(j, 1) is adjusted. The voltages of the storage cells (BT) are thereby equalized.

5. The circuit according to claim 4, characterized in that The vertical switch (SV) is at least unidirectionally interruptible.

6. The circuit according to claim 4 or 5, characterized in that At least one of the vertical switches (SV) is a mechanical switch, or At least one of the vertical switches (SV) is a transistor, in particular a MOSFET.

7. The circuit according to any one of the preceding claims, characterized in that Each storage unit (BT) is a battery or a battery module or a battery cell.

8. The circuit according to any one of the preceding claims, characterized in that The memory cell (BT) is based on or contains iron phosphate or is based on a solid electrolyte.

9. The circuit according to any one of the preceding claims, characterized in that Each memory cell (BT) has a voltage of 400 Vdc.

10. The circuit according to any one of the preceding claims, characterized in that The equalizing source (SY) is supplied potential-free from the series circuit of the storage cells (BT), or The balancing source (SY) is fed from one of the storage cells (BT) of the series circuit or from an external energy source, in particular from a grid.

11. The circuit according to any one of the preceding claims, characterized in that The balancing source (SY) comprises a balancing current regulating device configured to regulate the balancing current to zero before opening one of the switches.

12. A method for equalizing the voltage of a storage cell (BT) by means of a circuit according to any one of claims 1 to 3 or by means of a circuit according to any one of claims 4 to 6, In a first step, at least one storage unit (BT') to be adjusted is determined with the aid of the management system. In a second step, the at least one storage cell (BT') to be adjusted is connected to the equalization source (SY), thereby adjusting the voltage of the at least one storage cell (BT') to be adjusted, thereby equalizing the voltages of the storage cells (BT).

13. The method according to claim 12, characterized in that The voltage level of the equalization source (SY) is matched to the voltage (BT') of the memory cell to be adjusted.

14. The method according to any one of claims 12 or 13, characterized in that The memory cell to be adjusted (BT') is a memory cell having the highest voltage or the lowest voltage.

15. The method according to any one of claims 12 to 14, characterized in that The voltage of the memory cell (BT') to be adjusted is adjusted via a CCCV method.

16. The method according to any one of claims 12 to 15, characterized in that After the equalization of the voltage of the at least one memory cell (BT') to be regulated has been completed, the memory cell is disconnected from the equalization source (SY).

17. The method according to claim 16, characterized in that The equalization of the voltages of the storage cells (BT) is terminated when the relative voltage differences of the storage cells (BT) are less than 10%, in particular less than 1%.

18. The method according to any one of claims 12 to 17, characterized in that A maximum of N storage cells (BT) are recharged together, wherein the storage cells (BT) are directly connected to one another in an electrically direct sequence.

19. A system for equalizing the voltage of a storage unit (BT), the system comprising at least two storage units (BT), a voltage equalization source (SY) and at least one management system, wherein the storage unit (BT) and the equalization source (SY) are detachably connected by means of a circuit according to any one of claims 1 to 11, wherein the management system is configured to determine the voltage of a single said storage cell (BT), The management system is configured to connect the storage unit (BT') to be adjusted to the equalization source (SY).

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