An instruction processing method and device, an electronic device, and a readable storage medium

Abstract

Embodiments of the present application provide an instruction processing method and device, electronic equipment and readable storage medium, relating to the technical field of computer. In the method, n instructions are selected from an instruction stream as to-be-decoded instructions of a current round, and the to-be-decoded instructions are decoded by using n decoding units to obtain a microinstruction sequence; n is an integer not less than 2. According to the input width of a renaming unit, the microinstructions in a preset cache and the microinstructions in the microinstruction sequence are delivered to the renaming unit; the preset cache is used to store the microinstructions not delivered in the last round. The microinstructions not delivered in the microinstruction sequence are written into the preset cache. n instructions are reselected from the instruction stream as to-be-decoded instructions of a next round, and the step of decoding the to-be-decoded instructions by using the n decoding units is continued to be executed until a stop condition is reached, so that the decoding throughput and decoding efficiency can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of computer, in particular to an instruction processing method and device, electronic equipment and readable storage medium. BACKGROUND

[0002] In the instruction processing process, there is a step of decoding instructions. After decoding instructions, microinstructions are obtained, and the microinstructions are transmitted to a renaming unit for renaming operation, and then executed in subsequent steps.

[0003] In the prior art, after decoding a piece of instruction and transmitting the microinstructions obtained by decoding the instruction to the renaming unit, the next instruction decoding is started. In this way, the instruction decoding efficiency is low, and the decoding throughput is low.

[0004] The number of microinstructions obtained by decoding different instructions is different, which leads to the decoding throughput of the instruction decoding stage being not fixed, and the stable decoding throughput cannot be guaranteed. SUMMARY

[0005] Embodiments of the present application provide an instruction processing method and device, electronic equipment and readable storage medium, which can solve the problem of low instruction decoding efficiency and low decoding throughput.

[0006] To solve the above problem, an instruction processing method is disclosed in embodiments of the present application, and the method comprises:

[0007] n instructions are selected from an instruction stream as to-be-decoded instructions of a current round, and n decoding units are used to decode the to-be-decoded instructions to obtain a microinstruction sequence; n is an integer not less than 2;

[0008] According to the input width of the renaming unit, the microinstructions in a preset buffer and the microinstructions in the microinstruction sequence are transmitted to the renaming unit; the preset buffer is used to store the microinstructions not transmitted in the last round;

[0009] The microinstructions not transmitted in the microinstruction sequence are written into the preset buffer, n instructions are reselected from the instruction stream as to-be-decoded instructions of a next round, and the step of decoding the to-be-decoded instructions by using n decoding units is returned until a stop condition is reached.

[0010] On the other hand, an instruction processing device is disclosed in embodiments of the present application, and the device comprises:

[0011] A first processing module is configured to select n instructions from an instruction stream as to-be-decoded instructions of a current round, and decode the to-be-decoded instructions by using n decoding units to obtain a microinstruction sequence; n is an integer not less than 2;

[0012] a delivery module configured to deliver, according to an input width of the renaming unit, microinstructions in a preset buffer and microinstructions in the microinstruction sequence to the renaming unit; the preset buffer is configured to store microinstructions not delivered in a previous round;

[0013] a writing module configured to write, to the preset buffer, microinstructions not delivered in the microinstruction sequence;

[0014] a second processing module configured to reselect n instructions from the instruction stream as to-be-decoded instructions in a next round, and return to the step of decoding the to-be-decoded instructions by using the n decoding units until a stop condition is reached.

[0015] In yet another aspect, an electronic device is disclosed, which includes a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is configured to store executable instructions, and the executable instructions cause the processor to execute the foregoing method.

[0016] The embodiment of the present application also discloses a readable storage medium, which stores executable instructions, and when executed by one or more processors, causes the processor to execute the method as described above.

[0017] The embodiment of the present application includes the following advantages: the instruction processing method provided by the embodiment of the present application selects n instructions from an instruction stream as to-be-decoded instructions in a current round, and decodes the to-be-decoded instructions by using n decoding units to obtain a microinstruction sequence; n is an integer not less than 2. According to an input width of a renaming unit, microinstructions in a preset buffer and microinstructions in the microinstruction sequence are delivered to the renaming unit; the preset buffer is configured to store microinstructions not delivered in a previous round. Microinstructions not delivered in the microinstruction sequence are written to the preset buffer. n instructions are reselected from the instruction stream as to-be-decoded instructions in a next round, and the step of decoding the to-be-decoded instructions by using the n decoding units is executed until a stop condition is reached. In this way, decoding n instructions each time can improve the number of microinstructions in the microinstruction sequence obtained in the current round, so that sufficient microinstructions can be delivered to the renaming unit, thereby improving decoding throughput and decoding efficiency.

[0018] And each time according to the input width of the renaming unit, the microinstruction is transmitted to the renaming unit, that is, the input width of the microinstruction is transmitted to the renaming unit each time, avoiding single instruction decoding, decoding throughput is not fixed, and the problem of stable decoding throughput cannot be guaranteed. At the same time, by introducing a preset cache, the microinstruction not transmitted in the last round is stored, and the microinstruction in the preset cache is transmitted to the renaming unit in the current round, so that for the microinstruction in the last round which is limited by the input width and cannot enter the renaming stage, the microinstruction in the preset cache does not need to be re-decoded, that is, these microinstructions can be transmitted to the renaming unit in the current round, thereby improving the overall processing efficiency to a certain extent. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] Figure 1 is a step flow chart of an instruction processing method provided by the embodiments of the present application;

[0021] Figure 2 is a re-decoding judgment flow chart provided by the embodiments of the present application;

[0022] Figure 3 is a related diagram of the number of microinstructions provided by the embodiments of the present application;

[0023] Figure 4 is another related diagram of the number of microinstructions provided by the embodiments of the present application;

[0024] Figure 5 is a processing process diagram provided by the embodiments of the present application;

[0025] Figure 6 is another processing process diagram provided by the embodiments of the present application;

[0026] Figure 7 is another processing process diagram provided by the embodiments of the present application;

[0027] Figure 8 is a diagram of an initial one-hot encoding shown by the embodiments of the present application;

[0028] Figure 9 is a selection diagram provided by the embodiments of the present application;

[0029] Figure 10is a schematic diagram of instruction processing shown by an embodiment of the present application;

[0030] Figure 11 is a schematic diagram of microinstruction delivery provided by an embodiment of the present application;

[0031] Figure 12 is a block diagram of an instruction processing device provided by an embodiment of the present application;

[0032] Figure 13 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0034] First, the application scenarios involved in the embodiments of the present application are described. In the process of processing instructions of the network on chip, instructions are fetched first, and then decoded. Fetching instructions refers to the process of obtaining instructions from the memory. Decoding refers to the process of analyzing and translating the instructions obtained in the instruction fetching stage into control signals required for instruction scheduling and execution. Decoding throughput refers to the number of microinstructions actually processed per cycle, that is, the number of microinstructions actually delivered to the renaming unit. The instruction processing method provided by the embodiments of the present application can be applied to the vector instruction extension instruction set (RVV). The RVV includes vector addition instructions, vector subtraction instructions, vector multiplication instructions, vector division instructions, bitwise logical operation instructions, comparison instructions, shift instructions, maximum and minimum value instructions, data shuffle instructions, and reduction instructions. The instructions in the RVV have the characteristic that the vector configuration is not encoded in the vector instruction. The instructions in the RVV use an independent vector configuration instruction to set the vector configuration register (VTYPE CSR). The vector configuration instruction is an instruction used to set the vector configuration, for example, the VSETVL, VSETVLI, and VSETIVLI instructions. The vector configuration register is a register defined in the RVV to control the vector configuration. The VTYPE register includes a vector length multiplier (LMUL) field and a selected element width (SEW) field.

[0035] Wherein, LMUL and SEW are both 3 bits, SEW is used to specify the bit width of the operand of the vector instruction, and LMUL is used to specify the number of vector registers of the operand of the vector instruction. Taking the vector addition instruction vadd.vv v4, v8, v12 as an example, when LMUL = 4, the vadd.vv v4, v8, v12 instruction requires to add the corresponding elements in the four pairs of vector registers v8-v11 and v12-v15 respectively, and write the result into the v4-v7 registers. That is, the vadd.vv v4, v8, v12 instruction when LMUL = 4 is equivalent to four instructions "vadd.vv v4, v8, v12", "vadd.vv v5, v9, v13", "vadd.vv v6, v10, v14" and "vadd.vv v7, v11, v15" when LMUL = 1. The larger LMUL is, the more micro-instructions obtained by decoding the instruction.

[0036] The prior art uses the way of "delay decoding", that is, decoding one by one. This design can only process one vector instruction at a time, and if there is an unprocessed instruction in the decoding stage, the decoding stage must be blocked. Until the instruction is completely split into micro-instructions and enters the renaming stage, the decoding stage can receive the next instruction that needs to be decoded. And each time only one instruction is processed, when the input width of the renaming unit is large, the number of micro-instructions generated is insufficient for the input width, which will cause that the renaming unit cannot be supplied with sufficient micro-instructions, and further cause that the decoding throughput when processing the instruction stream is low. And the decoding throughput of the decoding stage will change with the LMUL of the instruction, and the number of micro-instructions obtained by decoding different instructions is different, which causes that the decoding throughput of the instruction decoding stage is not fixed, and cannot guarantee stable decoding throughput.

[0037] Specifically, when LMUL is small, the number of generated micro-instructions is small, and correspondingly, the decoding throughput is low, which cannot support the decoding throughput required by a high-performance processor. The difficulty brought by LMUL to the design of high-performance vector micro-architecture is how to realize high-throughput instruction decoding, which becomes a technical problem to be solved urgently.

[0038] The instruction processing method provided by the embodiment of the application will be described in detail below.

[0039] Referring to Figure 1 , a step flow chart of an instruction processing method provided by an embodiment of the application is shown, as Figure 1 shown, the method can specifically include the following steps:

[0040] Step 101, selecting n instructions from an instruction stream as to-be-decoded instructions of a current round, and decoding the to-be-decoded instructions by using n decoding units to obtain a micro-instruction sequence; n is an integer not less than 2.

[0041] Step 102, delivering the micro-instructions in a preset buffer and the micro-instructions in the micro-instruction sequence to the renaming unit according to an input width of the renaming unit; the preset buffer is used to store the micro-instructions not delivered in the last round.

[0042] Step 103, writing the micro-instructions not delivered in the micro-instruction sequence to the preset buffer.

[0043] Step 104, reselecting n instructions from the instruction stream as the instructions to be decoded in the next round, and returning to the step of decoding the instructions to be decoded by the n decoding units until a stop condition is reached.

[0044] In the embodiment of the present application, the instructions included in the instruction stream are the instructions to be decoded, i.e., the pre-decoding instructions, and the instructions in the instruction stream can be represented as MOP (Macro Operation). The micro-instructions can also be referred to as instruction micro-operations. After decoding an instruction, at least one micro-instruction is generated, and the micro-instruction can be represented as UOP (Micro Operation). The n decoding units form a decoding unit group, the n decoding units are parallel decoding units, one decoding unit is one decode channel (Decode Channel), and the number n of the decoding units included in the decoding unit group is the decoding input width (MopWidth). MopWidth can be used to represent the maximum number of instructions that can be processed simultaneously by the decoding unit group. The first instruction in the n instructions enters the first decoding unit, and the subsequent instructions in the n instructions enter the subsequent decoding units of the first decoding unit in turn.

[0045] The input width of the renaming unit is the decoding output width (UopWidth), which refers to the maximum number of micro-instructions that can be output by the decoding unit group to the renaming unit. The specific values of the decoding input width and the decoding output width can be set according to actual conditions, and the embodiment of the present application does not limit this. Exemplarily, in one embodiment, MopWidth can be 8, and UopWidth can be 8. Further, the micro-instructions generated by all decoding units based on the instructions of the current round form the micro-instruction sequence of the current round. For any decoding unit, the specific implementation of decoding an instruction into a micro-instruction can refer to the existing manner, and the embodiment of the present application does not limit this.

[0046] The preset buffer can be represented as a DecodeBuffer, the preset buffer can be a storage unit, and the size (BufferSize) of the preset buffer can be set based on the UopWidth, where the size of the preset buffer is used to represent the maximum number of microinstructions that can be stored in the preset buffer. For example, the BufferSize can be smaller than the input width of the renaming unit, so that at least one microinstruction in the microinstruction sequence generated in the current round can be ensured to be delivered each time. The instruction stream includes a plurality of to-be-decoded instructions, and the instruction stream can include vector instructions. For example, the instruction stream is a mixed instruction stream including a plurality of scalar instructions and vector instructions, and the scalar instructions and vector instructions in the instruction stream can be arranged in any order. In an actual application scenario, the number of instructions included in the instruction stream is greater than n, and therefore, the processing of the instruction stream needs to be completed through multiple rounds. One round corresponds to one clock cycle, and every n instructions in the instruction stream are used as the input of one round, that is, n instructions in the instruction stream are processed in one round.

[0047] For example, it is assumed that the instruction stream includes 32 instructions: instruction 1 to instruction 32. In the first round, instructions 1 to 8 can be processed, in the second round, instructions 9 to 16 can be processed, in the third round, instructions 17 to 24 can be processed, and in the fourth round, instructions 25 to 32 can be processed. In this example, the first round is the first round, when the second round is entered, the current round is the second round, correspondingly, the last round is the first round, and the next round is the third round. When the third round is entered, the current round is the third round, correspondingly, the last round is the second round, and the next round is the fourth round. When the fourth round is entered, the current round is the fourth round, correspondingly, the last round is the third round. After the fourth round is completed, since there is no remaining instruction, if the preset buffer is currently empty, the processing flow is directly ended. If the preset buffer is not empty, the microinstructions in the preset buffer are delivered to the renaming unit in the next clock cycle (i.e., the next round), until the preset buffer is empty, and the processing flow is ended. That is, in the embodiment of the present application, the stop condition is preset, and the stop condition is that there is no remaining instruction in the instruction stream and the preset buffer is empty. In this way, it can be ensured that all the microinstructions decoded from the instructions in the instruction stream are delivered to the renaming unit. It should be noted that when there are less than n remaining instructions, all the remaining instructions can be used as the to-be-decoded instructions in the next round.

[0048] It can be understood that when the current round is the first round, there is no last round, and correspondingly, the preset buffer is empty at this time. Correspondingly, when the microinstructions in the preset buffer and the microinstructions in the microinstruction sequence are delivered to the renaming unit, the microinstructions delivered to the renaming unit in this time are all the microinstructions in the microinstruction sequence.

[0049] In the embodiment of the present application, the preset buffer is arranged to store the microinstructions completed in one round but limited by the input width of the renaming unit and unable to enter the renaming stage. In the current round, the microinstructions in the preset buffer are controlled to enter the renaming stage in advance, and the microinstructions in the microinstruction sequence generated in the current round are supplemented according to the input width of the renaming unit, so that the input width of the renaming unit in each round is determined, and the decoding throughput is fixed to the input width of the renaming unit. Of course, the microinstructions generated in the current round and not transmitted to the renaming unit are also written into the preset buffer, and after the next round is started, the current round becomes the last round, so that the preset buffer stores the microinstructions not transmitted in the last round.

[0050] In summary, in the instruction processing method provided by the embodiment of the present application, n instructions are selected from the instruction stream as the to-be-decoded instructions of the current round, and the n decoding units are used to decode the to-be-decoded instructions to obtain a microinstruction sequence; n is an integer not less than 2. According to the input width of the renaming unit, the microinstructions in the preset buffer and the microinstructions in the microinstruction sequence are transmitted to the renaming unit; the preset buffer is used to store the microinstructions not transmitted in the last round. The microinstructions not transmitted in the microinstruction sequence are written into the preset buffer. The n instructions are reselected from the instruction stream as the to-be-decoded instructions of the next round, and the step of decoding the to-be-decoded instructions by the n decoding units is continued to be executed until a stop condition is reached. In this way, the number of microinstructions in the microinstruction sequence obtained in each round is increased, so that sufficient microinstructions can be transmitted to the renaming unit, thereby improving the decoding throughput and the decoding efficiency.

[0051] Moreover, the microinstructions are transmitted to the renaming unit according to the input width of the renaming unit each time, that is, the input width of microinstructions is transmitted to the renaming unit each time, so that the decoding of a single instruction is avoided, the decoding throughput is not fixed, and the problem that the stable decoding throughput cannot be guaranteed is solved. Meanwhile, by introducing the preset buffer, the microinstructions not transmitted in the last round are stored, and the microinstructions in the preset buffer are continuously transmitted to the renaming unit in the current round, so that for the microinstructions limited by the input width and unable to enter the renaming stage in the last round, the instructions corresponding to the microinstructions in the preset buffer do not need to be redecoded, and these microinstructions can be transmitted to the renaming unit in the current round, thereby improving the overall processing efficiency to a certain extent.

[0052] Optionally, the step of transmitting the microinstructions in the preset buffer and the microinstructions in the microinstruction sequence to the renaming unit according to the input width of the renaming unit comprises the following steps:

[0053] Step 1021, taking the microinstruction in the preset cache as a first target microinstruction, and taking the first p-q microinstructions in the microinstruction sequence as second target microinstructions.

[0054] Step 1022, delivering the first target microinstruction and the second target microinstructions to the renaming unit; p is the input width, and q is the number of the first target microinstruction.

[0055] q represents the number of the microinstruction currently stored in the preset cache in the current round. The specific value of q can be different in different rounds. p-q represents the value of p minus q, and p represents the input width of the renaming unit, i.e., the decoding output width. Since at most p microinstructions are delivered to the renaming unit in each round, p-q microinstructions in the microinstruction sequence are supplemented, i.e., the first target microinstruction and the second target microinstructions (the first p-q microinstructions in the microinstruction sequence) are delivered to the renaming unit, in the case of ensuring that the q microinstructions stored in the preset cache in the last round are all delivered in the current round.

[0056] In the embodiment of the application, the microinstruction in the preset cache is taken as the first target microinstruction, and the first p-q microinstructions in the microinstruction sequence are taken as the second target microinstructions. The first target microinstruction and the second target microinstructions are delivered to the renaming unit. In this way, p microinstructions can be delivered to the renaming unit in combination with the microinstruction sequence in the current round while ensuring that the microinstruction in the preset cache is delivered first each time, thereby ensuring the decoding throughput when processing the instruction stream.

[0057] Optionally, in the first implementation, the step of writing the undelivered microinstructions in the microinstruction sequence into the preset cache comprises:

[0058] Step 1031, starting from the first decoding unit in the n decoding units, sequentially adding the number of microinstructions generated by the decoding unit to q.

[0059] Step 1032, taking the instruction processed by the last decoding unit participating in the addition as the end instruction of the current round in the case that the addition value is not less than p.

[0060] Step 1033, writing the microinstruction corresponding to the end instruction of the current round in the remaining microinstructions in the microinstruction sequence into the preset cache.

[0061] The end instruction is an instruction corresponding to the last micro instruction in the first p-q micro instructions (i.e., the second target micro instruction). In this implementation, in the case where part of the micro instructions generated by an instruction are passed to the renaming unit, the micro instructions generated by the instruction that are not passed are written to the preset buffer. Since the preset buffer is essentially a storage unit, storing new data in the preset buffer will cause additional power consumption. Therefore, in this implementation, a more conservative approach is used. In the case where none of the micro instructions split from an instruction can enter the renaming stage in the current round, the micro instructions split from the instruction are not written to the preset buffer. The instruction continues to be decoded in the next round, which can reduce the power consumption of the decoding stage. In the case where part of the micro instructions split from an instruction can enter the renaming stage, the remaining micro instructions that cannot enter the renaming stage are written to the preset buffer. This allows the instructions from which part of the micro instructions enter the renaming stage to not be stored and re-decoded in the decoding stage, avoiding the situation where too many micro instructions are split from an instruction and block the decoding unit. Accordingly, in this implementation, the BufferSize can be one less than the maximum number of micro instructions split from a single instruction, for example, BufferSize is 7. This ensures that the preset buffer can meet the storage requirements.

[0062] Specifically, the number of microinstructions calculating components can be set in parallel for the n decoding units to calculate the number of microinstructions obtained by decoding the instructions of each decoding unit, i.e., the number of microinstructions generated by each decoding unit. The number of microinstructions generated by the decoding units is added to q in turn according to the preset order of the decoding units. After each addition, it is detected whether the added value satisfies the condition of being not less than p. If yes, the addition operation is stopped, indicating that the instructions processed by the decoding unit added this time may have some microinstructions that cannot enter the renaming stage. Therefore, the instructions processed by the decoding unit added this time, i.e., the instructions processed by the last decoding unit added, are taken as the end instructions of the current round. Assuming that p is 8, there is 1 microinstruction in the preset cache in the current round, i.e., q = 1, and decoding units 1-8 decode instructions 4, instructions 5, instructions 6, instructions 7, instructions 8, instructions 9, instructions 10, and instructions 1, respectively. The number of microinstructions generated by decoding units 1-8 is 1, 4, 4, 1, 1, 1, 1, and 1, respectively. After the first addition, the added value is 2, and since the added value is less than 8, the addition is continued. After the second addition, the added value is 6, and the addition is continued. After the third addition, the added value is 10, and the added value satisfies the condition of being not less than 8, and the addition is ended. The instructions processed by the last decoding unit added (instructions 6) are taken as the end instructions of the current round. In this way, it is equivalent to completing the processing of all the microinstructions generated by the decoding units whose first microinstruction in the generated microinstructions has an order number less than p in the current round. For the non-first decoding unit, the order number of the first microinstruction in the generated microinstructions is q + the number of microinstructions generated by all the decoding units before the decoding unit + 1.

[0063] Figure 2is a re-decoding judgment flow schematic diagram provided by the embodiment of the present application. Specifically, the instruction processing device further comprises a second selection unit, i.e., BufferSelector. The second selection unit calculates the sequence number of the first microinstruction in the microinstruction generated by each decoding unit. Specifically, the number of microinstructions generated by each decoding unit is received. The second selection unit starts from 1, first adds the number of microinstructions in the preset buffer q to obtain the sequence number of the first microinstruction in the microinstruction generated by the first decoding unit. Then, the number of microinstructions generated by the first decoding unit is continuously added to obtain the sequence number of the first microinstruction in the microinstruction generated by the second decoding unit. In this way, when the cumulative value is greater than p, the counting is ended. Alternatively, the sequence number of the first microinstruction in the microinstruction generated by all decoding units is directly calculated. The instruction processed by the last decoding unit whose sequence number of the first microinstruction is not greater than p is taken as the end instruction. For the above example, the sequence numbers of the first microinstruction in the microinstruction generated by each decoding unit are 2, 3, 7, 11, 12, 13, 14, and 15 respectively. Among them, the sequence numbers of the first microinstruction of the first three decoding units are not greater than p, and thus the instruction (instruction 6) processed by the third decoding unit is taken as the end instruction. For the instruction processed by the decoding unit whose sequence number of the first microinstruction is not greater than p, the processing in the current round is completed, and there is no need to re-enter the decoding stage in the next round. For the instruction processed by the decoding unit whose sequence number of the first microinstruction is greater than p, the instruction re-enters the decoding stage in the next round. For the above example, the processing of the first three instructions is completed in the current round, and the remaining five instructions re-enter the decoding stage in the next round. It should be noted that the embodiment of the present application does not limit the algorithm and circuit for how the instruction enters the decoding stage before the decoding stage.

[0064] In the embodiment of the present application, for the instruction which does not need to re-enter the decoding stage in the next round, the instruction completes the entering of the decoding unit to the entering of the microinstruction into the renaming stage or the preset buffer in the current round, i.e., from the entering of the instruction into the decoding unit to the entering of the generated microinstruction into the renaming stage or the preset buffer, only one clock cycle is used to complete, and thus this implementation manner is more efficient and can improve the performance of the decoding stage.

[0065] Further, if the cumulative value is equal to p when the cumulative operation is ended, it is indicated that there is no instruction with only part of the microinstruction entering the renaming stage in the current round, and the microinstruction corresponding to the end instruction of the current round in the remaining microinstructions in the microinstruction sequence (i.e., the microinstruction except the second target microinstruction in the microinstruction sequence) is empty, i.e., the microinstruction written into the preset buffer in the current round is empty. If the cumulative value is greater than p when the cumulative operation is ended, it is indicated that there is an instruction with only part of the microinstruction entering the renaming stage in the current round, and there is at least one microinstruction corresponding to the end instruction of the current round in the remaining microinstructions in the microinstruction sequence, i.e., at least one microinstruction is written into the preset buffer in the current round.

[0066] Optionally, the step of reselecting n instructions from the instruction stream as instructions to be decoded in the next round comprises:

[0067] Step 1041, taking the next instruction of the end instruction in the instruction stream as the start instruction of the next round.

[0068] Step 1042, selecting n continuous instructions starting from the start instruction as instructions to be decoded in the next round.

[0069] Specifically, for each round, at most n continuous instructions are read from the instruction stream as instructions to be decoded in the round. Specifically, for the next round of the current round, the instruction fetching starts from the next instruction of the end instruction of the current round. For example, assuming that the end instruction of the current round is instruction 6, then the next round can obtain 8 instructions after instruction 6 in the instruction stream as instructions to be decoded in the next round, and the processing of the next round is started. In this way, it can be ensured that each round starts from the subsequent instruction of the instruction that has been processed in the previous round, thereby avoiding missing instructions.

[0070] Optionally, the step of decoding the instructions to be decoded by using n decoding units can comprise:

[0071] Step 1011, for any decoding unit, processing the instruction input into the decoding unit by using the decoding unit to obtain the micro-instruction corresponding to the instruction.

[0072] The embodiment of the present application can further comprise: step S31, taking the number of micro-instructions corresponding to the instructions as a first number, if the first number is not a preset fixed number, determining the fixed number with the smallest difference from the first number as a target number; adding invalid micro-instructions to the micro-instructions corresponding to the instructions to make the first number reach the target number.

[0073] The invalid micro-instruction refers to a decoding bubble. The decoding bubble refers to a bubble output by a decoding stage and is not a valid micro-instruction. Specifically, the first quantity can be made to reach the target quantity by inserting a bubble instruction (NOP). The quantity of micro-instructions corresponding to the instruction (the first quantity) is the quantity of micro-instructions generated by the decoding unit when processing the instruction. If the quantity of micro-instructions is a preset fixed quantity, no decoding bubble needs to be added. If the quantity of micro-instructions is not a preset fixed quantity, a decoding bubble is added to make the quantity of micro-instructions generated by each decoding unit reach one of the preset fixed quantities. In this way, by constraining the quantity of micro-instructions generated by each decoding unit to be a preset fixed quantity, the input value of an addition circuit that implements a related accumulation operation in a hardware circuit is constrained to be one of the fixed quantities, which can greatly reduce the implementation complexity of the addition circuit used to implement the accumulation operation. At the same time, the fixed quantity with the smallest difference from the first quantity is determined as the target quantity, which can minimize the quantity of invalid micro-instructions that need to be inserted and avoid the problem of frequent decoding bubbles.

[0074] The preset fixed quantity can be set in advance according to actual conditions, and embodiments of the present application do not limit this. For example, several commonly used quantities can be set as fixed quantities. In this way, for instructions whose quantity of micro-instructions obtained after processing is not a fixed quantity, a decoding bubble is added to the micro-instructions generated for the instruction to reach a commonly used quantity. For example, the preset fixed quantity can include 1, 2, 4, and 8, that is, the quantity of micro-instructions finally generated by each decoding unit is constrained to be one of 1, 2, 4, and 8. In embodiments of the present application, the instruction processing apparatus can further include a micro-instruction Selector (first selection unit). The input of the first selection unit and the second selection unit including a plurality of addition circuits is only 1, 2, 4, and 8, for example, the input of eight of the nine 4-bit addition circuits is only these four values, and the input value of the remaining addition circuits can cover the quantity of micro-instructions that can be included in the preset cache. In this way, compared with an addition circuit that supports more numerical input values, for example, an addition circuit that supports 0-8 arbitrary value input, the circuit area is smaller, the area overhead of the hardware circuit is smaller, and the timing is better. The first selection unit and the second selection unit can use a shorter logic gate level to implement the selection logic of the micro-instruction.

[0075] In the embodiment of the present application, when the to-be-decoded instruction is input, the corresponding vector configuration information (VTYPE information) is also input synchronously, which is used to guide the processing of the vector instruction. The VTYPE information is configured only at one instruction in the to-be-decoded instruction, and the VTYPE information can be used for subsequent instructions until the VTYPE information is modified. The VTYPE information in the vector configuration instruction is extracted and efficiently and correctly propagated to each instruction in the instruction stream before the instruction stream enters the decoding stage. The embodiment of the present application does not limit this.

[0076] Figure 3 is a schematic diagram of the number of microinstructions provided by the embodiment of the present application, as shown in Figure 3 For a decoding unit, the number of microinstructions generated by the decoding unit based on the input instruction and the vector configuration information is one of 1, 2, 4, or 8. It is assumed that the instruction processed by the decoding unit is: vluxseg7ei8.v, Figure 4 is another schematic diagram of the number of microinstructions provided by the embodiment of the present application, as shown in Figure 4 7 microinstructions are generated: microinstruction 0~microinstruction 6. Therefore, 1 decoding bubble can be used to fill the end of the microinstruction sequence generated by the decoding unit, so that the number of microinstructions generated by the decoding unit in the current round is 8.

[0077] Taking n as 8, that is, including 8 decoding units as an example, the following Table 1 illustrates how the multi-channel decoding unit decodes the instruction sequence in the assembly code.L10:

[0078]

[0079] Table 1

[0080] In the table,.L10 represents the label of the instruction sequence, e32, m4, ta, ma represents the vector configuration information. Specifically, e32, m4, ta, ma are all vector configuration information, which correspond to SEW, LMUL, Vector Tail Agnostic (VTA), and Vector Mask Agnostic (VMA) in VTYPE. SEW and LMUL are related to instruction splitting, and VTA and VMA are independent of instruction splitting. VTA is used to indicate the processing mode of the tail elements in the target vector register, and VMA is used to indicate the processing mode of the elements masked by the mask in the target vector register. In this example, m4 is used to indicate that the LMUL used by the subsequent instruction is set to 4.

[0081] Assuming that instruction 10 always jumps in this example, that is, instructions 1 to 10 are executed in a loop in the instruction stream, the instruction stream can be regarded as: instruction 1, instruction 2, ... instruction 10, instruction 1, instruction 2, ... instruction 10, instruction 1, instruction 2, ...

[0082] Let ij denote the j-th microinstruction derived from the i-th instruction. Figure 5 This is a schematic diagram of a processing procedure provided by an embodiment of the present invention, such as... Figure 5 As shown, at time T, there are 0 microinstructions in the preset cache, and instructions 1-8 enter the decoding stage. After decoding, instructions 1-3 are processed in the current round. Instructions 1 and 2 generate a total of 5 microinstructions, all of which enter the renaming stage. Of the 4 microinstructions generated by instruction 3, only the first 3 can enter the renaming stage, and the remaining 1 microinstruction enters the preset cache. Because all the microinstructions split from instruction 4 cannot enter the renaming stage, the preset cache does not receive the microinstructions split from instruction 4, and instructions 4-8 re-enter the decoding stage in the next round. It should be noted that in this embodiment of the invention, after the microinstructions in the preset cache are passed to the renaming unit in the current round, the preset cache is cleared, and then the operation of writing the unpassed microinstructions in the current round's microinstruction sequence to the preset cache is performed. Alternatively, a counter can be set for the preset cache to represent the number of valid microinstructions in the preset cache, and microinstructions exceeding the counter position (i.e., microinstructions in the preset cache that have been passed to the renaming unit in the current round) can be determined as invalid microinstructions. In each round, only valid microinstructions from the preset cache are passed.

[0083] Next, proceed to the next round (at time T+1). Figure 6 This is a schematic diagram of another processing procedure provided by an embodiment of the present invention, such as... Figure 6 As shown, at time T+1, there is one microinstruction (microinstruction 3.4) in the preset cache. Instructions 4-10 and instruction 1 enter the decoding stage. After decoding, instructions 4-6 are processed in the current round (at time T+1), generating a total of 9 microinstructions. The one microinstruction in the preset cache, and all microinstructions corresponding to instructions 4 and 5 respectively, enter the renaming stage. The first two microinstructions of instruction 6 enter the renaming stage, and the last two microinstructions enter the preset cache. Instructions 7-10 and instruction 1 re-enter the decoding stage in the next round.

[0084] Then, the next round will continue (at time T+2). Figure 7 This is a schematic diagram of another processing procedure provided by an embodiment of the present invention, such as... Figure 7As shown, at T+2 time, there are 2 microinstructions (microinstruction 6.3 and microinstruction 6.4) in the preset cache, instructions 7~10 and instructions 1~4 enter the decoding stage, after decoding, instructions 7~10 and instructions 1~2 complete processing in the current round (at this time, the current round is T+2 time), and 9 microinstructions are generated in total. The 2 microinstructions in the preset cache, the 5 microinstructions generated by instructions 7~10 and instructions 1, and the first 1 microinstruction generated by instruction 2 enter the renaming stage, and the last 3 microinstructions generated by instruction 2 enter the preset cache. And continue to start the next round.

[0085] It should be noted that in the embodiment of the application, the preset cache can also not be set, the input width of the renaming unit is increased, all microinstructions in the microinstruction sequence of the current round are transmitted to the renaming unit, and the decoding throughput is improved. Further, only part of the decoding units can be provided with the ability to process instructions that need to be split. Among them, the instructions that need to be split refer to the instructions that generate at least two microinstructions, and the instructions that do not need to be split refer to the instructions that generate only one microinstruction. Accordingly, when n instructions are input, the vector instructions in the n instructions are input to the decoding unit with the ability to process instructions that need to be split. Alternatively, all decoding units are provided with the ability to process instructions that need to be split, so that the input of each decoding unit can be any scalar instruction and vector instruction.

[0086] In the embodiment of the application, by using multiple parallel decoding units, the function of decoding multiple instructions at the same time is realized, and the decoding throughput of the decoding unit is increased. And each time p microinstructions are selected, the problem that the decoding throughput of the decoding stage changes with LMUL is solved. And for the instruction stream mixed with instructions that need to be split and instructions that do not need to be split, n instructions are input to the decoding unit each time, and the microinstructions generated by other instructions can be filled before and after the microinstructions generated by one instruction, to ensure that the microinstructions obtained in the current round can provide sufficient microinstructions for the renaming unit, thereby improving the processing efficiency of the instruction stream and the decoding throughput of the instruction stream. When the decoding output width is large, the decoding and splitting of the mixed instruction stream are efficiently supported.

[0087] Optionally, in the second implementation manner, the step of writing the microinstructions in the microinstruction sequence that are not transmitted into the preset cache can include:

[0088] In step 1034, the first r microinstructions in the remaining microinstructions in the microinstruction sequence are determined as microinstructions to be written; and the r is the size of the preset cache.

[0089] In step 1035, the instruction corresponding to the last microinstruction in the to-be-written microinstruction is taken as a target instruction, and if the to-be-written microinstruction includes all microinstructions corresponding to the target instruction, the to-be-written microinstruction is written into the preset cache.

[0090] In step 1036, if the to-be-written microinstruction does not include all microinstructions corresponding to the target instruction, the microinstructions other than the microinstruction corresponding to the target instruction in the to-be-written microinstruction are written into the preset cache.

[0091] In this implementation, the BufferSize of DecodeBuffer is expressed by r, which can be greater than the maximum number of microinstructions split from a single instruction, thereby ensuring that the preset cache can store more microinstructions. In this way, when the remaining microinstructions are written into DecodeBuffer, the last microinstruction written into DecodeBuffer is ensured to be the last microinstruction of the instruction in the case of writing as many microinstructions as possible into DecodeBuffer.

[0092] Specifically, the first r microinstructions in the remaining microinstructions in the microinstruction sequence can be taken as to-be-written microinstructions. The instruction corresponding to the last microinstruction in the to-be-written microinstruction is taken as a target instruction, which refers to the instruction from which the last microinstruction is obtained after decoding. Based on the constraint that the last microinstruction written into DecodeBuffer is the last microinstruction of the instruction, if the to-be-written microinstruction includes all microinstructions corresponding to the target instruction, it is indicated that the last microinstruction in the to-be-written microinstruction is the last microinstruction of the target instruction, and thus the to-be-written microinstruction can be directly written into the preset cache. Conversely, if the to-be-written microinstruction does not include all microinstructions corresponding to the target instruction, it is indicated that the last microinstruction in the to-be-written microinstruction is not the last microinstruction of the target instruction, and the to-be-written microinstruction includes part of the microinstructions of the target instruction. Therefore, only the microinstructions other than the microinstruction corresponding to the target instruction in the to-be-written microinstruction can be written into the preset cache. In this way, the problem of wasting processing resources can be avoided by avoiding writing part of the microinstructions split from an instruction, continuing to decode the instruction in the next round, and generating microinstructions repeated with the microinstructions in the preset cache.

[0093] Exemplarily, assuming r is 10, corresponding to the round of T moment in the above example, the first r microinstructions in the remaining microinstructions are: microinstruction 3.4, microinstruction 4.1, microinstruction 5.1-microinstruction 5.4, microinstruction 6.1-microinstruction 6.4, since the first r microinstructions include all microinstructions corresponding to the target instruction (instruction 6). Therefore, the microinstruction 3.4, microinstruction 4.1, microinstruction 5.1-microinstruction 5.4, microinstruction 6.1-microinstruction 6.4 are written into the preset cache. Assuming r is 9, corresponding to the round of T moment in the above example, the first r microinstructions in the remaining microinstructions are: microinstruction 3.4, microinstruction 4.1, microinstruction 5.1-microinstruction 5.4, microinstruction 6.1-microinstruction 6.3, since the first r microinstructions do not include all microinstructions corresponding to the target instruction (instruction 6). Therefore, the microinstruction 3.4, microinstruction 4.1, microinstruction 5.1-microinstruction 5.4 are written into the preset cache.

[0094] Optionally, the step of reselecting n instructions from the instruction stream as instructions to be decoded in the next round can comprise:

[0095] In step 1043, the instruction corresponding to the last microinstruction written into the preset cache is taken as the end instruction of the current round.

[0096] In step 1044, the next instruction of the end instruction in the instruction stream is taken as the start instruction of the next round.

[0097] In step 1045, n continuous instructions starting from the start instruction are selected as instructions to be decoded in the next round.

[0098] Corresponding to the second implementation, the last microinstruction written into the preset cache is taken as the end instruction of the current round. Exemplarily, corresponding to the above example in which r is 10, instruction 6 can be taken as the end instruction, and accordingly, n instructions after instruction 6 are selected. Corresponding to the above example in which r is 9, instruction 5 can be taken as the end instruction, and accordingly, n instructions after instruction 5 are selected as instructions to be decoded in the next round, and the processing of the next round is started. In this way, it can be ensured that each round starts from the subsequent instruction of the instruction processed in the last round, thereby avoiding instruction omission.

[0099] Optionally, the step of delivering the first target microinstruction and the second target microinstruction to the renaming unit comprises:

[0100] Step 1022a, any one of the first target microinstruction and the second target microinstruction is taken as a first microinstruction, a first selection signal of the first microinstruction is generated by a first selection unit based on an order of the first microinstruction in a target sequence; the target sequence includes the first target microinstruction and the microinstruction sequence, and the first target microinstruction in the target sequence is located before the microinstruction sequence;

[0101] Step 1022b, the first selection signal is executed to select the first microinstruction and deliver to the renaming unit.

[0102] In the embodiment of the application, the target sequence can be obtained according to the two rules that the microinstruction in the preset cache is arranged before the microinstruction sequence of the current round and the microinstructions output by the plurality of decoding units are sequentially arranged (for example, sequentially arranged according to the order of the encoding of the decoding unit from small to large). In the embodiment of the application, by setting the first selection unit, the first selection signal of the first microinstruction is generated by the first selection unit based on the order of the first microinstruction in the target sequence, and the first microinstruction that needs to be delivered to the renaming unit can be conveniently selected by executing the first selection signal.

[0103] The first selection unit is a microinstruction Selector, and the first selection signal can be a one-hot encoding of the first microinstruction, that is, a one-hot code signal. Specifically, in the initial one-hot encoding corresponding to the sequence number of the first microinstruction in the target sequence, the bit representing the actual source of the first microinstruction is set to 1 to obtain the first selection signal of the first microinstruction. That is, the selection signal represented by the initial one-hot encoding after the setting is taken as the first selection signal of the first microinstruction. One of the bits in the initial one-hot encoding corresponding to the sequence number of the first microinstruction in the target sequence represents a source corresponding to the microinstruction of the sequence number. The initial one-hot encoding can be set to all 0s by default. The sequence number of the microinstruction in the target sequence indicates the number of the microinstruction in the target sequence, that is, the order of the microinstruction in the target sequence. For example, the sequence number of the xth microinstruction in the target sequence is x. Specifically, due to the above two rules and the rule that each decoding unit splits a fixed number of microinstructions, the possible source of each microinstruction in the target sequence is fixed. The source of the microinstruction is related to the sequence number of the microinstruction. For example, p=8, the first target microinstruction and the second target microinstruction that need to be delivered to the renaming unit in the current round are the first 8 microinstructions in the target sequence.

[0104] According to the three rules that the number of microinstructions split from each decoding unit is 1, 2, 4, 8, the microinstructions in the preset cache are arranged in front of the microinstruction sequence of the current round, and the microinstructions output by the decoding units in the microinstruction sequence of the current round are arranged in sequence, 8 microinstructions transmitted to the renaming unit can be obtained, i.e. the source represented by each bit in the initial one-hot encoding of the 1st microinstruction to the 8th microinstruction. Assuming that the size of the preset cache is 7, no. 1, no. 2, …, no. 7 represent the 1st microinstruction, the 2nd microinstruction, …, the 7th microinstruction in the preset cache respectively, and a decoding unit includes 8 ports (port): port 1~port 8, one port can output one microinstruction, and the yth microinstruction generated by the decoding unit is generated by the yth port of the decoding unit. Figure 8 is a schematic diagram of an initial one-hot encoding shown by an embodiment of the present application, as Figure 8 shown, for the 1st microinstruction that needs to be transmitted to the renaming unit, the 1st microinstruction in the preset cache and the 1st microinstruction generated by the 1st decoding unit (corresponding to port 1 of decoding unit 1) can be selected, therefore, the initial one-hot encoding corresponding to the 1st microinstruction includes two bits corresponding to no. 1 of the preset cache and port 1 of decoding unit 1 respectively. For the 2nd microinstruction that needs to be transmitted to the renaming unit, the 2nd microinstruction in the preset cache, the 1st microinstruction and the 2nd microinstruction generated by the 1st decoding unit (corresponding to port 1 and port 2 of decoding unit 1) and the 1st microinstruction generated by the 2nd decoding unit (corresponding to port 1 of decoding unit 2) can be selected. Therefore, the initial one-hot encoding corresponding to the second microinstruction includes four bits corresponding to no. 2 of the preset cache, port 1 of decoding unit 1, port 2 of decoding unit 1 and port 1 of decoding unit 2 respectively. Wherein, port g of decoding unit f represents the gth port of the fth decoding unit, corresponding to the gth microinstruction generated by the instruction output into the decoding unit.

[0105] Similarly, for the zth microinstruction (z is less than or equal to 7) that needs to be passed to the renaming unit, the zth microinstruction can be selected from the zth microinstruction in the preset cache, the 1st microinstruction generated by the 1st decoding unit, the 2nd microinstruction, …, the zth microinstruction (corresponding to the ports 1~z of the decoding unit 1), the 1st microinstruction generated by the 2nd decoding unit, …, the z-1th microinstruction (corresponding to the ports 1~z-1 of the decoding unit 2), …, the 1st microinstruction generated by the zth decoding unit (corresponding to the port 1 of the decoding unit z). Therefore, the initial one-hot encoding corresponding to the zth microinstruction includes a plurality of bits corresponding to the preset cache, the ports 1~z of the decoding unit 1, the ports 1~z-1 of the decoding unit 2, …, the port 1 of the decoding unit z, respectively. For the 8th microinstruction that needs to be passed to the renaming unit, because the preset cache only has 7 items, the 8th microinstruction does not need to be selected from the preset cache. The 8th microinstruction can be selected from a total of 36 ports of the eight decoding units.

[0106] At the T time corresponding to the above example, the first selection signal generated by the first selection unit can include: 01 0001 0000010

[0110] … 000000000000000001000000000000000000

[0112] In the embodiment of the present application, one-hot encoding can be used as the selection signal, and the selection can be realized by combining the AND-OR combination circuit in the first selection unit. For the wth microinstruction in the target sequence, the initial one-hot encoding of the microinstruction can represent the alternative microinstruction sequence of the microinstruction. Wherein, all the bits in the initial one-hot encoding from the microinstruction represent the source microinstruction, which constitutes the alternative microinstruction sequence. Exemplarily, for the 2nd microinstruction, the alternative microinstruction sequence of the 2nd microinstruction includes: the 2nd microinstruction in the preset cache (in this example, the preset cache does not include the 2nd microinstruction), the microinstruction output by the port 1 of the decoding unit 1: microinstruction 1.1, the microinstruction output by the port 2 of the decoding unit 1: microinstruction 1.2, and the microinstruction output by the port 1 of the decoding unit 2: microinstruction 2.1. Figure 9 is a selection schematic diagram provided by the embodiment of the present application, as Figure 9 shown, for the 2nd microinstruction, the alternative microinstruction sequence of the 2nd microinstruction, the first selection signal of the 2nd microinstruction (0001 is used as an example in Figure 9 ) as the input of the selection circuit of the 2nd microinstruction of the target sequence. According to the example, the output of the selection circuit of the 2nd microinstruction is microinstruction 2.1.

[0113] It can be understood that when the hth microinstruction needs to be selected as the target sequence, the alternative microinstruction sequence of the hth microinstruction, the selection signal of the hth microinstruction as the input of the selection circuit of the hth microinstruction of the target sequence, and the output of the selection circuit of the hth microinstruction is the hth microinstruction. Wherein, the selection signal can be the first selection signal, the second selection signal or the third selection signal in the embodiment of the present application.

[0114] Using one-hot encoding as the selection signal makes it possible to select the microinstruction to be transmitted to the renaming unit from the target sequence using a two-level AND-OR combination circuit. Using one-hot encoding as the selection signal and combining the AND-OR combination circuit to realize selection can realize a selection circuit with the shortest critical path and achieve optimal timing.

[0115] Optionally, the step of writing the microinstruction corresponding to the end instruction of the current round in the remaining microinstructions in the microinstruction sequence into the preset cache comprises:

[0116] Step 1033a, any microinstruction corresponding to the end instruction of the current round in the remaining microinstructions is taken as a second microinstruction, and a second selection signal is generated for the second microinstruction based on the order of the second microinstruction in the target sequence by a second selection unit; the target sequence includes the first target microinstruction and the microinstruction sequence, and the first target microinstruction is located before the microinstruction sequence in the target sequence.

[0117] Step 1033b, the second selection signal is executed to select the second microinstruction and write it into the preset cache.

[0118] The second selection unit is BufferSelector, and the second selection signal can be the one-hot encoding of the second micro instruction. Specifically, a bit corresponding to the actual source of the second micro instruction in the initial one-hot encoding corresponding to the sequence number of the second micro instruction in the target sequence is set to 1 to obtain the second selection signal of the second micro instruction. That is, the selection signal represented by the initial one-hot encoding after the setting is used as the second selection signal of the second micro instruction. Wherein, a bit in the initial one-hot encoding corresponding to the sequence number of the second micro instruction in the target sequence represents a source corresponding to the micro instruction of the sequence number, and the initial one-hot encoding corresponding to each sequence number can be set in advance, and the value of each initial one-hot encoding can be set to all 0 by default. For example, assuming that the micro instructions corresponding to the end instruction of the current round in the remaining micro instructions include micro instruction 6.3 and micro instruction 6.4, and the micro instruction 6.3 and the micro instruction 6.4 are the 9th micro instruction and the 10th micro instruction in the target sequence, the selection signals of the 9th micro instruction and the 10th micro instruction can be generated respectively to obtain the second selection signal of the 9th micro instruction and the second selection signal of the 10th micro instruction. In the embodiment of the application, the one-hot encoding of the second micro instruction can be used as the selection signal, and the selection can be realized by using the AND-OR combination circuit in the second selection unit.

[0119] It should be noted that for any micro instruction required to be written into the preset cache as the third micro instruction in the second implementation mode, the same method can be used to set a bit corresponding to the actual source of the third micro instruction in the initial one-hot encoding corresponding to the sequence number of the third micro instruction in the target sequence to 1 by the second selection unit to obtain the third selection signal of the third micro instruction. That is, the selection signal represented by the initial one-hot encoding after the setting is used as the third selection signal of the third micro instruction. The third selection signal is executed to select the third micro instruction and write it into the preset cache. The first selection signal, the second selection signal and the third selection signal in the embodiment of the application are all selections, and the first selection signal, the second selection signal and the third selection signal represent the selection signals of the first micro instruction, the second micro instruction and the third micro instruction respectively.

[0120] In the embodiment of the application, the second selection unit is set, and the second selection unit generates the second selection signal for the second micro instruction based on the sequence of the second micro instruction in the target sequence, so that the second micro instruction required to be written into the preset cache can be conveniently selected by executing the second selection signal.

[0121] Figure 10 is a schematic diagram of an instruction processing shown in the embodiment of the application, as Figure 10As shown, the to-be-decoded instruction and its vector configuration information are input into multiple decoding units, and microinstructions in the preset cache and microinstructions output by the multiple decoding units form a target sequence. A first selection unit can select a first microinstruction from the target sequence and pass the first microinstruction to the renaming unit, and a second selection unit can select a second microinstruction from the target sequence and write the second microinstruction to the preset cache.

[0122] It should be noted that in the last round, the number of microinstructions in the target sequence can be insufficient for UOPWidth due to the small number of remaining instructions. In this case, all microinstructions in the target sequence can be selected. That is, the number of microinstructions selected by the first selection unit from the target sequence satisfies the condition of not exceeding UOPWidth.

[0123] In the embodiment of the present application, for any current round, the number q of microinstructions included in the preset cache and the number of microinstructions decoded by each decoding unit are passed to the first selection unit and the second selection unit. The first selection unit and the second selection unit use q and the number of microinstructions decoded by each decoding unit to calculate the sequence numbers of the microinstructions in the preset cache and the sequence number of the first microinstruction generated by each decoding unit. Based on the sequence number of the first microinstruction generated by each decoding unit, the sequence numbers of all microinstructions in the target sequence are determined. The sequence number of the microinstruction is the sequence number of the microinstruction in the target sequence.

[0124] The way to calculate the sequence number of the first microinstruction generated by each decoding unit can be referred to as described above, and will not be described here. For each microinstruction in the preset cache, the sequence number of the e-th microinstruction is set to e, where e is not greater than q. For any decoding unit, the sequence number of the first microinstruction generated by the decoding unit is added k times, and the value obtained each time is used as the sequence number of another microinstruction generated by the decoding unit. Wherein, k is the total number of other microinstructions generated by the decoding unit, and k is an integer not less than 0. Accordingly, after obtaining the sequence numbers of the microinstructions, it is convenient to generate a selection signal for the microinstruction based on the sequence number of the microinstruction in the target sequence.

[0125] Figure 11 is a schematic diagram of the transmission of a microinstruction provided by an embodiment of the present application, as shown, Figure 11 For the microinstruction generated by the decoding unit in the current round, the sequence number of the microinstruction in the target sequence can be calculated. If the sequence number is not greater than the input width of the renaming unit, the microinstruction is passed to the renaming unit to enter the renaming stage.

[0126] Of course, if the sequence number is greater than the input width of the renaming unit, the microinstruction is written into the preset cache or discarded to be regenerated in the next round.

[0127] In the embodiment of the present application, the first selection unit and the second selection unit are introduced, and the microinstructions transmitted to the renaming unit and the microinstructions written into the preset cache are selected from the target sequence based on the two units. Since the first selection unit selects UopWidth microinstructions by default to be transmitted to the renaming unit, the problem that the decoding stage changes with LMUL is avoided to a certain extent, and the decoding stage can output the decoding throughput required to support high-performance processors.

[0128] Referring to Figure 12 , a block diagram of an instruction processing apparatus provided by an embodiment of the present application is shown, as Figure 12 indicated, the apparatus can specifically include:

[0129] The first processing module 201 is configured to select n instructions from an instruction stream as to-be-decoded instructions of a current round, and decode the to-be-decoded instructions using n decoding units to obtain a microinstruction sequence; n is an integer greater than or equal to 2;

[0130] The transmission module 202 is configured to transmit, to a renaming unit, microinstructions in a preset cache and microinstructions in the microinstruction sequence according to an input width of the renaming unit; the preset cache is configured to store microinstructions that are not transmitted in a previous round;

[0131] The writing module 203 is configured to write, to the preset cache, microinstructions in the microinstruction sequence that are not transmitted;

[0132] The second processing module 204 is configured to reselect n instructions from the instruction stream as to-be-decoded instructions of a next round, and return to the step of decoding the to-be-decoded instructions using the n decoding units for continuous execution until a stop condition is reached.

[0133] Optionally, the transmission module 202 is specifically configured to:

[0134] The microinstructions in the preset cache are taken as first target microinstructions, and the first p-q microinstructions in the microinstruction sequence are taken as second target microinstructions;

[0135] The first target microinstructions and the second target microinstructions are transmitted to the renaming unit; p is the input width, and q is the number of the first target microinstructions.

[0136] Optionally, the writing module 203 is specifically configured to:

[0137] starting from a first decoding unit of the n decoding units, the q is sequentially accumulated with a number of micro-instructions generated by the decoding units;

[0138] in a case that the accumulated value is not less than the p, an instruction processed by a last decoding unit participating in the accumulation is taken as an end instruction of the current round;

[0139] a micro-instruction corresponding to the end instruction of the current round among the remaining micro-instructions in the micro-instruction sequence is written into the preset cache.

[0140] Optionally, the second processing module 204 is specifically configured to:

[0141] a next instruction of the end instruction in the instruction stream is taken as a start instruction of the next round;

[0142] starting from the start instruction, n continuous instructions are selected as to-be-decoded instructions of the next round.

[0143] Optionally, the first processing module 201 is specifically configured to:

[0144] for any decoding unit, an instruction input into the decoding unit is processed by the decoding unit to obtain a micro-instruction corresponding to the instruction;

[0145] a number of the micro-instruction corresponding to the instruction is taken as a first number, if the first number is not a preset fixed number, a fixed number with a minimum difference value from the first number is determined as a target number, and invalid micro-instructions are added to the micro-instruction corresponding to the instruction so that the first number reaches the target number.

[0146] Optionally, the delivery module 202 is specifically configured to:

[0147] any micro-instruction in the first target micro-instruction and the second target micro-instruction is taken as a first micro-instruction, a first selection signal of the first micro-instruction is generated by a first selection unit based on an order of the first micro-instruction in a target sequence, the target sequence includes the first target micro-instruction and the micro-instruction sequence, and the first target micro-instruction is located before the micro-instruction sequence in the target sequence;

[0148] the first selection signal is executed to select the first micro-instruction and deliver it to the renaming unit.

[0149] Optionally, the writing module 203 is specifically configured to:

[0150] any microinstruction corresponding to the end instruction of the current round from the remaining microinstructions as a second microinstruction, generating a second selection signal for the second microinstruction based on an order of the second microinstruction in a target sequence by a second selection unit; the target sequence comprising the first target microinstruction and the microinstruction sequence, and the first target microinstruction being located before the microinstruction sequence in the target sequence;

[0151] performing the second selection signal to select the second microinstruction and write the preset cache.

[0152] Optionally, the delivery module 202 is specifically configured to:

[0153] determining the first r microinstructions from the remaining microinstructions in the microinstruction sequence as to-be-written microinstructions; the r being a size of the preset cache;

[0154] taking an instruction corresponding to a last microinstruction in the to-be-written microinstructions as a target instruction, and writing the to-be-written microinstructions into the preset cache if the to-be-written microinstructions comprise all microinstructions corresponding to the target instruction;

[0155] writing other microinstructions in the to-be-written microinstructions except for the microinstruction corresponding to the target instruction into the preset cache if the to-be-written microinstructions do not comprise all microinstructions corresponding to the target instruction.

[0156] Optionally, the second processing module 204 is specifically configured to:

[0157] taking an instruction corresponding to a last microinstruction written into the preset cache as an end instruction of the current round;

[0158] taking a next instruction of the end instruction in the instruction stream as a start instruction of the next round;

[0159] selecting continuous n instructions from the start instruction as to-be-decoded instructions of the next round.

[0160] To sum up, the instruction processing apparatus provided by the embodiment of the present application selects n instructions from the instruction stream as the to-be-decoded instructions of the current round, and decodes the to-be-decoded instructions by using the n decoding units to obtain a microinstruction sequence; n is an integer not less than 2. According to the input width of the renaming unit, the microinstructions in the preset buffer and the microinstructions in the microinstruction sequence are delivered to the renaming unit; the preset buffer is used to store the microinstructions that are not delivered in the last round. The microinstructions that are not delivered in the microinstruction sequence are written into the preset buffer. The n instructions are reselected from the instruction stream as the to-be-decoded instructions of the next round, and the step of decoding the to-be-decoded instructions by using the n decoding units is continued to be executed until a stop condition is reached. In this way, the number of microinstructions in the microinstruction sequence obtained in the current round can be increased each time, so that sufficient microinstructions can be delivered to the renaming unit, thereby improving the decoding throughput and the decoding efficiency.

[0161] Moreover, the microinstructions are delivered to the renaming unit according to the input width of the renaming unit each time, that is, the input width of microinstructions is delivered to the renaming unit each time, so that the decoding throughput is not fixed and the problem of being unable to guarantee stable decoding throughput is avoided. Meanwhile, by introducing the preset buffer, the microinstructions that are not delivered in the last round are stored, and the microinstructions in the preset buffer are continuously delivered to the renaming unit in the current round, so that the microinstructions that are limited by the input width and cannot enter the renaming stage in the last round can be delivered to the renaming unit in the current round without re-decoding the instructions corresponding to the microinstructions in the preset buffer, thereby improving the overall processing efficiency to a certain extent.

[0162] Reference Figure 13 is a structural schematic diagram of an electronic device provided by the embodiment of the present application. As shown in Figure 13 , the electronic device comprises a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication among each other through the communication bus; the memory is used to deposit executable instructions, and the executable instructions make the processor execute the instruction processing method of the foregoing embodiment. The executable instructions can constitute a program.

[0163] The embodiment of the present application provides a readable storage medium, which stores executable instructions, when executed by one or more processors, make the processor execute the instruction processing method of the foregoing embodiment.

[0164] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other.

[0165] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, apparatus, or computer program product. Accordingly, embodiments of the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, and the like) embodying computer program instructions. It is to be understood that all actions to obtain signals, information, or data in this application are performed in compliance with the corresponding data protection regulations of the country where the data is obtained, and with the authorization of the owner of the corresponding device. Embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to embodiments of the present application. It will be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, a special purpose computer, an embedded processor, or other programmable data processing terminal devices to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal devices, create means for implementing the functions specified in the flowcharts and / or block diagrams of the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to embodiments of the present application. Figure 1 one or more flows and / or blocks Figure 1 an apparatus to perform the functions specified in the flowchart

[0166] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal devices to work in a predictive manner, such that the instructions stored in the computer-readable memory produce a manufactured product including instruction means that implement the functions specified in the flowcharts and / or block diagrams of the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to embodiments of the present application. Figure 1 one or more flows and / or blocks Figure 1 an apparatus to perform the functions specified in the flowchart

[0167] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device to cause a series of operational steps to be performed on the computer or other programmable terminal device to produce a computer-implemented process such that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in the flowcharts and / or block diagrams of the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to embodiments of the present application. Figure 1 one or more flows and / or blocks Figure 1 an apparatus to perform the functions specified in the flowchart

[0168] Although preferred embodiments of the present application have been described, those skilled in the art will appreciate that additional modifications and changes can be made thereto without departing from the scope of the present application. Accordingly, the appended claims are intended to cover all such modifications and changes as fall within the scope of the present application.

[0169] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between such entities or operations. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0170] The above provides a detailed description of the instruction processing method, the instruction processing device, the electronic device and the readable storage medium. The principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the method and the core idea of the present application. For those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges can be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. An instruction processing method, characterized in that, The method includes: Select n instructions from the instruction stream as the instructions to be decoded in the current round, and use n decoding units to decode the instructions to be decoded to obtain a microinstruction sequence; where n is an integer not less than 2. According to the input width of the renaming unit, the micro-instructions in the preset cache and the micro-instruction sequence are passed to the renaming unit; the preset cache is used to store the micro-instructions that were not passed in the previous round. Write the undelivered microinstructions from the microinstruction sequence into the preset cache, select n instructions from the instruction stream as the instructions to be decoded in the next round, and return to the step of decoding the instructions to be decoded using n decoding units, until the stopping condition is met.

2. The method according to claim 1, characterized in that, The step of passing microinstructions from a preset cache and the microinstruction sequence to the renaming unit according to the input width of the renaming unit includes: The microinstructions in the preset cache are used as the first target microinstructions, and the first p-q microinstructions in the microinstruction sequence are used as the second target microinstructions. The first target microinstruction and the second target microinstruction are passed to the renaming unit; p is the input width, and q is the number of the first target microinstructions.

3. The method according to claim 2, characterized in that, The step of writing undelivered microinstructions from the microinstruction sequence to the preset cache includes: Starting from the first decoding unit among the n decoding units, the number of microinstructions generated by the decoding unit is sequentially added to q; If the accumulated value is not less than p, the instruction processed by the last decoding unit involved in the accumulation is taken as the end instruction of the current round. The microinstruction corresponding to the end instruction of the current round among the remaining microinstructions in the microinstruction sequence is written into the preset cache.

4. The method according to claim 3, characterized in that, The step of reselecting n instructions from the instruction stream as the instructions to be decoded in the next round includes: The instruction following the end instruction in the instruction stream is taken as the start instruction of the next round. Starting from the initial instruction, n consecutive instructions are selected as the instructions to be decoded in the next round.

5. The method according to claim 1, characterized in that, The decoding of the instruction to be decoded using n decoding units includes: For any of the decoding units, the instruction input to the decoding unit is processed to obtain the microinstruction corresponding to the instruction; The method further includes: taking the number of micro-instructions corresponding to the instruction as a first quantity; if the first quantity is not a preset fixed quantity, then determining the fixed quantity with the smallest difference between the first quantity and the first quantity as the target quantity; adding invalid micro-instructions to the micro-instructions corresponding to the instruction so that the first quantity reaches the target quantity.

6. The method according to claim 2, characterized in that, The step of passing the first target microinstruction and the second target microinstruction to the renaming unit includes: Either the first target microinstruction or the second target microinstruction is taken as the first microinstruction. The first selection unit generates a first selection signal for the first microinstruction based on the order of the first microinstruction in the target sequence. The target sequence includes the first target microinstruction and the microinstruction sequence, wherein the first target microinstruction is located before the microinstruction sequence in the target sequence. The first selection signal is executed to select the first microinstruction and pass it to the renaming unit.

7. The method according to claim 3, characterized in that, The step of writing the microinstruction corresponding to the end instruction of the current round from the remaining microinstructions in the microinstruction sequence into the preset cache includes: The remaining microinstructions are used as any microinstruction corresponding to the end instruction of the current round as the second microinstruction. The second selection unit generates a second selection signal for the second microinstruction based on the order of the second microinstruction in the target sequence. The target sequence includes the first target microinstruction and the microinstruction sequence, wherein the first target microinstruction is located before the microinstruction sequence in the target sequence. The second selection signal is executed to select the second microinstruction and write it to the preset cache.

8. The method according to claim 1, characterized in that, The step of writing undelivered microinstructions from the microinstruction sequence to the preset cache includes: The first r microinstructions among the remaining microinstructions in the microinstruction sequence are determined as the microinstructions to be written; where r is the size of the preset cache. The instruction corresponding to the last microinstruction in the microinstructions to be written is taken as the target instruction. If the microinstructions to be written include all the microinstructions corresponding to the target instruction, then the microinstructions to be written are written into the preset cache. If the microinstructions to be written do not include all the microinstructions corresponding to the target instruction, then the other microinstructions in the microinstructions to be written, excluding the microinstructions corresponding to the target instruction, are written into the preset cache.

9. The method according to claim 8, characterized in that, The step of reselecting n instructions from the instruction stream as the instructions to be decoded in the next round includes: The instruction corresponding to the last microinstruction written into the preset cache is used as the end instruction of the current round; The instruction following the end instruction in the instruction stream is taken as the start instruction of the next round. Starting from the initial instruction, n consecutive instructions are selected as the instructions to be decoded in the next round.

10. An instruction processing apparatus, characterized in that, The device includes: The first processing module is used to select n instructions from the instruction stream as the instructions to be decoded in the current round, and use n decoding units to decode the instructions to be decoded to obtain a microinstruction sequence; where n is an integer not less than 2. The transmission module is used to transmit micro-instructions in a preset cache and micro-instructions in the micro-instruction sequence to the renaming unit according to the input width of the renaming unit; the preset cache is used to store micro-instructions that were not transmitted in the previous round. The writing module is used to write undelivered microinstructions from the microinstruction sequence into the preset cache; The second processing module is used to reselect n instructions from the instruction stream as the instructions to be decoded in the next round, and return to the step of decoding the instructions to be decoded using n decoding units, until the stopping condition is met.

11. An electronic device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store executable instructions that cause the processor to perform the method as described in any one of claims 1 to 9.

12. A readable storage medium, characterized in that, It stores executable instructions that, when executed by one or more processors, cause the processors to perform the method as described in any one of claims 1 to 9.

Images