Dynamic power sharing with power event feedback

Abstract

The invention relates to dynamic power sharing with power event feedback. Techniques are described for incorporating telemetry related to power source load and frequency of power control events as part of a power balancing algorithm to control electronic device power budget between devices sharing a common power source. The techniques utilize telemetry and control loop algorithms to dynamically balance power between two or more electronic components, which may include CPUs and GPUs. Techniques described herein are used to monitor power source loads and the frequency of a set of predetermined events, which may include performance and / or power control events. Based on this information, the power budget of the device may be dynamically adjusted up or down to maximize performance, which is compared to conventional use of artificial static performance upper limits.

Description

Background Art

[0001] Many electronic device platforms are limited in the size of a power source, such as a power supply unit (PSU) or a battery charger, which can be connected internally or externally. Therefore, active power management is often required to ensure that the device power source does not become overburdened, resulting in an unexpected shutdown. Such active power management techniques typically include controlling the power consumption of the system's CPU (IA core), and potentially controlling the power consumption of the GPU. However, conventional active power management algorithms do not take the power source load into account when determining the power targets for the CPU and GPU, but instead focus on the temperature levels of the CPU and GPU or telemetry related to the system battery. Therefore, in order to protect the power source, system designers need to impose static power limits on the CPU and GPU, regardless of whether the power source is overloaded or has additional headroom. Therefore, current techniques for controlling the shared budget of device components (such as the CPU and GPU) are insufficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate the present disclosure and, together with the description, further serve to explain the principles and to enable one skilled in the relevant art to make and use the techniques discussed herein.

[0003] In the accompanying drawings, like reference numerals generally refer to like parts throughout the different views. These drawings are not necessarily to scale, but emphasis is generally placed upon illustrating the principles of the present disclosure. In the following description, reference is made to the following drawings, in which:

[0004] Figure 1 illustrates a conventional thermal-based solution for adjusting a power budget shared between two devices;

[0005] Figure 2 illustrates a power sharing process for adjusting a power budget shared between two devices based on the occurrence of a power protection event according to the present disclosure;

[0006] Figure 3A and Figure 3B illustrates a power rebalancing loop for adjusting a power budget shared between two devices according to the present disclosure;

[0007] Figure 4 Another view illustrating power budget adjustments made by a power balancing algorithm in response to the frequency of power monitoring events occurring over time;

[0008] Figure 5 FIGURE 1 illustrates a power sharing process for adjusting a power budget shared between two devices by adjusting the frequency of event monitoring according to the present disclosure; and

[0009] Figure 6 An electronic device according to the present disclosure is illustrated.

[0010] The present disclosure will be described with reference to the accompanying drawings.The drawing in which an element first appears is generally indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION

[0011] Reference is made to the accompanying drawings in the following detailed description, which illustrate exemplary details in which the present disclosure may be implemented. In the following description, numerous specific details are set forth in order to provide a complete understanding of the present disclosure. However, it will be apparent to those skilled in the art that various designs, including structures, systems, and methods, may be implemented without these specific details. The descriptions and representations herein are common means used by those experienced in the art or skilled in the art to most effectively convey the essence of their work to others skilled in the art. In other cases, well-known methods, procedures, components, and circuits have not been described in detail to avoid unnecessarily obscuring the present disclosure.

[0012] I. Technical Overview

[0013] The present disclosure relates generally to dynamic adjustment of power budgets of electronic device components, and particularly to techniques for using power event feedback to dynamically adjust the power budgets of electronic device components that share a common power source.

[0014] Likewise, conventional power source protection techniques have the disadvantage of placing static power requirements on electronic device component power budgets (such as CPUs and GPUs). Furthermore, current control mechanisms for balancing CPU and GPU power are based on temperature and battery telemetry. For example, Figure 1 The figure shows a conventional thermal-based solution for adjusting the power budget shared between two devices. Figure 1 As shown, the conventional solution receives thermal monitoring information indicating whether a particular electronic component (i.e., device A or B, again including the CPU and GPU, respectively) is thermally limited. If not, the current power budget of each device A, B is maintained until the next monitoring cycle, which may include periodic sampling "windows". However, if either device A, B is in a thermally limited state (i.e., "hot"), then Figure 1 The conventional solution shown is used to increase the power budget of another non-thermally constrained device while reducing the power budget of the thermally constrained device.

[0015] However, to the extent that current solutions are implemented to protect power sources, these control mechanisms only manage CPU power consumption, and therefore the CPU bears the entire burden of these control management techniques. Furthermore, these conventional solutions are unable to detect system-level power protection events, as only thermal data is available and used in these conventional power balancing algorithms. This can degrade performance by throttling the CPU in isolation from GPU performance.

[0016] The technology described herein addresses these problems by recognizing that increased performance can be achieved by incorporating telemetry related to the load of the power source and the frequency of power control events into the active management strategy of the electronic device. To this end, the technology further described in detail herein utilizes new telemetry and control loop algorithms to dynamically balance the shared power budget between two or more electronic components (which may include a CPU and a GPU). This allows for an overall higher level of system performance while still protecting the power source from entering an overcurrent protection mode. The algorithm described herein is used to utilize the power source load and the frequency of a set of predetermined power protection events, which may include performance-related events and / or power control events. Therefore, power source load monitoring is used to create power event notifications (as discussed in further detail herein), which may include the presence or absence of power protection events. Power source load monitoring can be performed via code executed locally on the CPU, wherein details about this functionality will be discussed in further detail below. In various non-limiting and illustrative scenarios, this may include: reading the executed code from a suitable voltage controller, and storing the event data in registers that the system-level power tuning application can then access (i.e., read). Additionally or alternatively, other suitable types of data (such as raw power source load) can also be monitored via the system-level power tuning application. In any case, based on this information, operating limits (i.e., the power budget of the electronic components) can be dynamically adjusted up or down to maximize performance, in contrast to the conventional use of artificial static performance caps.

[0017] As discussed herein, dynamic management of the power budget of electronic device components allows for higher overall system performance and a better user experience. Without such an approach, conventional power source protection methods would only reduce CPU performance to reduce system power. However, the performance management techniques described herein are used to balance system power protection across both the CPU and GPU (or other suitable components). This allows for the design of higher-performance products that utilize CPUs and GPUs with higher thermal design powers (TDPs) while maintaining a smaller power source (such as a PSU) than would otherwise be possible.

[0018] For ease of explanation, the details of the power management techniques are further described below in separate sections. However, it should be noted that presenting the power control management techniques in this manner is not intended to imply that the implementation of these techniques is limited to the techniques described in a single section. On the contrary, the techniques for power management control further described in any number of the following sections herein may be combined with each other. In addition, as a non-limiting and illustrative scenario, power control techniques are described herein with respect to CPUs and GPUs. The techniques described herein can be implemented using any suitable number of electronic components (also referred to herein as devices) that share a common power supply, such that the power budget of each device can be adjusted for any suitable number of electronic components via the power balancing control techniques discussed herein.

[0019] II. Using System Power Protection Events for Power Balancing

[0020] Figure 2 1 illustrates an example process flow for adjusting a power budget shared between two devices based on the occurrence of a power protection event according to the present disclosure. Figure 2 The process 200 shown may describe the process flow of a power balancing algorithm that utilizes system-level power protection events to adjust electronic component power budgets accordingly. Figure 2 The various blocks shown are discussed in further detail herein with respect to their respective functions. Figure 2 The functions provided by the illustrated blocks may be implemented via any suitable combination of hardware components and software components. The software in this context may be executed via any suitable platform in which the electronic components (ie, devices A, B) are implemented.

[0021] To provide various illustrative and non-limiting scenarios, device A may include a CPU, and device B may include a GPU, as discussed herein. However, the technology described herein is not limited to such implementations, and the power balancing techniques discussed herein may be implemented to adjust the power budget of any suitable number and / or type of components that share a common power source. Therefore, although devices A and B are primarily described herein in terms of being implemented as a CPU and a GPU, devices A and B may also be implemented as any suitable type of processor with a power budget, a USB-C port, a memory, a storage device, a peripheral device, etc. In addition, the power balancing techniques discussed herein may be implemented according to any suitable type of power source shared between any suitable number of devices, which is used to dynamically supply power over time based on various load requirements. This may include a PSU, a battery charger, etc.

[0022] When devices A and B are implemented as a CPU and a GPU, the CPU may perform lower-level power source monitoring using onboard and / or integrated firmware, which may include a power event monitoring algorithm executed locally on the CPU. The power event monitoring algorithm may be combined with the power event monitoring algorithm described above. Figure 1 The conventional thermal-based power budget adjustment algorithm discussed above is implemented. Figure 2 The illustrated process flow 200 (which may also be implemented via a power balancing algorithm) utilizes the CPU's locally executed power event monitoring data to perform higher system-level power budget adjustments, as discussed in further detail herein. Thus, the various power device budget adjustments discussed herein may be implemented independently or in conjunction with thermal-based power budget adjustments (such as those discussed above with respect to Figure 1 those discussed) are implemented in parallel.

[0023] To this end, the CPU can implement any suitable locally executed power event monitoring algorithm to write power protection data to any suitable memory location, such as a register or other addressable memory location, which is known to higher system-level software that executes the power balancing algorithm according to the process flow 200 discussed further herein. To provide an illustrative and non-limiting scenario, the power protection data can include power protection events triggered in response to various conditions being met, which are initiated by the CPU to perform power source protection. Such power protection events can then be written to any suitable memory location as described above based on monitoring performed by the locally executed power event monitoring function of the CPU.

[0024] To provide an illustrative and non-limiting scenario, this can include the CPU observing that a power source output (such as a PSU output) is above a predetermined threshold, thereby triggering the CPU's power protection algorithm to reduce the CPU's operating power in various ways, as discussed in further detail below. However, the CPU's power protection algorithm only affects the CPU's power consumption. Therefore, power protection events identified by the CPU's power protection algorithm in this manner are passed up to the system level and accessed (i.e., read) by higher-level software running on the electronic device. Therefore, the system power protection event monitoring block 202 represents functionality associated with power protection events, which are read from an appropriate memory location by higher-level software after being stored by the CPU, and the system power protection event monitoring block 202 can occur as part of the power balancing algorithm represented by process flow 200.

[0025] In other words, the CPU's power protection algorithm provides a first level of protection to protect the power source (such as a PSU) from overcurrent events, but it is limited to adjusting the CPU's operating power limits. On the other hand, the power balancing algorithm represented by process flow 200 enables parallel adjustment of the two device power budgets to produce the best overall performance. And by making the power balancing algorithm aware of system-level power protection events, the power balancing algorithm can dynamically adjust device performance based on system activity (such as load that may occur due to attached system peripherals) rather than CPU-triggered events. Therefore, as used herein, the term "power protection event" may include any suitable type of information that is relevant to adjusting the power budget of any suitable device that shares a common power source, in addition to or in lieu of CPU-triggered events. In this way, Figure 1 represents a shift in the thermal budget that causes the power budget of only one of devices A, B to shift upward or downward in response to a single event, whereas the power balancing algorithm represented by process flow 200 allows the power budgets of both devices A, B to be adjusted upward or downward in response to additional non-thermal power protection events.

[0026] In other words, the power balancing algorithm discussed in this article implements a control loop to continuously monitor the frequency of power protection events and adjust the power budgets of devices A, B upward or downward to achieve an acceptable power protection event rate. Figure 3A-Figure 3B The diagram illustrates a non-limiting and illustrative scenario in which a power balancing algorithm utilizes this control loop process to continuously adjust the power budgets of devices A, B to their optimal levels to ensure system stability and a good user experience.

[0027] To this end, it should be noted that whenever the power balancing algorithm invokes a power budget adjustment, such an event is also recorded in a suitable storage location (which may be the same location as the power protection event or a different location). This storage location is also monitored by higher-level system software as part of executing the power balancing algorithm discussed herein. And by measuring how frequently power protection events occur within each sampling window, the power balancing algorithm determines whether the power budgets of devices A and B are set too high for the current load of the entire system.

[0028] To provide a non-limiting and illustrative scenario, it should be noted that the power balancing algorithm periodically accesses the stored power event data. The power balancing algorithm is initially triggered when the frequency of power protection events is such that the number of power protection events occurring within the event threshold detection sampling window exceeds a predetermined threshold number of events. Then, based on the predetermined threshold limit of power events occurring within each sampling period, the power balancing algorithm determines whether "too many" events have occurred or whether fewer events or no events have occurred. The power balancing algorithm then takes action to adjust the power budget of devices A and B downward or upward. Therefore, this control loop process continuously attempts to keep the power budget of devices A and B as high as possible. Additional details about this process will be discussed further below.

[0029] Again, the power balancing algorithm represented by process flow 200 illustrates the power behavior of a system containing two devices sharing a common power source. The power balancing algorithm periodically accesses the stored power event data according to continuous monitoring (also referred to herein as "sampling") periods of any suitable length, which are Figure 3A and Figure 3B , which are illustrated as sampling periods 302.1-302.N and 352.1-352.N. The power balancing algorithm determines the number of power protection events that occur within each sampling period and then determines whether to adjust the power budgets of devices A and B upward or downward based on the number of power protection events that occur over time within these sampling periods, as discussed in further detail below. Thus, the power balancing algorithm enables selective adjustment of the operating power limits of devices A and B based on the frequency of power protection events over multiple sampling periods.

[0030] Continue to refer Figure 3A and Figure 3B The number of power protection events that occur within each sampling period 302.1-302.N and 352.1-352.N is used to drive the power balancing algorithm's decision on whether to increase the power budget, decrease the power budget, or maintain the current power budget without making any changes. It should be noted that the number of occurrences that trigger each response can be different to avoid oscillatory behavior. In other words, hysteresis is implemented so that the number of power protection events that occur within a sampling period that causes an increase in the power budget is different from the number of power protection events that occur within a sampling period that causes a decrease in the power budget.

[0031] For ease of explanation, the following illustrative scenario is used, where: the number of power protection events that occur within a sampling period that cause an increase in the power budget is set to 1. The number of power protection events that occur within a sampling period that cause a decrease in the power budget is set to 3. The number of power protection events that occur within a sampling period that do not cause a change in the current power budget is set to 2. It should be noted that any suitable threshold value can be defined in this manner to support adjustments to the device budget while avoiding instability and / or oscillatory behavior. For example, and with continued reference to Figure 3A , sampling periods 302.1, 302.4, and 302.8 each include three power protection events, and thus power balancing is used in response to balance the budget downward. However, sampling periods 302.2 and 302.5 include a single power protection event, and thus power balancing is used in response to balance the budget upward. For sampling periods 302.3 and 302.6, the hysteresis condition has not been met relative to the number of events that occurred within the previous sampling window, and thus the number of events within these sampling periods is deemed insufficient to adjust the current power budget. Finally, sampling periods 302.7, 302.9, and 302.N each include no power protection event, and thus power balancing can be removed entirely, or alternatively, the power budget can be increased again from its previous setting.

[0032] Keeping these event number thresholds in mind to continue the scenario, the power balancing algorithm first determines whether the initial event threshold number has been exceeded (block 204). In other words, the power balancing algorithm continues to monitor for power protection events during each sampling period 302.1-302.N until the initial threshold number of events is exceeded. This is also done in Figure 4 This is illustrated in FIG. 1 by the defined threshold and reference to block 204. Until this occurs, the power protection algorithm may remain in an inactive state, in which it continuously monitors for power protection events during each sampling period 302.1-302.N, but no adjustments are made to the device power budget, such as Figure 2 206 . However, once the initial power protection device threshold is met, the power balancing algorithm begins applying power budget reductions to devices A and B. In this case, a determination is then made as to whether a sufficient number of power protection events have occurred within each current sampling period 302.1-302.N to warrant any additional adjustments to the device power budgets. For the current scenario, for ease of explanation, this threshold number of events may include one power protection event, such that when no power protection events occur within the current sampling window, no changes are made to the current power budget setpoint, and process flow 200 repeats the process at the next sampling period (block 206).

[0033] However, if one or more power protection events have occurred within the current sampling period (block 208A, yes), process flow 200 continues with making a further determination as to whether an increase event hysteresis (block 208A) or decrease event hysteresis (block 208B) has expired. Figure 4 Further detailed diagrams are shown in Figure 4 The number of power protection events is plotted over time. Figure 4 As shown, once the initial threshold number of events is exceeded (block 204), if the number of power protection events still increases further, a stronger power reduction is applied (408A). However, if the number of power protection events begins to decrease (but is still above the initial threshold number of events (block 204)), the power reduction is reduced (408B). It should be noted that with respect to Figure 3A and Figure 3B The various power protection event thresholds discussed are related to Figure 4 The power protection event thresholds shown in the example are different. This is done to show that Figure 3A and Figure 3B Use of power protection event thresholds on a neat event time scale is shown.

[0034] It should be noted that the power balancing algorithm may also take "non-events" into account when determining whether to adjust the power budget and / or suspend use of the power balancing algorithm described herein. Figure 4 Shows that the number of events during this period is zero (i.e., only Figure 3A-Figure 3B Thus, in addition to or in lieu of satisfying the threshold number of events being exceeded (block 204), the power balancing algorithm may utilize the number of non-events being below the threshold to pause and / or adjust the power balancing discussed herein.

[0035] In addition, and continuing to refer to Figure 4 , the use of hysteresis via the power balancing algorithm described herein can utilize both event-based hysteresis (i.e., the number of events within a sampling period) and time-based hysteresis (i.e., the time-based dependency of both the current and past frequencies of event occurrences). In other words, the power balancing algorithm discussed herein can use both amplitude (number of events) as well as time (number of previous sampling periods) and can therefore function similarly to a low-pass filter. This is in Figure 4 , in addition to the event hysteresis on the y-axis, the power balancing algorithm is also illustrated via a time hysteresis represented on the x-axis. Thus, to provide an illustrative and non-limiting scenario, in addition to the number of events occurring within each individual sampling period, an increase in the frequency of event occurrences over time may also be considered, such that when the time-based hysteresis indicates a larger "jump" in increasing or decreasing the number of power protection events, the power balancing algorithm may use a larger "step size" to adjust the power budget.

[0036] Therefore, and continuing to refer to Figure 3A In the current scenario, assume that one power protection event occurring during sampling period 302.1 triggers the power balancing algorithm, i.e., the result of block 204 is "yes." Then, during sampling period 302.4, a total of three power protection events occur. Therefore, during the subsequent period (i.e., the sampling period), not only has the threshold number of power protection events (one) determined at block 204 been met or exceeded, but another threshold number of incremental power protection events (three) has also been met or exceeded. In this case, at block 208A, a determination is made that the number of power protection events is greater than or equal to the incremental event hysteresis threshold (i.e., three), and therefore, the power budgets of both devices A and B are reduced.

[0037] Continue About Figure 3A , a total of one power protection event subsequently occurs during the next sampling period 302.5. Therefore, at block 204, it is determined that the threshold number of power protection events (one) has still been met or exceeded, and at block 208B, it is determined that the number of power protection events is decreasing in number. That is, although the total number of power protection events is greater than or equal to the initial event threshold of 1, the number of power protection events is less than or equal to another threshold (i.e., the decreasing event hysteresis threshold of 1), indicating that the frequency of power protection events is decreasing over time. As a result, the power budgets of both devices A and B are increased.

[0038] Furthermore, once the number of power protection events falls below the initial event threshold of 1, such that no power protection events are determined (in this case, occurring during sampling period 302.7), the budget power reduction is completely removed. In this manner, the larger the "jump" in increasing or decreasing the number of power protection events, the more responsive the power balancing algorithm. Thus, because the power balancing algorithm utilizes different power protection event thresholds in this manner to adjust the power budgets of devices A and B upward or downward, power balancing utilizes a hysteresis band that represents the number of power protection events required during the current sampling window to cause any change in the power budgets of devices A and B relative to the previous state. Thus, if the subsequent power protection event count (determined by block 204 to be above the initial event threshold) is within the hysteresis band, the power budgets of devices A and B remain constant for the current sampling period, which helps reduce oscillations.

[0039] That is, using hysteresis in this manner ensures that the number of power protection events that occur between consecutive sampling periods has changed significantly from the number of the previous power protection event that triggered the power budget adjustment. Figure 3AIn the current scenario, the next sampling period 302.6 includes a total of two power protection events. While this does result in the initial event threshold being exceeded (block 204, yes), neither the conditions of the increment hysteresis determination block 208A nor the decrement hysteresis determination block 208B are met (i.e., both are no), causing the current power budget to be maintained (block 206), which in this case is the increased power budget resulting from the power protection events that occurred in the previous sampling period 302.5.

[0040] Thus, process flow 200 can continue until sampling period 302.7 occurs, during which no power protection events are recorded, and thus the power balancing algorithm can remove all power budget adjustments until the next sampling period 302.8, during which three power protection events are recorded. As a result, the conditions of increment hysteresis determination block 208A are again met, causing the power budgets of devices A and B to be reduced. This process of monitoring for the occurrence of power protection events continues in this manner for subsequent sampling periods.

[0041] Therefore, the power balancing algorithm adjusts the power budgets of devices A and B to increase and decrease the power budgets so that, in each case, the total shared power budget of device A and device B does not exceed a predetermined wattage. Accordingly, the power balancing algorithm will still attempt to allocate the power budgets of the individual devices based on workload demand. However, if power protection events are observed to be greater than or equal to a certain frequency threshold (i.e., the increase event hysteresis threshold of 3 used above), the power balancing algorithm adjusts the power budgets of both device A and device B downward. Additionally, when power protection events fall at or below a different threshold (i.e., the decrease event hysteresis threshold of 1 used above), the power balancing algorithm adjusts the power budgets of both device A and device B upward.

[0042] To provide an illustrative and non-limiting scenario, Figure 2The process flow shown assumes that the initial power budget for devices A+B is set to 300W, where device A is allocated 100W and device B is allocated 200W. However, due to increased power consumption by the rest of the platform (RoP), the PSU may reach and may even sometimes exceed its standard output rating, and therefore the power event monitoring function locally executed by the CPU may implement power reduction operations as power protection events. The power balancing algorithm detects these events and determines that it should reduce the total system power by 50W (device A+B=250W). Based on the applications running on the system, the power balancing algorithm decides to maintain the original 33% / 66% allocation of the power budget. Therefore, the power balancing algorithm reduces the power of device A to 83W and device B to 167W, continuing to monitor for future power protection events via subsequent sampling periods as described above. If the 50W power reduction is not enough and more power protection events are occurring, the power balancing algorithm can further reduce the total system power by another 50W (device A + B = 200W) and set device A to 66W and device B to 134W. As the RoP power consumption decreases, the power balancing algorithm will then detect that there are no further power protection events and will begin to adjust the power budgets of device A and device B upward. This process will then continue until the system returns to the maximum power budget level.

[0043] It should be noted that since many form factor systems have power sources (such as PSUs) that are limited in size / capacity, these systems cannot support worst-case power load conditions and must therefore be protected from unexpected shutdowns. The power balancing algorithm discussed herein enables the system to achieve higher overall performance by avoiding situations where the CPU and GPU are throttled in isolation, and therefore assumes the full burden of power source protection.

[0044] It should be noted that Figure 3A The figure shows that the power balancing algorithm as discussed above implements a plurality of sampling periods 302.1-302.N, each sampling period being associated with an event monitoring frequency. In other words, the power balancing algorithm periodically accesses the stored power protection events during each sampling period 302 to monitor power protection events, wherein the periodicity of the sampling periods 302.1-302.N thus defines the power event monitoring frequency. Figure 3A As shown, the plurality of sampling periods 302.1-302.N are continuous and closely adjacent to each other in time, but this is shown as a non-limiting and illustrative scenario. Figure 3A The control loop implemented by the power balancing algorithm shown is executed by periodically monitoring power protection events during each consecutive sampling period 302.1-302.N, where Figure 3AEach successive sampling period 302.1-302.N is shown to begin after the previous sampling period has ended. Figure 3A and Figure 3B Some small time period between each successive sampling period 302.1-302.N is shown in FIG, but except for processing and / or other system delays, each successive sampling period 302.1-302.N may begin immediately after the previous sampling period.

[0045] However, the monitoring frequency of the control loop implemented by the power balancing algorithm may be any suitable frequency, may use any suitable length of sampling period, and may adjust the monitoring frequency over time based on any suitable number of power protection events that have occurred within a previous threshold time period. That is, the power balancing algorithm may alternate between a slower monitoring control loop and a faster monitoring control loop in response to changes in the frequency of power protection events over time. This is achieved by comparing Figure 3A and Figure 3B This is illustrated by the frequencies of the sampling periods 302, 352 shown in FIG.

[0046] For example, using Figure 3A The power balancing algorithm identified by the sampling periods 302.1-302.N shown in FIG uses a "fast" control loop monitoring frequency for the entirety of the sampling periods 302.1-302.N. However, Figure 3B The power balancing algorithm shown in the figure can switch between a fast control loop monitoring frequency and a slower control loop monitoring frequency. To demonstrate this, continue to refer to Figure 3B , Figure 3B The diagram illustrates the use of a monitoring frequency event period 354. The monitoring frequency event period 354 can be defined as any suitable predetermined time period for determining the occurrence of a power protection event that triggers a change between the monitoring frequencies of the fast and slow monitoring control loops implemented by the power balancing algorithm. To provide a non-limiting and illustrative scenario, the monitoring frequency event period 354 can be a time period equal to a predetermined number of sampling periods 352.1-352.N. As another non-limiting and illustrative scenario, the monitoring frequency event period 354 can be a predefined time period (such as a counter expiration) that is initiated when any power protection event is identified during access to power protection events during any of the sampling periods 352.1-352.N.

[0047] In any case, the power balancing algorithm determines the number of power protection events during each monitoring frequency event period, which can be compared to a predetermined event threshold. The predetermined event threshold used to trigger a transition from the fast monitoring control loop monitoring frequency to the slow monitoring control loop monitoring frequency can be the same as the predetermined event threshold used to trigger a transition from the slow monitoring control loop monitoring frequency back to the fast monitoring control loop monitoring frequency. Alternatively, the predetermined event thresholds used to trigger a transition from the fast monitoring control loop monitoring frequency to the slow monitoring control loop monitoring frequency and the predetermined event thresholds used to trigger a transition from the slow monitoring control loop monitoring frequency to the fast monitoring control loop monitoring frequency can be different from each other to achieve hysteresis and avoid oscillatory behavior for this purpose.

[0048] Return Reference Figure 3B , shows that the power balancing algorithm initially operates according to the fast monitoring control loop monitoring frequency. However, the number of power protection events that occur within the monitoring frequency event period 354.1 is assumed to be less than the predetermined threshold event value, and therefore an event timeout period 354.1 is shown that triggers the transition to the slow monitoring control loop monitoring frequency. As a result, the next sampling period 352.4 occurs after the previous sampling period 352.3, but at a delayed time thereafter, as shown in FIG. Figure 3B As shown. Thus, the time difference between sampling periods 352.3 and 352.4 can define the slow monitoring control loop monitoring frequency. Monitoring frequency event period 354 can also be used as a time period for determining whether a threshold number of power protection events has been exceeded, as discussed above with respect to block 204. In this case, the power balancing algorithm can suspend monitoring entirely until a threshold number of power monitoring events is again detected within a future monitoring frequency event period, thereby triggering the power balancing algorithm to once again operate according to the fast monitoring control loop monitoring frequency.

[0049] For example, and as Figure 3B As shown, it is assumed that the number of power protection events occurring within the next monitoring frequency event period 354.2 is greater than the predetermined threshold event value, and thus a transition from the slow (or paused) monitoring control loop monitoring frequency back to the fast monitoring control loop monitoring frequency is triggered. As a result, the following sampling periods 352.5-352.N again occur one after another (or immediately after one another) with a smaller time delay, as shown in FIG. Figure 3B This process continues such that the power balancing algorithm can alternate between these different control loop monitoring frequencies based on the history of how often power protection events occur over time.

[0050] Figure 5 FIGURE 1 illustrates a power sharing process for adjusting the power shared between two devices by adjusting the frequency of event monitoring according to the present disclosure. Figure 5The process flow 500 shown is similar to Figure 2 The process flow 200 shown is the same, where Figure 2 and Figure 5 Each of the figures shows similar blocks that perform the same functions as one another. Figure 5 The illustrated process flow 500 indicates that the system power protection event monitoring block 202 may operate according to different monitoring control loop monitoring frequencies, as discussed above. Although only two different frequencies are shown and discussed herein, it should be noted that the process flow 500 may implement any suitable number of control loop monitoring frequencies, each identified by a corresponding predetermined power protection event threshold.

[0051] Therefore, if Figure 5 The "fast loop" and "slow loop" lines shown correspond to a determination that the current control loop monitoring frequency is to be adjusted. It should be noted that the identification of power control events within each monitoring frequency event time period and the decision to adjust the control loop monitoring frequency can be generated via the power balancing algorithm itself, or alternatively, via another component within the system in which the power balancing algorithm is implemented. As a non-limiting and illustrative scenario, if a predetermined threshold number of power control events is exceeded within the monitoring frequency event time period, the CPU can generate (e.g., as part of its locally executed power event monitoring function) an interrupt (block 502) to signal a switch to faster control loop monitoring behavior, as described above. Additionally or alternatively, the interrupt (block 502) can be generated via a lower level system power protection manager.

[0052] The power budgets of devices A and B may alternatively be referred to herein as operating power limits and may be adjusted and / or defined according to any suitable technique, including known techniques. In a non-limiting and illustrative scenario, the operating power limits may be defined according to associated maximum performance limits, such that adjustments to the performance limits of devices A and B result in corresponding adjustments to the power budgets, as discussed herein. Alternatively, the operating power limits may be defined according to a predefined maximum power consumption limit.

[0053] Regardless of how the power budget is defined, the power budget can be adjusted based on any suitable adjustment to power parameters implemented by devices A and B. Thus, in one non-limiting and illustrative scenario, devices A and B can operate according to predefined performance limits that can be adjusted from a maximum performance limit of 100% to a reduced performance limit of 80%, 50%, etc. Additionally or alternatively, the power budget can be adjusted via a clock frequency adjustment to a slower clock frequency and / or a reduction in the maximum allowable operating temperature implemented by devices A and / or B (which in turn results in a performance degradation of the respective devices). As an illustrative and non-limiting scenario, the frequency of a CPU can be reduced to a low-power mode (LFM) level based on the downward adjustment of its power budget as discussed herein.

[0054] Additionally or alternatively, the power budget can be adjusted by utilizing an existing power balancing algorithm implemented by one of devices A and B (such as a CPU). In some non-limiting and illustrative scenarios, this can include adjusting the performance limits of devices A and / or B according to one or more different timescales. These performance metrics can be associated with a locally executed power control algorithm implemented by the CPU and / or GPU, which defines several different timescales for performance limits. This may include the processor's "long-term" or expected steady-state power consumption, which may include a thermal design power (TDP) or other suitable performance limit defined on a long-term timescale of several milliseconds. Additional performance limit timescales may include a short-term performance limit, which may define the processor's short-term maximum power draw. This number is typically higher than the long-term expected steady-state power consumption, and the CPU may enter this state when the workload applied allows the CPU to use the short-term maximum power draw on a shorter timescale of several microseconds.

[0055] The power balancing algorithms discussed herein may be implemented according to any combination of the techniques discussed herein. Figure 2 The power budgets of devices A and B are adjusted as shown, which may include modifying the long-term and short-term maximum power draw values. In this way, the power balancing algorithm discussed herein can adjust the performance limits of devices A and B on different time scales to affect the performance and power behavior of the system.

[0056] III. Electronic Equipment

[0057] Figure 6An electronic device according to the present disclosure is illustrated. Electronic device 600 can be identified using any suitable type of device that implements the power balancing techniques discussed herein, which can be used to adjust the power budget of any suitable number and / or type of components sharing a common power source. To provide some illustrative and non-limiting scenarios, electronic device 600 can be implemented as a wireless device, user equipment (UE), mobile phone, laptop, tablet, wearable device, etc.

[0058] Electronic device 600 may include processing circuitry 602, which may be configured as any suitable number and / or type of computer processors and may be used to control electronic device 600 and / or other components of electronic device 600. Processing circuitry 602 may be identified by one or more processors (or suitable portions thereof) implemented by electronic device 600. Processing circuitry 602 may be identified by one or more processors (such as a host processor, a digital signal processor, one or more microprocessors, a central processing unit (CPU), a baseband processor, a microcontroller, an application-specific integrated circuit (ASIC), a portion (or all) of a field-programmable gate array (FPGA), etc. Processing circuitry 602 may be identified by a CPU and / or one of devices A and B discussed herein. Processing circuitry 602 may utilize power provided by power source 604.

[0059] Processing circuit system 602 can be configured to execute instructions for performing arithmetic, logical and / or input / output (I / O) operations, and / or for controlling the operation of one or more components of electronic device 600, to perform the various functions described herein. Processing circuit system 602 can include one or more microprocessor cores, memory registers, buffers, clocks, etc., and can generate electronic control signals associated with components of electronic device 600 to control and / or modify the operation of these components. Processing circuit system 602 can communicate with memory 608 and any other components of electronic device 600, and / or control functions associated with memory 608 and any other components of electronic device 600. Thus, processing circuit system 602 can generate control signals or cause other components to generate such control signals to generate and store power protection event data, as discussed herein.

[0060] The electronic device 600 includes a power source 604, which may be implemented as power delivery circuitry for supplying power to the processing circuitry 602 and one or more of the components 606.1-606.N, and / or charging a battery of the electronic device 600. Thus, the power source 604 may include any suitable type of power management circuitry, power regulator, etc., and may be configured to selectively provide power to the electronic device 600 via an external power source or the battery of the electronic device 600.

[0061] The electronic device 600 includes any suitable number N of components 606.1-606.N. These components 606.1-606.N may be implemented as any suitable number and / or type of components that share a power source 604 with the processing circuitry 602. Thus, the components 606.1-606.N may be identified with one or more graphics processors (such as dedicated graphics processing units (GPUs)), one of the devices A, B discussed herein, or any other suitable device having a controlled power budget as discussed herein.

[0062] Memory 608 stores data and / or instructions that, when executed by processing circuitry 602 and / or other suitable processing circuitry of electronic device 600, enable electronic device 600 to perform various functions, such as monitoring for power protection events and / or adjusting the power budgets of various components of shared power source 604, as discussed in further detail herein. Memory 608 can be implemented as any suitable type of volatile and / or non-volatile memory, including read-only memory (ROM), random access memory (RAM), flash memory, magnetic storage media, optical disks, erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), and the like. Memory 608 can be non-removable, removable, or a combination of both. Memory 608 can be implemented as a non-transitory computer-readable medium that stores one or more executable instructions (such as logic, algorithms, code, and the like). The instructions, logic, code, and the like stored in memory 608 are represented by power balancing control module 609. The processing circuit system 602 and / or other suitable processing circuit systems of the electronic device 600 can execute instructions stored in the memory 608 to enable any of the techniques described herein to be functionally implemented, which may include the execution of a power balancing algorithm. The power balancing control module 609 can store computer-readable instructions that, when executed by the processing circuit system 602 and / or other suitable processing circuit systems of the electronic device 600, enable the electronic device 600 to perform any of the functions described herein with respect to the execution of the power balancing algorithm.

[0063] IV. General Configuration of Computer-Readable Media

[0064] A non-transitory computer-readable medium is provided. The non-transitory computer-readable medium has instructions stored thereon, which, when executed by a processing circuit system of an electronic device, causes the electronic device to: determine the number of power protection events that occur within a corresponding sampling period in a plurality of sampling periods, the power protection event being associated with a power source that provides power to a first component and a second component of the electronic device; and selectively adjust the operating power limits of the first component and the second component based on the frequency of occurrence of the power protection event within the plurality of sampling periods. In addition to or in lieu of the optional features previously explained in this paragraph, and in any combination with the optional features previously explained in this paragraph, the first component includes a central processing unit (CPU) and the second component includes a dedicated graphics processing unit (GPU). In addition to or in lieu of the optional features previously explained in this paragraph, and in any combination with the optional features previously explained in this paragraph, the power source includes a power supply unit (PSU), and the power protection event includes a power limit event initiated by the first component in response to the power output of the PSU exceeding a threshold power level. Additionally or alternatively, and in any combination with the optional features previously explained in this paragraph, a plurality of sampling periods are associated with an event monitoring frequency, the sampling periods being consecutive and temporally adjacent to one another. Additionally or alternatively, and in any combination with the optional features previously explained in this paragraph, the plurality of sampling periods are associated with an event monitoring frequency that is based on a number of power protection events occurring within a predetermined time period. Additionally or alternatively, and in any combination with the optional features previously explained in this paragraph, the instructions, when executed by the processing circuitry, cause the electronic device to: increase the monitoring frequency in response to the number of power protection events occurring within the predetermined time period exceeding a threshold number of events. Additionally or alternatively, and in any combination with the optional features previously explained in this paragraph, the instructions, when executed by the processing circuitry, cause the electronic device to: increase the operating power limit of the first component and the second component in response to the number of power limit events occurring within a sampling period of the plurality of sampling periods being less than or equal to a first threshold number of events. In addition to or in lieu of the optional features previously explained in this paragraph, and in any combination with the optional features previously explained in this paragraph, the instructions, when executed by the processing circuit system, cause the electronic device to: reduce the operating power limit of the first component and the second component in response to the number of power limit events occurring within another sampling period in the plurality of sampling periods being greater than or equal to a second threshold number of events that is different from the first threshold number of events.In addition to or in lieu of the optional features previously explained in this paragraph, and in any combination with the optional features previously explained in this paragraph, the instructions, when executed by the processing circuitry, cause the electronic device to selectively adjust operating power limits of the first component and the second component by: reducing the operating power limits of the first component and the second component to a reduced operating power limit when a number of power limiting events occurring within a first sampling period in a plurality of sampling periods exceeds a first threshold number of events; and increasing the operating power limits of the first component and the second component from the reduced operating power limit to the increased operating power limit when a number of power limiting events occurring within a second sampling period in the plurality of sampling periods subsequent to the first sampling period is less than a second threshold number of events. In addition to or in lieu of the optional features previously explained in this paragraph, and in any combination with the optional features previously explained in this paragraph, the instructions, when executed by the processing circuitry, cause the electronic device to: adjust the operating power limits of the first component and the second component by adjusting performance limits of the first component and / or the second component according to one or more different time scales.

[0065] V. General Configuration of Electronic Equipment

[0066] An electronic device is provided. The electronic device includes: a first component; a second component; a memory configured to store instructions; and a processing circuit system configured to execute instructions stored on the memory to: determine the number of power protection events that occur within a corresponding sampling period in a plurality of sampling periods, the power protection event being associated with a power source that provides power to the first component and the second component; and selectively adjust the operating power limit of the first component and the second component based on the frequency of occurrence of the power protection event within the plurality of sampling periods. In addition to or in lieu of the optional features previously explained in this paragraph, and in any combination with the optional features previously explained in this paragraph, the first component includes a central processing unit (CPU) and the second component includes a dedicated graphics processing unit (GPU). In addition to or in lieu of the optional features previously explained in this paragraph, and in any combination with the optional features previously explained in this paragraph, the power source includes a power supply unit (PSU), and the power protection event includes a power limit event initiated by the first component in response to the power output of the PSU exceeding a threshold power level. Additionally or alternatively, and in any combination with the optional features previously explained in this paragraph, a plurality of sampling periods are associated with an event monitoring frequency, the sampling periods being consecutive and temporally adjacent to one another. Additionally or alternatively, and in any combination with the optional features previously explained in this paragraph, the plurality of sampling periods are associated with an event monitoring frequency that is based on a number of power protection events occurring within a predetermined time period. Additionally or alternatively, and in any combination with the optional features previously explained in this paragraph, the processing circuitry is configured to execute instructions to: increase the monitoring frequency in response to the number of power protection events occurring within the predetermined time period exceeding a threshold number of events. Additionally or alternatively, and in any combination with the optional features previously explained in this paragraph, the processing circuitry is configured to execute instructions to: increase the operating power limit of the first component and the second component in response to the number of power limit events occurring within a sampling period of the plurality of sampling periods being less than or equal to a first threshold number of events. In addition to or in lieu of the optional features previously explained in this paragraph, and in any combination with the optional features previously explained in this paragraph, the processing circuit system is configured to execute instructions to: in response to a number of power limit events occurring within another sampling period of the plurality of sampling periods being greater than or equal to a second threshold number of events that is different from the first threshold number of events, reduce the operating power limit of the first component and the second component.Additionally or alternatively, and in any combination with the optional features previously explained in this paragraph, the processing circuitry is configured to execute instructions to selectively adjust operating power limits of the first component and the second component by: reducing the operating power limits of the first component and the second component to a reduced operating power limit when a number of power limit events occurring within a first sampling period in a plurality of sampling periods exceeds a first threshold number of events; and increasing the operating power limits of the first component and the second component from the reduced operating power limit to the increased operating power limit when a number of power limit events occurring within a second sampling period in the plurality of sampling periods subsequent to the first sampling period is less than a second threshold number of events. Additionally or alternatively, and in any combination with the optional features previously explained in this paragraph, the processing circuitry is configured to execute instructions to: adjust the operating power limits of the first component and the second component by adjusting performance limits of the first component and / or the second component according to one or more different time scales. Example

[0067] The following examples relate to various techniques of this disclosure.

[0068] Examples (e.g., Example 1) relate to a non-transitory computer-readable medium having instructions stored thereon that, when executed by a processing circuit system of an electronic device, cause the electronic device to: determine a number of power protection events that occur within a corresponding sampling period in a plurality of sampling periods, wherein the power protection event is associated with a power source that provides power to a first component and a second component of the electronic device; and selectively adjust an operating power limit of the first component and the second component based on a frequency of occurrence of the power protection event within the plurality of sampling periods.

[0069] Another example (eg, Example 2) relates to the previously described example (eg, Example 1), wherein the first component includes a central processing unit (CPU), and wherein the second component includes a dedicated graphics processing unit (GPU).

[0070] Another example (e.g., Example 3) relates to a previously described example (e.g., one or more of Examples 1-2), wherein the power source includes a power supply unit (PSU), and wherein the power protection event includes a power limiting event initiated by the first component in response to a power output of the PSU exceeding a threshold power level.

[0071] Another example (eg, Example 4) relates to the previously described examples (eg, one or more of Examples 1-3), wherein a plurality of sampling periods are associated with the event monitoring frequency, the sampling periods being consecutive and temporally adjacent to each other.

[0072] Another example (eg, Example 5) relates to the previously described examples (eg, one or more of Examples 1-4), wherein the plurality of sampling periods is associated with an event monitoring frequency based on a number of power protection events occurring within a predetermined time period.

[0073] Another example (e.g., Example 6) relates to the previously described examples (e.g., one or more of Examples 1-5), wherein the instructions, when executed by the processing circuit system, cause the electronic device to: increase the monitoring frequency in response to the number of power protection events occurring within a predetermined time period exceeding a threshold number of events.

[0074] Another example (e.g., Example 7) relates to the previously described examples (e.g., one or more of Examples 1-6), wherein the instructions, when executed by the processing circuit system, cause the electronic device to: increase the operating power limit of the first component and the second component in response to the number of power limiting events occurring within a sampling cycle in a plurality of sampling cycles being less than or equal to a first threshold number of events.

[0075] Another example (e.g., Example 8) relates to the previously described examples (e.g., one or more of Examples 1-7), wherein the instructions, when executed by the processing circuit system, cause the electronic device to: reduce the operating power limit of the first component and the second component in response to the number of power limiting events occurring within another sampling period of a plurality of sampling periods being greater than or equal to a second threshold number of events that is different from the first threshold number of events.

[0076] Another example (e.g., Example 9) relates to the previously described examples (e.g., one or more of Examples 1-8), wherein the instructions, when executed by the processing circuit system, cause the electronic device to selectively adjust the operating power limits of the first component and the second component by: reducing the operating power limits of the first component and the second component to a reduced operating power limit when the number of power limiting events occurring within a first sampling period in a plurality of sampling periods exceeds a first threshold number of events; and increasing the operating power limits of the first component and the second component from the reduced operating power limit to the increased operating power limit when the number of power limiting events occurring within a second sampling period in the plurality of sampling periods after the first sampling period is less than a second threshold number of events.

[0077] Another example (e.g., Example 10) relates to the previously described examples (e.g., one or more of Examples 1-9), wherein the instructions, when executed by the processing circuit system, cause the electronic device to: adjust the operating power limits of the first component and the second component by adjusting the performance limits of the first component and / or the second component according to one or more different time scales.

[0078] An example (e.g., Example 11) relates to an electronic device, comprising: a first component; a second component; a memory configured to store instructions; and a processing circuit system configured to execute the instructions stored on the memory to: determine a number of power protection events that occurred within a corresponding sampling period of a plurality of sampling periods, The power protection event is associated with a power source that provides power to the first component and the second component; and based on the occurrence frequency of the power protection event within multiple sampling periods, the operating power limit of the first component and the second component is selectively adjusted.

[0079] Another example (eg, Example 12) relates to the previously described example (eg, Example 11), wherein the first component includes a central processing unit (CPU), and wherein the second component includes a dedicated graphics processing unit (GPU).

[0080] Another example (e.g., Example 13) relates to a previously described example (e.g., one or more of Examples 11-12), wherein the power source includes a power supply unit (PSU), and wherein the power protection event includes a power limiting event initiated by the first component in response to a power output of the PSU exceeding a threshold power level.

[0081] Another example (eg, Example 14) relates to the previously described examples (eg, one or more of Examples 11-13), wherein a plurality of sampling periods are associated with the event monitoring frequency, the sampling periods being consecutive and temporally adjacent to each other.

[0082] Another example (eg, Example 15) relates to the previously described examples (eg, one or more of Examples 11-14), wherein a plurality of sampling periods is associated with an event monitoring frequency that is based on a number of power protection events occurring within a predetermined time period.

[0083] Another example (e.g., Example 16) relates to the previously described examples (e.g., one or more of Examples 11-15), wherein the processing circuit system is configured to execute instructions to: increase the monitoring frequency in response to the number of power protection events occurring within a predetermined time period exceeding a threshold number of events.

[0084] Another example (e.g., Example 17) relates to the previously described examples (e.g., one or more of Examples 11-16), wherein the processing circuit system is configured to execute instructions to: increase the operating power limit of the first component and the second component in response to the number of power limiting events occurring within a sampling period of multiple sampling periods being less than or equal to a first threshold number of events.

[0085] Another example (e.g., Example 18) relates to the previously described examples (e.g., one or more of Examples 11-17), wherein the processing circuit system is configured to execute instructions to: reduce the operating power limit of the first component and the second component in response to the number of power limit events occurring within another sampling period in a plurality of sampling periods being greater than or equal to a second threshold number of events that is different from the first threshold number of events.

[0086] Another example (e.g., Example 19) involves previously described examples (e.g., one or more of Examples 11-18), wherein the processing circuit system is configured to execute instructions to selectively adjust the operating power limits of the first component and the second component by: reducing the operating power limits of the first component and the second component to a reduced operating power limit when the number of power limiting events occurring within a first sampling period in a plurality of sampling periods exceeds a first threshold number of events; and increasing the operating power limits of the first component and the second component from the reduced operating power limit to the increased operating power limit when the number of power limiting events occurring within a second sampling period in the plurality of sampling periods after the first sampling period is less than a second threshold number of events.

[0087] Another example (e.g., Example 20) relates to a previously described example (e.g., one or more of Examples 11-19), wherein the processing circuit system is configured to execute instructions to: adjust the operating power limits of the first component and the second component by adjusting the performance limits of the first component and / or the second component according to one or more different time scales.

[0088] An example (e.g., Example 21) relates to a storage device having instructions stored thereon, which, when executed by a processing device of an electronic device, causes the electronic device to: determine a number of power protection events that occur within a corresponding sampling period in a plurality of sampling periods, wherein the power protection event is associated with a power providing device that provides power to a first component and a second component of the electronic device; and selectively adjust the operating power limit of the first component and the second component based on the frequency of occurrence of the power protection event within the plurality of sampling periods.

[0089] Another example (eg, Example 22) relates to the previously described example (eg, Example 21), wherein the first component includes a central processing unit (CPU), and wherein the second component includes a dedicated graphics processing unit (GPU).

[0090] Another example (e.g., Example 23) relates to a previously described example (e.g., one or more of Examples 21-22), wherein the power providing device includes a power supply unit (PSU), and wherein the power protection event includes a power limiting event initiated by the first component in response to the power output of the PSU exceeding a threshold power level.

[0091] Another example (eg, Example 24) relates to the previously described examples (eg, one or more of Examples 21-23), wherein a plurality of sampling periods are associated with the event monitoring frequency, the sampling periods being consecutive and temporally adjacent to each other.

[0092] Another example (eg, Example 25) relates to the previously described examples (eg, one or more of Examples 21-24), wherein a plurality of sampling periods is associated with an event monitoring frequency that is based on a number of power protection events occurring within a predetermined time period.

[0093] Another example (e.g., Example 26) relates to the previously described examples (e.g., one or more of Examples 21-25), wherein the instructions, when executed by the processing device, cause the electronic device to: increase the monitoring frequency in response to the number of power protection events occurring within a predetermined time period exceeding a threshold number of events.

[0094] Another example (e.g., Example 27) relates to the previously described examples (e.g., one or more of Examples 21-26), wherein the instructions, when executed by the processing device, cause the electronic device to: increase the operating power limit of the first component and the second component in response to the number of power limiting events occurring within a sampling period of multiple sampling periods being less than or equal to a first threshold number of events.

[0095] Another example (e.g., Example 28) relates to the previously described examples (e.g., one or more of Examples 21-27), wherein the instructions, when executed by the processing device, cause the electronic device to: reduce the operating power limit of the first component and the second component in response to the number of power limiting events occurring within another sampling period in a plurality of sampling periods being greater than or equal to a second threshold number of events that is different from the first threshold number of events.

[0096] Another example (e.g., Example 29) relates to the previously described examples (e.g., one or more of Examples 21-28), wherein the instructions, when executed by the processing device, cause the electronic device to selectively adjust the operating power limits of the first component and the second component by: reducing the operating power limits of the first component and the second component to a reduced operating power limit when the number of power limiting events occurring in a first sampling period in a plurality of sampling periods exceeds a first threshold number of events; and increasing the operating power limits of the first component and the second component from the reduced operating power limit to the increased operating power limit when the number of power limiting events occurring in a second sampling period in the plurality of sampling periods after the first sampling period is less than a second threshold number of events.

[0097] Another example (e.g., Example 30) relates to the previously described examples (e.g., one or more of Examples 21-29), wherein the instructions, when executed by the processing device, cause the electronic device to: adjust the operating power limits of the first component and the second component by adjusting the performance limits of the first component and / or the second component according to one or more different time scales.

[0098] An example (e.g., Example 31) relates to an electronic device comprising: a first component; a second component; a storage device for storing instructions; and a processing device for executing the instructions stored on the storage device to: determine a number of power protection events that occur within a corresponding sampling period in a plurality of sampling periods, wherein the power protection event is associated with a power providing device that provides power to the first component and the second component; and selectively adjust the operating power limit of the first component and the second component based on the frequency of occurrence of the power protection event within the plurality of sampling periods.

[0099] Another example (eg, Example 32) relates to the previously described example (eg, Example 31), wherein the first component includes a central processing unit (CPU), and wherein the second component includes a dedicated graphics processing unit (GPU).

[0100] Another example (e.g., Example 33) relates to a previously described example (e.g., one or more of Examples 31-32), wherein the power providing device includes a power supply unit (PSU), and wherein the power protection event includes a power limiting event initiated by the first component in response to the power output of the PSU exceeding a threshold power level.

[0101] Another example (eg, Example 34) relates to the previously described examples (eg, one or more of Examples 31-33), wherein a plurality of sampling periods are associated with the event monitoring frequency, the sampling periods being consecutive and temporally adjacent to each other.

[0102] Another example (eg, Example 35) relates to the previously described examples (eg, one or more of Examples 31-34), wherein a plurality of sampling periods is associated with an event monitoring frequency that is based on a number of power protection events occurring within a predetermined time period.

[0103] Another example (e.g., Example 36) relates to the previously described examples (e.g., one or more of Examples 31-35), wherein the processing device executes instructions to: increase the monitoring frequency in response to the number of power protection events occurring within a predetermined time period exceeding a threshold number of events.

[0104] Another example (e.g., Example 37) relates to the previously described examples (e.g., one or more of Examples 31-36), wherein the processing device executes instructions to: in response to a number of power limiting events occurring within a sampling period of multiple sampling periods being less than or equal to a first threshold number of events, increase the operating power limit of the first component and the second component.

[0105] Another example (e.g., Example 38) relates to the previously described examples (e.g., one or more of Examples 31-37), wherein the processing device executes instructions to: reduce the operating power limit of the first component and the second component in response to the number of power limit events occurring within another sampling period in the plurality of sampling periods being greater than or equal to a second threshold number of events that is different from the first threshold number of events.

[0106] Another example (e.g., Example 39) involves the previously described examples (e.g., one or more of Examples 31-38), wherein the processing device executes instructions to selectively adjust the operating power limits of the first component and the second component by: reducing the operating power limits of the first component and the second component to a reduced operating power limit when the number of power limiting events occurring in a first sampling period in a plurality of sampling periods exceeds a first threshold number of events; and increasing the operating power limits of the first component and the second component from the reduced operating power limit to the increased operating power limit when the number of power limiting events occurring in a second sampling period in the plurality of sampling periods after the first sampling period is less than a second threshold number of events.

[0107] Another example (e.g., Example 40) relates to a previously described example (e.g., one or more of Examples 31-39), wherein the processing device executes instructions to: adjust the operating power limits of the first component and the second component by adjusting the performance limits of the first component and / or the second component according to one or more different time scales.

[0108] Apparatus as shown and described.

[0109] Method as shown and described. Conclusion

[0110] The foregoing description will sufficiently reveal the general nature of the implementations of the present disclosure that others can readily modify and / or adapt various applications of such specific implementations by applying knowledge within the art without undue experimentation and without departing from the general concepts of the present disclosure. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and range of equivalents of the disclosed implementations. It should be understood that the wording or terminology herein is for purposes of description and not limitation, so that the terms or wording of this specification will be interpreted by those skilled in the art in accordance with the teachings and guidance.

[0111] Each described implementation may include certain features, structures, or characteristics, but not every implementation may necessarily include such certain features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same implementation. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an implementation, it is understood that it is within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other implementations, whether or not explicitly described.

[0112] The exemplary implementations described herein are provided for illustrative purposes only and are not intended to be limiting. Other implementations are possible, and the exemplary implementations may be modified. Therefore, this description is not intended to limit the present disclosure. Instead, the scope of the present disclosure is limited only by the appended claims and their equivalents.

[0113] Throughout the drawings, unless otherwise described, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures.

[0114] The terms "at least one" and "one or more" may be understood to include numbers greater than or equal to one (e.g., one, two, three, four, [...], etc.). The term "a plurality" may be understood to include numbers greater than or equal to two (e.g., two, three, four, five, [...], etc.).

[0115] The words "plurality" and "multiple" in the specification and claims expressly refer to a quantity greater than one. Thus, any phrase that expressly invokes the above words to refer to a certain number of elements (e.g., "plurality [elements]," "multiple [elements]") expressly refers to more than one of said elements. The terms "group(s)," "set(s)," "set(s)," "series(s)," "sequence(s)," "group(s)," and the like in the specification and claims, if present, refer to a quantity equal to or greater than one, i.e., one or more. The terms "proper subset," "reduced subset," and "smaller subset" refer to a subset of a set that is not equal to the set, illustratively, to a subset of a set that contains fewer elements than the set.

[0116] The phrase "at least one of," with respect to a group of elements, may be used herein to mean at least one element from the group consisting of the elements. The phrase "at least one of," with respect to a group of elements, may be used herein to mean a selection of: one of the listed elements, one element of a plurality of listed elements, a plurality of individual listed elements, or a plurality of a plurality of individual listed elements.

Claims

1. A non-transitory computer-readable medium having instructions stored thereon, the instructions, when executed by processing circuitry of an electronic device, causing the electronic device to: determining a number of power protection events that occurred within a corresponding sampling period in a plurality of sampling periods, in, The power protection event is associated with a power source that provides power to the first component and the second component of the electronic device; as well as Based on the frequency of occurrence of the power protection event within the plurality of sampling periods, operating power limits of the first component and the second component are selectively adjusted.

2. The non-transitory computer-readable medium of claim 1, wherein: The first component includes a central processing unit CPU, and The second component includes a dedicated graphics processing unit (GPU).

3. The non-transitory computer-readable medium of claim 1 , wherein: The power source comprises a power supply unit PSU, and Wherein the power protection event comprises a power limiting event initiated by the first component in response to a power output of the PSU exceeding a threshold power level.

4. The non-transitory computer-readable medium of claim 1, wherein: The plurality of sampling periods are associated with an event monitoring frequency, and the plurality of sampling periods are continuous and adjacent to each other in time.

5. The non-transitory computer-readable medium of any one of claims 1 to 4, wherein: The plurality of sampling periods is associated with an event monitoring frequency, the event monitoring frequency being based on a number of power protection events occurring within a predetermined time period.

6. The non-transitory computer readable medium of claim 5, wherein: The instructions, when executed by the processing circuitry, cause the electronic device to increase the monitoring frequency in response to a number of power protection events occurring within the predetermined time period exceeding a threshold number of events.

7. The non-transitory computer readable medium of any one of claims 1 to 4, wherein: The instructions, when executed by the processing circuit system, cause the electronic device to: in response to the number of power limit events occurring in one of the multiple sampling periods being less than or equal to a first threshold number of events, increase the operating power limit of the first component and the second component.

8. The non-transitory computer readable medium of claim 7, wherein: When executed by the processing circuit system, the instructions cause the electronic device to: reduce the operating power limit of the first component and the second component in response to the number of power limiting events occurring in another sampling period of the multiple sampling periods being greater than or equal to a second threshold event number that is different from the first threshold event number.

9. The non-transitory computer readable medium of any one of claims 1 to 4, wherein: When executed by the processing circuitry, the instructions cause the electronic device to selectively adjust operating power limits of the first component and the second component by: reducing the operating power limits of the first component and the second component to reduced operating power limits when a number of power limit events occurring within a first sampling period of the plurality of sampling periods exceeds a first threshold number of events; as well as When a number of power limit events occurring in a second sampling period of the plurality of sampling periods after the first sampling period of the plurality of sampling periods is less than a second threshold number of events, the operating power limit of the first component and the second component is increased from the lowered operating power limit to an increased operating power limit.

10. The non-transitory computer readable medium of any one of claims 1 to 4, wherein: The instructions, when executed by the processing circuitry, cause the electronic device to adjust operating power limits of the first and second components by adjusting performance limits of the first and second components according to one or more different time scales.

11. An electronic device, comprising: First component; Second component; a memory configured to store instructions; as well as processing circuitry configured to execute the instructions stored on the memory to: determining a number of power protection events that occurred within a corresponding sampling period in a plurality of sampling periods, wherein the power protection event is associated with a power source that provides power to the first component and the second component; as well as Based on the frequency of occurrence of the power protection event within the plurality of sampling periods, operating power limits of the first component and the second component are selectively adjusted.

12. The electronic device according to claim 11, wherein The first component includes a central processing unit CPU, and The second component includes a dedicated graphics processing unit (GPU).

13. The electronic device according to claim 11, wherein The power source comprises a power supply unit PSU, and Wherein the power protection event comprises a power limiting event initiated by the first component in response to a power output of the PSU exceeding a threshold power level.

14. The electronic device according to claim 11, wherein The plurality of sampling periods are associated with an event monitoring frequency, and the plurality of sampling periods are continuous and adjacent to each other in time.

15. The electronic device according to any one of claims 11 to 14, wherein: The plurality of sampling periods is associated with an event monitoring frequency, the event monitoring frequency being based on a number of power protection events occurring within a predetermined time period.

16. The electronic device according to claim 15, wherein The processing circuitry is configured to execute the instructions to increase the monitoring frequency in response to a number of the power protection events occurring within the predetermined time period exceeding a threshold number of events.

17. The electronic device according to any one of claims 11 to 14, wherein: The processing circuitry is configured to execute the instructions to increase an operating power limit of the first component and the second component in response to a number of power limit events occurring within a sampling period of the plurality of sampling periods being less than or equal to a first threshold number of events.

18. The electronic device according to claim 17, wherein: The processing circuitry is configured to execute the instructions to: in response to a number of power limit events occurring within another sampling period of the plurality of sampling periods being greater than or equal to a second threshold number of events that is different from the first threshold number of events, reduce an operating power limit of the first component and the second component.

19. The electronic device according to any one of claims 11 to 14, wherein: The processing circuitry is configured to execute the instructions to selectively adjust operating power limits of the first component and the second component by: reducing the operating power limits of the first component and the second component to reduced operating power limits when a number of power limit events occurring within a first sampling period of the plurality of sampling periods exceeds a first threshold number of events; as well as When a number of power limit events occurring in a second sampling period of the plurality of sampling periods after the first sampling period of the plurality of sampling periods is less than a second threshold number of events, the operating power limit of the first component and the second component is increased from the lowered operating power limit to an increased operating power limit.

20. The electronic device according to any one of claims 11 to 14, wherein: The processing circuitry is configured to execute the instructions to adjust operating power limits of the first component and the second component by adjusting performance limits of the first component and / or the second component according to one or more different time scales.

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