Flexible direct current converter valve system and modulation method thereof

Abstract

The invention provides a flexible direct current converter valve system and a modulation method thereof. Based on a novel hybrid module series structure, target voltage modulation is carried out by controlling a switch device trigger pulse in stages through polarity distribution of modulation wave voltage and bridge arm current. And executing a four-stage pulse adjustment process in an inversion or rectification mode, and dynamically managing the removal and input time sequence of the improved half-bridge power module. According to the method, the trigger pulse is accurately regulated and controlled according to the real-time polarity and the transition state of the voltage and the current, and the problems of instantaneous overcurrent and local overheating of a switching device under the overload condition in the traditional bridge arm topology are avoided. Through staged logic control, the system maintains the stability of the modulation wave voltage, reduces the thermal stress accumulation of the device, improves the endurance capability of the converter valve under a complex working condition, does not need external current limiting intervention, and enhances the operation flexibility and reliability.

Description

Technical Field

[0001] The present application relates to the field of flexible DC converter valves, and in particular to a flexible DC converter valve system and a modulation method thereof. Background Art

[0002] For the flexible DC converter valve, due to its consideration of DC side fault ride-through, step-down operation and other operating conditions, the bridge arm needs to have negative voltage output capability. Therefore, each bridge arm can be composed of a full-bridge power module and an improved half-bridge power module connected in series. Each module consists of a switching device and a capacitor. Different switching states determine the charging and discharging direction of the capacitor, thereby controlling the capacitor voltage.

[0003] However, existing flexible DC converter valves are limited by the maximum junction temperature of their power modules and lack high overload capability. Under overload conditions, the junction temperature of the device will exceed the maximum temperature limit specified in the device manual. In other words, the overload capability of existing flexible DC converter valve topologies depends on the high-temperature resistance of the components at their maximum junction temperature. In overload conditions, such as when the short-circuit current exceeds the specified limit, the flexible DC valve can only operate in current-limiting mode or adopt strategies such as unipolar blocking. This not only limits the support provided by the flexible DC system to the grid but can also cause system instability.

[0004] Therefore, a flexible DC converter valve topology with overload capability and its corresponding flexible DC converter valve modulation method are needed to improve the effectiveness of the flexible DC valve in overload scenarios and solve the current technical problem of insufficient overload capability of the flexible DC converter valve. Summary of the Invention

[0005] The purpose of this application is to solve at least one of the above-mentioned technical deficiencies, especially the technical defect of insufficient overload capacity of flexible DC converter valves in the prior art.

[0006] In a first aspect, the present application provides a flexible DC converter valve system, comprising: a plurality of target bridge arms, each of the target bridge arms being formed by connecting at least one improved half-bridge power module in series with at least one conventional full-bridge power module, wherein the switching devices of the improved half-bridge power module include an insulated gate bipolar transistor T1, a first thyristor T2, a second thyristor T3, and a third thyristor T4, and the first thyristor T2 and the second thyristor T3 share a trigger pulse to drive a circuit;

[0007] A control module, configured to control the trigger pulses of the switching devices in the improved half-bridge power module in stages according to the zero-crossing limits of the modulation wave voltage and the bridge arm current;

[0008] The staged control includes executing a preset four-stage pulse adjustment process in an inverter mode or a rectifier mode.

[0009] In a second aspect, the present application provides a flexible DC converter valve modulation method, the method being applied to a control module in a flexible DC converter valve system, the flexible DC converter valve system further comprising a plurality of target bridge arms, each of the target bridge arms being formed by connecting at least one improved half-bridge power module in series with at least one conventional full-bridge power module, and the switching devices of the improved half-bridge power module comprising an insulated gate bipolar transistor T1, a first thyristor T2, a second thyristor T3, and a third thyristor T4, and the first thyristor T2 and the second thyristor T3 sharing a trigger pulse to drive the circuit;

[0010] According to the polarity distribution of the modulation wave voltage and the bridge arm current, the trigger pulse of each switching device in the improved half-bridge power module is controlled in stages;

[0011] The staged control includes executing a preset four-stage pulse adjustment process in an inverter mode or a rectifier mode.

[0012] As an optional implementation, in the inverter mode, the four-stage pulse adjustment process is cyclically executed according to a preset sequence, and the polarity distribution of the modulation wave voltage and the bridge arm current in the four stages includes:

[0013] Phase 1: the modulation wave voltage is positive and the bridge arm current transitions from negative to positive;

[0014] The second stage: the modulation wave voltage transitions from positive to negative and the bridge arm current is positive;

[0015] The third stage: the modulation wave voltage transitions from negative to positive and the bridge arm current is positive;

[0016] Phase 4: the modulation wave voltage is positive and the bridge arm current transitions from positive to negative.

[0017] As an optional implementation, in the inverter mode, executing the preset four-stage pulse adjustment process includes:

[0018] In the first stage, the trigger pulse of the insulated gate bipolar transistor T1 in each of the switching devices is set to a low level throughout the process;

[0019] Setting the trigger pulse of the third thyristor T4 of the improved half-bridge power module, in which the trigger pulse of the insulated gate bipolar transistor T1 is high at the beginning of this stage, to a high level;

[0020] During the modulation wave voltage reduction process, according to the determined improved half-bridge power module removal order, the trigger pulses of the third thyristor T4 corresponding to the improved half-bridge power module in the on state are sequentially set to a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a high level to remove the corresponding improved half-bridge power module;

[0021] In the second stage, the trigger pulse of the insulated gate bipolar transistor T1 in each improved half-bridge power module is kept at a low level throughout the process, the trigger pulses of the first thyristor T2 and the second thyristor T3 are kept at a high level, and the trigger pulse of the third thyristor T4 is kept at a low level;

[0022] In the third stage, the trigger pulse of the insulated gate bipolar transistor T1 in each of the improved half-bridge power modules is kept at a low level throughout, the trigger pulse of the third thyristor T4 is kept at a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a low level;

[0023] In the fourth stage, the trigger pulse of the third thyristor T4 of each improved half-bridge power module is maintained at a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a low level. According to the determined order of putting the improved half-bridge power modules into operation, the insulated gate bipolar transistor T1 in each improved half-bridge power module is set to a high level in sequence to put the corresponding improved half-bridge power module into operation.

[0024] As an optional implementation, in the rectification mode, the four-stage pulse adjustment process is cyclically executed according to a preset sequence, and the polarity distribution of the modulation wave voltage and the bridge arm current in the four stages includes:

[0025] Phase 1: The modulation wave voltage is positive and the bridge arm current transitions from positive to negative;

[0026] The second stage: the modulation wave voltage transitions from positive to negative and the bridge arm current is negative;

[0027] The third stage: the modulation wave voltage transitions from negative to positive and the bridge arm current is negative;

[0028] Phase 4: the modulation wave voltage is positive and the bridge arm current transitions from negative to positive.

[0029] As an optional implementation, in the rectification mode, executing the preset four-stage pulse adjustment process includes:

[0030] In the first stage, the trigger pulse of the third thyristor T4 in each improved half-bridge power module is set to a low level throughout the process;

[0031] Setting the trigger pulse of the insulated gate bipolar transistor T1 of the improved half-bridge power module, in which the trigger pulse of the third thyristor T4 is high at the beginning of this stage, to a high level;

[0032] During the modulation wave voltage reduction process, according to the determined improved half-bridge power module removal order, the trigger pulses of the insulated gate bipolar transistors T1 corresponding to the improved half-bridge power modules in the on-state are sequentially set to a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a high level to remove the corresponding improved half-bridge power modules;

[0033] In the second stage, the trigger pulse of the insulated gate bipolar transistor T1 in each improved half-bridge power module is kept at a low level throughout the process, the trigger pulses of the first thyristor T2 and the second thyristor T3 are kept at a high level, and the trigger pulse of the third thyristor T4 is kept at a low level;

[0034] In the third stage, the trigger pulse of the insulated gate bipolar transistor T1 in each of the improved half-bridge power modules is kept at a low level throughout, the trigger pulse of the third thyristor T4 is kept at a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a low level;

[0035] In the fourth stage, the trigger pulses of the insulated gate bipolar transistor T1, the first thyristor T2 and the second thyristor T3 in each of the improved half-bridge power modules are kept at a low level throughout the process. According to the determined order of putting the improved half-bridge power modules into operation, the third thyristor T4 in each of the improved half-bridge power modules is set to a high level in sequence to put the corresponding improved half-bridge power module into operation.

[0036] As an optional implementation, the method further includes:

[0037] monitoring the capacitor voltage value of each improved half-bridge power module in real time and generating a voltage sorting list;

[0038] According to the voltage sorting list, a cut-off sequence of the improved half-bridge power modules and a start-up sequence of the improved half-bridge power modules are generated.

[0039] As an optional implementation, the method further includes:

[0040] Real-time monitoring of the capacitor voltage value of each full-bridge power module and generating a level supplement sequence;

[0041] During the removal process of the improved half-bridge power modules, if all the improved half-bridge power modules have been removed, then the full-bridge power modules are removed in sequence according to the level supplementation to generate the required modulation wave voltage;

[0042] Furthermore, during the operation of the improved half-bridge power modules, if all the improved half-bridge power modules are currently operated, the full-bridge power modules are operated in sequence according to the level supplementation sequence to generate the required modulation wave voltage.

[0043] In a third aspect, the present application provides a computer device comprising one or more processors and a memory, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the one or more processors, the steps of the method described in the second aspect are performed.

[0044] In a fourth aspect, the present application provides a storage medium storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors execute the steps of the method described in the second aspect.

[0045] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0046] Based on any of the above embodiments, the flexible DC converter valve system and modulation method provided by this application significantly improves operating efficiency in overload scenarios through the coordinated design of a hybrid power module structure and staged pulse control. The system uses a series combination of an improved half-bridge power module and a conventional full-bridge power module. The improved half-bridge power module simplifies the drive logic by sharing a trigger pulse and enhances controllability by utilizing the complementary characteristics of the insulated gate bipolar transistor T1 and the thyristor. The control module performs a four-stage pulse adjustment process in the inverter or rectifier mode based on the zero-crossing limit of the modulation wave voltage and the bridge arm current, managing the trigger state of the switching device in stages. This design enables the system to dynamically adjust the order of power module activation and deactivation based on the real-time transition characteristics of voltage and current, avoiding transient overcurrent and excessive junction temperature of the device under overload conditions. Furthermore, by real-time monitoring of capacitor voltage, a sorted list is generated to optimize module switching timing, and the level supplementation mechanism of the full-bridge power module is utilized to maintain the stability of the modulation wave voltage. This series of technologies eliminates the reliance on current limiting mode or unipolar locking strategies, improves the flexible DC valve's tolerance and grid support reliability under extreme operating conditions such as excessive short-circuit current, and reduces the risk of system instability. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0048] Figure 1 A schematic diagram of the structure of the flexible DC converter valve system related technology provided in one embodiment of the present application;

[0049] Figure 2 A schematic structural diagram of a flexible DC converter valve system provided in one embodiment of the present application;

[0050] Figure 3 A schematic diagram of phased waveforms of an inverter mode of a modulation method for a flexible DC converter valve system provided in one embodiment of the present application;

[0051] Figure 4 A schematic diagram of phased waveforms of a rectification mode of a modulation method for a flexible DC converter valve system provided in one embodiment of the present application;

[0052] Figure 5 This is a diagram of the internal structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0054] See also Figure 1 , Figure 1 A schematic diagram of the structure of the flexible DC converter valve system related technology provided in one embodiment of the present application is shown in FIG. Figure 1 As shown in the figure, in HVDC projects, the converter valve generally adopts a modular multilevel converter (MMC) topology composed of a mixture of full-bridge power modules and improved half-bridge power modules, which is called a flexible DC converter valve. During normal operation of the MMC, for the sake of module safety, it is usually required that the voltage of all modules remain consistent. The MMC valve control has a corresponding sorting unit to sort the modules to maintain voltage stability. Figure 1The figure shows a typical MMC topology. Considering operating conditions such as DC-side fault ride-through and step-down operation, the bridge arm needs to have negative voltage output capability. Therefore, each bridge arm is generally composed of a series mixture of a full-bridge power module and an improved half-bridge power module. Each module consists of a switching device and a capacitor. Different switching states determine the charging and discharging direction of the capacitor, which can control the capacitor voltage.

[0055] The existing flexible DC converter valve is subject to the limitation of the maximum junction temperature in its power module and does not have a high overload capacity. The junction temperature of the device in the overload operating condition will exceed the maximum temperature limit of the device manual. In other words, the overload capacity of the existing flexible DC converter valve topology depends on the high temperature resistance level of the device at its maximum junction temperature. Due to the insufficient overload capacity, this type of flexible DC converter valve topology chooses to adopt a current limiting mode or a single-pole locking strategy when the short-circuit current exceeds the standard. This not only limits the support role of the flexible DC to the power grid, but may also cause system instability. The flexible DC converter valve with overload capacity proposed in this application will alleviate the overcurrent problem of the flexible DC at the source, making the flexible DC more controllable and having a stronger support capability.

[0056] In summary, the technical concept of this application is that the flexible DC converter valve system and modulation method provided by this application significantly improves the operating efficiency in overload scenarios through the coordinated design of hybrid power module structure and staged pulse control. The system adopts a series combination of an improved half-bridge power module and a conventional full-bridge power module, wherein the improved half-bridge power module simplifies the drive logic by sharing a trigger pulse and enhances controllability by utilizing the complementary characteristics of the insulated gate bipolar transistor T1 and the thyristor. Based on the zero-crossing limit of the modulation wave voltage and the bridge arm current, the control module executes a four-stage pulse adjustment process in the inverter or rectification mode, and manages the triggering state of the switching device in stages. This design enables the system to dynamically adjust the power module input and output sequence according to the real-time transition characteristics of voltage and current, avoiding instantaneous overcurrent and excessive junction temperature of the device under overload conditions. Furthermore, by real-time monitoring of the capacitor voltage, a sorted list is generated to optimize the module switching timing, and the level supplement mechanism of the full-bridge power module is used to maintain the stability of the modulation wave voltage. This series of technologies eliminates the reliance on current limiting mode or unipolar locking strategies, improves the flexible DC valve's tolerance and grid support reliability under extreme operating conditions such as excessive short-circuit current, and reduces the risk of system instability.

[0057] The method provided in this application is described in detail below based on corresponding implementation methods in some actual application scenarios.

[0058] See also Figure 2 , Figure 2 A structural diagram of a flexible DC converter valve system provided in one embodiment of the present application is shown in FIG. Figure 2As shown, the system includes: a plurality of target bridge arms, each of the target bridge arms is formed by connecting at least one improved half-bridge power module in series with at least one conventional full-bridge power module, and the switching devices of the improved half-bridge power module include an insulated gate bipolar transistor T1, a first thyristor T2, a second thyristor T3 and a third thyristor T4, and the first thyristor T2 and the second thyristor T3 share a trigger pulse to drive the circuit;

[0059] A control module, configured to control the trigger pulses of the switching devices in the improved half-bridge power module in stages according to the zero-crossing limits of the modulation wave voltage and the bridge arm current;

[0060] The staged control includes executing a preset four-stage pulse adjustment process in an inverter mode or a rectifier mode.

[0061] at the same time, Figure 2 The structure shown is not shown because conventional main circuit equipment such as flexible DC transformers and bridge arm reactors are no different from conventional flexible DC converter valves. Only the structure of the improved half-bridge power module is emphasized.

[0062] The flexible DC converter valve system provided in this application can still use the same control method as traditional flexible DC in its control section, differing in the modulation process. Traditional flexible DC converter valve modulation uses a nearest neighbor modulation strategy, which sequentially activates a corresponding number of power modules based on the size of the modulation wave and the voltage level of each module, thus completing the modulation process. The modulation method provided in this application can be divided into four stages according to the different operating conditions of inversion and rectification. For details, please refer to the relevant implementation method.

[0063] The flexible DC converter valve system provided in this application achieves improved overload capacity through a hybrid series structure with multiple target bridge arms. Each target bridge arm is composed of an improved half-bridge power module connected in series with a conventional full-bridge power module. The improved half-bridge power module uses a switching device combination of an insulated gate bipolar transistor T1, a first thyristor T2, a second thyristor T3, and a third thyristor T4. The first thyristor T2 and the second thyristor T3 share a trigger pulse, significantly simplifying the complexity of the drive circuit. The control module controls the trigger pulses of each switching device in stages based on the zero-crossing limits of the modulation wave voltage and the bridge arm current, executing a preset four-stage pulse adjustment process in either inverter or rectifier mode. This design enables the system to dynamically adjust the power module's switching state under overload conditions such as excessive short-circuit current, preventing the switching device's junction temperature from exceeding the safety limit due to transient current surges. By meticulously managing the power module's state switching in stages, the system can maintain stable operation without relying on current limiting mode or unipolar blocking strategies, thereby enhancing its support capacity and overall reliability for the power grid.

[0064] Based on this, the present application provides a flexible DC converter valve modulation method, which is applied to a control module in a flexible DC converter valve system. The flexible DC converter valve system also includes multiple target bridge arms, each of which is formed by connecting at least one improved half-bridge power module in series with at least one conventional full-bridge power module. The switching devices of the improved half-bridge power module include an insulated gate bipolar transistor T1, a first thyristor T2, a second thyristor T3, and a third thyristor T4. The first thyristor T2 and the second thyristor T3 share a trigger pulse to drive the circuit.

[0065] According to the polarity distribution of the modulation wave voltage and the bridge arm current, the trigger pulse of each switching device in the improved half-bridge power module is controlled in stages;

[0066] The staged control includes executing a preset four-stage pulse adjustment process in an inverter mode or a rectifier mode.

[0067] The flexible DC converter valve modulation method provided in this embodiment is based on the hybrid module series structure of the target bridge arm, and controls the trigger pulse of the switching device in stages through the polarity distribution of the modulation wave voltage and the bridge arm current. A four-stage pulse adjustment process is executed in the inverter or rectification mode to dynamically manage the removal and input timing of the improved half-bridge power module. This method accurately controls the trigger pulse according to the real-time polarity of the voltage and current and the transition state, avoiding the instantaneous overcurrent and local overheating problems of the switching device under overload conditions. Through staged logical control, the system reduces the thermal stress accumulation of the device while maintaining the stability of the modulation wave voltage, improves the tolerance of the converter valve under complex working conditions, and does not require external current limiting intervention, thereby enhancing operational flexibility and reliability.

[0068] As an optional implementation, in the inverter mode, the four-stage pulse adjustment process is cyclically executed according to a preset sequence, and the polarity distribution of the modulation wave voltage and the bridge arm current in the four stages includes:

[0069] Phase 1: the modulation wave voltage is positive and the bridge arm current transitions from negative to positive;

[0070] The second stage: the modulation wave voltage transitions from positive to negative and the bridge arm current is positive;

[0071] The third stage: the modulation wave voltage transitions from negative to positive and the bridge arm current is positive;

[0072] Phase 4: the modulation wave voltage is positive and the bridge arm current transitions from positive to negative.

[0073] This embodiment refines the four-stage pulse adjustment process in the inverter mode, and performs cyclic execution control according to the modulation wave voltage and the bridge arm current polarity and changes. By dividing the transition state of current and voltage into four clear stages, the system can accurately match the timing of power module state switching. For example, the transition period from negative to positive current corresponds to the power module's removal requirement, while the voltage polarity change stage requires the module state to be stable. This timing control avoids the switching device from being subjected to bidirectional current stress at the moment of state switching, thereby suppressing the abnormal increase in junction temperature and improving the response stability of overload conditions in the inverter mode.

[0074] As an optional implementation, in the inverter mode, executing the preset four-stage pulse adjustment process includes:

[0075] In the first stage, the trigger pulse of the insulated gate bipolar transistor T1 in each of the switching devices is set to a low level throughout the process;

[0076] Setting the trigger pulse of the third thyristor T4 of the improved half-bridge power module, in which the trigger pulse of the insulated gate bipolar transistor T1 is high at the beginning of this stage, to a high level;

[0077] During the modulation wave voltage reduction process, according to the determined improved half-bridge power module removal order, the trigger pulses of the third thyristor T4 corresponding to the improved half-bridge power module in the on state are sequentially set to a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a high level to remove the corresponding improved half-bridge power module;

[0078] In the second stage, the trigger pulse of the insulated gate bipolar transistor T1 in each improved half-bridge power module is kept at a low level throughout the process, the trigger pulses of the first thyristor T2 and the second thyristor T3 are kept at a high level, and the trigger pulse of the third thyristor T4 is kept at a low level;

[0079] In the third stage, the trigger pulse of the insulated gate bipolar transistor T1 in each of the improved half-bridge power modules is kept at a low level throughout, the trigger pulse of the third thyristor T4 is kept at a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a low level;

[0080] In the fourth stage, the trigger pulse of the third thyristor T4 of each improved half-bridge power module is maintained at a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a low level. According to the determined order of putting the improved half-bridge power modules into operation, the insulated gate bipolar transistor T1 in each improved half-bridge power module is set to a high level in sequence to put the corresponding improved half-bridge power module into operation.

[0081] This implementation further defines the specific operation of four-stage pulse adjustment in inverter mode. In the first stage, the insulated gate bipolar transistor (IGBT) T1 is completely shut down. During the voltage reduction process, the thyristor triggering state is gradually switched in the order of removal to remove the improved half-bridge power module. Subsequent stages sequentially fix the voltage levels of other switching devices (e.g., maintaining a low voltage level for the thyristors in the second and third stages). This process ensures a smooth and orderly removal of the improved half-bridge power module by locking the triggering states of key components in stages, avoiding current fluctuations and voltage oscillations caused by the simultaneous operation of multiple components. Through refined voltage level control, the system effectively disperses switching losses under overload conditions, reduces the risk of thermal accumulation in components, and improves the continuity of valve operation.

[0082] See also Figure 3 , Figure 3 A schematic diagram of phased waveforms of an inverter mode of a modulation method for a flexible DC converter valve system provided in one embodiment of the present application is shown in FIG. Figure 3 As shown, according to the schematic diagram of the upper bridge arm modulation wave voltage and bridge arm current in a typical inverter mode, the polarity and zero-crossing point of the voltage and current are divided into four typical stages, namely the aforementioned first to fourth stages.

[0083] It should be noted that in this application, Upa represents the modulation wave voltage, ipa represents the bridge arm current, and the subsequent Figure 4 Same thing.

[0084] In the first stage, the modulated wave voltage is positive, and the bridge arm current is positive. From the fourth stage to the first stage, there is a current zero-crossing point. For the submodule in the active state, the trigger pulse to the third thyristor T4 is 1, and the trigger pulses to the first thyristor T2 and the second thyristor T3 are 0, placing the half-bridge power module in the active state. During this stage, as the bridge arm voltage decreases, the trigger pulses to the first thyristor T2T and the second thyristor T3 are set to 1, in ascending order of voltage. The trigger pulse to the third thyristor T4 is simultaneously set to 0, prioritizing the removal of the improved half-bridge power module. At this point, the improved half-bridge power module in the active state is in the charging state.

[0085] In the second stage, the modulation wave voltage is negative and the bridge arm current is positive. Since only the full-bridge power module can generate a negative level, the first thyristor T2 and the second thyristor T3 still maintain the trigger pulse of 1, and the thyristor pulse of the insulated gate bipolar transistor T1 still maintains the trigger pulse of 0.

[0086] In the third phase, the modulating wave voltage is positive, and the bridge arm current is positive. During this phase, the trigger pulses for the first and second thyristors T2 and T3 are set to zero. Because the current does not cross zero during this phase, the thyristors remain cut off. The modulating wave voltage during this phase is generated entirely by the full-bridge power modules according to their sequencing.

[0087] In the fourth phase, the modulation wave voltage is positive and the bridge arm current is negative. Due to the current zero crossing in phase 3-4, all improved half-bridge power modules exit the cut-off state. At this point, pulses are applied to the insulated gate bipolar transistors T1 of the improved half-bridge power modules in descending order of the improved half-bridge power module voltages, according to the requirements of the modulation wave Upa. This activates the improved half-bridge power modules, prioritizing the improved half-bridge power modules. Once the half-bridge power module is depleted, the full-bridge power module is activated. At this point, the activated improved half-bridge power modules are in a discharged state.

[0088] In addition, in the first stage, if the full-bridge power module is not enough to form the modulation wave at that time after all the improved half-bridge power modules are removed, it will be removed in sequence according to the demand for the modulation wave. In the second stage, according to the demand for the modulation wave, it will be reversely put into use. In the second stage, according to the demand for the modulation wave, it will be forwardly put into use according to the sorting of voltage levels. In the fourth stage, if it is still not enough to form the modulation wave at that time after all the improved half-bridge power modules are put into use, it will be put into use in sequence according to the demand for the modulation wave.

[0089] As an optional implementation, in the rectification mode, the four-stage pulse adjustment process is cyclically executed according to a preset sequence, and the polarity distribution of the modulation wave voltage and the bridge arm current in the four stages includes:

[0090] Phase 1: The modulation wave voltage is positive and the bridge arm current transitions from positive to negative;

[0091] The second stage: the modulation wave voltage transitions from positive to negative and the bridge arm current is negative;

[0092] The third stage: the modulation wave voltage transitions from negative to positive and the bridge arm current is negative;

[0093] Phase 4: the modulation wave voltage is positive and the bridge arm current transitions from negative to positive.

[0094] This implementation method designs a four-stage pulse adjustment process for the rectification mode, and performs cyclic control according to the modulation wave voltage and bridge arm current polarity and changes. By binding the current direction change and voltage polarity migration to different stages, the system synchronously optimizes the switching logic of the power module under the rectification condition. For example, the transition period from positive to negative current triggers the removal of the improved half-bridge power module, while the voltage polarity reversal stage maintains the module state. This process ensures that the power module input and removal actions in the rectification mode are strictly matched with the current path changes, avoiding device overstress caused by current reversal, thereby enhancing the system's adaptability under rectification overload conditions.

[0095] As an optional implementation, in the rectification mode, executing the preset four-stage pulse adjustment process includes:

[0096] In the first stage, the trigger pulse of the third thyristor T4 in each improved half-bridge power module is set to a low level throughout the process;

[0097] Setting the trigger pulse of the insulated gate bipolar transistor T1 of the improved half-bridge power module, in which the trigger pulse of the third thyristor T4 is high at the beginning of this stage, to a high level;

[0098] During the modulation wave voltage reduction process, according to the determined improved half-bridge power module removal order, the trigger pulses of the insulated gate bipolar transistors T1 corresponding to the improved half-bridge power modules in the on-state are sequentially set to a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a high level to remove the corresponding improved half-bridge power modules;

[0099] In the second stage, the trigger pulse of the insulated gate bipolar transistor T1 in each improved half-bridge power module is kept at a low level throughout the process, the trigger pulses of the first thyristor T2 and the second thyristor T3 are kept at a high level, and the trigger pulse of the third thyristor T4 is kept at a low level;

[0100] In the third stage, the trigger pulse of the insulated gate bipolar transistor T1 in each of the improved half-bridge power modules is kept at a low level throughout, the trigger pulse of the third thyristor T4 is kept at a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a low level;

[0101] In the fourth stage, the trigger pulses of the insulated gate bipolar transistor T1, the first thyristor T2 and the second thyristor T3 in each of the improved half-bridge power modules are kept at a low level throughout the process. According to the determined order of putting the improved half-bridge power modules into operation, the third thyristor T4 in each of the improved half-bridge power modules is set to a high level in sequence to put the corresponding improved half-bridge power module into operation.

[0102] This implementation refines the four-stage pulse operation in rectification mode. In the first stage, the third thyristor T4 is completely turned off, and as the voltage decreases, the insulated gate bipolar transistor T1 is sequentially switched to disconnect the improved half-bridge power module. Subsequent stages maintain the triggering states of other components (e.g., maintaining a low transistor level in the second and third stages). This design isolates the actions of key components in stages (e.g., prioritizing the locking of the third thyristor T4) to ensure conflict-free disconnection of the improved half-bridge power module. Furthermore, by keeping some components off during the current reverse transition, the reverse recovery losses of the switching devices in rectification mode are reduced, suppressing the rapid rise in junction temperature and thereby improving the system's durability under overload conditions.

[0103] See also Figure 4 , Figure 4 A schematic diagram of phased waveforms of a rectification mode of a flexible DC converter valve system modulation method provided in one embodiment of the present application is shown in FIG. Figure 4 As shown in the figure, the schematic diagram of the upper bridge arm modulation wave voltage and bridge arm current in a typical rectification mode is divided into four typical stages based on the polarity and zero-crossing point boundaries of the voltage and current, namely the first to fourth stages in the rectification mode, but the polarity and zero-crossing point boundaries of the voltage and current here are different from those in the inversion mode.

[0104] In the first stage, the modulated wave voltage is positive and the bridge arm current is negative. During the fourth stage, the current crosses zero. For the submodule in the active state, the trigger pulse to the third thyristor T4 is 0, the trigger pulse to the insulated gate bipolar transistor T1 is set to 1, and the trigger pulses to the first thyristor T2 and the second thyristor T3 are 0. The half-bridge power module is in the active state. During this stage, as the bridge arm voltage decreases, the trigger pulses to the first thyristor T2 and the second thyristor T3 are set to 1, in descending order of voltage. Simultaneously, the trigger pulse to the insulated gate bipolar transistor T1 is set to 0, prioritizing the disconnection of the improved half-bridge power module. At this point, the improved half-bridge power module in the active state is in the discharging state.

[0105] In the second stage, the modulation wave voltage is negative and the bridge arm current is negative. Since only the full-bridge power module can generate a negative level, the first thyristor T2 and the second thyristor T3 still maintain the trigger pulse of 1, and the third thyristor T4 still maintains the trigger pulse of 0.

[0106] In the third phase, the modulating wave voltage is positive and the bridge arm current is negative. During this phase, the trigger pulses for the first and second thyristors T2 and T3 are set to zero. Because the current does not cross zero during this phase, the thyristors remain cut off. The modulating wave voltage during this phase is generated entirely by the full-bridge power modules according to their sequencing.

[0107] In the fourth stage, the modulation wave voltage is positive, and the bridge arm current is positive. Since the current crosses zero between the third and fourth stages, all improved half-bridge power modules exit the cut-off state. At this point, pulses are applied to the third thyristor T4 of each improved half-bridge power module in ascending order of the improved half-bridge power module voltage, based on the modulation wave voltage requirements. This activates the improved half-bridge power module, prioritizing the improved half-bridge power module. Once the half-bridge power module is depleted, the full-bridge power module is activated. At this point, the activated improved half-bridge power module is in a charging state.

[0108] In addition, in the first stage, if the full-bridge power module is not enough to form the modulation wave at that time after all the improved half-bridge power modules are removed, it will be removed in sequence according to the demand for the modulation wave. In the second stage, according to the demand for the modulation wave, it will be reversely put into use. In the second stage, according to the demand for the modulation wave, it will be forwardly put into use according to the sorting of voltage levels. In the fourth stage, if it is still not enough to form the modulation wave at that time after all the improved half-bridge power modules are put into use, it will be put into use in sequence according to the demand for the modulation wave.

[0109] As an optional implementation, the method further includes:

[0110] monitoring the capacitor voltage value of each improved half-bridge power module in real time and generating a voltage sorting list;

[0111] According to the voltage sorting list, a cut-off sequence of the improved half-bridge power modules and a start-up sequence of the improved half-bridge power modules are generated.

[0112] This implementation adds a real-time monitoring and sorting process for capacitor voltage values. By generating a voltage sorting list for the improved half-bridge power modules, the order for removing and switching on the improved half-bridge power modules is dynamically generated. This strategy avoids the risk of overvoltage or undervoltage caused by voltage imbalance between modules based on the actual distribution of capacitor voltages (e.g., high-voltage modules are removed first). At the same time, the capacitor voltage of the full-bridge power module is monitored in real time and a level supplement sequence is generated to ensure that the full-bridge power module supplements the modulation wave voltage demand after the improved half-bridge power module is completely removed. This collaborative design optimizes the voltage support capability of the hybrid module and reduces system oscillations caused by voltage mutations under overload conditions.

[0113] As an optional implementation, the method further includes:

[0114] Real-time monitoring of the capacitor voltage value of each full-bridge power module and generating a level supplement sequence;

[0115] During the removal process of the improved half-bridge power modules, if all the improved half-bridge power modules have been removed, then the full-bridge power modules are removed in sequence according to the level supplementation to generate the required modulation wave voltage;

[0116] Furthermore, during the operation of the improved half-bridge power modules, if all the improved half-bridge power modules are currently operated, the full-bridge power modules are operated in sequence according to the level supplementation sequence to generate the required modulation wave voltage.

[0117] This implementation further provides a level-compensation mechanism for full-bridge power modules. After all improved half-bridge power modules have been removed or switched on, the system dynamically adjusts the full-bridge power module status based on the level-compensation sequence. By controlling the capacitor voltage sequencing and the compensation timing, the continuity of the modulated wave voltage during module switching is ensured. This design avoids voltage sags or interruptions when switching between improved half-bridge and full-bridge power modules, maintaining voltage output stability, especially under overload conditions, thereby improving the system's dynamic response and anti-disturbance performance.

[0118] Schematically, as Figure 5 As shown, Figure 5 This is a schematic diagram of the internal structure of a computer device provided in an embodiment of the present application. The computer device 300 can be provided as a server. Figure 5 Computer device 300 includes a processing component 302, which further includes one or more processors, and a memory resource represented by memory 301 for storing instructions executable by processing component 302, such as an application. The application stored in memory 301 may include one or more modules, each corresponding to a set of instructions. In addition, processing component 302 is configured to execute the instructions to perform the method of any of the above embodiments.

[0119] The computer device 300 may further include a power supply component 303 configured to perform power management of the computer device 300, a wired or wireless network interface 304 configured to connect the computer device 300 to a network, and an input / output (I / O) interface 305. The computer device 300 may operate based on an operating system stored in the memory 301, such as Windows Server™, Mac OS X™, Unix™, Linux™, Free BSD™, or the like.

[0120] Those skilled in the art will understand that Figure 5The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0121] An embodiment of the present application provides a storage medium storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors execute a method as provided in any embodiment.

[0122] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0123] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can be referenced to each other.

[0124] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A flexible DC converter valve system, characterized in that: The system comprises: Multiple target bridge arms, each of the target bridge arms is formed by connecting at least one improved half-bridge power module in series with at least one conventional full-bridge power module, and the switching devices of the improved half-bridge power module include an insulated gate bipolar transistor T1, a first thyristor T2, a second thyristor T3, and a third thyristor T4, and the first thyristor T2 and the second thyristor T3 share a trigger pulse to drive the circuit; A control module, configured to control the trigger pulses of the switching devices in the improved half-bridge power module in stages according to the zero-crossing limits of the modulation wave voltage and the bridge arm current; The staged control includes executing a preset four-stage pulse adjustment process in an inverter mode or a rectifier mode.

2. A method for modulating a flexible DC converter valve, characterized in that: The method is applied to a control module in a flexible DC converter valve system, wherein the flexible DC converter valve system further includes a plurality of target bridge arms, each of which is formed by connecting at least one improved half-bridge power module in series with at least one conventional full-bridge power module, and the switching devices of the improved half-bridge power module include an insulated gate bipolar transistor T1, a first thyristor T2, a second thyristor T3, and a third thyristor T4, and the first thyristor T2 and the second thyristor T3 share a trigger pulse to drive the circuit; According to the polarity distribution of the modulation wave voltage and the bridge arm current, the trigger pulse of each switching device in the improved half-bridge power module is controlled in stages; The staged control includes executing a preset four-stage pulse adjustment process in an inverter mode or a rectifier mode.

3. The method according to claim 2, characterized in that In the inverter mode, the four-stage pulse adjustment process is executed cyclically according to a preset sequence, and the polarity distribution of the modulation wave voltage and the bridge arm current in the four stages includes: Phase 1: the modulation wave voltage is positive and the bridge arm current transitions from negative to positive; The second stage: the modulation wave voltage transitions from positive to negative and the bridge arm current is positive; The third stage: the modulation wave voltage transitions from negative to positive and the bridge arm current is positive; Phase 4: the modulation wave voltage is positive and the bridge arm current transitions from positive to negative.

4. The method according to claim 3, characterized in that In the inverter mode, the preset four-stage pulse adjustment process is executed, including: In the first stage, the trigger pulse of the insulated gate bipolar transistor T1 in each of the switching devices is set to a low level throughout the process; Setting the trigger pulse of the third thyristor T4 of the improved half-bridge power module, in which the trigger pulse of the insulated gate bipolar transistor T1 is high at the beginning of this stage, to a high level; During the modulation wave voltage reduction process, according to the determined improved half-bridge power module removal order, the trigger pulses of the third thyristor T4 corresponding to the improved half-bridge power module in the on state are sequentially set to a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a high level to remove the corresponding improved half-bridge power module; In the second stage, the trigger pulse of the insulated gate bipolar transistor T1 in each improved half-bridge power module is kept at a low level throughout the process, the trigger pulses of the first thyristor T2 and the second thyristor T3 are kept at a high level, and the trigger pulse of the third thyristor T4 is kept at a low level; In the third stage, the trigger pulse of the insulated gate bipolar transistor T1 in each of the improved half-bridge power modules is kept at a low level throughout, the trigger pulse of the third thyristor T4 is kept at a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a low level; In the fourth stage, the trigger pulse of the third thyristor T4 of each improved half-bridge power module is maintained at a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a low level. According to the determined order of putting the improved half-bridge power modules into operation, the insulated gate bipolar transistor T1 in each improved half-bridge power module is set to a high level in sequence to put the corresponding improved half-bridge power module into operation.

5. The method according to claim 2, characterized in that In the rectification mode, the four-stage pulse adjustment process is executed cyclically according to a preset sequence, and the polarity distribution of the modulation wave voltage and the bridge arm current in the four stages includes: Phase 1: The modulation wave voltage is positive and the bridge arm current transitions from positive to negative; The second stage: the modulation wave voltage transitions from positive to negative and the bridge arm current is negative; The third stage: the modulation wave voltage transitions from negative to positive and the bridge arm current is negative; Phase 4: the modulation wave voltage is positive and the bridge arm current transitions from negative to positive.

6. The method according to claim 5, characterized in that In the rectification mode, the preset four-stage pulse adjustment process is executed, including: In the first stage, the trigger pulse of the third thyristor T4 in each improved half-bridge power module is set to a low level throughout the process; Setting the trigger pulse of the insulated gate bipolar transistor T1 of the improved half-bridge power module, in which the trigger pulse of the third thyristor T4 is high at the beginning of this stage, to a high level; During the modulation wave voltage reduction process, according to the determined improved half-bridge power module removal order, the trigger pulses of the insulated gate bipolar transistors T1 corresponding to the improved half-bridge power modules in the on-state are sequentially set to a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a high level to remove the corresponding improved half-bridge power modules; In the second stage, the trigger pulse of the insulated gate bipolar transistor T1 in each improved half-bridge power module is kept at a low level throughout the process, the trigger pulses of the first thyristor T2 and the second thyristor T3 are kept at a high level, and the trigger pulse of the third thyristor T4 is kept at a low level; In the third stage, the trigger pulse of the insulated gate bipolar transistor T1 in each of the improved half-bridge power modules is kept at a low level throughout, the trigger pulse of the third thyristor T4 is kept at a low level, and the trigger pulses of the first thyristor T2 and the second thyristor T3 are set to a low level; In the fourth stage, the trigger pulses of the insulated gate bipolar transistor T1, the first thyristor T2 and the second thyristor T3 in each of the improved half-bridge power modules are kept at a low level throughout the process. According to the determined order of putting the improved half-bridge power modules into operation, the third thyristor T4 in each of the improved half-bridge power modules is set to a high level in sequence to put the corresponding improved half-bridge power module into operation.

7. The method according to claim 4 or 6, characterized in that The method further comprises: monitoring the capacitor voltage value of each improved half-bridge power module in real time and generating a voltage sorting list; According to the voltage sorting list, a cut-off sequence of the improved half-bridge power modules and a start-up sequence of the improved half-bridge power modules are generated.

8. The method according to claim 7, characterized in that The method further comprises: Real-time monitoring of the capacitor voltage value of each full-bridge power module and generating a level supplement sequence; During the removal process of the improved half-bridge power modules, if all the improved half-bridge power modules have been removed, then the full-bridge power modules are removed in sequence according to the level supplementation to generate the required modulation wave voltage; Furthermore, during the operation of the improved half-bridge power modules, if all the improved half-bridge power modules are currently operated, the full-bridge power modules are operated in sequence according to the level supplementation sequence to generate the required modulation wave voltage.

9. A computer device, characterized in that: The method comprises one or more processors and a memory, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the one or more processors, the steps of the method according to any one of claims 2 to 8 are performed.

10. A storage medium, characterized in that: The storage medium stores computer-readable instructions, which, when executed by one or more processors, enable the one or more processors to perform the steps of the method according to any one of claims 2 to 8.

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