Gallium nitride electronic device and preparation method thereof

Abstract

The invention discloses a gallium nitride electronic device and a preparation method thereof, and belongs to the technical field of semiconductors, the gallium nitride electronic device comprises a gallium nitride substrate and a semiconductor structure layer arranged on the gallium nitride substrate; the gallium nitride substrate is provided with shallow-energy-level donor impurities and deep-energy-level acceptor impurities, the deep-energy-level acceptor impurities are used for compensating the shallow-energy-level donor impurities, and the deep-energy-level acceptor impurities are metal impurities; a compensation layer is arranged at the interface of the gallium nitride substrate and the semiconductor structure layer, and the concentration of deep-energy-level acceptor impurities in the compensation layer is larger than that of the deep-energy-level acceptor impurities in the gallium nitride substrate. Metal impurities are doped in the gallium nitride substrate to serve as deep-energy-level acceptor impurities to compensate shallow-energy-level donor impurities, the concentration of impurity atoms adsorbed on the surface of the gallium nitride substrate can be reduced, and the performance of a gallium nitride electron tube device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and more specifically, relates to a gallium nitride electronic device and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN)-based semiconductor materials possess excellent properties, including wide bandgap, high breakdown voltage, high strong-field drift velocity, high-temperature resistance, and radiation resistance. The GaN-based High Electron Mobility Transistor (HEMT) structure generates a high-density, high-mobility two-dimensional electron gas, making it particularly suitable for the production of high-voltage, high-efficiency, high-density, and high-power microwave and millimeter-wave devices. GaN-based HEMT transistors are widely used in cutting-edge equipment operating in microwave and millimeter-wave frequency bands, and have crucial applications in phased array radar, aerospace, smart weapons, satellite communications, and electronic warfare.

[0003] GaN homogeneous substrates obtained by the hydride vapor phase epitaxy (HVPE) method, or GaN substrate materials obtained by the metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE) methods, will have a high concentration of silicon (Si) impurities during the growth process and storage process. The sources of Si impurities are mainly adsorption during the storage process of the substrate and the background Si concentration of the substrate itself. If the GaN single crystal substrate is exposed to air during storage, the surface will adsorb Si impurities in the air (such as silicon dioxide or silicon particles). This adsorption has a time-accumulating effect. The longer the storage time, the greater the adsorption amount, resulting in a significant increase in the Si concentration at the interface. During the growth of GaN single crystals, trace amounts of Si elements may be introduced into the raw materials or growth environment, forming the "background Si concentration" of the substrate. In the subsequent epitaxial growth or heat treatment process, high temperature will accelerate the diffusion of Si, causing it to accumulate at the interface. As a shallow donor, Si can cause an n-type conductive layer to form on the GaN substrate surface, increasing parasitic capacitance and reducing the switching speed of HEMT devices. Furthermore, Si impurities can induce parasitic conductive channels at the homoepitaxial regrowth interface, causing leakage in the GaN buffer layer of the aluminum gallium nitride / gallium nitride heterojunction material. This can lead to poor pinch-off characteristics in HEMT devices and poor electrical isolation between devices on the same chip.

[0004] In the prior art, carbon doping is commonly used to offset leakage in GaN HEMT devices caused by Si impurities. Carbon doping compensates for the donor properties of Si, and carbon, acting as an acceptor impurity, interacts with Si through a charge compensation mechanism, reducing background carrier concentration and improving device breakdown voltage. However, carbon doping of GaN layers in HEMT devices presents challenges in terms of device performance, not only requiring epitaxial growth and a lengthy process, but also manifests itself in two key aspects. Firstly, the carbon doping concentration is closely related to MOCVD growth conditions. Low temperatures (below 1000°C) and low V / III ratios (below 2000) significantly increase the carbon concentration. This, however, is accompanied by a three-dimensional island growth pattern, resulting in increased surface roughness (RMS greater than 2nm) and deep pit defects (greater than 50nm in depth), which directly impact the device breakdown voltage. Secondly, carbon atoms occupying nitrogen sites form deep energy traps (approximately 0.9eV), which couple with the piezoelectric field generated by the spontaneous polarization of the AlGaN barrier layer, reducing the two-dimensional electron gas mobility.

[0005] Conventional surface treatment methods (such as cleaning) cannot effectively reduce the concentration of Si impurity atoms or protect the GaN regrowth interface from damage. While existing technologies can address the issue of Si impurity leakage through carbon doping, this can still negatively impact device performance. Therefore, effectively reducing the concentration of impurity atoms (especially Si atoms) adsorbed on the surface of GaN homogeneous substrates and improving the performance of GaN HEMT devices remains a pressing technical challenge. Summary of the Invention

[0006] In response to the shortcomings of the existing technology, the present invention provides a gallium nitride electronic device and a method for preparing the same. The purpose of the present invention is to solve the problem that when reducing the concentration of impurity atoms adsorbed on the surface of the gallium nitride substrate, the gallium nitride electronic device will cause severe leakage and low output power.

[0007] According to one aspect of the present invention, there is provided a gallium nitride electronic device, comprising a gallium nitride substrate and a semiconductor structure layer disposed on the gallium nitride substrate;

[0008] The gallium nitride substrate contains shallow energy level donor impurities and deep energy level acceptor impurities, the deep energy level acceptor impurities are used to compensate for the shallow energy level donor impurities, and the deep energy level acceptor impurities are metal impurities;

[0009] A compensation layer is provided at the interface between the gallium nitride substrate and the semiconductor structure layer, and the concentration of deep energy level acceptor impurities in the compensation layer is greater than the concentration of deep energy level acceptor impurities in the gallium nitride substrate.

[0010] Preferably, the melting point of the deep energy level acceptor impurity is greater than the decomposition temperature of gallium nitride;

[0011] And / or, the material of the compensation layer includes GaN;

[0012] And / or, the deep energy level acceptor impurities are Fe impurities, Ni impurities or Mn impurities;

[0013] And / or, the concentration of Fe impurities in the gallium nitride substrate is 5×10 17 cm- 3 1×10 19 cm- 3 ;

[0014] And / or, the concentration of Fe impurities in the compensation layer is 5×10 18 cm- 3 ~5×10 19 cm- 3 ;

[0015] And / or, the thickness of the compensation layer is 20 nm to 60 nm;

[0016] And / or, the compensation layer is formed at a temperature of 850°C to 1100°C.

[0017] Preferably, the gallium nitride electronic device is a HEMT.

[0018] Preferably, the semiconductor structure layer comprises a buffer layer, a channel layer and a barrier layer sequentially arranged in a direction away from the gallium nitride substrate, and the barrier layer has a groove;

[0019] The semiconductor structure layer further includes a dielectric layer and a passivation layer, wherein the dielectric layer is arranged on the inner wall and the bottom of the groove, and the passivation layer is arranged on the barrier layer;

[0020] The gallium nitride electronic device further includes a source electrode, a drain electrode, and a gate electrode, wherein the gate electrode covers the dielectric layer; the source electrode and the drain electrode are arranged on a side of the barrier layer away from the gallium nitride substrate and are spaced apart;

[0021] The buffer layer and the channel layer are made of GaN; and / or the barrier layer is made of AlGaN; and / or the sum of the thicknesses of the buffer layer and the compensation layer is 80 nm to 120 nm.

[0022] According to another aspect of the present invention, a method for preparing a gallium nitride electronic device is provided, comprising:

[0023] Providing a first gallium nitride substrate; wherein the first gallium nitride substrate contains shallow-level donor impurities and deep-level acceptor impurities, and the deep-level acceptor impurities are metal impurities, and the deep-level acceptor impurities are used to compensate for the shallow-level donor impurities;

[0024] performing a heat treatment on the first gallium nitride substrate and introducing a growth source to form a gallium nitride substrate and a compensation layer;

[0025] forming a semiconductor structure layer on the compensation layer;

[0026] The concentration of deep energy level acceptor impurities in the compensation layer is greater than the concentration of deep energy level acceptor impurities in the gallium nitride substrate.

[0027] Preferably, the semiconductor structure layer includes a buffer layer, and the material of the buffer layer is the same as that of the compensation layer; the step of heat-treating the first gallium nitride substrate and introducing a growth source to form the gallium nitride substrate and the compensation layer includes:

[0028] introducing hydrogen into the growth chamber and performing a heat treatment on the first gallium nitride substrate to gradually decompose the first gallium nitride substrate from the surface and enrich the deep level acceptor impurities on the surface of the remaining portion of the first gallium nitride substrate, thereby obtaining a second gallium nitride substrate having the deep level acceptor impurities enriched on the surface;

[0029] The growth source is introduced into the growth chamber to form the gallium nitride substrate, the compensation layer, and the buffer layer which are stacked in sequence.

[0030] Preferably, the step of introducing the growth source into the growth chamber to form the gallium nitride substrate, the compensation layer, and the buffer layer stacked in sequence comprises:

[0031] introducing the growth source into the growth chamber so that deep-level acceptor impurities on the surface of the second gallium nitride substrate and the growth source form the compensation layer, and the second gallium nitride substrate is transformed into the gallium nitride substrate;

[0032] continuing to introduce the growth source into the growth chamber to form the buffer layer on the compensation layer;

[0033] Wherein, the thickness of the compensation layer is 20 nm to 60 nm, and / or the sum of the thicknesses of the buffer layer and the compensation layer is 80 nm to 120 nm.

[0034] Preferably, the growth source includes a gallium source and a nitrogen source, and the preparation of the buffer layer includes:

[0035] At a temperature of 1050° C. to 1100° C., a nitrogen source with a flow rate of 1500-2000 sccm, a gallium source with a flow rate of 50-100 sccm, and a carrier gas with a flow rate of 2000-3000 sccm are introduced to deposit the buffer layer.

[0036] Preferably, the deep energy level acceptor impurities are Fe impurities, and the preparation process of the first gallium nitride substrate is:

[0037] At a temperature of 1000° C. to 1050° C., introducing a nitrogen source at a rate of 1000 ml / min to 1100 ml / min, a chlorine source at a rate of 50 ml / min to 55 ml / min, and a doped iron source at a rate of 100 ml / min to 120 ml / min into a reaction chamber to prepare the first gallium nitride substrate;

[0038] The introduction time is 20 min to 200 min, and the concentration of Fe impurities in the first gallium nitride substrate is 5×10 17 cm -3 ~1×10 19 cm -3 .

[0039] Preferably, in the heat treatment process, the heat treatment temperature is 850°C to 1100°C;

[0040] And / or, the semiconductor structure layer further includes a channel layer and a barrier layer, and growing the semiconductor structure layer on the substrate with deep energy level acceptor impurities enriched on the surface specifically includes:

[0041] forming the channel layer and the barrier layer in sequence on the buffer layer, thereby forming the semiconductor structure layer;

[0042] And / or, the method further comprises:

[0043] A source electrode, a drain electrode and a gate electrode are formed on the semiconductor structure layer.

[0044] Preferably, the material of the channel layer includes GaN;

[0045] Under the conditions of a temperature of 1100° C. to 1150° C. and a pressure of 80 Torr to 100 Torr, a gallium source and a nitrogen source are introduced into a reaction chamber to deposit the channel layer with a thickness of 0.8-2.5 μm on the buffer layer;

[0046] And / or, the material of the barrier layer includes Al x Ga 1-x N, 0.1≤x≤0.15;

[0047] Under the conditions of a temperature of 1060° C. to 1100° C. and a pressure of 60 Torr to 80 Torr, a gallium source, an aluminum source, and a nitrogen source are introduced into the reaction chamber to deposit the barrier layer with a thickness of 100-300 nm on the channel layer;

[0048] And / or, forming a source electrode, a drain electrode and a gate electrode on the semiconductor structure layer includes:

[0049] Etching the semiconductor structure layer to form a groove with a depth of 15nm-30nm;

[0050] Depositing a first dielectric layer with a thickness of 2-8 nm and a second dielectric layer with a thickness of 2-10 nm on the inner wall and bottom of the groove in sequence to obtain a dielectric layer;

[0051] Depositing a passivation layer with a thickness of 80 nm to 150 nm on the surface of the semiconductor structure layer not covered by the dielectric layer; etching a portion of the passivation layer until the semiconductor structure layer is exposed to form a drain region and a source region;

[0052] The gate electrode is deposited on the dielectric layer, and the source electrode and the drain electrode are deposited in the source region and the drain region respectively; wherein the source electrode and the drain electrode are spaced apart.

[0053] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0054] (1) The present invention provides a gallium nitride electronic device, wherein the gallium nitride substrate has shallow energy level donor impurities and deep energy level acceptor impurities, and the deep energy level acceptor impurities are metal impurities; by introducing metal impurities into the gallium nitride substrate to form a metal-doped gallium nitride substrate, the background carrier concentration is compensated by utilizing the characteristics of the deep acceptor energy level of metal ions, thereby compensating the concentration of impurity atoms adsorbed on the surface of the gallium nitride substrate, especially the concentration of Si atoms, thereby effectively solving the problems of excessive carbon concentration and deep energy level traps formed by carbon atoms occupying nitrogen sites in traditional carbon doping methods, resulting in serious leakage and low output power of gallium nitride-based high electron mobility transistor devices, thereby improving the quality of gallium nitride electronic devices.

[0055] (2) The present invention provides a method for preparing a gallium nitride electronic device, providing a first gallium nitride substrate having shallow energy level donor impurities and deep energy level acceptor impurities, wherein the deep energy level acceptor impurities are metal impurities. The first gallium nitride substrate is heat-treated and a growth source is introduced, so that the metal impurities are thermally decomposed at high temperature and remain on the surface of the substrate, thereby achieving effective compensation of Si, avoiding many challenges brought about by the use of carbon doping, simplifying the preparation process, and solving the problems of complex process and high cost of traditional carbon doping methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A schematic diagram showing the relationship between Si impurity concentration and structure depth provided in an embodiment of the present invention;

[0057] Figure 2 A schematic structural diagram of a gallium nitride electronic device provided by an embodiment of the present invention;

[0058] Figure 3A flow chart of a method for preparing a gallium nitride electronic device provided in an embodiment of the present invention;

[0059] Figure 4 This is a schematic diagram of the device structure after the buffer layer is prepared according to the preparation method of an embodiment of the present invention;

[0060] Figure 5 This is a schematic diagram of the device structure after the channel layer is prepared according to the preparation method of an embodiment of the present invention;

[0061] Figure 6 This is a schematic diagram of the device structure after the barrier layer is prepared according to the preparation method of an embodiment of the present invention;

[0062] Figure 7 Schematic diagram of the relationship between Fe impurity concentration and structural depth in an embodiment of the present invention that has undergone in-situ heat treatment and has not undergone in-situ heat treatment.

[0063] Explanation of the reference numerals: 1 is a gallium nitride substrate, 2 is a compensation layer, 3 is a semiconductor structure layer, 31 is a buffer layer, 32 is a channel layer, 33 is a barrier layer, 34 is a dielectric layer, 341 is a first dielectric layer, 342 is a second dielectric layer, 35 is a passivation layer, 4 is a source electrode, 5 is a drain electrode, and 6 is a gate electrode. DETAILED DESCRIPTION

[0064] In view of the shortcomings of the prior art, the inventors of this case, after long-term research and extensive practice, have proposed the technical solution of the present invention. The following will further explain this technical solution, its implementation process and principles.

[0065] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0066] In addition, in the description of the present invention, it should be understood that the terms "upper", "lower", "inside", "outside", "horizontal", "vertical", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0067] Throughout this specification, references to terms such as "one embodiment," "an embodiment," or "the embodiment" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. Throughout this specification, the illustrative use of these terms does not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0068] See Figure 1 , Figure 1 A schematic diagram of the relationship between Si impurity concentration and structure depth provided in an embodiment of the present invention, Figure 1 The relationship between Si impurity concentration and structure depth is shown. The depth of the protrusion corresponds to the position of the substrate interface. It can be seen that the Si impurity concentration at the substrate interface can be as high as 5E19cm- 3 This high Si impurity concentration greatly reduces the performance of GaN electronic devices. Therefore, how to effectively reduce the concentration of impurity atoms (especially Si atoms) adsorbed on the surface of the GaN substrate and improve the performance of GaN-based high electron mobility transistor devices is a technical problem that needs to be solved urgently.

[0069] The first aspect of the present invention provides a gallium nitride electronic device. Figure 2 , Figure 2 This is a schematic structural diagram of a gallium nitride electronic device provided in an embodiment of the present invention. The gallium nitride electronic device includes a gallium nitride substrate 1 and a semiconductor structure layer 3 provided on the gallium nitride substrate 1.

[0070] The gallium nitride substrate 1 contains shallow-level donor impurities and deep-level acceptor impurities. The deep-level acceptor impurities are used to compensate for the shallow-level donor impurities and are metallic impurities. A compensation layer 2 is provided at the interface between the gallium nitride substrate 1 and the semiconductor structure layer 3. The concentration of the deep-level acceptor impurities in the compensation layer 2 is greater than that in the gallium nitride substrate 1.

[0071] The use of deep-level acceptor impurities to compensate for shallow-level donor impurities effectively solves the problems of excessive carbon concentration and deep-level traps formed by carbon atoms occupying nitrogen sites in traditional carbon doping methods, resulting in severe leakage and low output power in gallium nitride-based high electron mobility transistor devices, thereby improving the quality of gallium nitride electronic devices.

[0072] Preferably, the melting point of the deep level acceptor impurity is greater than the decomposition temperature of GaN.

[0073] Preferably, the deep energy level acceptor impurities are Fe impurities, Ni impurities or Mn impurities; the Fe impurity concentration in the gallium nitride substrate 1 is 5×10 17 cm -3~1×10 19 cm -3 ; The Fe impurity concentration in the compensation layer 2 is 5×10 18 cm -3 ~5×10 19 cm -3 The Fe impurity concentration in the gallium nitride substrate 1 is, for example, 5×10 17 cm -3 , 6×10 17 cm -3 , 7×10 17 cm -3 , 8×10 17 cm -3 , 9×10 17 cm -3 , 1×10 18 cm -3 , 2×10 18 cm -3 , 3×10 18 cm -3 , 4×10 18 cm -3 , 5×10 18 cm -3 , 6×10 18 cm -3 , 7×10 18 cm -3 , 8×10 18 cm -3 , 9×10 18 cm -3 or 1×10 19 cm -3 The Fe impurity concentration in the compensation layer 2 is, for example, 5×10 18 cm -3 , 6×10 18 cm -3 , 7×10 18 cm -3 , 8×10 18 cm -3 , 9×10 18 cm -3 , 1×10 19 cm -3 , 2×10 19 cm -3 , 3×10 19 cm -3 , 4×10 19 cm -3 or 5×10 19 cm -3 .

[0074] Furthermore, the compensation layer 2 has a thickness of 20 nm to 60 nm, and is formed at a temperature of 850° C. to 1100° C. Preferably, the thickness of the compensation layer 2 is, for example, 20 nm, 30 nm, 40 nm, 50 nm, or 60 nm, and the compensation layer 2 is formed at a temperature of, for example, 850° C., 900° C., 950° C., 1000° C., 1050° C., or 1100° C.

[0075] Further, such as Figure 2 As shown, the semiconductor structure layer 3 includes a buffer layer 31, a channel layer 32, and a barrier layer 33, which are sequentially arranged in a direction away from the gallium nitride substrate 1. The barrier layer 33 has a groove. The semiconductor structure layer 3 also includes a dielectric layer 34 and a passivation layer 35. The dielectric layer 34 is arranged on the inner wall and bottom of the groove, and the passivation layer 35 is arranged on the barrier layer 33.

[0076] The gallium nitride electronic device further includes a source electrode 4, a drain electrode 5, and a gate electrode 6. The gate electrode 6 covers the dielectric layer 34. The source electrode 4 and the drain electrode 5 are disposed on a side of the barrier layer 33 away from the gallium nitride substrate 1 and are spaced apart.

[0077] Furthermore, the buffer layer 31 and the channel layer 32 are made of GaN, and the barrier layer 33 is made of AlGaN. x Ga 1-x N, 0.1≤x≤0.15. The buffer layer 31 is, for example, a GaN buffer layer, the channel layer 32 is, for example, a GaN channel layer, and the barrier layer 33 is, for example, an Al x Ga 1-x N barrier layer, channel layer 32 and barrier layer 33 form a heterojunction structure Al x Ga 1-x N / GaN, Al x Ga 1-x The N / GaN heterojunction structure produces a high concentration of two-dimensional electron gas through spontaneous polarization and piezoelectric polarization, giving gallium nitride electronic devices the advantages of high current density, low on-resistance, and high power density.

[0078] Furthermore, the sum of the thicknesses of the buffer layer 31 and the compensation layer 2 is 80 nm to 120 nm. The thickness of the channel layer 32 is 0.8 μm to 2.5 μm. The thickness of the barrier layer 33 is 100 nm to 300 nm. Preferably, the thickness of the compensation layer 2 is, for example, 30 nm, the thickness of the buffer layer 31 is, for example, 60 nm, the thickness of the channel layer 32 is, for example, 0.8 μm, 1.0 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2.0 μm, 2.2 μm, or 2.5 μm, and the thickness of the barrier layer 33 is, for example, 100 nm, 120 nm, 140 nm, 160 nm, 180 nm, 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, or 300 nm.

[0079] The second aspect of the present invention provides a method for preparing a gallium nitride electronic device, Figure 2 Gallium nitride electronic device in the illustrated embodiment. Figure 3 The preparation method includes steps S100 to S300.

[0080] Step S100 , providing a first gallium nitride substrate; wherein the first gallium nitride substrate contains shallow-level donor impurities and deep-level acceptor impurities, and the deep-level acceptor impurities are metal impurities, and the deep-level acceptor impurities are used to compensate for the shallow-level donor impurities.

[0081] In this embodiment, a metal-doped gallium nitride substrate is selected when fabricating gallium nitride electronic devices (such as a GaN-based HEMT structure). Metal-doped gallium nitride substrates offer the following advantages when forming GaN-based HEMT structures: The metal, acting as an acceptor impurity, can compensate for the background electron concentration in the GaN, making the GaN material semi-insulating and thereby increasing the substrate's resistivity. This is crucial for HEMT devices, as a high-resistivity substrate can reduce leakage current and improve device performance and reliability. Furthermore, metal doping can improve the device's high-frequency characteristics, making it more suitable for high-frequency, high-power devices.

[0082] In step S200 , the first gallium nitride substrate is subjected to a heat treatment and a growth source is introduced to form a gallium nitride substrate and a compensation layer, wherein the concentration of deep-level acceptor impurities in the compensation layer is greater than the concentration of deep-level acceptor impurities in the gallium nitride substrate.

[0083] Step S300: forming a semiconductor structure layer on the compensation layer.

[0084] Under the condition of temperature of 1000℃~1050℃, a nitrogen source at a flow rate of 1000ml / min~1100ml / min, a chlorine source at a flow rate of 50ml / min~55ml / min, and a doped iron source at a flow rate of 100ml / min~120ml / min are introduced into the reaction chamber to prepare a first gallium nitride substrate, wherein the deep energy level acceptor impurities in the first gallium nitride substrate are Fe impurities. For example, the temperature can be 1000℃, 1010℃, 1020℃, 1030℃, 1040℃ or 1050℃; the nitrogen source can be NH3, and the flow rate of the nitrogen source can be 1000ml / min, 1010ml / min, 1020ml / min, 1030ml / min, 1040ml / min, 1050ml / min, 1060ml / min, 1070ml / min, 1080ml / min, 1090ml / min or 1100ml / min; the chlorine source can be HCl, chlorine The flow rate of the source can be 50ml / min, 51ml / min, 52ml / min, 53ml / min, 54ml / min or 55ml / min; the doped iron source can be ferrocene, and the flow rate of the doped iron source can be 100ml / min, 102ml / min, 104ml / min, 106ml / min, 108ml / min, 110ml / min, 112ml / min, 114ml / min, 116ml / min, 118ml / min or 120ml / min.

[0085] Furthermore, the introduction time of the nitrogen source, the chlorine source and the doped iron source is 20 min to 200 min, and the concentration of Fe impurities in the first gallium nitride substrate is 5×10 17 cm- 3 ~1×10 19 cm- 3 For example, the passage time can be 20 min, 40 min, 60 min, 80 min, 100 min, 120 min, 140 min, 160 min, 180 min or 200 min,

[0086] In one embodiment, the preparation process of the first gallium nitride substrate is described by taking the metal impurity as Fe impurity as an example. Specifically, the first gallium nitride substrate is prepared through the following steps S101 to S103.

[0087] Step S101: Place a sapphire substrate with a cleaned surface into an HVPE furnace to generate a GaN substrate.

[0088] The GaN substrate is a gallium nitride substrate without Fe doping. Preferably, the layer thickness of the GaN substrate is controlled within the range of 1 μm to 5 μm, for example, the thickness of the generated GaN substrate is 1 μm, 2 μm, 3 μm, 2 μm, 4 μm or 5 μm.

[0089] Step S102 : introducing ferrocene carrier gas, ammonia gas and hydrogen chloride into the HVPE furnace at a temperature of 1000° C. to 1050° C. to generate an iron-doped GaN single crystal wafer.

[0090] The flow rate of the ferrocene is 100 ml / min to 120 ml / min, the flow rate of the ammonia is 1000 ml / min to 1100 ml / min, and the flow rate of the hydrogen chloride is 50 ml / min to 55 ml / min. Furthermore, the three gases are introduced for a total of 20 minutes to 200 minutes.

[0091] Step S103 , peeling off the sapphire substrate in the Fe-doped GaN single crystal wafer to obtain a first GaN substrate doped with Fe impurities.

[0092] After the growth is completed, the temperature is lowered and the Fe-doped GaN single crystal is taken out. The sapphire substrate in the Fe-doped GaN single crystal is removed by stripping to obtain a first GaN substrate doped with Fe impurities. The first GaN substrate is a semi-insulating Fe-doped GaN single crystal. Preferably, the Fe doping concentration of the obtained first GaN substrate doped with Fe impurities is in the range of 5×10 17 cm- 3 ~1×10 19 cm- 3 , for example, 1×10 18 cm- 3 .

[0093] Preferably, the semiconductor structure layer includes a buffer layer, and the material of the buffer layer is the same as that of the compensation layer. In step S200, the first gallium nitride substrate is heat-treated and a growth source is introduced to form the gallium nitride substrate and the compensation layer, which includes the following steps S201-S202.

[0094] In step S201, hydrogen gas is introduced into the growth chamber to heat-treat the first gallium nitride substrate, causing the first gallium nitride substrate to gradually decompose from the surface and enrich deep-level acceptor impurities on the surface of the remaining portion of the first gallium nitride substrate, thereby obtaining a second gallium nitride substrate having a surface enriched with deep-level acceptor impurities.

[0095] Preferably, when the first gallium nitride substrate is heat-treated, the heat treatment temperature is 850° C. to 1100° C., and the heat treatment time is 10-600 seconds. For example, the heat treatment temperature is 850° C., 900° C., 950° C., 1000° C., 1050° C., or 1100° C., and the heat treatment time is 10 seconds, 20 seconds, 50 seconds, 100 seconds, 2000 seconds, or 600 seconds.

[0096] In step S202 , a growth source is introduced into the growth chamber to form a gallium nitride substrate, a compensation layer, and a buffer layer stacked in sequence.

[0097] Preferably, step S202 includes: introducing a growth source into the growth chamber so that deep-level acceptor impurities on the surface of the second gallium nitride substrate and the growth source form a compensation layer, thereby converting the second gallium nitride substrate into a gallium nitride substrate; and continuing to introduce the growth source into the growth chamber to form a buffer layer on the compensation layer. Further preferably, the thickness of the compensation layer is 20 nm to 60 nm, and the combined thickness of the buffer layer and the compensation layer is 80 nm to 120 nm.

[0098] Preferably, the preparation of the buffer layer includes: introducing a nitrogen source with a flow rate of 1500-2000 sccm, a gallium source with a flow rate of 50-100 sccm, and a carrier gas with a flow rate of 2000-3000 sccm at a temperature of 1050° C. to deposit the buffer layer.

[0099] In this embodiment, the compensation layer can be formed by a simpler process instead of a complex MOCVD deposition process. The buffer layer formed on the compensation layer is used to improve the interface bonding between the channel layer and the gallium nitride substrate. After step S200, the structure including the gallium nitride substrate 1, the compensation layer 2, and the buffer layer 31 is formed as shown in FIG. Figure 4 shown.

[0100] As a specific embodiment, the compensation layer is formed by in-situ thermal decomposition. This method is simple and easy to operate. Taking the deep energy level acceptor impurities in the gallium nitride substrate as Fe impurities as an example, the specific implementation process of step S200 is illustrated, including the following steps 1 to 3.

[0101] Step 1: Place the first gallium nitride substrate into the MOCVD equipment.

[0102] Step 2: hydrogen is introduced into the MOCVD device, and the MOCVD device is heated to a temperature between 850° C. and 1100° C. The first gallium nitride substrate is thermally decomposed in situ in the hydrogen atmosphere, and the remaining Fe after decomposition remains on the surface of the substrate.

[0103] Specifically, before performing MOCVD deposition of the buffer layer, only hydrogen is introduced into the MOCVD equipment, and the MOCVD equipment is heated to a temperature between 850°C and 1100°C. The first gallium nitride substrate is then heated in situ in a hydrogen atmosphere. Upon heating, GaN decomposes into metallic gallium and nitrogen. The decomposition chemical formula is as follows:

[0104] 2GaN(S)=2Ga(g)+N2(g)

[0105] The hydrogen atmosphere can prevent the oxidation of GaN and doped Fe impurities.

[0106] It's important to note that the heating temperature should not exceed 1100°C, as this accelerates the decomposition of GaN, decomposing the majority of the Fe-doped first GaN substrate. At temperatures between 850°C and 1100°C, decomposition begins at the surface of the first GaN substrate, effectively preventing its complete decomposition. The decomposition of the first GaN substrate progresses downward from the surface, with the decomposed nitrogen volatilizing. The remaining metallic gallium, a liquid at high temperatures, will slide off the surface of the Fe-doped first GaN substrate. However, since the Fe impurities are uniformly distributed throughout the bulk of the first GaN substrate, with Fe having a melting point above 1500°C and a volatilization temperature above 2700°C, after GaN decomposition, the Fe in the GaN material, due to its low saturated vapor pressure, will remain on the surface of the remaining portion of the first GaN substrate, resulting in a second GaN substrate with a surface enriched in Fe impurities.

[0107] Step 3: Gallium source and nitrogen source are introduced into the MOCVD device to deposit and form a buffer layer, and the Fe retained on the surface of the substrate forms a compensation layer.

[0108] Taking a GaN buffer layer as an example, Step 3 is described as follows: After 50 seconds of in-situ decomposition at high temperature, a gallium source and a nitrogen source are introduced into the MOCVD device to deposit the GaN buffer layer. Although the Fe remaining after decomposition in Step 2 does not completely cover the GaN substrate, the Fe impurities accumulate on the substrate surface after decomposition. Therefore, when the GaN buffer layer (referred to as the GaN buffer layer) is deposited, an Fe-rich compensation layer is formed at the interface between the substrate and the GaN buffer layer.

[0109] The GaN buffer layer is formed in an MOCVD device using MOCVD technology. Preferably, the GaN buffer layer is deposited at a temperature of 1050° C. to 1100° C. using a gas mixture having an ammonia flow rate of 1500 sccm to 2000 sccm, a gallium source flow rate of 50 sccm to 100 sccm, and a hydrogen flow rate of 2000 sccm to 3000 sccm.

[0110] It should be noted that although GaN decomposes at temperatures between 1050°C and 1100°C, the deposition rate is faster than the decomposition rate, resulting in a thicker deposition, ultimately forming a GaN buffer layer. This preparation method does not require a complex carbon doping process, and an Fe-rich compensation layer can be formed during the formation of the GaN buffer layer.

[0111] The above method does not require a complicated C doping process, and an Fe-enriched compensation layer can be formed during the process of forming the buffer layer.

[0112] Preferably, the semiconductor structure layer further includes a channel layer and a barrier layer. Growing the semiconductor structure layer on a substrate whose surface is enriched with deep-level acceptor impurities specifically includes: sequentially forming a channel layer and a barrier layer on a buffer layer to form the semiconductor structure layer.

[0113] Further preferably, the material of the channel layer includes GaN. The specific process of forming the channel layer on the buffer layer is as follows: under the conditions of a temperature of 1100° C. to 1150° C. and a pressure of 80 Torr to 100 Torr, a gallium source and a nitrogen source are introduced into the reaction chamber to deposit a channel layer with a thickness of 0.8-2.5 μm on the buffer layer.

[0114] More preferably, the material of the barrier layer includes Al x Ga 1-x N, 0.1≤x≤0.15. The specific process of forming the barrier layer on the channel layer is as follows: Under the conditions of a temperature of 1060°C to 1100°C and a pressure of 60 Torr to 80 Torr, a gallium source, an aluminum source, and a nitrogen source are introduced into the reaction chamber to deposit a barrier layer with a thickness of 100-300 nm on the channel layer.

[0115] Taking the buffer layer and the channel layer both made of GaN and the barrier layer made of AlGaN as an example, the specific implementation process of step S300 is described, which specifically includes the following steps S301-S302.

[0116] Step S301 : forming a GaN channel layer on the GaN buffer layer by continuing to use MOCVD technology.

[0117] In order to improve the quality of the formed GaN channel layer, the temperature of the vapor deposition can be increased. For example, in this embodiment, triethyl gallium and high-purity ammonia are used as gallium source and nitrogen source respectively, and a GaN channel layer with a thickness of 0.8μm to 2.5μm is deposited on the GaN buffer layer by MOCVD at a temperature of 1100℃ to 1150℃ and a pressure of 80Torr to 100Torr. After this step, the structure formed including the gallium nitride substrate 1, the compensation layer 2, the buffer layer 31 and the channel layer 32 is as shown in FIG. Figure 5 shown.

[0118] Step S302 : preparing an AlGaN barrier layer on the GaN channel layer.

[0119] The Al content in the AlGaN barrier layer is 10 mol% to 15 mol%, for example, the Al content in the AlGaN barrier layer can be Al 0.1 Ga 0.9 N or Al 0.15 Ga 0.85 A specific content between N, for the convenience of writing, abbreviated as Al x Ga 1-x N, 0.1≤x≤0.15. The Al formed x Ga 1-x The N barrier layer and the GaN channel layer form a heterojunction structure Al x Ga 1-x NGaN, Al x Ga 1-x The N / GaN heterojunction structure produces a high concentration of two-dimensional electron gas through spontaneous polarization and piezoelectric polarization, giving gallium nitride electronic devices the advantages of high current density, low on-resistance, and high power density.

[0120] Specifically, triethylgallium, trimethylaluminum and high-purity ammonia are used as gallium source, aluminum source and nitrogen source respectively, and the formation temperature is lowered. Under the conditions of temperature of 1060℃~1100℃ and pressure of 60Torr~80Torr, an Al2O3 layer with a thickness of 100nm~300nm is deposited on the GaN channel layer by MOCVD method. x Ga 1-x After this step, the structure formed includes the gallium nitride substrate 1, the compensation layer 2, the buffer layer 31, the channel layer 32 and the barrier layer 33 as shown in FIG. Figure 6 shown.

[0121] Preferably, the above preparation method further includes step S400: forming a source electrode, a drain electrode and a gate electrode on the semiconductor structure layer.

[0122] Further preferably, step S400 includes the following steps S410 to S440.

[0123] Step S410: etching the semiconductor structure layer to form a groove with a depth of 15 nm to 30 nm.

[0124] For example, a process combining photolithography and dry etching is used to etch the barrier layer in the semiconductor structure layer to form a groove with a depth of 15 nm to 30 nm. For example, the depth of the groove can be 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, or 30 nm.

[0125] Step S420, as Figure 2 As shown, a first dielectric layer 341 with a thickness of 2-8 nm and a second dielectric layer 342 with a thickness of 2-10 nm are sequentially deposited on the inner wall and bottom of the groove to obtain a dielectric layer 34 .

[0126] The first dielectric layer 341 is, for example, an aluminum oxide (Al2O3) layer, and the second dielectric layer 342 is, for example, a hafnium dioxide (HfO2) layer. The first dielectric layer 341 and the second dielectric layer 342 form a double-layer gate dielectric layer (i.e., dielectric layer 34). Specifically, in step S420, an atomic layer deposition process is used, for example, to form relatively dense aluminum oxide and hafnium dioxide layers. The aluminum oxide layer has a thickness of, for example, 2 nm to 8 nm, and the hafnium dioxide layer has a thickness of, for example, 2 nm to 10 nm, forming a double-layer gate dielectric layer.

[0127] Step S430 , depositing a passivation layer with a thickness of 80 nm to 150 nm on the surface of the semiconductor structure layer not covered by the dielectric layer; etching a portion of the passivation layer until the semiconductor structure layer is exposed to form a drain region and a source region.

[0128] The material of the passivation layer is, for example, SiO 2 or SiN, and the thickness of the passivation layer can be 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, or 150 nm.

[0129] Step S440 , depositing a gate electrode on the dielectric layer, and depositing a source electrode and a drain electrode in the source region and the drain region respectively; wherein the source electrode and the drain electrode are spaced apart.

[0130] In the source region, the drain region and the gate groove region, a Ti / Al / Ni / Au metal combination or an alloy material thereof is deposited by an electron beam evaporation process or a sputtering process to form a source electrode, a drain electrode and a gate electrode.

[0131] The technical solution of the present invention is further described in detail below in conjunction with several preferred embodiments and the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. The test methods in the following examples where specific conditions are not specified are generally based on conventional conditions.

[0132] Example 1

[0133] The present embodiment provides a method for manufacturing a gallium nitride electronic device, including the following steps.

[0134] Step 1: At a temperature of 1000° C., a nitrogen source at a flow rate of 1000 ml / min, a chlorine source at a flow rate of 50 ml / min, and a doped iron source at a flow rate of 100 ml / min were introduced into the reaction chamber for 20 minutes to prepare a first gallium nitride substrate.

[0135] The first gallium nitride substrate contains Fe and Si impurities. The Fe impurities are used to compensate for the Si impurities. The concentration of the Fe impurities in the first gallium nitride substrate is 5×10 17 cm- 3 .

[0136] Step 2: heat-treating the first gallium nitride substrate and introducing a growth source to form a stacked gallium nitride substrate, a compensation layer, and a buffer layer.

[0137] S21: hydrogen is introduced into the growth chamber to perform heat treatment on the first gallium nitride substrate, so that the first gallium nitride substrate gradually decomposes from the surface and Fe impurities are enriched on the surface of the remaining portion of the first gallium nitride substrate, thereby obtaining a second gallium nitride substrate with Fe impurities enriched on the surface.

[0138] S22: introducing a growth source into the growth chamber to form a gallium nitride substrate, a compensation layer, and a buffer layer stacked in sequence.

[0139] S221: At a temperature of 1050° C., a nitrogen source with a flow rate of 1500 sccm, a gallium source with a flow rate of 50 sccm, and a carrier gas with a flow rate of 2000 sccm are introduced into the growth chamber, so that the Fe impurities on the surface of the second gallium nitride substrate form a compensation layer with a thickness of 20 nm with the nitrogen source and the gallium source, and the second gallium nitride substrate is converted into a gallium nitride substrate.

[0140] S222: Under the condition of a temperature of 1050° C., a nitrogen source with a flow rate of 1500 sccm, a gallium source with a flow rate of 50 sccm, and a carrier gas with a flow rate of 2000 sccm are continuously introduced into the growth chamber to form a buffer layer with a thickness of 60 nm on the compensation layer.

[0141] Step 3: forming a channel layer and a barrier layer in sequence on the buffer layer to form a semiconductor structure layer.

[0142] S31: Under the conditions of a temperature of 1100° C. and a pressure of 80 Torr, a gallium source and a nitrogen source are introduced into the reaction chamber to deposit a channel layer with a thickness of 0.8 μm on the buffer layer.

[0143] S32: Under the conditions of temperature of 1060°C and pressure of 60 Torr, a gallium source, an aluminum source and a nitrogen source are introduced into the reaction chamber to deposit a 200nm thick Al2O3 layer on the channel layer. 0.1 Ga 0.9 N barrier layer.

[0144] Step 4: forming a source electrode, a drain electrode and a gate electrode on the semiconductor structure layer.

[0145] S41: etching the semiconductor structure layer to form a groove with a depth of 15 nm.

[0146] S42: depositing a first dielectric layer with a thickness of 2 nm and a second dielectric layer with a thickness of 2 nm on the inner wall and the bottom of the groove in sequence to obtain a dielectric layer.

[0147] S43: depositing a passivation layer with a thickness of 80 nm on the surface of the semiconductor structure layer not covered by the dielectric layer; etching a portion of the passivation layer until the semiconductor structure layer is exposed to form a drain region and a source region.

[0148] S44: depositing a gate electrode on the dielectric layer, and depositing a source electrode and a drain electrode in the source region and the drain region respectively; wherein the source electrode and the drain electrode are spaced apart.

[0149] During the formation and storage of the GaN substrate, Si impurities will accumulate on the substrate surface. During the in-situ thermal decomposition and deposition process to form the buffer layer, Si impurities will be present in the Fe compensation layer due to the relatively high melting point of Si. Since Si is a shallow-level donor impurity and Fe is a deep-level acceptor impurity, the deep acceptor energy level characteristics of Fe compensate for the background carrier concentration, thereby compensating for the concentration of Si impurity atoms adsorbed on the GaN substrate surface.

[0150] Comparative Example 1-1

[0151] The method for preparing a gallium nitride electronic device proposed in this comparative example is basically the same as that in Example 1, with the only difference being that there is no Fe impurity in the first gallium nitride substrate prepared therein.

[0152] Example 1-2

[0153] The method for preparing a gallium nitride electronic device proposed in this embodiment is substantially the same as that in embodiment 1, with the only difference being that the heating temperature in step S221 and step S222 is 700° C.

[0154] Examples 1-3

[0155] The method for preparing a gallium nitride electronic device proposed in this embodiment is substantially the same as that in embodiment 1, with the only difference being that the heating temperature in step S221 and step S222 is 1200° C.

[0156] Examples 1-4

[0157] The method for preparing a gallium nitride electronic device proposed in this embodiment is basically the same as that in embodiment 1, except that the Fe impurity concentration of the first gallium nitride substrate prepared in step 1 is 4×1017 cm- 3 .

[0158] Examples 1-5

[0159] The method for preparing a gallium nitride electronic device proposed in this embodiment is basically the same as that in embodiment 1, except that the Fe impurity concentration of the first gallium nitride substrate prepared in step 1 is 2×10 19 cm- 3 .

[0160] The performance characterization results of the gallium nitride electronic devices prepared in Example 1 and Comparative Examples 1-1 to Example 1-5 are shown in Table 1.

[0161] Table 1

[0162] project Output power Example 1 6W / mm Comparative Example 1-1 4.8W / mm Example 1-2 5.7W / mm Examples 1-3 5.9W / mm Examples 1-4 5.8W / mm Examples 1-5 5.6W / mm

[0163] Example 2

[0164] The present embodiment provides a method for manufacturing a gallium nitride electronic device, including the following steps.

[0165] Step 1: At a temperature of 1020° C., a nitrogen source at a flow rate of 1050 ml / min, a chlorine source at a flow rate of 52 ml / min, and a doped iron source at a flow rate of 110 ml / min were introduced into the reaction chamber for 100 minutes to prepare a first gallium nitride substrate.

[0166] The first GaN substrate contains Fe impurities and shallow-level donor impurities. The Fe impurities are used to compensate for the shallow-level donor impurities. The concentration of the Fe impurities in the first GaN substrate is 5×10 18 cm- 3 .

[0167] Step 2: heat-treating the first gallium nitride substrate and introducing a growth source to form a stacked gallium nitride substrate, a compensation layer, and a buffer layer.

[0168] S21: hydrogen is introduced into the growth chamber to perform heat treatment on the first gallium nitride substrate, so that the first gallium nitride substrate gradually decomposes from the surface and Fe impurities are enriched on the surface of the remaining portion of the first gallium nitride substrate, thereby obtaining a second gallium nitride substrate with Fe impurities enriched on the surface.

[0169] S22: introducing a growth source into the growth chamber to form a gallium nitride substrate, a compensation layer, and a buffer layer stacked in sequence.

[0170] S221: At a temperature of 1070° C., a nitrogen source with a flow rate of 1700 sccm, a gallium source with a flow rate of 80 sccm, and a carrier gas with a flow rate of 2500 sccm are introduced into the growth chamber, so that the Fe impurities on the surface of the second gallium nitride substrate form a compensation layer with a thickness of 40 nm with the nitrogen source and the gallium source, and the second gallium nitride substrate is converted into a gallium nitride substrate.

[0171] S222: Under the condition of a temperature of 1070° C., a nitrogen source with a flow rate of 1700 sccm, a gallium source with a flow rate of 80 sccm, and a carrier gas with a flow rate of 2500 sccm are continuously introduced into the growth chamber to form a buffer layer with a thickness of 60 nm on the compensation layer.

[0172] Step 3: forming a channel layer and a barrier layer in sequence on the buffer layer to form a semiconductor structure layer.

[0173] S31: Under conditions of a temperature of 1125° C. and a pressure of 90 Torr, a gallium source and a nitrogen source are introduced into the reaction chamber to deposit a channel layer with a thickness of 1.5 μm on the buffer layer.

[0174] S32: Under the conditions of temperature of 1080°C and pressure of 70 Torr, a gallium source, an aluminum source and a nitrogen source are introduced into the reaction chamber to deposit a 200nm thick Al2O3 layer on the channel layer. 0.12 Ga 0.88 N barrier layer.

[0175] Step 4: forming a source electrode, a drain electrode and a gate electrode on the semiconductor structure layer.

[0176] S41: etching the semiconductor structure layer to form a groove with a depth of 22 nm;

[0177] S42: depositing a first dielectric layer with a thickness of 5 nm and a second dielectric layer with a thickness of 6 nm on the inner wall and bottom of the groove in sequence to obtain a dielectric layer;

[0178] S43: depositing a passivation layer with a thickness of 115 nm on the surface of the semiconductor structure layer not covered by the dielectric layer; etching a portion of the passivation layer until the semiconductor structure layer is exposed to form a drain region and a source region.

[0179] S44: depositing a gate electrode on the dielectric layer, and depositing a source electrode and a drain electrode in the source region and the drain region respectively; wherein the source electrode and the drain electrode are spaced apart.

[0180] Comparative Example 2-1

[0181] The method for preparing a gallium nitride electronic device proposed in this comparative example is basically the same as that of Example 2, with the only difference being that there is no Fe impurity in the first gallium nitride substrate prepared therein.

[0182] Example 2-2

[0183] The method for preparing a gallium nitride electronic device proposed in this embodiment is substantially the same as that in embodiment 2, with the only difference being that the heating temperature in step S221 and step S222 is 700° C.

[0184] Example 2-3

[0185] The method for preparing a gallium nitride electronic device proposed in this embodiment is substantially the same as that in embodiment 2, with the only difference being that the heating temperature in step S221 and step S222 is 1200° C.

[0186] Examples 2-4

[0187] The method for preparing a gallium nitride electronic device proposed in this embodiment is basically the same as that in embodiment 2, except that the Fe impurity concentration of the first gallium nitride substrate prepared in step 1 is 4×10 17 cm- 3 .

[0188] Examples 2-5

[0189] The method for preparing a gallium nitride electronic device proposed in this embodiment is basically the same as that in embodiment 2, except that the Fe impurity concentration of the first gallium nitride substrate prepared in step 1 is 2×10 19 cm- 3 .

[0190] The performance characterization results of the gallium nitride electronic devices prepared in Example 2 and Comparative Examples 2-1 to Example 2-5 are shown in Table 2.

[0191] Table 2

[0192] project Output power Example 2 10W / mm Comparative Example 2-1 8.4W / mm Example 2-2 9.8W / mm Example 2-3 9.6W / mm Examples 2-4 9.7W / mm Examples 2-5 9.5W / mm

[0193] Example 3

[0194] The present embodiment provides a method for manufacturing a gallium nitride electronic device, including the following steps.

[0195] Step 1: At a temperature of 1050° C., a nitrogen source at a flow rate of 1100 ml / min, a chlorine source at a flow rate of 55 ml / min, and a doped iron source at a flow rate of 120 ml / min were introduced into the reaction chamber for 200 minutes to prepare a first gallium nitride substrate.

[0196] The first gallium nitride substrate contains Fe impurities and shallow energy level donor impurities. The Fe impurities are used to compensate for the shallow energy level donor impurities. The concentration of the Fe impurities in the first gallium nitride substrate is 1×10 19 cm- 3 .

[0197] Step 2: heat-treating the first gallium nitride substrate and introducing a growth source to form a stacked gallium nitride substrate, a compensation layer, and a buffer layer.

[0198] S21: hydrogen is introduced into the growth chamber to perform heat treatment on the first gallium nitride substrate, so that the first gallium nitride substrate gradually decomposes from the surface and Fe impurities are enriched on the surface of the remaining portion of the first gallium nitride substrate, thereby obtaining a second gallium nitride substrate with Fe impurities enriched on the surface.

[0199] S22: introducing a growth source into the growth chamber to form a gallium nitride substrate, a compensation layer, and a buffer layer stacked in sequence.

[0200] S221: At a temperature of 1100° C., a nitrogen source with a flow rate of 2000 sccm, a gallium source with a flow rate of 100 sccm, and a carrier gas with a flow rate of 3000 sccm are introduced into the growth chamber, so that the Fe impurities on the surface of the second gallium nitride substrate form a compensation layer with a thickness of 60 nm with the nitrogen source and the gallium source, and the second gallium nitride substrate is converted into a gallium nitride substrate.

[0201] S222: Under the condition of a temperature of 1100° C., a nitrogen source with a flow rate of 2000 sccm, a gallium source with a flow rate of 100 sccm, and a carrier gas with a flow rate of 3000 sccm are continuously introduced into the growth chamber to form a buffer layer with a thickness of 60 nm on the compensation layer.

[0202] Step 3: forming a channel layer and a barrier layer in sequence on the buffer layer to form a semiconductor structure layer.

[0203] S31: Under the conditions of a temperature of 1150° C. and a pressure of 100 Torr, a gallium source and a nitrogen source are introduced into the reaction chamber to deposit a channel layer with a thickness of 2.5 μm on the buffer layer.

[0204] S32: Under the conditions of temperature of 1100°C and pressure of 80 Torr, a gallium source, an aluminum source and a nitrogen source are introduced into the reaction chamber to deposit a 300nm thick Al2O3 layer on the channel layer. 0.15 Ga 0.85 N barrier layer.

[0205] Step 4: forming a source electrode, a drain electrode and a gate electrode on the semiconductor structure layer.

[0206] S41: etching the semiconductor structure layer to form a groove with a depth of 30 nm;

[0207] S42: depositing a first dielectric layer with a thickness of 8 nm and a second dielectric layer with a thickness of 10 nm on the inner wall and bottom of the groove in sequence to obtain a dielectric layer;

[0208] S43: depositing a passivation layer with a thickness of 150 nm on the surface of the semiconductor structure layer not covered by the dielectric layer; etching a portion of the passivation layer until the semiconductor structure layer is exposed to form a drain region and a source region.

[0209] S44: depositing a gate electrode on the dielectric layer, and depositing a source electrode and a drain electrode in the source region and the drain region respectively; wherein the source electrode and the drain electrode are spaced apart.

[0210] Comparative Example 3-1

[0211] The method for preparing a gallium nitride electronic device proposed in this comparative example is basically the same as that of Example 3, with the only difference being that there is no Fe impurity in the first gallium nitride substrate prepared therein.

[0212] Example 3-2

[0213] The method for preparing a gallium nitride electronic device proposed in this embodiment is substantially the same as that in embodiment 3, with the only difference being that the heating temperature in step S221 and step S222 is 700° C.

[0214] Example 3-3

[0215] The method for preparing a gallium nitride electronic device proposed in this embodiment is substantially the same as that in embodiment 3, with the only difference being that the heating temperature in step S221 and step S222 is 1200° C.

[0216] Examples 3-4

[0217] The method for preparing a gallium nitride electronic device proposed in this embodiment is basically the same as that in embodiment 3, except that the Fe impurity concentration of the first gallium nitride substrate prepared in step 1 is 4×10 17 cm- 3 .

[0218] Examples 3-5

[0219] The method for preparing a gallium nitride electronic device proposed in this embodiment is basically the same as that in embodiment 3, except that the Fe impurity concentration of the first gallium nitride substrate prepared in step 1 is 2×10 19 cm- 3 .

[0220] Comparative Examples 3-6

[0221] The method for preparing a gallium nitride electronic device proposed in this comparative example is basically the same as that of Example 3, except that step 2 does not include step S21, that is, the first gallium nitride substrate is not heat-treated.

[0222] The performance characterization results of the gallium nitride electronic devices prepared in Example 3 and Comparative Examples 3-1 to 3-6 are shown in Table 3.

[0223] Table 3

[0224] project Output power Example 3 15W / mm Comparative Example 3-1 13.8W / mm Example 3-2 14.7W / mm Example 3-3 14.9W / mm Examples 3-4 14.5W / mm Examples 3-5 14.6W / mm Comparative Examples 3-6 13.2W / mm

[0225] The comparison results of Example 3 and Comparative Examples 3-6 are as follows Figure 7 shown. Figure 7 The relationship between the Fe impurity concentration and the depth of the structure after in-situ heat treatment and without in-situ heat treatment is shown. Figure 7 It can be seen that after the in-situ heat treatment on the surface of the gallium nitride substrate, the concentration of Fe impurities increases by nearly an order of magnitude. In-situ heat treatment alone can well meet the preparation requirements without the need for more complicated processes.

[0226] Combining Table 1, Table 2, and Table 3, we can draw the following conclusions. Compared with the GaN electronic device using a non-Fe-doped GaN substrate, the GaN electronic device using the Fe-doped GaN substrate in this application has a greatly improved output power, with the improvement reaching up to 25%; and 5×10 17 cm- 3 ~1×10 19 cm- 3 In the range, the higher the Fe doping concentration, the higher the output power of GaN electronic devices; when the Fe doping concentration is higher than 1×10 19 cm- 3 or less than 5×10 17 cm- 3 When heating a GaN substrate in a hydrogen atmosphere, either too high or too low a temperature will reduce the output power of the GaN device. GaN devices produced at a heating temperature between 850°C and 1100°C have the highest output power.

[0227] The embodiment of the present invention provides a gallium nitride electronic device and a preparation method thereof. To address the problem that the existing gallium nitride electronic device causes severe leakage and low output power of the GaN HEMT device when reducing the concentration of impurity atoms adsorbed on the surface of the gallium nitride substrate, it is proposed to introduce metal impurities on the surface of the gallium nitride substrate to form a metal-doped gallium nitride substrate instead of carbon doping, and to use Fe 3+ / Fe 2+The deep acceptor energy level compensates for the background carrier concentration, thereby compensating for the concentration of impurity atoms adsorbed on the surface of the GaN substrate, particularly the concentration of Si atoms, thereby resolving the problems existing in the prior art. Furthermore, an in-situ heating method (controlled at a temperature of 850-1100°C) can be used to thermally decompose the metal-doped GaN substrate in a hydrogen atmosphere. This allows the metal impurities to decompose at high temperatures and remain on the substrate surface, effectively compensating for Si and avoiding the many challenges associated with carbon doping, thereby simplifying the fabrication process.

[0228] The gallium nitride electronic device fabrication method provided by the embodiments of the present invention effectively improves the electrical performance at the interface. It is simple, easy, and low-cost, and solves the problem of parasitic conductive channels caused by Si impurities. It avoids the limitations of traditional surface treatment methods (cleaning), provides a more effective impurity compensation solution, and provides a new approach to improving the performance of GaN-based HEMT devices.

[0229] It should be understood that the above embodiments are merely illustrative of the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent variations or modifications made in accordance with the spirit and substance of the present invention are intended to be encompassed within the scope of protection of the present invention.

Claims

1. A gallium nitride electronic device comprising a gallium nitride substrate and a semiconductor structure layer disposed on the gallium nitride substrate; characterized in that: The gallium nitride substrate contains shallow energy level donor impurities and deep energy level acceptor impurities, the deep energy level acceptor impurities are used to compensate for the shallow energy level donor impurities, and the deep energy level acceptor impurities are metal impurities; A compensation layer is provided at the interface between the gallium nitride substrate and the semiconductor structure layer, and the concentration of deep energy level acceptor impurities in the compensation layer is greater than the concentration of deep energy level acceptor impurities in the gallium nitride substrate.

2. The gallium nitride electronic device according to claim 1, characterized in that The melting point of the deep energy level acceptor impurity is greater than the decomposition temperature of gallium nitride; And / or, the material of the compensation layer includes GaN; And / or, the deep energy level acceptor impurities are Fe impurities, Ni impurities or Mn impurities; And / or, the concentration of Fe impurities in the gallium nitride substrate is 5×10 17 cm -3 ~1×10 19 cm -3 ; And / or, the concentration of Fe impurities in the compensation layer is 5×10 18 cm -3 ~5×10 19 cm -3 ; And / or, the thickness of the compensation layer is 20 nm to 60 nm; And / or, the compensation layer is formed at a temperature of 850°C to 1100°C.

3. The gallium nitride electronic device according to claim 1, characterized in that The semiconductor structure layer includes a buffer layer, a channel layer, and a barrier layer sequentially arranged in a direction away from the gallium nitride substrate, and the barrier layer has a groove; The semiconductor structure layer further includes a dielectric layer and a passivation layer, wherein the dielectric layer is arranged on the inner wall and the bottom of the groove, and the passivation layer is arranged on the barrier layer; The gallium nitride electronic device further includes a source electrode, a drain electrode, and a gate electrode, wherein the gate electrode covers the dielectric layer; the source electrode and the drain electrode are arranged on a side of the barrier layer away from the gallium nitride substrate and are spaced apart; The buffer layer and the channel layer are made of GaN; and / or the barrier layer is made of AlGaN; and / or the sum of the thicknesses of the buffer layer and the compensation layer is 80 nm to 120 nm.

4. A method for preparing a gallium nitride electronic device, characterized in that: include: Providing a first gallium nitride substrate; wherein the first gallium nitride substrate contains shallow-level donor impurities and deep-level acceptor impurities, and the deep-level acceptor impurities are metal impurities, and the deep-level acceptor impurities are used to compensate for the shallow-level donor impurities; performing a heat treatment on the first gallium nitride substrate and introducing a growth source to form a gallium nitride substrate and a compensation layer; forming a semiconductor structure layer on the compensation layer; The concentration of deep energy level acceptor impurities in the compensation layer is greater than the concentration of deep energy level acceptor impurities in the gallium nitride substrate.

5. The preparation method according to claim 4, characterized in that The semiconductor structure layer includes a buffer layer, and the material of the buffer layer is the same as that of the compensation layer. The first gallium nitride substrate is subjected to heat treatment and a growth source is introduced to form the gallium nitride substrate and the compensation layer, comprising: introducing hydrogen into the growth chamber and performing a heat treatment on the first gallium nitride substrate to gradually decompose the first gallium nitride substrate from the surface and enrich the deep level acceptor impurities on the surface of the remaining portion of the first gallium nitride substrate, thereby obtaining a second gallium nitride substrate having the deep level acceptor impurities enriched on the surface; The growth source is introduced into the growth chamber to form the gallium nitride substrate, the compensation layer, and the buffer layer which are stacked in sequence.

6. The preparation method according to claim 5, characterized in that The step of introducing the growth source into the growth chamber to form the gallium nitride substrate, the compensation layer, and the buffer layer stacked in sequence includes: introducing the growth source into the growth chamber so that deep-level acceptor impurities on the surface of the second gallium nitride substrate and the growth source form the compensation layer, and the second gallium nitride substrate is transformed into the gallium nitride substrate; continuing to introduce the growth source into the growth chamber to form the buffer layer on the compensation layer; Wherein, the thickness of the compensation layer is 20 nm to 60 nm, and / or the sum of the thicknesses of the buffer layer and the compensation layer is 80 nm to 120 nm.

7. The preparation method according to claim 6, characterized in that The growth source includes a gallium source and a nitrogen source, and the preparation of the buffer layer includes: At a temperature of 1050° C. to 1100° C., a nitrogen source with a flow rate of 1500-2000 sccm, a gallium source with a flow rate of 50-100 sccm, and a carrier gas with a flow rate of 2000-3000 sccm are introduced to deposit the buffer layer.

8. The preparation method according to claim 4, characterized in that The deep energy level acceptor impurity is Fe impurity, and the preparation process of the first gallium nitride substrate is: At a temperature of 1000° C. to 1050° C., introducing a nitrogen source at a rate of 1000 ml / min to 1100 ml / min, a chlorine source at a rate of 50 ml / min to 55 ml / min, and a doped iron source at a rate of 100 ml / min to 120 ml / min into a reaction chamber to prepare the first gallium nitride substrate; The introduction time is 20 min to 200 min, and the concentration of Fe impurities in the first gallium nitride substrate is 5×10 17 cm -3 ~1×10 19 cm -3 .

9. The preparation method according to claim 5, characterized in that In the heat treatment process, the heat treatment temperature is 850°C to 1100°C; And / or, the semiconductor structure layer further includes a channel layer and a barrier layer, and growing the semiconductor structure layer on the substrate with deep energy level acceptor impurities enriched on the surface specifically includes: forming the channel layer and the barrier layer in sequence on the buffer layer, thereby forming the semiconductor structure layer; And / or, the method further comprises: A source electrode, a drain electrode and a gate electrode are formed on the semiconductor structure layer.

10. The preparation method according to claim 9, characterized in that The material of the channel layer includes GaN; Under the conditions of a temperature of 1100° C. to 1150° C. and a pressure of 80 Torr to 100 Torr, a gallium source and a nitrogen source are introduced into a reaction chamber to deposit the channel layer with a thickness of 0.8-2.5 μm on the buffer layer; And / or, the material of the barrier layer includes Al x Ga 1-x N, 0.1≤x≤0.15; Under the conditions of a temperature of 1060° C. to 1100° C. and a pressure of 60 Torr to 80 Torr, a gallium source, an aluminum source, and a nitrogen source are introduced into the reaction chamber to deposit the barrier layer with a thickness of 100-300 nm on the channel layer; And / or, forming a source electrode, a drain electrode and a gate electrode on the semiconductor structure layer includes: Etching the semiconductor structure layer to form a groove with a depth of 15nm-30nm; Depositing a first dielectric layer with a thickness of 2-8 nm and a second dielectric layer with a thickness of 2-10 nm on the inner wall and bottom of the groove in sequence to obtain a dielectric layer; Depositing a passivation layer with a thickness of 80 nm to 150 nm on the surface of the semiconductor structure layer not covered by the dielectric layer; etching a portion of the passivation layer until the semiconductor structure layer is exposed to form a drain region and a source region; The gate electrode is deposited on the dielectric layer, and the source electrode and the drain electrode are deposited in the source region and the drain region respectively; wherein the source electrode and the drain electrode are spaced apart.

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