Back contact battery, manufacturing method thereof and photovoltaic module

Abstract

The embodiment of the invention relates to the photovoltaic field, and provides a back contact battery and a manufacturing method thereof, and a photovoltaic module, the back contact battery comprises a substrate, the substrate is provided with a first surface and a second surface which are opposite to each other along a first direction, and the second surface is provided with first regions and second regions which are alternately arranged along a second direction; the first dielectric layer and the first doping layer are stacked on the first region, and P-type doping elements are arranged in the first doping layer; the second dielectric layer and the second doping layer are stacked on the second region, and the second doping layer is provided with N-type doping elements; wherein the first doped layer comprises N layers of stacked first doped films, the crystallization rate of the (N-1) th layer of first doped film is higher than the crystallization rate of the Nth layer of first doped film in the direction away from the substrate, and N is a positive integer greater than or equal to 2. The embodiment of the invention is at least beneficial to improving the photoelectric conversion efficiency of the back contact battery.

Description

Technical Field

[0001] The present application relates to the photovoltaic field, and in particular to a back-contact cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] Solar cells are becoming increasingly popular as a sustainable source of clean energy. A solar cell uses the photovoltaic principle to generate charge carriers, converting sunlight into electricity. Grid lines are typically used in solar cells to extract the charge carriers, allowing for efficient use of the electrical energy. Current mainstream solar cell types include BC cells (back contact cells), TOPCON cells (tunnel oxide passivated contact), PERC cells (passivated emitter and real cell), and heterojunction cells.

[0003] In order to further avoid the grid lines blocking the front of the solar cell, the research on BC cells (Back Contact) has become more and more in-depth. By designing film layers with different characteristics in different areas on the back of the BC cell, the optical loss and the recombination of photogenerated carriers can be reduced, thereby improving the photoelectric conversion efficiency of the BC cell.

[0004] However, the battery efficiency of current BC batteries still needs to be further improved. Summary of the Invention

[0005] The embodiments of the present application provide a back-contact cell and a method for manufacturing the same, a photovoltaic module back-contact cell and a method for manufacturing the same, and a photovoltaic module, which are at least beneficial to improving the photoelectric conversion efficiency of the back-contact cell.

[0006] According to some embodiments of the present application, on the one hand, the embodiments of the present application provide a back-contact battery, comprising: a substrate, the substrate having a first surface and a second surface opposite to each other along a first direction, the second surface having a first region and a second region alternately arranged along a second direction; a first dielectric layer and a first doping layer stacked on the first region, the first doping layer having a P-type doping element; a second dielectric layer and a second doping layer stacked on the second region, the second doping layer having an N-type doping element; wherein the first doping layer comprises N stacked layers of first doping films, and in a direction away from the substrate, the crystallization rate of the (N-1)th layer of the first doping film is higher than the crystallization rate of the Nth layer of the first doping film, and N is a positive integer greater than or equal to 2.

[0007] In some embodiments, a grain size in the (N-1)th layer of the first doping film is smaller than a grain size in the Nth layer of the first doping film.

[0008] In some embodiments, N is 2, the crystallization rate of the (N-1)th layer of the first doped film is greater than or equal to 99%, and the crystallization rate of the Nth layer of the first doped film is less than 95%.

[0009] In some embodiments, N is 2, the grain size of the (N-1)th layer of the first doping film is 100 nm to 180 nm, and the grain size of the Nth layer of the first doping film is 190 nm to 300 nm.

[0010] In some embodiments, along the first direction, a thickness of the (N-1)th layer of the first doping film is smaller than a thickness of the Nth layer of the first doping film.

[0011] In some embodiments, along the first direction, N is 2, the thickness of the (N-1)th layer of the first doped film is 10 nm to 60 nm, and the thickness of the Nth layer of the first doped film is 10 nm to 500 nm.

[0012] In some embodiments, the second doped layer includes M layers of second doped films stacked together, and along the direction away from the substrate, the crystallization rate of the (M-1)th layer of the second doped film is higher than the crystallization rate of the Mth layer of the second doped film, where M is a positive integer greater than or equal to 2.

[0013] In some embodiments, a grain size of the (M-1)th layer of the second doped film is smaller than a grain size of the Mth layer of the second doped film.

[0014] In some embodiments, along the first direction, the thickness of the first doping layer is greater than the thickness of the second doping layer.

[0015] In some embodiments, at least one of the first doping layer and the second doping layer is polysilicon doped with carbon or nitrogen; or, the material of the second doping layer includes amorphous silicon.

[0016] In some embodiments, the material of at least one of the first dielectric layer and the second dielectric layer includes aluminum oxide or silicon nitride; or, the material of at least one of the first dielectric layer and the second dielectric layer includes at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride; or, the material of the second dielectric layer includes at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0017] In some embodiments, the doping concentration of the P-type doping element in the first doping layer is 5×10 18 atom / cm 3 ~8×10 20 atom / cm 3; and / or, the doping concentration of the N-type doping element in the second doping layer is 5×10 19 atom / cm 3 ~9×10 20 atom / cm 3 .

[0018] In some embodiments, the back-contact battery further includes: a first passivation layer, located on the first surface, and at least on the surface of both the first doping layer and the second doping layer away from the substrate; a second passivation layer, located on the surface of the first passivation layer away from the substrate; wherein, along the first direction, the thickness of the first passivation layer is 3nm~10nm; and / or, along the first direction, the thickness of the second passivation layer is 70nm~90nm.

[0019] According to some embodiments of the present application, another aspect of the present application further provides a method for manufacturing a back-contact battery, comprising: providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other along a first direction, wherein the second surface has a first region and a second region alternately arranged along a second direction; forming a first dielectric layer and a first doping layer stacked on the first region, wherein the first doping layer has a P-type doping element; forming a second dielectric layer and a second doping layer stacked on the second region, wherein the second doping layer has an N-type doping element; wherein the step of forming the first doping layer comprises: forming a first semiconductor layer on the second surface using a first deposition process, wherein the first deposition process The method comprises N deposition stages connected in sequence, wherein the deposition temperature of the (N-1)th deposition stage is lower than the deposition temperature of the Nth deposition stage, and N is a positive integer greater than or equal to 2; performing a first doping treatment on the first semiconductor layer, so that the first semiconductor layer is converted into an initial first doping layer doped with a P-type doping element; performing a first patterning treatment on the initial first doping layer, retaining only the initial first doping layer located on the first region as the first doping layer, and the first doping layer comprises N layers of first doping films stacked together, and in a direction away from the substrate, the crystallization rate of the (N-1)th layer of the first doping film is higher than the crystallization rate of the Nth layer of the first doping film.

[0020] In some embodiments, the step of forming the second doping layer includes: forming a second semiconductor layer on the second surface using a second deposition process, the second deposition process includes M temperature control stages connected in sequence, the process temperature of the (M-1)th temperature control stage is lower than the process temperature of the Mth temperature control stage, and M is a positive integer greater than or equal to 2; performing a second doping treatment on the second semiconductor layer, so that the second semiconductor layer is converted into an initial second doping layer doped with N-type doping elements; performing a second graphic treatment on the initial second doping layer, retaining only the initial second doping layer located on the second region as the second doping layer, and the second doping layer includes M layers of second doping films stacked together, and in the direction away from the substrate, the crystallization rate of the (M-1)th layer of the second doping film is higher than the crystallization rate of the Mth layer of the second doping film.

[0021] In some embodiments, M is 2, and the second deposition process includes a first temperature control stage and a second temperature control stage connected in sequence. The process temperature of the first temperature control stage is 520°C~570°C, and the process temperature of the second temperature control stage is 580°C~650°C.

[0022] In some embodiments, before forming the second semiconductor layer, a semi-finished back-contact battery to be used to form the second semiconductor layer is placed in a reaction chamber; during the process of forming the second semiconductor layer using the second deposition process, a carbon-containing gas or a nitrogen-containing gas is introduced into the reaction chamber, so that the formed second semiconductor layer is doped with carbon elements or nitrogen elements.

[0023] In some embodiments, in the step of performing the second doping treatment on the second semiconductor layer, a second protective layer is also formed on the side of the initial second doping layer away from the substrate; a second laser is used to remove the second protective layer located on the first region; a second etching process is used to remove the initial second doping layer located on the first region, and the remaining initial second doping layer is the second doping layer; wherein, the second laser is a purple laser or a green laser, and the power of the laser generating the second laser is 5W~80W.

[0024] In some embodiments, N is 2, the first deposition process includes a first deposition stage and a second deposition stage connected in sequence, the deposition temperature of the first deposition stage is 520°C~570°C, and the deposition temperature of the second deposition stage is 580°C~650°C.

[0025] In some embodiments, before forming the first semiconductor layer, a semi-finished back-contact battery to be used to form the first semiconductor layer is placed in a reaction chamber; during the process of forming the first semiconductor layer using the first deposition process, a carbon-containing gas or a nitrogen-containing gas is introduced into the reaction chamber, so that the formed first semiconductor layer is doped with carbon elements or nitrogen elements.

[0026] In some embodiments, in the step of performing the first doping treatment on the first semiconductor layer, a first protective layer is also formed on the side of the initial first doping layer away from the substrate; a first laser is used to remove the first protective layer located on the second region; a first etching process is used to remove the initial first doping layer located on the second region, and the remaining initial first doping layer is the first doping layer; wherein, the first laser is a purple laser or a green laser, and the power of the laser generating the first laser is 5W~80W.

[0027] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a photovoltaic module, comprising: a cell string, formed by connecting a plurality of back-contact cells as described in any one of the above items, or formed by connecting a plurality of back-contact cells formed by the manufacturing method of the back-contact cell as described in any one of the above items; an encapsulation film for covering the surface of the cell string; and a cover plate for covering the surface of the encapsulation film facing away from the cell string.

[0028] The technical solution provided by the embodiments of the present application has at least the following advantages: The first doped layer is designed to have a stacked structure including multiple first doped films with different crystallinity. On the one hand, the first doped film with a higher crystallinity near the substrate can improve its own film uniformity, which helps to prevent grain precipitation on the surface of the first doped film with a higher crystallinity near the substrate. Therefore, the first doped film with a higher crystallinity near the substrate can be designed to have a higher crystallinity to prevent the grains in the first doped layer from damaging other film layers close to it, such as the first dielectric layer and the substrate, thereby ensuring the stability of the performance of other film layers close to the first doped layer and improving the passivation effect of other film layers close to the first doped layer on the substrate, thereby reducing the recombination probability of photogenerated carriers. On the other hand, the first doped film with a lower crystallinity far from the substrate helps to improve the surface roughness of the first doped film far from the substrate. For example, the surface of the first doped film with a lower crystallinity far from the substrate has larger grains. Therefore, when designing an electrode on the side of the first doped layer far from the substrate, it is beneficial to use the first doped film with a lower crystallinity to improve the contact performance between the first doped layer and the electrode, thereby improving the electrode's collection efficiency of photogenerated carriers and thereby improving the fill factor of the back contact cell. Such multi-faceted effects can not only enhance the passivation effect on the substrate with the cooperation of the first doping layer and the first dielectric layer, but also reduce the migration barrier of photogenerated carriers in the first doping layer, thereby further improving the photoelectric conversion efficiency of the back contact battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present application or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 A first partial cross-sectional schematic diagram of a back-contact battery provided in one embodiment of the present application; Figure 2 A second partial cross-sectional schematic diagram of a back-contact battery provided in one embodiment of the present application; Figure 3 A third partial cross-sectional schematic diagram of a back-contact battery provided in one embodiment of the present application; Figure 4 A process flow chart corresponding to a method for manufacturing a back-contact battery provided in another embodiment of the present application; Figure 5 A schematic partial cross-sectional view after forming a first semiconductor layer in a method for manufacturing a back-contact battery according to another embodiment of the present application; Figure 6 A schematic partial cross-sectional view after a first doping treatment is performed in a method for manufacturing a back-contact cell provided in another embodiment of the present application; Figure 7 A schematic partial cross-sectional view of a back-contact cell after being processed by a first laser in a method for manufacturing the back-contact cell according to another embodiment of the present application; Figure 8 A schematic partial cross-sectional view of a back-contact cell after being processed using a first etching process in a method for manufacturing a back-contact cell provided in another embodiment of the present application; Figure 9 A schematic partial cross-sectional view after forming a second semiconductor layer in a method for manufacturing a back-contact battery according to another embodiment of the present application; Figure 10 A schematic partial cross-sectional view of a back-contact cell after a second doping treatment is performed in a method for manufacturing a back-contact cell according to another embodiment of the present application; Figure 11 A schematic partial cross-sectional view of a back-contact cell after being processed by a second laser in a method for manufacturing the back-contact cell according to another embodiment of the present application; Figure 12 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided in another embodiment of the present application; Figure 13 A partial cross-sectional schematic diagram of a photovoltaic module provided in yet another embodiment of the present application.

[0031] Description of reference numerals: 100, substrate; 110, first surface; 120, second surface; 1201, first region; 1202, second region; 1203, isolation region; 101, first dielectric layer; 111, initial first dielectric layer; 102, first doped layer; 112, first doped film; 1121, first internal doped film; 1122, first external doped film; 122, initial first doped layer; 1221, initial first internal doped layer; 1222, initial first external doped layer; 103, second dielectric layer; 113, initial second dielectric layer; 104, second doped layer; 114, second doped film ; 1141, second inner doping film; 1142, second outer doping film; 124, initial second doping layer; 1241, initial second inner doping layer; 1242, initial second outer doping layer; 105, first semiconductor layer; 115, first semiconductor film; 116, first protective layer; 126, second protective layer; 107, second semiconductor layer; 117, second semiconductor film; 118, first passivation layer; 128, second passivation layer; 119, first electrode; 129, second electrode; 40, back contact battery; 41, encapsulation film; 42, cover plate; 43, conductive tape. DETAILED DESCRIPTION

[0032] As can be seen from the background technology, the battery efficiency of BC batteries still needs to be further improved.

[0033] Analysis found that in BC batteries, when the doped layer is used as a field passivation layer and a transport layer for photogenerated carriers, since the crystallization rate of the doped layer is within a single numerical range, it is difficult to achieve a good balance between improving the passivation effect of the BC battery and reducing the migration barrier of photogenerated carriers in the doped layer.

[0034] The embodiments of the present application provide a back-contact cell and a method for manufacturing the same, as well as a photovoltaic module. In the back-contact cell, the first doped layer is designed to be a stacked structure including multiple layers of first doped films with different crystallinity. On the one hand, the first doped film with a higher crystallinity close to the substrate can improve its own film uniformity, which helps to prevent grain precipitation on the surface of the first doped film with a higher crystallinity close to the substrate. Thus, the first doped film close to the substrate can be designed to have a higher crystallinity to avoid damage to other film layers close to it by the grains in the first doped layer, such as the first dielectric layer and the substrate, to ensure the performance of other film layers close to the first doped layer. Stability can be improved to enhance the passivation effect of other film layers close to the first doping layer on the substrate, thereby reducing the recombination probability of photogenerated carriers. On the other hand, the first doping film far from the substrate has a lower crystallinity, which helps to improve the surface roughness of the first doping film far from the substrate. For example, the surface of the first doping film with a lower crystallinity away from the substrate has larger grains. Therefore, when designing the electrode on the side of the first doping layer far from the substrate, it is beneficial to use the first doping film with a lower crystallinity to improve the contact performance between the first doping layer and the electrode, thereby improving the electrode's collection efficiency of photogenerated carriers and thus improving the fill factor of the back contact battery. Such multi-faceted effects can not only enhance the passivation effect on the substrate with the cooperation of the first doping layer and the first dielectric layer, but also reduce the migration barrier of photogenerated carriers in the first doping layer, thereby further improving the photoelectric conversion efficiency of the back contact battery.

[0035] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0036] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0037] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0038] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0039] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0040] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0041] In the accompanying drawings corresponding to the embodiments of this application, the thickness and area of ​​layers are exaggerated for better understanding and ease of description. When a component (such as a layer, film, region, or substrate) is described as being on or on the surface of another component, the component may be "directly" located on the surface of the other component, or a third component may be present between the two components. Conversely, when a component is described as being on the surface of another component, or as being formed or disposed on the surface of one component, it indicates that there is no third component between the two components. Furthermore, when a component is described as being "substantially" formed on another component, this means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0042] In the description of the embodiments of this application, when a component is referred to as "including" another component, unless otherwise specified, this does not exclude other components, and other components may further be included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on" another component, it may be "directly on" the other component (i.e., located on the surface of the other component with no other components between them) or another component may be present between them. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "directly on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, this means that no other components are located between them.

[0043] The terms used herein in the description of the various embodiments are intended only to describe the specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is intended to include the plural form unless the context clearly indicates otherwise. A component includes a layer, film, region, or plate.

[0044] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to help readers better understand the embodiments of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present application can still be implemented.

[0045] An embodiment of the present application provides a back-contact battery, which will be described in detail below with reference to the accompanying drawings.

[0046] refer to Figure 1 、 Figure 2 or Figure 3 The back-contact cell includes: a substrate 100, the substrate 100 having a first surface 110 and a second surface 120 opposite to each other along a first direction X, the second surface 120 having a first area 1201 and a second area 1202 alternately arranged along a second direction Y; a first dielectric layer 101 and a first doping layer 102 stacked on the first area 1201, the first doping layer 102 having a P-type doping element; a second dielectric layer 103 and a second doping layer 104 stacked on the second area 1202, the second doping layer 104 having an N-type doping element; wherein the first doping layer 102 includes N stacked layers of first doping films 112, and along a direction away from the substrate 100, the crystallization rate of the (N-1)th layer of the first doping film 112 is higher than the crystallization rate of the Nth layer of the first doping film 112, where N is a positive integer greater than or equal to 2.

[0047] in, Figure 1 A first partial cross-sectional schematic diagram of a back-contact battery provided in one embodiment of the present application; Figure 2A second partial cross-sectional schematic diagram of a back-contact battery provided in one embodiment of the present application; Figure 3 This is a third partial cross-sectional diagram of a back contact battery provided in one embodiment of the present application. It should be noted that: Figures 1 to 3 In the example, N is 2, that is, the first doping layer 102 includes two stacked first doping films 112. In actual applications, N can be designed to be 3, 4, or 5 according to specific needs.

[0048] It is worth noting that the first doping layer 102 is designed to include a stacked structure of multiple layers of first doping films 112 with different crystallinity, that is, different degrees of crystallization. On the one hand, the first doping film 112 with a higher crystallinity close to the substrate 100 can be regarded as a film layer structure with uniform internal grain distribution, so as to improve the film layer uniformity of the first doping film 112 with a higher crystallinity close to the substrate 100, and help to ensure that there is no grain precipitation on the surface of the first doping film 112 with a higher crystallinity close to the substrate 100, so that the first doping film 112 with a higher crystallinity close to the substrate 100 can be designed to have a higher crystallinity, so as to avoid the grains in the first doping layer 102 from damaging other film layers close to it, such as the first dielectric layer 101 and the substrate 100, so as to ensure that the first doping layer 102 is close to the first doping layer 102. The stability of the performance of other film layers near the first doped layer 102 is enhanced, thereby improving the passivation effect of other film layers on the substrate 100 near the first doped layer 102, thereby reducing the recombination probability of photogenerated carriers. On the other hand, the low crystallinity of the first doped film 112 away from the substrate 100 helps to improve the surface roughness of the first doped film 112 away from the substrate 100. For example, the surface of the first doped film 112 with a low crystallinity away from the substrate 100 has larger grains. Therefore, when designing an electrode on the side of the first doped layer 102 away from the substrate 100, the first doped film 112 with a low crystallinity is beneficial for improving the contact performance between the first doped layer 102 and the electrode, thereby improving the electrode's collection efficiency of photogenerated carriers and thereby improving the fill factor of the back-contact cell. Such multi-faceted effects can not only enhance the passivation effect on the substrate 100 through the cooperation of the first doped layer 102 and the first dielectric layer 101, but also reduce the migration barrier of photogenerated carriers in the first doped layer 102, thereby further improving the photoelectric conversion efficiency of the back-contact cell.

[0049] It should be noted that the crystallinity of the first doped film 112 of any layer in the first doped layer 102 can be determined through Raman spectroscopy. In Raman spectroscopy, the crystalline and amorphous portions of the first doped film 112 exhibit spectral peaks of varying intensities. By observing the intensities of the spectral peaks in different regions of the first doped film 112, the crystallinity of the first doped film 112 can be estimated.

[0050] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings.

[0051] In some embodiments, the N-type doping element may be at least one of Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As); the P-type semiconductor substrate is doped with a P-type element, and the P-type doping element may be at least one of Group III elements such as boron (B), aluminum (Al), gallium (Ga), or gallium (In).

[0052] The specific structure of the first doping layer 102 is described in detail below.

[0053] In some embodiments, reference Figures 1 to 3 , the grain size of the (N-1)th layer of the first doped film 112 can be smaller than the grain size of the Nth layer of the first doped film 112. It is worth noting that the size distribution of the multiple grains contained in the first doped film 112 with a higher crystallization rate is more uniform. In other words, the size difference between different grains in the first doped film 112 with a higher crystallization rate is not large. For example, dendritic grains are less likely to appear, which is less likely to cause damage to the film layers close to the first doped film 112, that is, the first dielectric layer 101 and the substrate 100. In contrast, the first doped film 112 with a lower crystallization rate is more likely to have different grains with large size differences. This allows the electrode to have more contact area with the grains in the first doped film 112 when part of the material in the subsequent electrode penetrates into the first doped film 112, thereby improving the contact performance between the electrode and the first doped film 112. Based on this, the grain size of the (N-1)th layer of the first doped film 112 is designed to be smaller than the grain size of the Nth layer of the first doped film 112, which is beneficial for improving the passivation effect of the first doped layer 102 and the first dielectric layer 101 on the substrate 100 and improving the contact performance between the first doped layer 102 and the electrode.

[0054] It should be noted that, in some cases, the grain size in the (N-1)th layer of the first doped film 112 is smaller than the grain size in the Nth layer of the first doped film 112, which can be characterized by: the average value of the sizes of the multiple grains in the Nth layer of the first doped film 112 is larger than the average value of the sizes of the multiple grains in the (N-1)th layer of the first doped film 112; in other cases, the grain size in the (N-1)th layer of the first doped film 112 is smaller than the grain size in the Nth layer of the first doped film 112, which can be characterized by: the size of the majority of the grains (for example, more than 80% of the grains) in the Nth layer of the first doped film 112 is larger than the size of the majority of the grains (for example, more than 80% of the grains) in the (N-1)th layer of the first doped film 112.

[0055] It is worth noting that the grain size of the first doping film 112 can be tested by SEM (Scanning Electron Microscope).

[0056] In some embodiments, reference Figures 1 to 3 , N is 2, the crystallization rate of the (N-1)th first doping film 112 can be greater than or equal to 99%, and the crystallization rate of the Nth first doping film 112 can be less than 95%. In other words, the first doping layer 102 can include two first doping films 112, one inside and one outside. The first first doping film 112 is a first inner doping film 1121 closer to the first dielectric layer 101, and the second first doping film 112 is a first outer doping film 1122.

[0057] Based on this, the crystallization rate of the first inner doped film 1121 is designed to be greater than or equal to 99%, and the crystallization rate of the first outer doped film 1122 is designed to be less than 95%. This results in both layers of the first doped film 112 having relatively high crystallization rates, which helps ensure that both layers of the first doped film 112 have relatively high film uniformity, thereby ensuring that both layers of the first doped film 112 have relatively high film quality and provide relatively good field passivation effects on the substrate 100. Furthermore, a crystallization rate of the first inner doped film 1121 close to 100% helps further ensure that the first inner doped film 1121 contains multiple grains of similar size, thereby preventing the grains in the first inner doped film 1121 from damaging the first dielectric layer 101 or the substrate 100, thereby ensuring that the first dielectric layer 101 has relatively good chemical passivation effects on the substrate 100. Furthermore, appropriately reducing the crystallization rate of the first outer doped film 1122 helps increase the contact area between the first outer doped film 1122 and the electrode by leveraging the larger grains in the first outer doped film 1122.

[0058] In some embodiments, reference Figures 1 to 3 , N is 2, the grain size of the (N-1)th layer of the first doping film 112 can be 100nm~180nm, for example, it can be 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, 155nm, 160nm, 165nm, 170nm or 175nm; the grain size of the Nth layer of the first doping film 112 can be 190nm~300nm, for example, it can be 195nm, 200nm, 205nm, 210nm, 215nm, 220nm, 225nm, 230nm, 235nm, 240nm, 245nm, 250nm, 255nm, 260nm, 265nm, 270nm, 275nm, 280nm, 285nm, 290nm or 295nm, etc.

[0059] In some embodiments, reference Figures 1 to 3, along the first direction X, the thickness of the (N-1)th layer of the first doped film 112 is less than the thickness of the Nth layer of the first doped film 112. Thus, when an electrode is subsequently designed on the side of the first doped layer 102 away from the substrate 100, the first doped film 112 closest to the electrode in the first doped layer 102, i.e., the outermost first doped film, has the greatest thickness. This facilitates utilizing the large thickness of the outermost first doped film and the large grains within the outermost first doped film to enhance the barrier effect of the outermost first doped film on the material constituting the electrode, thereby reducing the risk of the electrode burning through the first doped layer 102 during electrode fabrication.

[0060] In some embodiments, reference Figures 1 to 3 , N is 2, along the first direction X, the thickness of the (N-1)th layer of the first doping film 112, that is, the thickness of the first internal doping film 1121 can be 10nm~60nm, for example, can be 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm or 55nm; the thickness of the Nth layer of the first doping film 112, that is, the thickness of the first external doping film 1122 can be 10nm~500nm, for example, can be 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, etc. 0nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm, 300nm, 310nm, 320nm, 330nm, 340nm, 350nm, 360nm, 370nm, 380nm, 390nm, 400nm, 410nm, 420nm, 430nm, 440nm, 450nm, 460nm, 470nm, 480nm or 490nm, etc.

[0061] In some examples, the thickness of the first inner doping film 1121 may be 20 nm, and the thickness of the first outer doping film 1122 may be 330 nm.

[0062] The specific structure of the second doping layer 104 is described in detail below.

[0063] In some embodiments, reference Figure 2 or Figure 3 The second doping layer 104 may include M layers of second doping films 114 stacked together, and along the direction away from the substrate 100, the crystallization rate of the (M-1)th layer of the second doping film 114 is higher than the crystallization rate of the Mth layer of the second doping film 114, where M is a positive integer greater than or equal to 2.

[0064] It should be noted that Figure 2 and Figure 3 In the example, M is 2, that is, the second doping layer 104 includes two stacked second doping films 114. In actual applications, M can be designed to be 3, 4, or 5 according to specific needs.

[0065] It is worth noting that, similar to the first doping layer 102, the second doping layer 104 is also designed to include a multilayer structure of second doping films 114 with different crystallinity, that is, different degrees of crystallization. On the one hand, the second doping film 114 with a higher crystallinity close to the substrate 100 can be regarded as a film layer structure with uniform internal grain distribution, so as to improve the film layer uniformity of the second doping film 114 with a higher crystallinity close to the substrate 100, and help to ensure that there is no grain precipitation on the surface of the second doping film 114 with a higher crystallinity close to the substrate 100, so that the second doping film 114 with a higher crystallinity close to the substrate 100 can be designed to have a higher crystallinity, so as to avoid the grains in the second doping film 114 from damaging other film layers close to it, such as the second dielectric layer 103 and the substrate 100, so as to ensure that the second doping film 114 with a higher crystallinity close to the substrate 100 is not damaged. The stability of the performance of other film layers in the second doped layer 104 is enhanced, thereby improving the passivation effect of other film layers near the second doped layer 104 on the substrate 100, thereby reducing the recombination probability of photogenerated carriers. On the other hand, the lower crystallinity of the second doped film 114 away from the substrate 100 helps to improve the surface roughness of the second doped film 114 away from the substrate 100. For example, the surface of the second doped film 114 with a lower crystallinity away from the substrate 100 has larger grains. Therefore, when designing an electrode on the side of the second doped layer 104 away from the substrate 100, the second doped film 114 with a lower crystallinity is beneficial for improving the contact performance between the second doped layer 104 and the electrode, thereby improving the electrode's collection efficiency of photogenerated carriers and thereby improving the fill factor of the back-contact solar cell. These multiple effects can not only enhance the passivation effect of the second doped layer 104 on the substrate 100 through the cooperation of the second doped layer 104 and the second dielectric layer 103, but also reduce the migration barrier of photogenerated carriers in the second doped layer 104, thereby further improving the photoelectric conversion efficiency of the back-contact solar cell.

[0066] It should be noted that the crystallinity of the second doped film 114 of any layer in the second doped layer 104 can also be obtained through Raman spectroscopy testing.

[0067] In some cases, reference Figure 2 or Figure 3The grain size of the (M-1)th layer of the second doped film 114 can be smaller than that of the Mth layer of the second doped film 114. It is worth noting that the size differences between different grains in the second doped film 114 with a higher crystallinity are less pronounced. For example, dendritic grains are less likely to form, which reduces the likelihood of damage to the layers near the second doped film 114, namely, the second dielectric layer 103 and the substrate 100. In contrast, the second doped film 114 with a lower crystallinity is more likely to have grains with significantly different sizes. This allows for greater contact area between the electrode and the grains in the second doped film 114 when part of the material in the subsequent electrode penetrates into the second doped film 114, thereby improving the contact performance between the electrode and the second doped film 114. Therefore, designing the grain size of the (M-1)th layer of the second doped film 114 to be smaller than that of the Mth layer of the second doped film 114 is beneficial for both enhancing the passivation effect of the second doped layer 104 and the second dielectric layer 103 on the substrate 100 and improving the contact performance between the second doped layer 104 and the electrode.

[0068] It should be noted that, in some cases, the grain size in the (M-1)th layer of the second doped film 114 is smaller than the grain size in the Mth layer of the second doped film 114, which can be characterized by: the average value of the sizes of the multiple grains in the Mth layer of the second doped film 114 is larger than the average value of the sizes of the multiple grains in the (M-1)th layer of the second doped film 114; in other cases, the grain size in the (M-1)th layer of the second doped film 114 is smaller than the grain size in the Mth layer of the second doped film 114, which can be characterized by: the size of the majority of the grains (for example, more than 80% of the grains) in the Mth layer of the second doped film 114 is larger than the size of the majority of the grains (for example, more than 80% of the grains) in the (M-1)th layer of the second doped film 114.

[0069] It is worth noting that the grain size of the second doping film 114 can be tested by SEM (Scanning Electron Microscope).

[0070] In some cases, reference Figure 2 or Figure 3 , M is 2, the crystallization rate of the (M-1)th second doping film 114 can be greater than or equal to 99%, and the crystallization rate of the Mth second doping film 114 can be less than 95%. In other words, the second doping layer 104 can include two inner and outer second doping films 114. The first second doping film 114 is a second inner doping film 1141 closer to the second dielectric layer 103, and the second second doping film 114 is a second outer doping film 1142.

[0071] Based on this, the crystallization rate of the second inner doped film 1141 is designed to be greater than or equal to 99%, and the crystallization rate of the second outer doped film 1142 is designed to be less than 95%. This results in both layers of the second doped film 114 having high crystallization rates, which helps ensure that both layers of the second doped film 114 have high film uniformity, thereby ensuring that both layers of the second doped film 114 have high film quality and provide excellent field passivation effects on the substrate 100. Furthermore, a crystallization rate of the second inner doped film 1141 close to 100% helps further ensure that the second inner doped film 1141 contains multiple grains of similar size, thereby preventing the grains in the second inner doped film 1141 from damaging the second dielectric layer 103 or the substrate 100, thereby ensuring that the second dielectric layer 103 has an excellent chemical passivation effect on the substrate 100. Furthermore, appropriately reducing the crystallization rate of the second outer doped film 1142 helps increase the contact area between the second outer doped film 1142 and the electrode by leveraging the larger grains in the second outer doped film 1142.

[0072] In some cases, reference Figure 2 or Figure 3 , M is 2, the grain size of the (M−1)th second doping film 114 may be 100 nm to 180 nm, and the grain size of the Mth second doping film 114 may be 190 nm to 300 nm.

[0073] In some cases, reference Figure 2 or Figure 3 , along the first direction X, the thickness of the (M-1)th second doped film 114 is less than the thickness of the Mth second doped film 114. Thus, when an electrode is subsequently designed on the side of the second doped layer 104 away from the substrate 100, the second doped film 114 closest to the electrode in the second doped layer 104, i.e., the outermost second doped film, has the greatest thickness. This facilitates utilizing the large thickness of the outermost second doped film and the large grains within the outermost second doped film to enhance the barrier effect of the outermost second doped film on the material constituting the electrode, thereby reducing the risk of the electrode burning through the second doped layer 104 during electrode fabrication.

[0074] In some cases, reference Figure 2 or Figure 3 , M is 2, along the first direction X, the thickness of the (M-1)th layer of the second doped film 114, that is, the second inner doped film 1141 can be 10nm~60nm; the thickness of the Mth layer of the second doped film 114, that is, the second outer doped film 1142 can be 10nm~500nm.

[0075] In some examples, the thickness of the second inner doping film 1141 may be 20 nm, and the thickness of the second outer doping film 1142 may be 180 nm.

[0076] In other embodiments, reference Figure 1 In the direction away from the substrate 100, the first doped layer 102 includes an N-type first doped film 112 with a gradually decreasing crystallinity. The second doped layer 104 can also be a single-layer structure. It is worth noting that the film properties of the doped layer, such as the crystallinity, are also affected by the doping elements contained in the doped layer. The first doped layer 102 is doped with a P-type doping element, and the second doped layer 104 is doped with an N-type doping element. Due to the difference in the doping elements contained in the first doped layer 102 and the second doped layer 104, the second doped layer 104 having a single-layer structure can also take into account the passivation performance of the second dielectric layer 103 on the substrate 100 and the contact performance between the second doped layer 104 and the electrode.

[0077] The material of the first doping layer 102 and the material of the second doping layer 104 are described in detail below.

[0078] In some embodiments, reference Figures 1 to 3 The material of the first doping layer 102 and the material of the second doping layer 104 both include polysilicon, and the back contact cell is a TBC cell (TOPCon Back Contact, referring to a cross-passivated back contact cell).

[0079] In some cases, reference Figure 2 or Figure 3 , similar to the first doping layer 102, the second doping layer 104 is a stacked structure including multiple layers of second doping films 114 with different crystallinity rates. Figure 1 Different from the first doped layer 102 , the second doped layer 104 is a single-layer polysilicon layer.

[0080] In some cases, reference Figures 1 to 3 At least one of the first doped layer 102 and the second doped layer 104 is polysilicon doped with carbon or nitrogen. It is worth noting that the first doped layer 102 and the second doped layer 104 are collectively referred to as doped layers. Doping carbon or nitrogen in both the first doped layer 102 and the second doped layer 104 is beneficial for increasing the band gap of the doped layer, thereby reducing the parasitic absorption of light by the doped layer and increasing the photogenerated carrier density generated by the substrate 100.

[0081] In some examples, based on the first doping layer 102 being polycrystalline silicon doped with both P-type doping elements and carbon or nitrogen elements, the second doping layer 104 can be polycrystalline silicon doped with N-type doping elements, or polycrystalline silicon doped with both N-type doping elements and carbon or nitrogen elements; in other examples, based on the first doping layer 102 being polycrystalline silicon doped with P-type doping elements, the second doping layer 104 can be polycrystalline silicon doped with N-type doping elements, or polycrystalline silicon doped with both N-type doping elements and carbon or nitrogen elements.

[0082] It should be noted that, the case where the first doping layer 102 contains a P-type doping element includes that each layer of the first doping film 112 in the first doping layer 102 contains a P-type doping element; the case where the first doping layer 102 is doped with carbon elements or nitrogen elements includes that at least one layer of the first doping film 112 in the first doping layer 102 is doped with carbon elements or nitrogen elements; the case where the second doping layer 104 contains an N-type doping element includes that each layer of the second doping film 114 in the second doping layer 104 contains an N-type doping element; the case where the second doping layer 104 is doped with carbon elements or nitrogen elements includes that at least one layer of the second doping film 114 in the second doping layer 104 is doped with carbon elements or nitrogen elements.

[0083] In other embodiments, reference Figure 1 The material of the first doped layer 102 may include polycrystalline silicon, the material of the second doped layer 104 may include amorphous silicon, and the back contact cell is an HTBC cell, which is a hybrid back contact photovoltaic cell (heterojunction tunnel oxide passivated contact, hybrid passivated back contact photovoltaic cell, abbreviated as HTBC). It is worth noting that in this case, unlike the first doped layer 102, the second doped layer 104 may be a single amorphous silicon layer.

[0084] The thickness of the first doping layer 102 and the thickness of the second doping layer 104 are described in detail below. It should be noted that the thickness of the first doping layer 102 mentioned below refers to the total thickness of the N-layer first doping film 112 in the first doping layer 102, and the thickness of the second doping layer 104 refers to the thickness of the second doping layer 104 with a single film layer structure, or the total thickness of the M-layer second doping film 114 in the second doping layer 104.

[0085] In some embodiments, along the first direction X, the thickness of the first doping layer 102 and the thickness of the second doping layer 104 can both be 50nm~500nm, for example, can be 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm or 450nm.

[0086] In some embodiments, reference Figures 1 to 3 , along the first direction X, the thickness of the first doping layer 102 may be greater than the thickness of the second doping layer 104 .

[0087] It's worth noting that the film properties of the doped layer, such as its burn-through resistance, are affected by the doping elements within the doped layer. During subsequent electrode fabrication, the presence of a P-type doping element in the first doped layer 102 makes it more susceptible to electrode burn-through compared to the presence of an N-type doping element in the second doped layer 104. Therefore, making the first doped layer 102 thicker than the second doped layer 104 further reduces the risk of electrode burn-through during electrode fabrication.

[0088] In some embodiments, reference Figures 1 to 3 The doping concentration of the P-type doping element in the first doping layer 102 may be 5×10 18 atom / cm 3 ~8×10 20 atom / cm 3 , for example, it can be 6×10 18 atom / cm 3 , 7×10 18 atom / cm 3 , 8×10 18 atom / cm 3 , 9×10 18 atom / cm 3 , 1×10 19 atom / cm 3 , 2×10 19 atom / cm 3 , 3×10 19 atom / cm 3 , 4×10 19 atom / cm 3 , 5×10 19 atom / cm 3 , 6×10 19 atom / cm 3 , 7×10 19 atom / cm 3 , 8×10 19 atom / cm 3 , 9×10 19 atom / cm 3 , 1×10 20 atom / cm 3 , 2×10 20 atom / cm 3 , 3×10 20 atom / cm 3 , 4×10 20 atom / cm 3 , 5×10 20 atom / cm3 , 6×10 20 atom / cm 3 or 7×10 20 atom / cm 3 wait.

[0089] In some embodiments, reference Figures 1 to 3 The doping concentration of the N-type doping element in the second doping layer 104 may be 5×10 19 atom / cm 3 ~9×10 20 atom / cm 3 , for example, it can be 6×10 19 atom / cm 3 , 7×10 19 atom / cm 3 , 8×10 19 atom / cm 3 , 9×10 19 atom / cm 3 , 1×10 20 atom / cm 3 , 2×10 20 atom / cm 3 , 3×10 20 atom / cm 3 , 4×10 20 atom / cm 3 , 5×10 20 atom / cm 3 , 6×10 20 atom / cm 3 , 7×10 20 atom / cm 3 or 8×10 20 atom / cm 3 wait.

[0090] The following describes in detail the material of the first dielectric layer 101 and the material of the second dielectric layer 103. It should be noted that in the same back contact cell, the material of the first dielectric layer 101 and the material of the second dielectric layer 103 can be the same or different.

[0091] In some embodiments, reference Figures 1 to 3 The material of at least one of the first dielectric layer 101 and the second dielectric layer 103 includes aluminum oxide or silicon nitride.

[0092] In some cases, the material of the first dielectric layer 101 and the material of the second dielectric layer 103 may both include aluminum oxide or silicon nitride, and the first dielectric layer 101 and the second dielectric layer 103 are both tunneling layers, and the back contact cell is a TBC cell.

[0093] It is worth noting that, compared to a tunneling layer made of silicon oxide, designing the first and second dielectric layers 101, 103 to be made of aluminum oxide or silicon nitride further reduces distortion in the first and second dielectric layers 101, 103, thereby improving the passivation effect of the first and second dielectric layers 101, 103 on the substrate 100. Furthermore, boron tends to accumulate in silicon oxide layers, thereby degrading the passivation properties of silicon oxide. Designing the first and second dielectric layers 101, 103 to be made of aluminum oxide or silicon nitride helps prevent boron accumulation in the first and second dielectric layers 101, 103, thereby ensuring higher passivation properties for the first and second dielectric layers 101, 103.

[0094] In other cases, under the premise that the material of the first dielectric layer 101 includes aluminum oxide or silicon nitride, the material of the second dielectric layer 103 may include at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride, then the first dielectric layer 101 and the second dielectric layer 103 are both tunneling layers, and the back contact battery is a TBC battery; alternatively, the material of the second dielectric layer 103 may include at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon, and the back contact battery is a HTBC battery.

[0095] In some other cases, the material of the second dielectric layer 103 may include aluminum oxide or silicon nitride, and the material of the first dielectric layer 101 may include at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride. In this case, the first dielectric layer 101 and the second dielectric layer 103 are both tunneling layers, and the back contact battery is a TBC battery.

[0096] In other embodiments, reference Figures 1 to 3 The material of at least one of the first dielectric layer 101 and the second dielectric layer 103 may include at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride.

[0097] In some cases, the material of the first dielectric layer 101 and the material of the second dielectric layer 103 may include at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride, and the back contact cell is a TBC cell.

[0098] In other cases, the material of the first dielectric layer 101 may include at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride, the material of the second dielectric layer 103 may include at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon, and the back contact cell is a HTBC cell.

[0099] In some embodiments, along the first direction X, the thickness of the first dielectric layer 101 and the second dielectric layer 103 can be 1 nm to 2 nm, for example, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm or 1.9 nm.

[0100] In some embodiments, reference Figure 3 The back-contact cell may further include: a first passivation layer 118, located on the first surface 110 and at least on the surface of the first doped layer 102 and the second doped layer 104 away from the substrate 100; and a second passivation layer 128, located on the surface of the first passivation layer 118 away from the substrate 100. It is worth noting that both the first passivation layer 118 and the second passivation layer 128 can serve as passivation anti-reflection layers to reduce the reflectivity of the ultimately formed back-contact cell to light, thereby improving the absorption and utilization efficiency of the incident light by the back-contact cell.

[0101] In some cases, the material of the first passivation layer 118 may be aluminum oxide, and the material of the second passivation layer 128 may be silicon nitride.

[0102] In some cases, along the first direction X, the thickness of the first passivation layer 118 may be 3 nm to 10 nm, for example, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, or 9 nm.

[0103] In some cases, along the first direction X, the thickness of the second passivation layer 128 can be 70nm~90nm, for example, it can be 71nm, 72nm, 73nm, 74nm, 75nm, 76nm, 77nm, 78nm, 79nm, 80nm, 81nm, 82nm, 83nm, 84nm, 85nm, 86nm, 87nm, 88nm or 89nm, etc.

[0104] In some embodiments, reference Figure 3 The back-contact cell may further include: a first electrode 119, which is in contact with at least the side of the first doped layer 102 away from the substrate 100; and a second electrode 129, which is in contact with at least the side of the second doped layer 104 away from the substrate 100. It should be noted that the aforementioned "electrode designed on the side of the first doped layer 102 away from the substrate 100" refers to the first electrode 119, and the aforementioned "electrode designed on the side of the second doped layer 104 away from the substrate 100" refers to the second electrode 129.

[0105] In summary, the first doping layer 102 is designed to be a stacked structure including multiple layers of first doping films 112 with different crystallinity rates. On the one hand, the first doping film 112 with a higher crystallinity rate close to the substrate 100 can improve the uniformity of its own film layer, which helps to prevent the surface of the first doping film 112 with a higher crystallinity rate close to the substrate 100 from precipitating grains. Therefore, the first doping film 112 close to the substrate 100 can be designed to have a higher crystallinity rate to avoid the grains in the first doping layer 102 from damaging other film layers close to it, such as the first dielectric layer 101 and the substrate 100, so as to ensure the stability of the performance of other film layers close to the first doping layer 102, thereby improving the performance of the first doping film 112 close to the substrate 100. On the other hand, the other film layers of the first doped layer 102 have a passivation effect on the substrate 100, thereby reducing the recombination probability of photogenerated carriers. On the other hand, the first doped film 112 away from the substrate 100 has a low crystallinity, which helps to improve the surface roughness of the first doped film 112 away from the substrate 100. For example, the surface of the first doped film 112 with a low crystallinity away from the substrate 100 has larger grains. Therefore, when designing an electrode on the side of the first doped layer 102 away from the substrate 100, it is beneficial to use the first doped film 112 with a low crystallinity to improve the contact performance between the first doped layer 102 and the electrode, thereby improving the electrode's collection efficiency of photogenerated carriers and thus improving the fill factor of the back-contact cell. Such multi-faceted effects can not only improve the passivation effect on the substrate 100 with the cooperation of the first doped layer 102 and the first dielectric layer 101, but also reduce the migration barrier of photogenerated carriers in the first doped layer 102, thereby further improving the photoelectric conversion efficiency of the back-contact cell.

[0106] Another embodiment of the present application also provides a method for manufacturing a back-contact cell, which is used to form the back-contact cell provided in the aforementioned embodiment. The following detailed description of the method for manufacturing a back-contact cell provided in another embodiment of the present application is provided in conjunction with the accompanying drawings. It should be noted that parts that are identical or corresponding to the aforementioned embodiments are not repeated here.

[0107] refer to Figure 4 as well as Figures 5 to 11 , Figure 4 A process flow chart corresponding to a method for manufacturing a back-contact battery provided in another embodiment of the present application; Figures 5 to 11 A partial cross-sectional schematic diagram corresponding to each step in a method for manufacturing a back-contact battery provided in another embodiment of the present application; the method for manufacturing a back-contact battery includes at least the following steps: S1: Reference Figure 5 , providing a substrate 100, the substrate 100 having a first surface 110 and a second surface 120 opposite to each other along a first direction X, and the second surface 120 having first areas 1201 and second areas 1202 alternately arranged along a second direction Y.

[0108] S2: Combined with reference Figures 5 to 8 , forming a first dielectric layer 101 and a first doping layer 102 stacked on the first region 1201, wherein the first doping layer 102 contains a P-type doping element.

[0109] In step S2, the step of forming the first doping layer 102 may include: referring to Figure 5 , a first semiconductor layer 105 is formed on the second surface 120 by a first deposition process, the first deposition process includes N deposition stages connected in sequence, the deposition temperature of the (N-1)th deposition stage is lower than the deposition temperature of the Nth deposition stage, N is a positive integer greater than or equal to 2; combined with reference Figure 5 and Figure 6 , performing a first doping treatment on the first semiconductor layer 105 so that the first semiconductor layer 105 is converted into an initial first doping layer 122 doped with a P-type doping element; Figures 6 to 8 , the initial first doping layer 122 is subjected to a first patterning process, and only the initial first doping layer 122 located on the first region 1201 is retained as the first doping layer 102, and the first doping layer 102 includes N stacked layers of first doping films 112. In the direction away from the substrate 100, the crystallization rate of the (N-1)th layer of the first doping film 112 is higher than the crystallization rate of the Nth layer of the first doping film 112.

[0110] S3: Combined with reference Figures 9 to 11 ,as well as Figure 2 , forming a second dielectric layer 103 and a second doping layer 104 stacked on the second region 1202 , wherein the second doping layer 104 contains N-type doping elements.

[0111] It is worth noting that before the first doping treatment is performed, that is, before the P-type doping element is doped, the first semiconductor layer 105 is formed by variable temperature deposition. In other words, the first semiconductor layer 105 includes an N-layer first semiconductor film 115 stacked together. After the first doping treatment and the first patterning treatment are performed on the first semiconductor layer 105, the N-layer first semiconductor film 115 is sequentially transformed into an N-layer first doped film 112.

[0112] Based on this, during the step of forming the first semiconductor layer 105, the deposition temperature of the (N-1)th deposition stage is designed to be lower than the deposition temperature of the Nth deposition stage. In other words, the deposition temperature of the first deposition process is designed to increase step by step. This increase in deposition temperature, on the one hand, prevents the formation of large grains in the first semiconductor film 115 near the substrate 100, prevents the precipitation of grains on the surface of the first semiconductor film 115 near the substrate 100, and prevents damage to the first dielectric layer 101 and the substrate 100, thereby ensuring that the first dielectric layer 101 effectively passivates the substrate 100. On the other hand, it facilitates the formation of larger grains, such as dendrites, in the first semiconductor film 115 away from the substrate 100. These multiple effects ultimately facilitate the formation of a first doped layer 102 having a higher crystallinity of the (N-1)th layer of the first doped film 112 than that of the Nth layer of the first doped film 112.

[0113] The following is a detailed description of a method for manufacturing a back-contact battery provided in another embodiment of the present application.

[0114] In some embodiments, reference Figure 5 Before forming the first semiconductor layer 105 on the second surface 120, the method for manufacturing a back contact battery further includes: forming an initial first dielectric layer 111 on the second surface 120; Figures 6 to 8 In the step of performing the first patterning process on the initial first doping layer 122 , the initial first dielectric layer 111 is further patterned, and only the initial first dielectric layer 111 located on the first region 1201 is retained as the first dielectric layer 101 .

[0115] The following describes in detail the method for manufacturing the first doping layer 102 .

[0116] In some embodiments, reference Figure 5 , N is 2, and the first deposition process includes a first deposition stage and a second deposition stage connected in sequence. The deposition temperature of the first deposition stage can be 520° C. to 570° C., for example, 525° C., 530° C., 535° C., 540° C., 545° C., 550° C., 555° C., 560° C., or 565° C.; the deposition temperature of the second deposition stage is 580° C. to 650° C., for example, 585° C., 590° C., 595° C., 600° C., 605° C., 610° C., 615° C., 620° C., 625° C., 630° C., 635° C., 640° C., or 645° C. This is advantageous in ensuring that the crystallization rate of the first semiconductor film 115 formed in the first deposition stage is higher than the crystallization rate of the first semiconductor film 115 formed in the second deposition stage.

[0117] It should be noted that, in conjunction with the reference Figure 5 and Figure 6The formed first semiconductor layer 105 includes two layers of first semiconductor films 115. Based on this, the initial first doping layer 122 formed after the first semiconductor layer 105 is subjected to the first doping treatment includes an initial first inner doping layer 1221 and an initial first outer doping layer 1222 that are stacked.

[0118] In some embodiments, before forming the first semiconductor layer 105, a semi-finished back-contact cell on which the first semiconductor layer 105 is to be formed is placed in a reaction chamber. During the process of forming the first semiconductor layer 105 using the first deposition process, a carbon-containing gas or a nitrogen-containing gas is introduced into the reaction chamber, so that the formed first semiconductor layer 105 is doped with carbon or nitrogen. This facilitates doping the first doped layer 102 formed based on the first semiconductor layer 105 with carbon or nitrogen, thereby increasing the band gap of the first doped layer 102, reducing the parasitic absorption of light by the first doped layer 102, and thereby increasing the density of photogenerated carriers generated by the substrate 100.

[0119] It should be noted that, since the first deposition process includes N deposition stages connected in sequence, the step of introducing carbon-containing gas or nitrogen-containing gas into the reaction chamber can be designed in at least one deposition stage, so that at least one layer of the first semiconductor film 115 is doped with carbon elements or nitrogen elements, and at least one layer of the first doped film 112 in the first doping layer 102 formed based on the first semiconductor layer 105 is doped with carbon elements or nitrogen elements.

[0120] In some examples, the carbon-containing gas may be methane, and the nitrogen-containing gas may be ammonia.

[0121] In some embodiments, in conjunction with reference Figure 5 and Figure 6 In the step of performing the first doping treatment on the first semiconductor layer 105, a first protective layer 116 is formed on the side of the initial first doping layer 122 away from the substrate 100; Figure 6 and Figure 7 , the first protective layer 116 located on the second area 1202 is removed by a first laser; Figure 7 and Figure 8 , a first etching process is used to remove the initial first doping layer 122 located on the second region 1202 , and the remaining initial first doping layer 122 is the first doping layer 102 .

[0122] in, Figure 5 A schematic partial cross-sectional view after forming a first semiconductor layer in a method for manufacturing a back-contact battery according to another embodiment of the present application; Figure 6 A schematic partial cross-sectional view after a first doping treatment is performed in a method for manufacturing a back-contact cell provided in another embodiment of the present application; Figure 7A schematic partial cross-sectional view of a back-contact cell after being processed by a first laser in a method for manufacturing the back-contact cell according to another embodiment of the present application; Figure 8 A schematic partial cross-sectional view of a back-contact cell manufacturing method according to another embodiment of the present application after a first etching process is used.

[0123] In some cases, in conjunction with reference Figures 6 to 8 An isolation region 1203 is also designed between the first region 1201 and the second region 1202. In the step of using the first laser to remove the first protective layer 116 located on the second region 1202, the first laser is also used to remove the first protective layer 116 located on the isolation region 1203; in the step of using the first etching process to remove the initial first doping layer 122 located on the second region 1202, the first etching process is also used to remove the initial first doping layer 122 located on the isolation region 1203.

[0124] In some cases, the first laser can be a purple laser or a green laser, and the power of the laser generating the first laser can be 5W~80W, for example, it can be 10W, 15W, 20W, 25W, 30W, 35W, 40W, 45W, 50W, 55W, 60W, 65W, 70W or 75W, etc.

[0125] It's worth noting that both purple lasers and green lasers are picosecond lasers, which are ultrashort pulse lasers. Purple lasers can also refer to ultraviolet picosecond lasers, and green lasers can also refer to green picosecond lasers. Compared to green lasers, purple lasers have a shorter wavelength, penetrate deeper into the film layer, and their energy is more concentrated on the film surface, both of which help reduce the risk of significant laser damage to the initial first doped layer 122 caused by the first laser.

[0126] In some examples, the P-type doping element may be boron (B). Therefore, during the first doping step of the first semiconductor layer 105, the first protective layer 116 formed on the side of the initial first doping layer 122 away from the substrate 100 may be borosilicate glass (BSG). Furthermore, both the initial first doping layer 122 and the first protective layer 116 are coated around a portion of the first surface 110.

[0127] In some examples, in conjunction with reference Figure 7 and Figure 8The steps of performing the first etching process include: first using a chain pickling process to remove the first protective layer (not shown in the figure) plated on the first surface 110; then using an alkaline etching process to remove the initial first doping layer 122 plated on the first surface 110 and located on the second area 1202, and further removing the initial first dielectric layer 111 located on the second area 1202. The remaining initial first dielectric layer 111 located on the first area 1201 is the first dielectric layer 101.

[0128] In one example, during the alkaline etching process, after removing the initial first doping layer 122 and the initial first dielectric layer 111 located on the second region 1202, the exposed second region 1202 is polished so that the surface of the portion of the substrate 100 located in the second region 1202 is further recessed toward the interior of the substrate 100 than the surface of the portion of the substrate 100 located in the first region 1201. For example, the height difference between the surface of the first region 1201 and the surface of the second region 1202 is 3 μm to 8 μm. In other words, the portion of the substrate 100 located in the second region 1202 is etched to a depth of 3 μm to 8 μm.

[0129] In one example, an isolation region 1203 is further designed between the first region 1201 and the second region 1202 , and the alkaline etching process further removes the initial first doping layer 122 and the initial first dielectric layer 111 located on the isolation region 1203 .

[0130] The following describes in detail the method for manufacturing the second doping layer 104 .

[0131] In some embodiments, the step of forming the second doping layer 104 may include: referring to Figure 9 , a second semiconductor layer 107 is formed on the second surface 120 by a second deposition process, the second deposition process includes M temperature control stages connected in sequence, the process temperature of the (M-1)th temperature control stage is lower than the process temperature of the Mth temperature control stage, M is a positive integer greater than or equal to 2; combined with reference Figure 9 and Figure 10 , performing a second doping treatment on the second semiconductor layer 107 so that the second semiconductor layer 107 is converted into an initial second doping layer 124 doped with an N-type doping element; Figure 10 、 Figure 11 and Figure 2 , the initial second doping layer 124 is subjected to a second patterning process, and only the initial second doping layer 124 located on the second region 1202 is retained as the second doping layer 104, and the second doping layer 104 includes M layers of second doping films 114 stacked together. In the direction away from the substrate 100, the crystallization rate of the (M-1)th layer of the second doping film 114 is higher than the crystallization rate of the Mth layer of the second doping film 114.

[0132] It is worth noting that before the second doping treatment is performed, that is, before the N-type doping element is doped, the second semiconductor layer 107 can also be formed by temperature-variable deposition. In other words, the second semiconductor layer 107 includes M layers of stacked second semiconductor films 117. After the second semiconductor layer 107 is subsequently subjected to the second doping treatment and the second patterning treatment, the M layers of second semiconductor films 117 are sequentially transformed into M layers of second doped films 114.

[0133] Based on this, during the step of forming the second semiconductor layer 107, the process temperature of the (M-1)th temperature control stage is designed to be lower than the process temperature of the Mth temperature control stage. In other words, the process temperature of the second deposition process is designed to increase step by step. This increase in process temperature, on the one hand, prevents the formation of large grains in the second semiconductor film 117 near the substrate 100, prevents the precipitation of grains on the surface of the second semiconductor film 117 near the substrate 100, and prevents damage to the second dielectric layer 103 and the substrate 100, thereby ensuring that the second dielectric layer 103 effectively passivates the substrate 100. On the other hand, it facilitates the formation of larger grains, such as dendrites, in the second semiconductor film 117 away from the substrate 100. These multiple effects ultimately facilitate the formation of a second doped layer 104 with a higher crystallinity than the Mth second doped film 114.

[0134] In some cases, reference Figure 9 Before forming the second semiconductor layer 107 on the second surface 120, the method for manufacturing a back contact battery further includes: forming an initial second dielectric layer 113 on the second surface 120; Figure 10 、 Figure 11 and Figure 2 In the step of performing a second patterning process on the initial second doping layer 124 , a second patterning process is further performed on the initial second dielectric layer 113 , and only the initial second dielectric layer 113 located on the second region 1202 is retained as the second dielectric layer 103 .

[0135] In some cases, reference Figure 9 , M is 2, and the second deposition process includes a first temperature control stage and a second temperature control stage connected in sequence. The process temperature of the first temperature control stage is 520°C to 570°C, and the process temperature of the second temperature control stage is 580°C to 650°C. This is conducive to making the crystallization rate of the second semiconductor film 117 formed in the first temperature control stage higher than the crystallization rate of the second semiconductor film 117 formed in the second temperature control stage.

[0136] It should be noted that, in conjunction with the reference Figure 9 and Figure 10The formed second semiconductor layer 107 includes two layers of second semiconductor films 117. Based on this, the initial second doping layer 124 formed after the second semiconductor layer 107 is subjected to the second doping treatment includes an initial second inner doping layer 1241 and an initial second outer doping layer 1242 stacked together.

[0137] In some cases, before forming the second semiconductor layer 107, a semi-finished back-contact cell on which the second semiconductor layer 107 is to be formed is placed in a reaction chamber. During the second deposition process for forming the second semiconductor layer 107, a carbon-containing gas or a nitrogen-containing gas is introduced into the reaction chamber, so that the formed second semiconductor layer 107 is doped with carbon or nitrogen. This facilitates doping the second doped layer 104 formed based on the second semiconductor layer 107 with carbon or nitrogen, thereby increasing the band gap of the second doped layer 104, reducing parasitic absorption of light by the second doped layer 104, and thereby increasing the density of photogenerated carriers generated by the substrate 100.

[0138] It should be noted that, since the second deposition process includes M temperature control stages connected in sequence, the step of introducing carbon-containing gas or nitrogen-containing gas into the reaction chamber can be designed in at least one temperature control stage, so that at least one layer of the second semiconductor film 117 is doped with carbon elements or nitrogen elements, and at least one layer of the second doped film 114 in the second doping layer 104 formed based on the second semiconductor layer 107 is doped with carbon elements or nitrogen elements.

[0139] In some examples, the carbon-containing gas may be methane, and the nitrogen-containing gas may be ammonia.

[0140] In some cases, in conjunction with reference Figure 9 and Figure 10 In the step of performing the second doping treatment on the second semiconductor layer 107, a second protective layer 126 is formed on the side of the initial second doping layer 124 away from the substrate 100; Figure 10 and Figure 11 , a second laser is used to remove the second protective layer 126 located on the first area 1201; Figure 11 and Figure 2 , a second etching process is used to remove the initial second doping layer 124 located on the first region 1201 , and the remaining initial second doping layer 124 is the second doping layer 104 .

[0141] in, Figure 9 A schematic partial cross-sectional view after forming a second semiconductor layer in a method for manufacturing a back-contact battery according to another embodiment of the present application; Figure 10 A schematic partial cross-sectional view of a back-contact cell after a second doping treatment is performed in a method for manufacturing a back-contact cell according to another embodiment of the present application; Figure 11A schematic partial cross-sectional view of a back-contact cell after being processed by a second laser in a method for manufacturing the back-contact cell provided in another embodiment of the present application.

[0142] In some cases, in conjunction with reference Figure 10 、 Figure 11 and Figure 2 An isolation region 1203 is also designed between the first region 1201 and the second region 1202. In the step of using a second laser to remove the second protective layer 126 located on the first region 1201, the second laser is also used to remove the second protective layer 126 located on the isolation region 1203; in the step of using a second etching process to remove the initial second doped layer 124 located on the first region 1201, the second etching process is also used to remove the initial second doped layer 124 located on the isolation region 1203.

[0143] In some cases, the second laser may be a purple laser or a green laser, and the power of the laser generating the second laser may be 5W to 80W.

[0144] In some examples, the N-type doping element may be phosphorus (P). Therefore, during the second doping step of the second semiconductor layer 107, the second protective layer 126 formed on the side of the initial second doping layer 124 away from the substrate 100 may be phosphosilicate glass (PSG). Furthermore, both the initial second doping layer 124 and the second protective layer 126 are coated around a portion of the first surface 110.

[0145] In some examples, in conjunction with reference Figure 11 and Figure 2 The steps of performing the second etching process include: first using a chain pickling process to remove the second protective layer 126 (not shown in the figure) plated on the first surface 110; then using an alkaline solution to remove the initial second doping layer 124 plated around the first surface 110 and located on the first area 1201, and further removing the initial second dielectric layer 113 located on the first area 1201. The remaining initial second dielectric layer 113 located on the second area 1202 is the second dielectric layer 103.

[0146] In one example, an isolation region 1203 is further designed between the first region 1201 and the second region 1202. When an alkaline solution is used to remove the initial second doping layer 124 and the initial second dielectric layer 113 located on the first region 1201, the initial second doping layer 124 and the initial second dielectric layer 113 located on the isolation region 1203 are also removed.

[0147] It should be noted that Figure 11The exposed isolation region 1203 is used as a polished surface as an example. In actual applications, after removing the initial second doping layer and the initial second dielectric layer on the first region, the exposed first surface and the isolation region are further textured to form a textured surface. For example, the textured surface reflectivity of the first surface and the isolation region is 7% to 10%, and the size of the pyramids constituting the textured surface is 1μm to 2μm.

[0148] In some embodiments, the step of providing a substrate includes: providing an initial substrate and performing double-sided polishing on the initial substrate to remove impurities on the surface of the initial substrate and form a substrate with a flat surface, thereby facilitating the subsequent preparation of other film layers, such as the initial first dielectric layer.

[0149] In some cases, the reflectivity of the first and second surfaces of the double-sided polished substrate may be 35% to 40%; and the depth of the original substrate removed by the double-sided polishing process may be about 3 μm to 8 μm.

[0150] In summary, at least in the step of forming the first semiconductor layer 105, the deposition temperature of the (N-1)th deposition stage is designed to be lower than the deposition temperature of the Nth deposition stage. This, on the one hand, prevents the formation of large grains in the first semiconductor film 115 near the substrate 100, prevents the precipitation of grains on the surface of the first semiconductor film 115 near the substrate 100, and prevents damage to the first dielectric layer 101 and the substrate 100, thereby ensuring that the first dielectric layer 101 effectively passivates the substrate 100. Furthermore, it facilitates the formation of larger grains, such as dendrites, in the first semiconductor film 115 away from the substrate 100. These multiple effects ultimately facilitate the formation of a first doped layer 102 with a higher crystallinity than that of the Nth first doped film 112.

[0151] The following is a specific embodiment of a method for manufacturing a back-contact battery provided in one embodiment of the present application, and a comparative example thereof: Example 1 Prepare the back contact cell 1 by the following steps: (1) An N-type single crystal silicon wafer is selected, the resistivity of the N-type single crystal silicon wafer is about 0.5 ohmmm to 10 ohmmm, and the thickness of the N-type single crystal silicon wafer in the first direction X is about 150 μm; the N-type single crystal silicon wafer is double-sided polished, for example, the front and back sides of the N-type single crystal silicon wafer are double-sided polished using a groove-type texturing device to obtain a substrate 100.

[0152] Specifically, the damaged layer on the surface of the N-type single crystal silicon wafer is first removed in a mixed solution including potassium hydroxide and hydrogen peroxide, and then alkaline polishing is performed in a sodium hydroxide solution or a potassium hydroxide solution to form a substrate 100 having a flat tower base morphology on the surface. The size of the tower base is about 15 μm, and the reflectivity of the tower base morphology is about 40%. The depth of the etched N-type single crystal silicon wafer is about 5 μm, which can more thoroughly remove the damage suffered by the N-type single crystal silicon wafer during the cutting process.

[0153] (2) Using the LPCVD process to prepare an aluminum oxide layer or a silicon nitride layer on the second surface as the initial first dielectric layer, wherein the thickness of the aluminum oxide layer or the silicon nitride layer can be 1nm to 2nm; further, using the LPCVD process to form a carbon-doped or nitrogen-doped first semiconductor layer on the aluminum oxide layer or the silicon nitride layer, the first semiconductor layer can be a silicon material with a mixture of internal crystalline and amorphous states. Specifically, using the first deposition process, the first semiconductor layer including two layers of first semiconductor films is deposited at a variable temperature; wherein the bottom first semiconductor film close to the substrate is deposited at 555°C and has a thickness of 20nm; and the outer first semiconductor film away from the substrate is deposited at 605°C and has a thickness of 330nm.

[0154] (3) The first semiconductor layer is subjected to high-temperature boron diffusion using a tubular diffusion device. After the boron diffusion, the intrinsic amorphous silicon is transformed into polycrystalline silicon, and the boron doping concentration in the polycrystalline silicon is 8×10 19 atom / cm 3 The first semiconductor layer is transformed into an initial first doped layer. The high-temperature boron diffusion process uses a temperature of 850°C to 1050°C. Furthermore, the high-temperature boron diffusion forms borosilicate glass (BSG) on the side of the initial first doped layer away from the substrate.

[0155] (4) The BSG on the second region is laser-processed using the first laser to remove the BSG on the second region. Specifically, a green laser is used, and the power of the laser generating the green laser is controlled to be 50W.

[0156] (5) First, a chain pickling process is used to remove the BSG plated on the first surface; then, an alkaline etching process is used to remove the initial first doping layer and the aluminum oxide layer or silicon nitride layer plated on the first surface and located on the second area, and the exposed second area is further polished. The chain pickling process can use a hydrofluoric acid solution with a concentration of 3% to 10%, and the alkaline etching process can use a sodium hydroxide solution or a potassium hydroxide solution. After the polishing process, the surface of the second area 1202 shows a tower base size of 30μm.

[0157] (6) Using the LPCVD process to prepare an aluminum oxide layer or a silicon nitride layer on the second surface as the initial second dielectric layer, wherein the thickness of the aluminum oxide layer or the silicon nitride layer can be 1nm to 2nm; further, using the LPCVD process to form a carbon-doped or nitrogen-doped second semiconductor layer on the aluminum oxide layer or the silicon nitride layer, the second semiconductor layer can be a silicon material with a mixture of internal crystalline and amorphous states. Specifically, using the second deposition process, the second semiconductor layer including two layers of second semiconductor films is deposited at a variable temperature; wherein the bottom second semiconductor film close to the substrate is deposited at 555°C and has a thickness of 20nm; and the outer second semiconductor film away from the substrate is deposited at 605°C and has a thickness of 180nm.

[0158] (7) Use tubular diffusion equipment to perform high-temperature phosphorus diffusion on the second semiconductor layer. After phosphorus diffusion, the intrinsic amorphous silicon is transformed into polycrystalline silicon, and the phosphorus doping concentration in the polycrystalline silicon is 4×10 20 atom / cm 3 The second semiconductor layer is transformed into the initial second doped layer. The high-temperature phosphorus diffusion process uses a temperature of 850°C to 950°C. Furthermore, the high-temperature phosphorus diffusion forms phospho-silicate glass (PSG) on the side of the initial second doped layer away from the substrate.

[0159] (8) Using a second laser to perform laser treatment on the PSG located on the first area to remove the PSG located on the first area. Specifically, a purple laser is used, and the power of the laser generating the purple laser is controlled to be 10W.

[0160] (9) First, a chain pickling process is used to remove the PSG plated on the first surface; then a slot-type texturing device is used to remove the initial second doping layer and the aluminum oxide layer or silicon nitride layer plated on the first surface and located on the second area and the isolation area, and the exposed first surface and isolation area are further texturized, for example, so that the reflectivity of the texture of the first surface and the isolation area is 8%, and the size of the pyramid constituting the texture is 2μm.

[0161] (10) ALD (Atomic Layer Deposition) process is used to deposit an aluminum oxide film, i.e., a first passivation layer, with a thickness of 4 nm on the front and back sides of the semi-finished back-contact battery formed in step (9).

[0162] (11) A silicon nitride film, i.e., a second passivation layer, with a thickness of 80 nm is deposited on the front and back sides of the semi-finished back-contact battery formed in step (10) using an ALD (atomic layer deposition) process.

[0163] (12) Screen printing is performed on the back side of the semi-finished back contact cell formed in step (11) to form an interdigitated emitter to finally form a back contact cell 1.

[0164] Comparative Example 1 Prepare back contact cell 2 by the following steps: Step (1) is the same as in Example 1 and will not be repeated here.

[0165] (2) A tunneling layer and an intrinsic amorphous silicon layer are prepared on the second surface using the LPCVD process. The thickness of the tunneling layer is 1nm~2nm, and the thickness of the intrinsic amorphous silicon layer is 350nm.

[0166] (3) Use tubular diffusion equipment to perform high-temperature boron diffusion on the second surface to achieve doping and crystallization of the intrinsic amorphous silicon layer, and convert the intrinsic amorphous silicon layer into a boron-doped polysilicon layer. The process temperature used for high-temperature boron diffusion is 850℃~1050℃, and the boron doping concentration in the polysilicon layer is 8×10 19 atom / cm 3 .

[0167] Steps (4) and (5) are the same as those in Example 1 and will not be repeated here.

[0168] (6) A tunneling layer and an intrinsic amorphous silicon layer are again prepared on the second surface using the LPCVD process. The thickness of the tunneling layer is 1nm~2nm, and the thickness of the intrinsic amorphous silicon layer is 350nm.

[0169] (7) Use tubular diffusion equipment to perform high-temperature phosphorus diffusion on the second surface to achieve doping and crystallization of the intrinsic amorphous silicon layer, and convert the intrinsic amorphous silicon layer into a phosphorus-doped polysilicon layer. The process temperature used for high-temperature phosphorus diffusion is 850℃~950℃, and the phosphorus doping concentration in the polysilicon layer is 4×10 20 atom / cm 3 .

[0170] Steps (8) to (12) are the same as those in Example 1 and will not be repeated here.

[0171] Table 1 shows the photovoltaic index corresponding to back contact cell 1 and back contact cell 2.

[0172]

[0173] Note: VOC stands for open circuit voltage, Isc stands for short circuit current, FF stands for fill factor, and EFF stands for photoelectric conversion efficiency.

[0174] From the experimental results, compared with the direct formation of the tunneling layer and the intrinsic amorphous silicon layer in Comparative Example 1, Example 1 uses the manufacturing method of the back-contact battery provided by an embodiment of the present application, and adopts a variable temperature deposition process to form the first semiconductor layer and the second semiconductor layer, which can ultimately increase the passivation effect on the first region and the second region, and improve the open circuit voltage of the back-contact battery. The first doped layer and the second doped layer finally formed have reduced parasitic absorption of light, thereby improving the current density of the back-contact battery. The roughness of the outer first doped film and the outer second doped film is relatively high, which is beneficial to the contact between the electrode and the outer first doped film and the outer second doped film, thereby improving the fill factor of the back-contact battery. Many aspects work together to make the back-contact battery 1 prepared in Example 1 have higher conversion efficiency.

[0175] Another embodiment of the present application further provides a photovoltaic module for converting received light energy into electrical energy. The photovoltaic module provided in another embodiment of the present application is described in detail below with reference to the accompanying drawings. It should be noted that portions identical or corresponding to the preceding embodiments are not described in detail here.

[0176] Combined with reference Figure 12 and Figure 13 ,as well as Figures 1 to 3 The photovoltaic module includes: a cell string, which is formed by connecting multiple back-contact cells 40 provided by the aforementioned embodiments, or by connecting multiple back-contact cells 40 formed by the manufacturing method of the back-contact cells provided by the aforementioned embodiments; an encapsulation film 41, which is used to cover the surface of the cell string; and a cover plate 42, which is used to cover the surface of the encapsulation film 41 facing away from the cell string.

[0177] in, Figure 12 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided in another embodiment of the present application; Figure 13 A partial cross-sectional schematic diagram of a photovoltaic module provided in yet another embodiment of the present application.

[0178] In some embodiments, the back-contact cell 40 is electrically connected in a whole cell or multiple slices to form multiple cell strings, and the multiple cell strings are electrically connected in series and / or parallel. The back-contact cell 40 can be a whole cell or a sliced ​​cell. A sliced ​​cell refers to a cell formed by cutting a complete whole cell.

[0179] In some embodiments, in conjunction with reference Figure 12 and Figure 13 , multiple back contact cells 40 can be electrically connected through conductive tapes 43 . Figure 12 and Figure 13Only one positional relationship between the back-contact cells 40 is illustrated, i.e., the electrodes of each back-contact cell 40 are arranged on the same side, so that the conductive ribbons 43 connect the same side of two adjacent back-contact cells 40. In other embodiments, the electrodes of two adjacent back-contact cells may be located on different sides, so that the conductive ribbons connect two adjacent back-contact cells on different sides.

[0180] In some embodiments, the encapsulation film 41 includes a first encapsulation layer and a second encapsulation layer, wherein the first encapsulation layer covers one of the front side and the back side of the back-contact cell 40, and the second encapsulation layer covers the other of the front side and the back side of the back-contact cell 40. Specifically, at least one of the first encapsulation layer and the second encapsulation layer can be an organic encapsulation film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyethylene octene co-elastomer (POE) film, or polyethylene terephthalate (PET) film. Alternatively, at least one of the first encapsulation layer and the second encapsulation layer can also be an EP film, an EPE film, or a PVP film. EP film refers to a coextruded film composed of stacked EVA film and POE film, EPE film refers to a coextruded film formed by stacking EVA film + POE film + EVA film, and PVP film refers to a coextruded film formed by stacking POE film + EVA film + POE film. Coextruded films can be produced by sequentially extruding one or more raw materials onto another pre-existing film during the film processing process, or by bonding different pre-existing films together.

[0181] In some cases, there is a boundary line between the first encapsulation layer and the second encapsulation layer before lamination. After the lamination process, the photovoltaic module is formed and there is no longer the concept of the first encapsulation layer and the second encapsulation layer, that is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0182] In some embodiments, the cover plate 42 may be a light-transmitting cover plate such as a glass cover plate or a plastic cover plate. Specifically, the surface of the cover plate 42 facing the encapsulation film 41 may have a concave-convex surface or a velvet surface including multiple raised structures, thereby increasing the utilization of incident light. The cover plate 42 includes a first cover plate and a second cover plate. The first cover plate faces the first encapsulation layer, and the second cover plate faces the second encapsulation layer.

[0183] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present application. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, the scope of protection of the embodiments of the present application shall be based on the scope defined in the claims.

Claims

1. A back contact battery, characterized in that: include: A substrate having a first surface and a second surface opposite to each other along a first direction, wherein the second surface has first areas and second areas alternately arranged along a second direction; a first dielectric layer and a first doping layer stacked on the first region, wherein the first doping layer contains a P-type doping element; a second dielectric layer and a second doping layer stacked on the second region, wherein the second doping layer contains an N-type doping element; The first doped layer includes N stacked first doped films, and along the direction away from the substrate, the crystallization rate of the (N-1)th first doped film is higher than the crystallization rate of the Nth first doped film, where N is a positive integer greater than or equal to 2.

2. The back contact battery according to claim 1, characterized in that The grain size of the (N-1)th layer of the first doping film is smaller than the grain size of the Nth layer of the first doping film.

3. The back contact battery according to claim 1 or 2, characterized in that N is 2, the crystallization rate of the (N-1)th layer of the first doped film is greater than or equal to 99%, and the crystallization rate of the Nth layer of the first doped film is less than 95%.

4. The back contact battery according to claim 1 or 2, characterized in that N is 2, the grain size of the (N-1)th layer of the first doping film is 100 nm to 180 nm, and the grain size of the Nth layer of the first doping film is 190 nm to 300 nm.

5. The back contact battery according to claim 1, characterized in that Along the first direction, the thickness of the (N-1)th layer of the first doping film is smaller than the thickness of the Nth layer of the first doping film.

6. The back contact cell according to claim 1 or 5, characterized in that N is 2, and along the first direction, the thickness of the (N-1)th layer of the first doped film is 10 nm to 60 nm, and the thickness of the Nth layer of the first doped film is 10 nm to 500 nm.

7. The back contact battery according to claim 1, characterized in that The second doped layer includes M layers of second doped films stacked together. Along the direction away from the substrate, the crystallization rate of the (M-1)th layer of the second doped film is higher than the crystallization rate of the Mth layer of the second doped film, and M is a positive integer greater than or equal to 2.

8. The back contact battery according to claim 7, characterized in that The grain size of the (M-1)th layer of the second doping film is smaller than the grain size of the Mth layer of the second doping film.

9. The back contact battery according to claim 1 or 7, characterized in that Along the first direction, the thickness of the first doping layer is greater than the thickness of the second doping layer.

10. The back contact battery according to claim 1, characterized in that At least one of the first doping layer and the second doping layer is polysilicon doped with carbon or nitrogen; or, the material of the second doping layer includes amorphous silicon.

11. The back contact battery according to claim 1, characterized in that The material of at least one of the first dielectric layer and the second dielectric layer includes aluminum oxide or silicon nitride; or the material of at least one of the first dielectric layer and the second dielectric layer includes at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride; or the material of the second dielectric layer includes at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

12. The back contact battery according to claim 1, characterized in that The doping concentration of the P-type doping element in the first doping layer is 5×10 18 atom / cm 3 ~8×10 20 atom / cm 3 ; and / or, the doping concentration of the N-type doping element in the second doping layer is 5×10 19 atom / cm 3 ~9×10 20 atom / cm 3 .

13. The back contact battery according to claim 1, characterized in that Also includes: a first passivation layer, located on the first surface, and at least on surfaces of the first doped layer and the second doped layer away from the substrate; a second passivation layer, located on a surface of the first passivation layer away from the substrate; Wherein, along the first direction, the thickness of the first passivation layer is 3 nm to 10 nm; and / or, along the first direction, the thickness of the second passivation layer is 70 nm to 90 nm.

14. A method for manufacturing a back contact battery, characterized in that: include: Providing a substrate, the substrate having a first surface and a second surface opposite to each other along a first direction, the second surface having first areas and second areas alternately arranged along a second direction; forming a first dielectric layer and a first doping layer stacked on the first region, wherein the first doping layer contains a P-type doping element; forming a second dielectric layer and a second doping layer stacked on the second region, wherein the second doping layer has an N-type doping element; Among them, the step of forming the first doping layer includes: forming a first semiconductor layer on the second surface using a first deposition process, the first deposition process includes N deposition stages connected in sequence, the deposition temperature of the (N-1)th deposition stage is lower than the deposition temperature of the Nth deposition stage, and N is a positive integer greater than or equal to 2; performing a first doping treatment on the first semiconductor layer, so that the first semiconductor layer is converted into an initial first doping layer doped with a P-type doping element; performing a first graphic treatment on the initial first doping layer, retaining only the initial first doping layer located on the first region as the first doping layer, and the first doping layer includes N layers of first doping films stacked together, and in the direction away from the substrate, the crystallization rate of the (N-1)th layer of the first doping film is higher than the crystallization rate of the Nth layer of the first doping film.

15. The method for manufacturing a back contact battery according to claim 14, characterized in that: The step of forming the second doping layer includes: forming a second semiconductor layer on the second surface using a second deposition process, the second deposition process comprising M temperature control stages connected in sequence, a process temperature of the (M-1)th temperature control stage being lower than a process temperature of the Mth temperature control stage, where M is a positive integer greater than or equal to 2; The second semiconductor layer is subjected to a second doping treatment so as to be converted into an initial second doping layer doped with an N-type doping element; the initial second doping layer is subjected to a second patterning treatment so as to retain only the initial second doping layer located on the second region as the second doping layer, and the second doping layer includes M layers of second doping films stacked together, and in a direction away from the substrate, a crystallization rate of the (M-1)th layer of the second doping film is higher than a crystallization rate of the Mth layer of the second doping film.

16. The method for manufacturing a back contact battery according to claim 15, characterized in that: M is 2, and the second deposition process includes a first temperature control stage and a second temperature control stage connected in sequence. The process temperature of the first temperature control stage is 520℃~570℃, and the process temperature of the second temperature control stage is 580℃~650℃.

17. The method for manufacturing a back contact battery according to claim 15, wherein: Before forming the second semiconductor layer, the semi-finished back-contact battery to be formed into the second semiconductor layer is placed in a reaction chamber; during the process of forming the second semiconductor layer using the second deposition process, a carbon-containing gas or a nitrogen-containing gas is introduced into the reaction chamber, so that the formed second semiconductor layer is doped with carbon elements or nitrogen elements.

18. The method for manufacturing a back contact battery according to claim 15, wherein: In the step of performing the second doping treatment on the second semiconductor layer, a second protective layer is further formed on a side of the initial second doping layer away from the substrate; removing the second protective layer on the first area using a second laser; Using a second etching process to remove the initial second doping layer located on the first region, and the remaining initial second doping layer is the second doping layer; The second laser is a purple laser or a green laser, and the power of the laser generating the second laser is 5W~80W.

19. The method for manufacturing a back contact battery according to claim 14, wherein: N is 2, the first deposition process includes a first deposition stage and a second deposition stage connected in sequence, the deposition temperature of the first deposition stage is 520°C~570°C, and the deposition temperature of the second deposition stage is 580°C~650°C.

20. The method for manufacturing a back contact battery according to claim 14, wherein: Before forming the first semiconductor layer, a semi-finished back-contact battery to be used to form the first semiconductor layer is placed in a reaction chamber; during the process of forming the first semiconductor layer using the first deposition process, a carbon-containing gas or a nitrogen-containing gas is introduced into the reaction chamber, so that the formed first semiconductor layer is doped with carbon elements or nitrogen elements.

21. The method for manufacturing a back contact battery according to claim 14, wherein: In the step of performing the first doping treatment on the first semiconductor layer, a first protective layer is further formed on a side of the initial first doping layer away from the substrate; removing the first protective layer on the second area using a first laser; Using a first etching process to remove the initial first doping layer located on the second region, so that the remaining initial first doping layer is the first doping layer; The first laser is a purple laser or a green laser, and the power of the laser generating the first laser is 5W~80W.

22. A photovoltaic module, characterized in that: include: A battery string formed by connecting a plurality of back-contact batteries according to any one of claims 1 to 13, or by connecting a plurality of back-contact batteries formed by the method for manufacturing a back-contact battery according to any one of claims 14 to 21; A packaging film, used to cover the surface of the battery string; A cover plate is used to cover the surface of the packaging film facing away from the battery string.

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