Predictive storage to load forwarding

Abstract

A method for performing predictive store-to-load forwarding on a processor includes receiving a load instruction; executing a predictive storage-to-load forwarding process, including obtaining a predicted storage queue id from a prediction table based on an address of a load instruction, searching a value from the storage queue based on the storage queue id, and executing a parallel verification process on the predicted storage queue id; determining that the parallel verification process is successful; and in response, reading a value for the load instruction from the store queue.

Description

Background Art

[0001] In modern computing, loading from and storing to memory are performance-critical operations in programs. Many modern computers support store-to-load forwarding (STLF), which allows data to be forwarded from a store instruction to a load instruction within the processing pipeline, rather than writing the data out to memory with a store instruction and reading the same data back with a load instruction.

[0002] To support STLF, the processor may maintain a store queue (SQ) that keeps track of all pending stores. When a subsequent load instruction is executed, the processor may check the store queue to determine whether the data to be loaded is in the processor's internal store queue. In this case, store-to-load forwarding can be performed by retrieving the data from the internal store queue rather than from memory. However, as modern execution windows increase, the size of the store queue also increases. For example, modern processors may have hundreds of pending store instructions in the store queue. Therefore, reading the entire large store queue for STLF may actually hurt performance. Summary of the Invention

[0003] This specification describes methods and systems for providing predictive store-to-load forwarding that can significantly improve the overhead of STLF on large store queues and execution windows. For example, large store queues can block instruction execution. The prediction method disclosed herein can achieve efficient STLF on large store queues, for example, by predicting the position of store instructions in the store queue rather than searching the entire store queue.

[0004] Particular embodiments of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages.

[0005] The described methods and systems improve the performance of central processing units (CPUs) with large store queues (e.g., large numbers of instructions), which typically pose challenges for efficient STLF. For example, the described methods and systems allow for more efficient STLF execution even with very large store queues (e.g., store queues with 100s or 1000s of entries), which traditionally reduce STLF efficiency. In some implementations, these methods and systems can improve CPU performance by approximately 1% to 2%.

[0006] The details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter of this specification will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1Ais a diagram of an example execution window containing instructions.

[0008] Figure 1B It is a diagram of the execution phase of the STLF process of an instruction.

[0009] Figure 2 is a diagram of the execution phase of the predictive STLF process.

[0010] Figure 3 is an example table that can be used in a predictive STLF procedure.

[0011] Figure 4 is a flow chart illustrating a method of a predictive STLF process.

[0012] Figure 5 is an example computing environment in which the predictive STLF process can be performed.

[0013] Like reference numbers and designations throughout the various drawings refer to like elements. DETAILED DESCRIPTION

[0014] FIG1 is a diagram of an example execution window 100 including instructions and the execution phase of the STLF process for the instructions. For example, the execution window 100 includes a store instruction 102 that writes data in register R1 to a location in memory, such as a location given by an address. In the example shown, the store instruction 102 is writing data to the memory location given by the address value in register R4 plus a 4-byte offset (R4+4).

[0015] Execution window 100 also includes a load instruction 104 that reads data from an address into register R2. In practice, data for loads and stores can be read from or written to one or more caches between the processor and main memory (e.g., DRAM devices). For simplicity, the examples in this specification omit the details of the intermediate caches, and therefore, writing to or reading from memory encompasses writing to or reading from one or more intermediate caches.

[0016] In the example shown, the load instruction 104 is reading data from the same address (R4 + 4) as the store instruction 102. The execution window also includes an add instruction 106, which can only be executed after the load instruction 104 has been executed.

[0017] Thus, the CPU can use the STLF procedure to execute add instruction 106 without waiting for store instruction 102 and load instruction 104 to complete. To do this, the CPU can store the data in register R1 in an internal store queue. Then, when load instruction 104 is executed, the CPU can compare the address of load instruction 104 with the addresses in the store queue. If there is a match, the CPU can forward the data from the store queue to register R2 without waiting for store instruction 102 to complete. Add instruction 106 can then be executed using the forwarded data stored in register R2.

[0018] Without STLF, the CPU writes data to memory, for example using a store instruction 102, reads the data from memory after writing the data, for example using a load instruction, and executes the add instruction. Waiting until the data is written to memory before executing the remainder of the instruction can reduce the CPU's performance by approximately 5 to 10%. However, Figure 1A The STLF stage shown in can be implemented to forward data from a store instruction to a load instruction so that the CPU does not have to wait until the data is written to memory.

[0019] Figure 1B 1 is a diagram of the execution stages 110 of the STLF process for instructions 102, 104, 106 included in the execution window 102. In the example shown, the STLF process is executed in five stages, but in other implementations, more or fewer stages may be executed. In the first, address generation (AGEN) stage 112, the CPU reads the load instruction 104 and determines the address (VA) corresponding to the load instruction 104.

[0020] In search phase 114, the CPU searches the store queue. In one example, the CPU may include, for example, a content-addressable memory (CAM) structure that holds in-flight memory instructions and supports simultaneous searches. The CPU searches the store queue to determine whether data exists for the in-flight store instruction. In the example shown, the store queue includes the store instruction corresponding to load instruction 104 because store instruction 102 precedes load instruction 104 in the execution window. This may require multiple (e.g., many) cycles when a large store queue is present.

[0021] In the third stage 116, the CPU reads data from the store queue after finding the location of the appropriate store instruction. For example, the CPU can read data that is being written to memory in response to a store instruction. Because the CPU can read this data from the store queue, the CPU does not have to wait for the data to be written to memory before using the data, such as in a load instruction.

[0022] In the fourth stage 118, the CPU aligns the data and executes the bypass stage to provide the data obtained from the store queue to one or more consumer instructions that are waiting for the data. For example, the CPU can execute the load instruction 104 and the add instruction 106 after reading the corresponding data from the store queue.

[0023] In the fifth stage 120, the CPU writes the data back to the specified memory address, such as a destination register. Writing back the data includes writing the read data to the specified memory address, such as the destination register. In some implementations, before the specified memory address is updated, such as during the bypass stage, the CPU can bypass the read data to a related instruction, such as an add (ADD) instruction.

[0024] As discussed above, for large storage queues, it becomes difficult to efficiently complete the STLF process. For example, it takes longer to complete the search phase 114 because larger storage queues have more indexes to search. Even with an efficient search algorithm, searching a large storage queue of, for example, 100 items may also require longer than a cycle. This results in a longer delay for the end user.

[0025] Figure 2 A diagram of the execution phase 200 of a predictive STLF process is shown. Using predictive STLF can avoid consuming multiple cycles to search a large storage queue. The example process can alternatively provide a predictable and limited number of cycles for determining the storage queue index. The predictive STLF process shown executes two separate processes in parallel within five stages, which are similar to the STLF process of Figure 1. However, the predictive STLF process can also achieve efficient results even when there is a storage queue with more than 100 entries. In some implementations, more or fewer stages can be performed.

[0026] In the first stage 202, the CPU reads a load instruction and determines the virtual address corresponding to the load instruction. For example, the CPU may read the load instruction because the load instruction exists in the execution window. The CPU executes the remainder of the STLF process phase instead of executing the load instruction, which would require waiting for a store instruction to write data to the memory address before reading the memory address.

[0027] In the second stage 204, the CPU performs a predictive process to generate a predicted store queue index containing a store instruction at a given address. This index can represent the location of the store instruction within the store queue. For example, the CPU can use a prediction table containing addresses and store queue indices to point the CPU to the location of the appropriate store instruction in the store queue. An exemplary prediction table is discussed further below. Because the prediction table is much smaller than the store queue, store queue index prediction can be easily implemented within a single cycle.

[0028] In the third stage 206, after generating the predicted location of the store instruction, the CPU reads data from the store queue. For example, the CPU can read data that is being written to memory in response to the store instruction. Because the CPU can read this data from the store queue, the CPU does not have to wait for the data to be written to memory before using the data, such as in a load instruction.

[0029] In the fourth stage 208, the CPU aligns the data and bypasses the data, for example, to the user and / or necessary instructions. For example, the CPU may execute the load instruction 104 and the add instruction 106 after reading the corresponding data from the store queue. In the fifth stage 120, the CPU writes the data back to the specified memory address, for example, the destination register.

[0030] The predictive STLF process includes a parallel verification process 220 that runs concurrently with the predictive STLF process. The parallel verification process 220 verifies whether the predictive STLF process correctly predicted the index of the store instruction in the store queue, for example, during the second stage 204. In the first stage 222, the CPU reads the load instruction and determines the virtual address corresponding to the load instruction. For example, the CPU may read the load instruction because the load instruction is present in the execution window.

[0031] In the second stage 224, the CPU searches the store queue to determine whether a store instruction exists for the given virtual address. In the example shown, the store queue includes a store instruction corresponding to the load instruction because the store instruction exists in the execution window before the load instruction. During the parallel verification process 220, because the predictive STLF process is executed simultaneously, the search may require two cycles. This reduces the latency that affects the end user, such as during the STLF process of Figure 1.

[0032] In the third stage 226, the CPU compares the result of the search with the predicted storage queue index. If the index of the search result is identical to the predicted storage queue index, the parallel verification process 220 is successful and determines that the predictive STLF process is successful. If the index of the search result is different from the predicted storage queue index, the parallel verification process determines that the predictive STLF process fails. When the predictive STLF process fails, the CPU updates the predicted storage queue index so that it is identical to the index of the search result. The CPU can also update other parameters of the predictive STLF process, such as parameters in the prediction table. Then, when the parallel verification process 220 determines that the predictive STLF process fails, the CPU executes the fourth stage 228.

[0033] In the fourth stage 228, the CPU replays the load function based on the search results determined in the third stage 226. For example, if only a few instructions were executed based on the incorrect predictive result, those instructions can be executed again using the correct data determined by the parallel verification process 220. Other instructions not related to the incorrect predictive result can continue to execute uninhibited. In some implementations, if many instructions were executed based on the incorrect predictive result, the CPU can perform a lightweight replay in which instructions executed after the incorrect predictive result can be correctly executed again. This can be helpful, for example, in situations where the incorrect predictive result has propagated to a large number of other instructions.

[0034] Figure 3 An exemplary table 300 is shown that can be used for a predictive STLF process. For example, the table 300 can be used as a Figure 2 300. The size of table 300 can be determined to hold a desired number of indexes. For example, in the embodiment shown, table 300 can hold 16 storage queue indexes. Saving 16 storage queues at a time can allow the predictive STLF process to efficiently forward data given a large storage queue (e.g., having 100 entries). The size of table 300 can be increased or decreased to allow the predictive STLF process to efficiently forward data given storage queues of different sizes. For example, a storage queue with more than 200 entries can use a larger table. For each index, table 300 can hold a store PC value 302, a load PC value 304, a storage queue index 306, and an age value 308.

[0035] When the CPU begins processing instructions from the execution window, it will encounter a store instruction, as described above. When the CPU encounters a store instruction, it will populate table 300 based on the store instruction. Similarly, when the CPU encounters a load instruction, it will use table 300 to perform the STLF, as described above, and will populate table 300 based on the load instruction. For example, the CPU may populate the table with store PC value 302, load PC value 304, store queue index 306, and age value 308. Age value 308 indicates the order in which store instruction values ​​are stored in table 300. When a new predicted value needs to be inserted into the table, the age value can be used to determine which entry to replace. The CPU can then begin executing the store instruction.

[0036] When the CPU encounters a store instruction, it searches table 300 for a corresponding store PC value 302. For example, store PC value 302 may represent a virtual address received from a store instruction. If table 300 includes a corresponding store PC value, the CPU updates store queue index 306 to correspond to the correct store PC value. For example, the CPU updates store queue index 306 to include a value representing the location of the store instruction within the store queue. The CPU also updates age value 308 to indicate that the value is newly stored. If table 300 does not include store PC value 302, the CPU updates the table to include store PC value 302. The CPU then updates store queue index 306 to correspond to the correct store PC value. The CPU also updates age value 308 to indicate that the value is newly stored.

[0037] When the CPU encounters a load instruction, it searches table 300 for a corresponding load PC value 304. For example, load PC value 304 may represent the virtual address received from the load instruction. If table 300 includes a corresponding load PC value, the CPU uses the corresponding store queue index 306 to predict where in the store queue the load PC value should be forwarded. This information may be carried to the load-store unit (LSU), where it is used to execute the load instruction. The CPU also updates age value 308 to indicate that the values ​​are newly stored. If table 300 does not include a corresponding load PC value, the CPU determines the store queue index, for example, via a parallel verification process. The CPU updates table 300 using the store queue index 306. The CPU also updates age value 308 to indicate that the values ​​are newly stored. If the parallel verification process does not identify a store instruction from which the load instruction should be forwarded, the load instruction may complete execution using data read from the cache.

[0038] Figure 4 is a flow chart illustrating an exemplary method of a predictive STLF process 400. The exemplary process may be executed by one or more processors. The exemplary process will be described as being executed by, for example, a processor configured according to the present specification. Figure 5 The processor 502 is further described below.

[0039] The processor dispatches an instruction (402), for example, from an execution window. For example, the processor may read an instruction from the execution window and dispatch the instruction based on the content of the instruction. If the instruction is a load instruction or a store instruction, the processor may dispatch the instruction according to method 400.

[0040] The processor determines whether the instruction matches a value stored in the Store Queue Prediction Table (SPT) (404). For example, Figure 3 Prediction table 300 includes a store PC value 302, a load PC value 304, a store queue index 306, and an age value 308. An instruction matches a value stored in the prediction table if the contents of the instruction match the store PC value or the load PC value. The processor can also determine when the contents of an instruction do not match a value stored in the prediction table.

[0041] If the instruction does not match the value stored in the prediction table, the processor determines whether the instruction is a load (406). If the instruction is a load, the processor continues to update the prediction table and re-execute the instruction (418), as will be discussed further below.

[0042] If the instruction matches a value stored in the prediction table, the processor may determine whether the instruction is a load instruction or whether the instruction is a store instruction (408).

[0043] If the processor determines that the instruction is a store instruction, the processor may update the store queue index in the prediction table (410). For example, the processor may update the store queue index to include a value indicating the position of the store instruction within the store queue. The processor may also update the age values ​​in the prediction table to indicate that these values ​​are newly stored.

[0044] The processor then executes the store instruction (412). For example, the processor may forward the store instruction to a load store unit (LSU) to execute the store instruction. The contents of the store instruction are stored at a virtual address in memory.

[0045] If the processor determines that the instruction is a load instruction, the processor may perform a predictive STLF process (414). For example, the processor may predict the index of a store instruction containing the virtual address given in the load instruction. For example, the processor may use a prediction table containing addresses and store queue indices to point the processor to the location of the appropriate store instruction in the store queue. After finding the location of the appropriate store instruction, the processor may read data from the store queue. For example, the processor may read data that is being written to memory by a store instruction. The processor may align the data and bypass the data to, for example, a user and / or necessary instructions.

[0046] The processor may also perform a parallel verification process (416) running concurrently with the predictive STLF process. The parallel verification process verifies whether the predictive STLF process correctly predicted the index of the store instruction in the store queue. The processor searches the store queue to determine whether a store instruction exists for the virtual address given by the load instruction. The processor compares the search result with the predicted store queue index. If the index of the search result is the same as the predicted store queue index, the parallel verification process succeeds and determines that the predictive STLF process succeeds. If the index of the search result is different from the predicted store queue index, the parallel verification process determines that the predictive STLF process failed.

[0047] If the prediction is incorrect, for example, the predictive STLF process fails, the processor updates the prediction table and re-executes the instruction (418). For example, the processor replays the load function based on the search results determined by the parallel verification process. For example, if only a few instructions were executed based on the incorrect predictive result, those instructions can be executed again using the correct data determined by the parallel verification process. Other instructions that are not related to the incorrect predictive result can continue to execute uninhibited. In some implementations, if many instructions were executed based on the incorrect predictive result, the CPU can refresh all instructions executed after the incorrect predictive result and can execute all instructions again. For example, this can be helpful in the case where the incorrect predictive result has propagated to a large number of other instructions. Once the instruction is re-executed using the correct data, the processor can move to the next instruction in the execution window.

[0048] If the prediction is correct, e.g., the predictive STLF process is successful, the processor updates the prediction table and executes the load instruction (420). For example, the load instruction and store queue index may be forwarded to a load store unit (LSU), where the load instruction and store queue index are used to execute the load instruction. The processor may also update the age values ​​in the prediction table to indicate that these values ​​are newly stored.

[0049] Figure 5 5 is an example computing environment 500 that can perform a predictive STLF process. The environment includes a processor 502 and a memory 504, such as a cache, random access memory (RAM), read-only memory (ROM), etc. The processor 502 can perform the predictive STLF process, as described above. The load store unit (LSU) 506 includes a predictive STLF module 508, which includes a prediction table 510 and a store queue 512. The prediction table 510 can be similar to, for example, Figure 3The prediction table 300 is shown in FIG. Store queue 512 may include a content-addressable memory (CAM) structure that holds in-flight memory instructions and supports simultaneous searches. LSU 506 communicates with main execution logic 514 to receive and send data. For example, communications 516 between the LSU and main execution logic may include store instructions, load instructions, stored values, etc. Processor 502 communicates with memory 504 to receive and send data. For example, communications 518 between the processor and memory may include memory addresses, stored values, etc.

[0050] Embodiments of the subject matter and functional operations described in this specification can be implemented in digital electronic circuitry, in computer hardware including the structures disclosed in this specification and their structural equivalents, or in a combination of one or more of these. The processes and logic flows can also be performed by special-purpose logic circuitry, such as an FPGA or ASIC, or by a combination of special-purpose logic circuitry and one or more programmed computers.

[0051] In addition to the embodiments described above, the following embodiments are also innovative:

[0052] Embodiment 1 is a method for performing speculative store-to-load forwarding on a processor, the method comprising:

[0053] Receive loading instructions;

[0054] Performs the speculative store-to-load forwarding process, including:

[0055] Obtaining a predicted store queue id from a prediction table based on the address of the load instruction,

[0056] looking up a value from a storage queue based on the storage queue id while performing a parallel validation process on the predicted storage queue id;

[0057] determining that the parallel verification process was successful; and

[0058] In response, the value for the load instruction is read from the store queue.

[0059] Embodiment 2 is the method of claim 1 , further comprising receiving a store instruction, and populating the prediction table based on the store instruction.

[0060] Embodiment 3 is the method of any one of embodiments 1 to 2, further comprising reloading a plurality of load instructions when the verification process fails.

[0061] Embodiment 4 is the method of any one of embodiments 1 to 3, wherein the parallel verification process includes searching the store queue for the address of the load instruction.

[0062] Embodiment 5 is the method of any one of embodiments 1 to 4, wherein the parallel validation process includes updating the prediction table upon successful prediction.

[0063] Embodiment 6 is the method of embodiment 5, wherein updating the prediction table comprises updating a value associated with an age of the load instruction.

[0064] Embodiment 7 is the method of any one of embodiments 1 to 6, wherein the parallel validation process includes updating the prediction table upon an unsuccessful prediction.

[0065] Embodiment 8 is the method of embodiment 7, wherein updating the prediction table comprises updating a value associated with the storage queue id.

[0066] Embodiment 9 is the method of any one of embodiments 1 to 8, further comprising receiving a storage instruction.

[0067] Embodiment 10 is the method of embodiment 9, further comprising updating the predicted store queue id based on the received store instruction.

[0068] Embodiment 11 is the method of embodiment 9, further comprising executing the store instruction after updating the predicted store queue id.

[0069] Embodiment 12 is a system for performing speculative store-to-load forwarding, the system comprising:

[0070] a memory configured to store instructions; and

[0071] A processor configured to execute the instructions to perform operations, the operations comprising:

[0072] Receive loading instructions;

[0073] Performs the speculative store-to-load forwarding process, including:

[0074] Obtaining a predicted store queue id from a prediction table based on the address of the load instruction,

[0075] looking up a value from a storage queue based on the storage queue id while performing a parallel validation process on the predicted storage queue id;

[0076] determining that the parallel verification process was successful; and

[0077] In response, the value for the load instruction is read from the store queue.

[0078] Embodiment 13 is the system of embodiment 12, further comprising receiving a store instruction, and populating the prediction table based on the store instruction.

[0079] Embodiment 14 is the system of any one of embodiments 12 to 13, further comprising reloading a plurality of load instructions when the verification process fails.

[0080] Embodiment 15 is the system of any one of embodiments 12 to 14, wherein the parallel verification process includes searching the store queue for the address of the load instruction.

[0081] Embodiment 16 is the system of any one of embodiments 12 to 15, wherein the parallel validation process includes updating the prediction table upon a successful prediction.

[0082] Embodiment 17 is the system of embodiment 16, wherein updating the prediction table comprises updating a value associated with an age of the load instruction.

[0083] Embodiment 18 is the system of any one of embodiments 12 to 17, wherein the parallel validation process includes updating the prediction table upon an unsuccessful prediction.

[0084] Embodiment 19 is the system of embodiment 18, wherein updating the prediction table comprises updating a value associated with the storage queue id.

[0085] Embodiment 20 is the system of any one of embodiments 12 to 19, further comprising receiving a storage instruction.

[0086] Embodiment 21 is the system of embodiment 20, further comprising updating the predicted store queue id based on the received store instruction.

[0087] Embodiment 22 is the system of embodiment 20, further comprising executing the store instruction after updating the predicted store queue id.

[0088] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but should be interpreted as descriptions of features that may be specific to a particular embodiment of a particular invention. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable subcombination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may involve a subcombination or a variant of the subcombination.

[0089] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all illustrated operations be performed to achieve the desired results. In certain situations, multitasking and parallel processing can be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0090] Specific embodiments of the present subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying figures do not necessarily require the particular order shown or sequential order to achieve the desired results. In certain circumstances, multitasking and parallel processing may be advantageous.

Claims

1. A method for performing speculative store-to-load forwarding on a processor, the method comprising: Receive loading instructions; Performs the speculative store-to-load forwarding process, including: Obtaining a predicted store queue id from a prediction table based on the address of the load instruction, looking up a value from a storage queue based on the storage queue id while performing a parallel validation process on the predicted storage queue id; determining that the parallel verification process was successful; as well as In response, the value for the load instruction is read from the store queue. 2 . The method of claim 1 , further comprising receiving a store instruction, and populating the prediction table based on the store instruction. 3 . The method of claim 1 , further comprising reloading a plurality of load instructions when the verification process fails.

4. The method according to any one of claims 1 to 3, wherein The parallel verification process includes searching the store queue for the address of the load instruction.

5. The method according to any one of claims 1 to 4, wherein The parallel validation process includes updating the prediction table upon successful prediction.

6. The method according to claim 5, wherein: Updating the prediction table includes updating a value associated with an age of the load instruction.

7. The method according to any one of claims 1 to 6, wherein The parallel validation process includes updating the prediction table in case of unsuccessful predictions.

8. The method of claim 7, wherein: Updating the prediction table includes updating a value associated with the storage queue id.

9. The method of any one of claims 1 to 8, further comprising receiving a storage instruction.

10. The method of claim 9, further comprising updating the predicted store queue id based on the received store instruction.

11. The method of claim 9, further comprising executing the store instruction after updating the predicted store queue id.

12. A system for performing speculative store-to-load forwarding, the system comprising: a memory configured to store instructions; as well as A processor configured to execute the instructions to perform operations, the operations comprising: Receive loading instructions; Performs the speculative store-to-load forwarding process, including: Obtaining a predicted store queue id from a prediction table based on the address of the load instruction, looking up a value from a storage queue based on the storage queue id while performing a parallel validation process on the predicted storage queue id; determining that the parallel verification process was successful; and In response, the value for the load instruction is read from the store queue.

13. The system of claim 12, further comprising receiving a store instruction, and populating the prediction table based on the store instruction.

14. The system of any one of claims 12 to 13, further comprising reloading a plurality of load instructions when the verification process fails.

15. The system of any one of claims 12 to 14, wherein: The parallel verification process includes searching the store queue for the address of the load instruction.

16. The system of any one of claims 12 to 15, wherein: The parallel validation process includes updating the prediction table upon successful prediction.

17. The system of claim 16, wherein: Updating the prediction table includes updating a value associated with an age of the load instruction.

18. The system of any one of claims 12 to 17, wherein: The parallel validation process includes updating the prediction table in case of unsuccessful predictions.

19. The system of claim 18, wherein: Updating the prediction table includes updating a value associated with the storage queue id.

20. The system of any one of claims 12 to 19, further comprising receiving a storage instruction.

21. The system of claim 20, further comprising updating the predicted store queue id based on the received store instruction.

22. The system of claim 20, further comprising executing the store instruction after updating the predicted store queue id.

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