Backboard system and storage system

Abstract

The invention discloses a backboard system and a storage system, and relates to the technical field of backboards, the backboard system is provided with a plurality of storage device slots, each storage device slot is provided with a signal multiplexing circuit and a protocol switching processor corresponding to the storage device slot, and the storage device slots are used for plugging a first solid state disk or a second solid state disk. The first solid state disk is a solid state disk based on a first communication protocol, and the second solid state disk is a solid state disk which is directly connected with a host through an interconnection high-speed bus and is based on a second communication protocol; the signal multiplexing circuit is used for sending transmission data of a target communication protocol to the host, and the target communication protocol is a first communication protocol or a second communication protocol; and the protocol switching processor is used for switching the communication protocol of the signal multiplexing circuit according to the pin signal of the protocol identification pin of the corresponding storage equipment slot. The overall efficiency of the storage system can be improved.

Description

Technical Field

[0001] The present application relates to the field of backplane technology, and in particular to a backplane system and a storage system. Background Art

[0002] NVMe (Non-Volatile Memory Express) solid-state drives (SSDs) are interface specifications and hardware products designed specifically for high-speed non-volatile storage. Their core advantage lies in their use of a PCIe direct-connect architecture to establish a data path directly with the CPU's PCIe channel.

[0003] The hardware logic and drivers of Redundant Array of Independent Disks (RAID) controllers in related technologies only support SAS / SATA bus transmission and are unable to directly configure RAID groups, schedule reads and writes, or perform fault recovery on NVMe drives. Using software RAID solutions as an alternative consumes significant CPU resources, negating the performance advantages of NVMe SSDs and reducing overall storage system efficiency. Summary of the Invention

[0004] The present application provides a backplane system and a storage system to at least solve the problem of reduced overall efficiency of the storage system in the related art.

[0005] In a first aspect, the present application provides a backplane system, wherein the backplane system is provided with a plurality of storage device slots, each storage device slot is provided with its corresponding signal multiplexing circuit and protocol switching processor, the protocol switching processor is respectively connected to the protocol identification pin and the signal multiplexing circuit of its corresponding storage device slot, and the signal multiplexing circuit of each storage device slot is respectively connected to the host, wherein:

[0006] The storage device slot is used to insert a first solid-state drive or a second solid-state drive, the first solid-state drive is a solid-state drive based on a first communication protocol, and the second solid-state drive is a solid-state drive directly connected to the host through an interconnected high-speed bus and based on a second communication protocol;

[0007] The signal multiplexing circuit is used to send transmission data of a target communication protocol to the host, where the target communication protocol is the first communication protocol or the second communication protocol;

[0008] The protocol switching processor is used to switch the communication protocol of the signal multiplexing circuit according to the pin signal of the protocol identification pin corresponding to the storage device slot.

[0009] In a second aspect, the present application further provides a storage system, comprising any of the above-mentioned backplane systems, solid-state hard disks corresponding to the storage device slots, and a baseboard management controller, wherein:

[0010] The baseboard management controller is used to send a notification instruction to each solid-state hard disk through a third communication protocol, bypassing the storage logic controller, and the notification instruction is used to indicate that a data block in the solid-state hard disk is erased or reused.

[0011] Through the backplane system and storage system provided by the present application, a plurality of storage device slots and signal multiplexing circuits are provided on the backplane system, and each storage device slot is provided with its corresponding protocol switching processor. The storage device slot can be plugged into a first solid-state hard drive or a second solid-state hard drive, the first solid-state hard drive can be an NVMe hard drive, and the second solid-state hard drive can be a storage device based on SAS / SATA bus transmission. The signal multiplexing circuit can send transmission data of the target communication protocol to the host, and the protocol switching processor can switch the communication protocol of the signal multiplexing circuit according to the pin signal of the corresponding storage device slot. The protocol switching processor can simultaneously support the first solid-state hard drive and the second solid-state hard drive, retaining the performance advantages of the NVMe hard drive, and performing RAID group configuration, read and write scheduling and fault recovery, which can improve the overall efficiency of the storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A schematic diagram of an application scenario provided in an embodiment of the present application;

[0014] Figure 2 A schematic structural diagram of a backplane system provided in an embodiment of the present application;

[0015] Figure 3 A schematic diagram of the structure of a storage device slot provided in an embodiment of the present application;

[0016] Figure 4 A schematic structural diagram of another backplane system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0018] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0019] NVMe protocol: NVMe is a high-performance host controller interface specification designed specifically for solid-state drives. It communicates directly with the CPU over the PCIe bus, bypassing traditional SATA / SAS controllers. The NVMe protocol significantly increases storage device throughput and IOPS (input / output operations per second), supports multi-queue parallel processing, and reduces latency.

[0020] Solid-state drive (SSD): A hard drive that uses flash memory chips as storage media. Compared with traditional mechanical hard drives, it has faster read and write speeds and lower latency. It is the core storage medium of modern high-performance storage systems.

[0021] PCIe bus: PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard that supports high-bandwidth data transfer. NVMe SSDs are typically connected via a PCIe interface. The latest PCIe Gen5 standard offers a single-channel bandwidth of up to 32GT / s.

[0022] RAID (Redundant Array of Independent Disks): RAID is a technology that combines multiple disks into a single logical unit to improve performance, redundancy, or both. Common RAID levels include: RAID 0: Striping, which improves performance but provides no redundancy. RAID 1: Mirroring, which provides data redundancy. RAID 5 / 6: Striping plus distributed parity, which balances performance and redundancy.

[0023] Traditional RAID controller: Traditional hardware RAID cards usually rely on SATA / SAS interfaces to manage hard drives, but cannot directly support the PCIe direct connection architecture of NVMe hard drives.

[0024] Figure 1 This is a schematic diagram of the application scenario provided by the embodiment of this application. Figure 1 The storage system 100 is a high-performance storage solution with software-defined storage as its core architecture, including a host 101, a hard disk controller 102 and multiple solid-state drives 103. The components work together to achieve efficient and reliable data storage and management.

[0025] Host 101 serves as the computing and control core of the entire system. In addition to performing routine business computing tasks, it also integrates a storage logic module. This storage logic module utilizes a software RAID (Redundant Array of Independent Disks) architecture, possesses extensive storage management capabilities, and performs core logic (e.g., data striping, checksum calculations, and fault recovery scheduling).

[0026] The hard disk controller 102 serves as the protocol conversion and data transmission hub between the host 101 and the solid-state drive 103. The hard disk controller 102 is connected to the host 101 through a PCIe channel and is responsible for managing NVMe protocol-related operations, such as I / O submission queue processing and data transmission scheduling.

[0027] Multiple solid-state hard disks 103 serve as solid-state hard disks corresponding to the storage logic module and are connected to the hard disk controller 102. Among them, the solid-state hard disk 103 can be an NVMe hard disk, and the hard disk controller 102 can be an NVMe controller.

[0028] In related technologies, the hardware logic and drivers of RAID controllers only support SAS / SATA bus transmission and are unable to directly configure RAID groups, schedule reads and writes, or perform fault recovery on NVMe drives. Software RAID modules can be used as an alternative, but this consumes significant CPU resources, negating the performance advantages of NVMe SSDs and reducing overall storage system efficiency.

[0029] In an embodiment of the present application, a plurality of storage device slots and a signal multiplexing circuit are provided on the backplane system, and each storage device slot is provided with its corresponding protocol switching processor. The backplane system is provided with a plurality of storage device slots, and each storage device slot is provided with its corresponding signal multiplexing circuit and protocol switching processor. The protocol switching processor is respectively connected to the protocol identification pin and the signal multiplexing circuit of its corresponding storage device slot, and the signal multiplexing circuit of each storage device slot is respectively connected to the host. The storage device slot can be plugged into a first solid-state hard drive or a second solid-state hard drive. The first solid-state hard drive can be an NVMe hard drive, and the second solid-state hard drive can be a storage device based on SAS / SATA bus transmission. The signal multiplexing circuit can send transmission data of the target communication protocol to the host, and the protocol switching processor can switch the communication protocol of the signal multiplexing circuit according to the pin signal of its corresponding storage device slot.

[0030] The processor can be switched through the protocol to support the first and second solid-state drives at the same time, retaining the performance advantages of NVMe hard drives, and performing RAID group configuration, read and write scheduling, and fault recovery, which can improve the overall efficiency of the storage system.

[0031] Figure 2 This is a schematic diagram of the structure of a backplane system provided in an embodiment of the present application. Figure 2 The backplane system includes multiple storage device slots, each of which is equipped with a corresponding signal multiplexing circuit and protocol switching processor. The protocol switching processor is respectively connected to the protocol identification pin of the corresponding storage device slot and the signal multiplexing circuit, and the signal multiplexing circuit of each storage device slot is respectively connected to the host.

[0032] The storage device slot can be used to plug in the first solid-state hard drive or the second solid-state hard drive.

[0033] The first solid-state drive may be a solid-state drive based on a first communication protocol, wherein the first communication protocol is a SAS / SATA protocol.

[0034] SAS stands for Serial Attached SCSI (SAS). The SAS protocol is a high-performance serial interface protocol used to connect storage devices (such as hard drives and solid-state drives). The SAS protocol includes three sub-protocols: the Serial SCSI Protocol (SSP), the SCSI Management Protocol (SMP), and the SATA Tunneling Protocol (STP). SSP transmits SCSI commands, SMP is used for device maintenance and management, and STP facilitates data transmission between SAS and SATA devices.

[0035] SATA stands for Serial Advanced Technology Attachment, which is a hard disk interface standard based on serial technology.

[0036] The SAS interface is backward compatible with SATA hard drives at the physical and protocol layers (that is, SATA hard drives can be directly connected to the SAS environment), but the SATA interface is not compatible with SAS hard drives.

[0037] The second solid-state drive may be a solid-state drive that is directly connected to the host via an interconnected high-speed bus and is based on a second communication protocol.

[0038] The interconnected high-speed bus is the Peripheral Component Interconnect Express (PCIe) bus. The PCIe bus is a high-speed serial computer expansion bus standard used to connect the CPU and high-performance peripherals (such as graphics cards, solid-state drives, network cards, etc.).

[0039] The second communication protocol is NVMe. NVMe (Non-Volatile Memory Express) is a high-performance storage protocol designed specifically for solid-state drives. Based on NVMe, a host computer can be directly connected to the SSD via the PCIe bus.

[0040] A backplane is a physical circuit board that can be used to connect multiple electronic components (such as storage device slots and processors). Its main function is to provide signal transmission paths, power distribution, and mechanical support, replacing traditional cable connections.

[0041] In practical applications, the 12-layer backplane connects each storage device slot via differential signaling, ensuring stable signal transmission and device integration, making it the core hardware support for multi-slot storage systems. Each backplane layer supports eight storage device slots, each equipped with independent power control circuitry, built-in temperature sensors, and airflow deflectors.

[0042] For any storage device slot, the storage device slot includes a plurality of connection pins, wherein the plurality of connection pins include a plurality of first pins for connecting to a first solid-state drive, a plurality of second pins for connecting to a second solid-state drive, and a common pin. The common pin may include a power pin and a ground pin.

[0043] Connection pins are metal contacts on the storage device slot that are used to achieve "mechanical connection" and "signal / power transmission".

[0044] The first pin can transmit SAS / SATA protocol signals (such as SCSI commands and data) for connecting to the first solid-state drive; the second pin can transmit PCIe bus signals and NVMe protocol signals for connecting to the second solid-state drive; the common pin can be used to transmit power (such as VCC) and ground (GND) signals, which can be shared by both solid-state drives.

[0045] Each storage device slot is provided with its corresponding protocol switching processor, which is connected to each pin of its corresponding storage device slot, and the protocol switching processors of multiple storage device slots are respectively connected to the signal multiplexing circuit.

[0046] The protocol switching processor can control the signal multiplexing circuit to switch the communication protocol to ensure that the signal transmitted between the slot and the host complies with the current hard disk protocol standard (for example, when an NVMe hard disk is identified, it switches to the PCIe / NVMe protocol).

[0047] The storage device slot also includes a protocol identification pin, and the protocol switching processor can switch the communication protocol of the signal multiplexing circuit according to the pin signal of the protocol identification pin.

[0048] When SSDs with different protocols (SAS / SATA vs. NVMe) are connected to the storage device slot, different pin signals will be output to the pin (for example, SAS / SATA hard disk outputs low level, NVMe hard disk outputs high level).

[0049] Based on the pin signal of the protocol identification pin, determine whether the connected solid-state drive (SAS / SATA) or the second solid-state drive (NVMe) is connected.

[0050] The signal multiplexing circuit can switch the circuit's signal path and protocol type (for example, switching between SAS / SATA protocol and NVMe protocol) under the control of the protocol switching processor, and can implement multiple storage device slots and multiplex the host's protocol interface resources.

[0051] In an embodiment of the present application, a plurality of storage device slots and a signal multiplexing circuit are provided on the backplane system, and each storage device slot is provided with its corresponding protocol switching processor. The storage device slot can be plugged into a first solid-state drive or a second solid-state drive, the first solid-state drive can be an NVMe hard drive, and the second solid-state drive can be a storage device based on SAS / SATA bus transmission. The signal multiplexing circuit can send transmission data of the target communication protocol to the host, and the protocol switching processor can switch the communication protocol of the signal multiplexing circuit according to the pin signal of its corresponding storage device slot. The protocol switching processor can simultaneously support the first solid-state drive and the second solid-state drive, retaining the performance advantages of the NVMe hard drive, and performing RAID group configuration, read and write scheduling, and fault recovery, thereby improving the overall efficiency of the storage system.

[0052] Specifically, the protocol switching processor can obtain the pin signal of the protocol identification pin corresponding to the storage device slot. If the pin signal is the first preset pin signal, it is determined that the target solid-state hard disk corresponding to the storage device slot is the first solid-state hard disk; if the pin signal is the second preset pin signal, it is determined that the target solid-state hard disk corresponding to the storage device slot is the second solid-state hard disk.

[0053] A high level is a preset voltage state in a digital circuit, representing a specific logic signal (usually "1"). A low level is the opposite voltage state in a digital circuit, representing another logic signal (usually "0").

[0054] In some possible embodiments, the first preset pin signal can be a high level, and the second preset pin signal can be a low level. The high level serves as an identification signal for the first SSD (SAS / SATA protocol). When the protocol identification pin detects this voltage, it is determined that the first SSD is connected. The low level can serve as an identification signal for the second SSD (NVMe protocol). When the protocol identification pin detects this voltage, it is determined that the second SSD is connected.

[0055] Among them, the first preset level signal and the second preset level signal can be determined based on the specific connection method between the protocol identification pin and each of the multiple connection pins. This application does not make any specific restrictions and only gives an example.

[0056] The protocol switching processor is further configured to switch the communication protocol of the signal multiplexing circuit to a target communication protocol corresponding to the target solid-state drive, where the target solid-state drive is the first solid-state drive or the second solid-state drive.

[0057] If the target SSD is the first SSD (SAS / SATA protocol), the target communication protocol is SAS protocol or SATA protocol; if the target SSD is the second SSD (NVMe protocol), the target communication protocol is NVMe protocol (based on PCIe bus).

[0058] In this application, the hard disk type is distinguished by the pin signal (high / low) of the protocol identification pin, which can sink the protocol identification logic from the software layer to the hardware layer, avoiding the delay of firmware detection or operating system driver in traditional solutions.

[0059] One end of the signal multiplexing circuit can communicate with the host through the PCIe interface, and the other end of the signal multiplexing circuit is connected to the protocol switching processor. The protocol switching processor can handle signal switching through logic gate components.

[0060] For example, when the logic gate component detects that the pin signal is the first preset pin signal, indicating that the first solid-state hard drive is inserted into the slot, the logic gate component will connect the first circuit. When the pin signal is detected as the second preset pin signal, indicating that the second solid-state hard drive is inserted into the slot, the logic gate component will connect the second circuit.

[0061] The logic gate component may be an AND gate or a NAND gate.

[0062] The following description will be made by taking the AND gate as an example of a logic gate component.

[0063] A first AND gate is installed between the first circuit and the protocol identification pin. One input of the first AND gate is connected to the pin signal, and the other input is fixed to a high level "1" (for example, connected to the power supply). When the pin signal is "1", the output is "1", connecting the first circuit.

[0064] A NOT gate and a second AND gate are installed between the second circuit and the protocol identification pin. The NOT gate is connected to the protocol identification pin, the NOT gate is connected to the second AND gate, and the second AND gate is connected to the second circuit. The NOT gate inverts the pin signal and then connects to the second AND gate. When the pin signal is "0," it inverts to "1," causing the AND gate to output "1," thus connecting the second circuit.

[0065] In the above design, when the first circuit is connected, the second circuit is disconnected; when the second circuit is connected, the first circuit is disconnected, which can ensure that only one circuit is enabled to avoid conflicts.

[0066] Specifically, one end of the signal multiplexing circuit establishes a physical connection with the host through the PCIe 4.0 / 5.0 interface, supports multiple link width configurations such as x4 / x8 / x16, and can dynamically adjust the number of data transmission channels according to system bandwidth requirements.

[0067] For example, when the x16 link is enabled in high-performance mode, the transmission rate can reach 32GB / s (PCIe 4.0) or 64GB / s (PCIe 5.0), ensuring high-speed data interaction between the host and the back-end storage device.

[0068] In some possible embodiments, a signal buffer and an equalizer may be integrated within the signal multiplexing circuit to effectively compensate for attenuation and noise in high-speed signal transmission and maintain signal integrity.

[0069] The other end of the signal multiplexing circuit is connected to the protocol switching processor. This circuit quickly directs storage device slots to the host, enabling multiple storage device slots to share host interface resources. This signal multiplexing circuit also eliminates the hardware redundancy of configuring separate host interfaces for each storage device slot, significantly reducing system cost and wiring complexity.

[0070] Specifically, the protocol switching processor can integrate logic gate components (NOR gates, inverters, NAND gates, etc.) to form hardware-level protocol switching processing logic. The logic gate components can achieve real-time switching control of high-speed signals.

[0071] In some possible implementations, the protocol switching processor also interacts with the host through a status register, providing real-time feedback on the current signal switching status (e.g., link connection status, error warning information). Upon detecting a signal transmission error (e.g., a CRC check failure), the processor can quickly generate an interrupt signal through logic gate combinational circuits, triggering the host's error recovery mechanisms (e.g., link reset, data retransmission).

[0072] The transmission data of the target communication protocol can be sent to the host through the signal multiplexing circuit, and the target communication protocol is the first communication protocol or the second communication protocol.

[0073] Figure 3 This is a schematic diagram of the structure of a storage device slot provided in an embodiment of the present application. Figure 3 The signal multiplexing circuit may include a first circuit and a second circuit. The first circuit is provided with a storage logic controller, and the storage logic controller is connected to the protocol switching processor and the host respectively through an interconnected high-speed bus. The second circuit directly connects the protocol switching processor to the host through an interconnected high-speed bus.

[0074] The storage logic controller may be a RAID controller, and the storage logic controller may perform storage management on the first solid-state hard disk corresponding to the storage device slot based on the target sub-logical controller.

[0075] The target sub-logic controller may be one of multiple sub-logic controllers in the storage logic controller, and the sub-logic controller is used to execute its corresponding storage logic.

[0076] The plurality of sub-logical controllers may include at least two of the following: a stripe unit controller, a mirror redundancy controller, a distributed parity controller, and a dual distributed parity controller.

[0077] The stripe unit controller may be RAID 0. The storage logic of RAID 0 is to divide data into stripe units of a fixed size (Stripe Size, usually 4K-256K) and write them to the disk in a round-robin manner.

[0078] Stripe Unit: refers to the fixed-size block formed after data is divided. It is the basic unit of data distribution in RAID 0 and its size is usually 4K-256K.

[0079] RAID 0: A non-redundant RAID level that divides data into stripes and stores them distributedly across multiple disks using round-robin writes (for example, Disk 1 stores Stripe 1, Disk 2 stores Stripe 2, and so on). This uses parallel read and write to improve performance, but lacks data redundancy. A single disk failure results in the loss of all data.

[0080] The mirrored redundant controller can be RAID 1. RAID 1 is a mirror-based redundant RAID level that provides 100% data replication across all member disks (for example, Disk A and Disk B are completely synchronized), forming a mirrored relationship. Its advantages include improved read performance (parallel reads) and strong fault tolerance (data is not lost even if a single disk fails). However, it comes at the expense of higher storage costs (requiring double the disk space).

[0081] The distributed parity controller can be RAID 5, a RAID level that balances performance and redundancy. It stripes data across multiple disks (for example, across three disks, two store the data stripe and one stores the parity information). Parity information is rotated across the disks, preventing a single disk from becoming a bottleneck due to parity information storage. It supports single-disk failure recovery, with a space utilization ratio of (n-1) / n (where n is the number of disks).

[0082] Parity: A data verification method that generates parity information by performing operations such as XOR on multiple data blocks. When a data block is lost, the lost data can be reconstructed using other data blocks and the parity information.

[0083] The dual distributed parity controller can be RAID 6. RAID 6's storage logic is an extended RAID 5 architecture, employing two independent parity algorithms (such as XOR parity plus another polynomial checksum) to generate two copies of parity information and store them in a distributed manner. This allows for tolerance of two simultaneous drive failures, making it suitable for scenarios requiring the highest data security. However, write performance is slightly lower (due to the need to calculate two parity copies), resulting in a space utilization ratio of (n-2) / n.

[0084] The distributed parity check controller and the dual distributed parity check controller may be FPGA acceleration cards based on FPGA, and the stripe unit controller and the mirror redundancy controller may be ASIC streamlined cards based on ASIC.

[0085] The RAID controller's sub-logic controllers (for example, the stripe unit controller and mirror redundancy controller) are implemented based on an Application-Specific Integrated Circuit (ASIC). ASICs can efficiently handle the data striping, redundancy checking, and fault recovery required by RAID technology through customized hardware logic.

[0086] In some possible embodiments, a sub-logic controller (eg, a distributed parity check controller and a dual distributed parity check controller) based on a field programmable gate array (FPGA) supports real-time burning of hardware logic of different RAID levels.

[0087] The hardware structure of FPGA is reconfigurable. The logic function of FPGA is determined by software configuration, and the configuration process can be completed while the system is running (i.e. "real-time burning"). In scenarios where flexible adjustment of hardware logic is required, for example, multiple RAID levels are supported in this application.

[0088] Sub-logic controllers of different RAID levels can correspond to configurable hardware modules. By dynamically loading the configuration files of the configurable hardware modules corresponding to each sub-logic controller, different configuration files allow the FPGA to behave as controllers of different RAID levels at different times.

[0089] Specifically, the storage logic controller may include a general logic module and a dedicated logic module. The general logic module is used to implement the general basic functions of each RAID level, and the dedicated logic module is used to implement the dedicated functions of each RAID level.

[0090] The dedicated logic module can switch the RAID level based on a switching instruction sent by the host: the host sends a switching instruction (for example, switching from RAID 5 to RAID 6); suspends the logical operation of the initial RAID level (for example, RAID 5) of the storage logic controller; loads the target configuration file of the target RAID level (for example, RAID 6) corresponding to the switching instruction, and updates the logical resources of the dedicated logic module according to the target configuration file to switch the initial RAID level of the storage logic controller to the target RAID level.

[0091] When suspending the logical operation of the initial RAID level of the storage logic controller, necessary intermediate states (eg, data in the cache and check information) are saved.

[0092] The protocol switching processor can perform circuit switching between the first circuit and the second circuit according to the type of the hard disk inserted into the solid state drive.

[0093] The first circuit and the second circuit are parallel circuits. The second circuit can be a pass-through card based on the JBOD mode, which can directly connect the solid-state hard disk to the host and bypass the RAID controller.

[0094] The TRIM command is a key ATA command for SSD garbage collection. It's used to mark invalid data blocks. When the operating system or a management device (such as a BMC) deletes data from the SSD, the TRIM command notifies the SSD controller that these data blocks are no longer valid and that the physical storage space they occupy can be released in advance. The SSD controller uses this command to perform background garbage collection, avoiding the performance degradation caused by the need to clear invalid data during subsequent writes. This command is crucial for maintaining the long-term read and write performance of the SSD, enabling the SSD controller to free up physical space in advance and avoid write performance degradation.

[0095] The hardware's storage logic controller is usually unable to transparently transmit TRIM instructions (especially RAID 5 / 6), resulting in the solid-state drive being unable to perceive data deletion and a sharp drop in performance after long-term operation.

[0096] The second circuit can enable the second solid-state drive to be directly connected to the host, bypassing the RAID controller and improving storage performance.

[0097] See Figure 3 The storage device slot is also provided with an error correction codec, which is connected to the storage logic controller. The error correction codec is used to perform error correction on the storage logic processing, which can realize accelerated verification of the storage.

[0098] The error correction codec can be a low-density parity-check code (LDPC) codec. This is a forward error correction system based on sparse matrix operations. It can efficiently detect and correct errors during transmission / storage by adding redundant check bits to transmitted data, reducing the amount of computation and accelerating storage verification. The error correction codec can include an encoder and a decoder.

[0099] In this application, the storage logic controller has multiple dedicated sub-logic controllers built in, each sub-logic controller independently executes specific storage logic, and implements functional hierarchical management through the storage logic controller and the protocol switching processor, which can increase the reliability of protocol conversion.

[0100] Figure 4 This is a structural diagram of another backplane system provided in an embodiment of the present application. Figure 4 The backplane system also includes a backplane controller, which is connected to the host and each storage logic controller.

[0101] The user can select the target sub-logical controller corresponding to the target storage logical controller through the management interface, and the host can generate a level switching request. The level switching request can include the processor identifier of the target storage logical controller and the controller identifier corresponding to the target sub-logical controller.

[0102] The backplane controller may generate a replacement instruction according to the level switching request sent by the host, and send the replacement instruction to the target storage logic controller to switch the sub-logical controller corresponding to the target storage logic controller to the target sub-logical controller.

[0103] Each sub-logic controller can be switched based on a logic gate component, wherein the use of the logic gate component can refer to the switching design of switching the first circuit and the second circuit mentioned above, which will not be repeated here.

[0104] See Figure 4 The backplane controller includes a hot-swap management controller, which can monitor the plug-in and plug-out signals of each storage device slot in real time.

[0105] The plug-in / plug-out signal is a digital signal used to identify the "plugged-in" or "plugged-out" status of a storage device. When the signal meets the "plug-in" threshold (such as the first preset signal), it indicates that the device has been connected; when it meets the "plug-out" threshold (such as the second preset signal), it indicates that the device has been removed.

[0106] Specifically, if the plug-in signal is the first preset signal, the plug-in signal indicates that the solid-state hard disk is inserted into the corresponding storage device slot; if it is the second preset signal, the plug-in signal indicates that the solid-state hard disk is removed from the corresponding storage device slot.

[0107] In some possible embodiments, the first preset signal may be at a high level, and the second preset signal may be at a low level.

[0108] See Figure 4 The hot-swap management controller may include a current sensor and a high-speed analog-to-digital converter, the current sensor is connected to the storage device slot, and the high-speed analog-to-digital converter is connected to the current sensor.

[0109] A current sensor is an electronic component that detects the current flow in a circuit in real time. It can detect the analog current signal from the hard drive in a storage device slot. For example, when a solid-state drive is inserted, the slot generates a load current; when it is removed, the current disappears or drops significantly.

[0110] The current sensor can be connected to the storage device slot through pins, which can improve the reliability of the current sensor detection.

[0111] The current sensor can be connected to multiple storage device slots through a multiplexer (MUX).

[0112] A multiplexer (MUX) is an electronic switching element that achieves "multiple inputs, single output." It allows a single current sensor to connect to multiple storage device slots simultaneously. By using timing control or signal gating, analog current signals from different slots can be collected sequentially, eliminating the need for a separate current sensor for each slot. This simplifies hardware design and reduces costs.

[0113] A high-speed analog-to-digital converter (High-Speed ​​ADC) is an electronic component that can quickly convert a continuously changing analog signal (such as the current analog signal output by a current sensor) into a discrete digital signal (i.e., the "plug-in / plug-out signal").

[0114] In this application, multiple storage device slots can be detected and monitored simultaneously through current sensors and high-speed analog-to-digital converters, saving backplane space.

[0115] In some possible embodiments, the hot-swap management controller is further configured to update the newly added hard disk based on log information of the target storage device slot during the period between the removal of a historical hard disk and the insertion of a newly added hard disk.

[0116] Log information is a detailed record of multiple pending data operations recorded by the system during the storage device insertion and removal period. Log information can include key information such as the source, size, target storage location, and initiation time of the data to be written.

[0117] The hot-swappable management controller can update new hard disks through log analysis, thereby improving the reliability of the storage infrastructure.

[0118] Specifically, log information during the plug-in and plug-out period can be obtained to generate hash values ​​for each data block to be written; after a new hard disk is inserted, the difference data blocks are determined based on the hash values ​​of each data block to be written and the hash values ​​of each hard disk data block of the new hard disk; and the difference data blocks are updated in the new hard disk.

[0119] A data block is the smallest unit of data processing and transmission in a storage system (not a single file). It is typically a fixed-size binary data fragment (such as a few KB or tens of KB). The system splits files into multiple data blocks for storage and performs hash calculations, comparisons, and writes on a per-block basis, improving data processing efficiency and flexibility.

[0120] The data blocks to be written should be written to the historical hard disk but are not successfully written because the hard disk is unplugged and are in the "waiting to write state".

[0121] A hash value is a fixed-length binary or hexadecimal string obtained by converting input data of any size (e.g., a data block) using a hash algorithm. For example, the hash algorithm can be SHA-256 or CRC32.

[0122] The hash values ​​generated by different data blocks are almost impossible to be the same, and the original data cannot be deduced from the hash values.

[0123] A hard disk data block is an existing data segment stored in a newly added hard disk, in units of "data blocks".

[0124] The plug-in / plug-out period is the time between the removal of the existing hard drive and the insertion of the new hard drive. During this period, there may be data blocks waiting to be written. After the new hard drive is inserted, the data blocks waiting to be written may have already been written to the new hard drive. The hash values ​​of each data block waiting to be written need to be compared with the hash values ​​of each data block on the new hard drive.

[0125] For any data block to be written, if its hash value does not exist in the hash values ​​of the data blocks on each hard disk, the data block to be written needs to be written to the newly added hard disk and is determined to be a difference data block. A difference data block is a data block that has not been written to the newly added hard disk.

[0126] In this application, after a new hard disk is inserted, the difference data blocks can be determined based on the hash value of each data block to be written and the hash value of each hard disk data block of the new hard disk. Only the difference data blocks are transmitted, which can improve efficiency and stability.

[0127] The hot-swap management controller is further configured to verify the synchronized differential data blocks in the newly added hard disk, and if the verification fails, switch to the backup storage logic controller.

[0128] The backup storage logical controller refers to a storage logical control unit deployed additionally in the storage system for redundant backup. It can implement core storage management tasks such as data read and write control and logical processing.

[0129] The backup storage logic controller can immediately take over the work and re-read or process data when the main storage logic controller fails (such as data verification failure or hardware abnormality), avoiding data loss or storage service interruption, and ensuring the reliability and continuity of the system storage function.

[0130] The checksum can be a cyclic redundancy check (CRC). CRC uses a preset mathematical polynomial algorithm (such as CRC-32 or CRC-64) to calculate the original data (such as synchronized difference data blocks) and generate a fixed-length binary value, the "CRC checksum value." The calculated CRC checksum value is compared with the preset checksum value before data transmission or storage. If the two match, the data is intact and error-free during transmission or storage. If they differ, the data may have been damaged or lost due to interference, hardware problems, or other issues, and requires reprocessing (such as rereading or retransmission).

[0131] When the verification fails, it is determined that the current difference data block is unreliable, and a switch can be made to a redundant backup storage logical controller to re-read the difference data block in the backup storage logical controller.

[0132] In this application, reliable storage services can be ensured by verifying the data integrity in real time and utilizing the redundancy of the backup storage logic controller to achieve automatic fault switching.

[0133] See Figure 4 The backplane also includes a backplane monitor, which is connected to each storage device slot and the backplane controller respectively. The backplane monitor can monitor the load of each storage device slot, obtain the hard disk load corresponding to each storage device slot, and send the hard disk load corresponding to each storage device slot to the backplane controller.

[0134] Hard disk load can be used to measure the current working pressure of the solid-state drive connected to the storage device slot. It is usually quantified by "data transfer volume per unit time", "number of read and write requests" or "resource utilization".

[0135] If the hard drive is highly loaded, the hard drive must frequently process large amounts of data reads and writes (such as continuously transferring large files). This places high demands on the bandwidth of the data transmission channel (such as the interconnected high-speed bus). If the hard drive is lightly loaded, the hard drive receives fewer read and write requests and transfers less data (such as only occasionally reading small files). This places low demands on the bandwidth of the transmission channel.

[0136] There are multiple storage device slots on the backplane. If the interconnection high-speed bus channels are unevenly distributed, performance will be degraded. When the hard disk corresponding to the storage device slot is heavily loaded, more data is transmitted, and more interconnection high-speed buses need to be allocated; when the hard disk corresponding to the storage device slot is lightly loaded, not so much data is transmitted, and fewer interconnection high-speed buses are required.

[0137] The backplane controller may allocate an interconnected high-speed bus to a storage device slot having a hard disk load greater than a preset load based on the hard disk load corresponding to each storage device slot.

[0138] The interconnect high-speed bus can be allocated through the allocation mechanism:

[0139] Trigger condition: At the rising edge of the clock, the current lane request signal (lane_request) is compared with the number of allocated lanes (current_alloc). When the requested number is greater than the allocated number, channel reallocation is triggered.

[0140] Allocation rules: Read the corresponding configuration from the preset lane priority table (lane_priority_table) according to the request identifier (request_id), and assign the result to the rerouting register (reroute_lanes) to achieve dynamic channel allocation.

[0141] Status update: Call the update_arbitration function to update the arbitration logic status according to the currently activated slots (active_slots) information to prepare for the next channel allocation.

[0142] The preset channel priority table may be a storage device slot list arranged from high to low according to the hard disk load corresponding to each storage device slot.

[0143] By comparing the priority table with real-time requests, the function of dynamically adjusting PCIe channel resources based on demand is realized, ensuring that high-priority requests can obtain more channel resources.

[0144] The solid-state hard disk corresponding to the storage device slot with a larger hard disk load can be given priority to obtain the interconnected high-speed bus channel, and the high-speed bus channel can be dynamically allocated, so that the solid-state hard disk corresponding to the storage device slot with a larger hard disk load can be given priority for data transmission, which can improve storage performance.

[0145] The backplane controller communicates with the backplane monitor via a two-wire communication interface. The two-wire communication interface is a 2Wire interface, which may include a data transmission line and a clock synchronization line.

[0146] The 2Wire interface enables data exchange between devices through two physical lines. The two lines are responsible for "data transmission" (transmitting actual data) and "clock synchronization" (ensuring that the data transmission rhythm of the sender and receiver is consistent).

[0147] See Figure 4 The backplane also includes a preset storage device slot, and the solid-state hard disk corresponding to the preset storage device slot is a preset hot spare hard disk.

[0148] The preset storage slot structure is the same as the structure of the storage device slot. Please refer to the storage device slot above and will not be repeated here.

[0149] The preset storage slots and the storage device slots are powered on and run simultaneously, but data is not stored synchronously in real time. The preset hot spare drive corresponding to the preset storage slot is activated only when the solid-state drive corresponding to the storage device slot fails.

[0150] The backplane controller can detect a hard disk failure in the solid-state hard disk corresponding to each storage device slot through the backplane monitor, and then migrate the data of the solid-state hard disk with the hard disk failure to a preset hot spare hard disk.

[0151] The preset hot spare hard drive is a spare solid-state drive pre-connected to the "preset storage device slot" and is in standby ready state to deal with other hard drive failures.

[0152] When the backplane monitor detects a fault in a solid-state drive in a storage device slot, the backplane controller can directly migrate the data in the faulty drive to the preset hot spare drive, avoiding data loss while reducing the "read-modify-write" operations on the faulty drive and improving system recovery efficiency.

[0153] Silent erasures can be scheduled on pre-set hot spare drives. This is a background data cleanup operation that automatically removes any remaining invalid data blocks without disrupting the drive's normal standby state (or its ability to receive data migration at any time). This frees up physical storage space in advance, ensuring the hot spare drive is always in a fast read / write state. When data migration is needed from a failed drive, data can be written directly and efficiently without the need for time-consuming space cleanup.

[0154] In some possible implementations, a backplane monitor monitors slot impedance changes in real time. If a sudden change exceeds 5Ω (ΔR > 5Ω), the connection is considered abnormal. To avoid subsequent signal reflections or device failure, the system proactively switches to a degraded mode (for example, disabling certain functions or activating a redundant, pre-set hot-spare hard drive) within 50ms to maintain basic operations and prevent damage.

[0155] In some possible embodiments, for any storage device slot, a vibration sensor and a temperature sensor are provided in the storage device slot, and the backplane controller can obtain vibration data within a first time period before the current moment through the vibration sensor, and obtain temperature data within a first time period before the current moment through the temperature sensor, determine the timing data based on the vibration data within the first time period and the temperature data within the first time period, and process the timing data through a hot plug prediction model to obtain a hot plug probability after the current moment; if the hot plug probability is greater than the preset probability, the data of the solid-state hard disk corresponding to the storage device slot is migrated to the preset hot spare hard disk.

[0156] The hot swap prediction model can be obtained by pre-training a long short-term memory (LSTM) model using a training set.

[0157] The first time length may be 2 seconds, and 2 seconds of time series data may be input into the hot-plug prediction model to output a predicted hot-plug probability.

[0158] In some possible embodiments, an online learning module can be deployed, that is, each time an actual plug-in or unplug occurs, new data is automatically added to the training set, and the model parameters are updated by incremental gradient descent. For example, it can be executed during the low-load period in the early morning every day.

[0159] Accordingly, an embodiment of the present application provides a storage system, including the backplane system in the above embodiment, solid-state hard drives corresponding to each storage device slot, and a baseboard management controller, wherein the baseboard management controller is used to implement the solid-state hard drives corresponding to each storage device slot through a third communication protocol.

[0160] The third communication protocol may be an Intelligent Platform Management Interface (IPMI) protocol. The IPMI protocol is a hardware-level management protocol that is independent of the operating system and the CPU and can implement out-of-band management of the server through a baseboard management controller (BMC) embedded in the motherboard.

[0161] The storage system provided in this embodiment can implement the above-mentioned backplane system. Its implementation principle and technical effects are similar and will not be described in detail in this embodiment.

[0162] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0163] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A backplane system, characterized in that: The backplane system is provided with a plurality of storage device slots, each storage device slot is provided with its corresponding signal multiplexing circuit and protocol switching processor, the protocol switching processor is respectively connected to the protocol identification pin and signal multiplexing circuit of its corresponding storage device slot, and the signal multiplexing circuit of each storage device slot is respectively connected to the host, wherein, The storage device slot is configured to receive a first solid-state drive or a second solid-state drive, wherein the first solid-state drive is a solid-state drive based on a first communication protocol, and the second solid-state drive is a solid-state drive directly connected to the host via an interconnected high-speed bus and based on a second communication protocol; The signal multiplexing circuit is configured to send transmission data of a target communication protocol to the host, where the target communication protocol is the first communication protocol or the second communication protocol; The protocol switching processor is used to switch the communication protocol of the signal multiplexing circuit according to the pin signal of the protocol identification pin corresponding to the storage device slot.

2. The system according to claim 1, wherein: The protocol switching processor is configured to obtain a pin signal of a protocol identification pin corresponding to the storage device slot, and if the pin signal is a first preset pin signal, determine that the target solid-state drive corresponding to the storage device slot is a first solid-state drive; if the pin signal is a second preset pin signal, determine that the target solid-state drive corresponding to the storage device slot is a second solid-state drive; The protocol switching processor is further configured to switch the communication protocol of the signal multiplexing circuit to a target communication protocol corresponding to the target solid-state drive, where the target solid-state drive is the first solid-state drive or the second solid-state drive.

3. The system according to claim 1, wherein: The signal multiplexing circuit includes a first circuit and a second circuit, the first circuit and the second circuit are parallel circuits, the first circuit is provided with a storage logic controller, the storage logic controller is connected to the protocol switching processor and the host respectively through an interconnected high-speed bus, and the second circuit is connected to the host through an interconnected high-speed bus, wherein, The storage logic controller is used to perform storage management on the first solid-state hard disk corresponding to the storage device slot based on the target sub-logic controller. The target sub-logic controller is one of the multiple sub-logic controllers in the storage logic controller, and the sub-logic controller is used to execute its corresponding storage logic.

4. The system according to claim 3, characterized in that The storage device slot is further provided with an error correction codec, which is connected to the storage logic controller and is used to perform error correction processing on the logic processing of the storage logic controller.

5. The system according to claim 3, wherein: The system further includes a backplane controller, which is connected to the host and each storage logic controller respectively, wherein: The backplane controller is configured to generate a replacement instruction according to the level switching request sent by the host, and send the replacement instruction to the target storage logic controller to switch the sub-logic controller corresponding to the target storage logic controller to the target sub-logic controller; The level switching request includes the processor identifier of the target storage logical controller and the controller identifier corresponding to the target sub-logical controller.

6. The system according to claim 5, characterized in that The plurality of sub-logical controllers include at least two of the following: a stripe unit controller, a mirror redundancy controller, a distributed parity check controller, and a dual distributed parity check controller.

7. The system according to claim 5, characterized in that The backplane controller includes a hot-swap management controller, which is connected to each storage device slot and is used to monitor the plug-in and pull-out signals of each storage device slot in real time; Among them, if the plug-in signal is a first preset signal, the plug-in signal indicates that a solid-state hard drive is inserted into the corresponding storage device slot; if the plug-in signal is a second preset signal, the plug-in signal indicates that a solid-state hard drive is removed from the corresponding storage device slot.

8. The system according to claim 7, characterized in that The hot-swap management controller includes a current sensor and a high-speed analog-to-digital converter, wherein: The current sensor is connected to each storage device slot, and the current sensor is used to detect the current analog signal of the hard disk corresponding to each storage device slot; The high-speed analog-to-digital converter is connected to the current sensor, and the high-speed analog-to-digital converter is used to convert the current analog signal detected by the current sensor into a plug-in / plug-out signal, and the plug-in / plug-out signal is a digital signal.

9. The system according to claim 7, wherein: The hot-swap management controller is further configured to update the newly added hard disk based on log information of the target storage device slot during a period when a historical hard disk is removed and a newly added hard disk is inserted.

10. The system according to claim 9, characterized in that The hot-swap management controller is used to: Obtain log information during the plug-in and unplug-out period and generate hash values ​​for each data block to be written; After a new hard disk is inserted, determining difference data blocks based on the hash values ​​of the data blocks to be written and the hash values ​​of the data blocks of each hard disk of the new hard disk; In the newly added hard disk, the difference data blocks are updated.

11. The system according to claim 10, wherein: The hot-swap management controller is further configured to perform verification processing on the difference data blocks in the newly added hard disk, and if the verification fails, switch to the backup storage logic controller.

12. The system according to claim 5, wherein: The backplane further includes a backplane monitor, which is connected to each storage device slot and the backplane controller respectively, wherein: The backplane monitor is configured to monitor the load of each storage device slot, obtain the hard disk load corresponding to each storage device slot, and send the hard disk load corresponding to each storage device slot to the backplane controller; The backplane controller is further configured to allocate an interconnected high-speed bus to a storage device slot having a hard disk load greater than a preset load based on the hard disk load corresponding to each storage device slot.

13. The system according to claim 12, wherein: The backplane controller is in communication connection with the backplane monitor via a two-wire communication interface, wherein the two-wire communication interface includes a data transmission line and a clock synchronization line.

14. The system according to claim 5, wherein: The backplane also includes a preset storage device slot, and the solid state hard disk corresponding to the preset storage device slot is a preset hot spare hard disk. The backplane controller is further configured to, through the backplane monitor, migrate data of the solid-state hard disk with the hard disk failure to the preset hot spare hard disk after a hard disk failure is detected in the solid-state hard disk corresponding to each storage device slot.

15. A storage system, characterized in that: The backplane system comprises the backplane system according to any one of claims 1 to 14, a solid-state hard disk corresponding to each storage device slot, and a baseboard management controller, wherein: The baseboard management controller is used to implement the solid-state hard disk corresponding to each storage device slot through a third communication protocol.

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