EVM instruction set abstract semantic description method and device based on theorem prover

Abstract

The invention relates to the technical field of block chains, and provides an EVM instruction set abstract semantic description method and device based on a theorem prover, electronic equipment and a computer program product. The method comprises the steps of obtaining a to-be-processed EVM instruction set; and converting the EVM instruction set into a corresponding abstract semantic description based on an inductive definition method in the theorem prover. According to the method, a theorem prover with high credibility is utilized, and instruction behaviors during operation of the EVM instruction set can be accurately and completely described mathematically, so that the accuracy of abstract semantic description for the EVM instruction set is improved, and a solid mathematical basis is provided for automatic reasoning and formalized verification of the smart contract.

Description

Technical Field

[0001] The present application relates to the field of blockchain technology, and in particular to a method, device, electronic device, and computer program product for describing the abstract semantics of an EVM instruction set based on a theorem prover. Background Art

[0002] In the field of blockchain technology, Ethereum's EVM instructions are typically executed one by one through specialized execution engines such as interpreters. Therefore, accurately describing the abstract semantics of the EVM instruction set to model the behavior of EVM instruction execution is crucial. However, existing EVM instruction set modeling methods lack high-reliability formal tools to ensure modeling correctness and verifiability, resulting in low accuracy in abstract semantic descriptions. This directly impacts subsequent automated reasoning and formal verification of smart contracts. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a method, apparatus, electronic device, and computer program product for abstract semantic description of an EVM instruction set based on a theorem prover. By introducing a highly reliable theorem prover, the accuracy of abstract semantic description of the EVM instruction set can be improved.

[0004] A first aspect of an embodiment of the present application provides an EVM instruction set abstract semantic description method based on a theorem prover, including:

[0005] Get the EVM instruction set to be processed;

[0006] In the theorem prover, the EVM instruction set is converted into the corresponding abstract semantic description based on the inductive definition method.

[0007] After obtaining the EVM instruction set to be processed, the technical solution of the embodiment of the present application converts the EVM instruction set into a corresponding abstract semantic description based on the inductive definition method in the theorem prover. The above process uses a high-reliability theorem prover to mathematically accurately and completely describe the instruction behavior of the EVM instruction set at runtime, thereby improving the accuracy of the abstract semantic description of the EVM instruction set and providing a solid mathematical foundation for automated reasoning and formal verification of smart contracts.

[0008] In one implementation of the embodiment of the present application, the EVM instruction set is converted into a corresponding abstract semantic description based on an inductive definition method in the theorem prover, including:

[0009] In the theorem prover, math data types are used to describe the integer data types of the EVM instruction set.

[0010] In one implementation of the embodiment of the present application, the EVM instruction set is converted into a corresponding abstract semantic description based on an inductive definition method in the theorem prover, including:

[0011] In the theorem prover, the integer list type is used to describe the stack data structure of the EVM instruction set, and the function map type is used to describe the abstract memory mapping relationship of the EVM instruction set from the address space to a single byte.

[0012] In one implementation of the embodiment of the present application, the EVM instruction set is converted into a corresponding abstract semantic description based on an inductive definition method in the theorem prover, including:

[0013] In the theorem prover, n-tuples are used to define the contract internal state and cross-contract call state that describe the EVM instruction set.

[0014] In one implementation of the embodiment of the present application, the EVM instruction set is converted into a corresponding abstract semantic description based on an inductive definition method in the theorem prover, including:

[0015] In the theorem prover, the inst induction type is used to describe various EVM instructions of the EVM instruction set.

[0016] In one implementation of the embodiment of the present application, various EVM instructions include arithmetic instructions, bit operation instructions, environment instructions, memory instructions, storage instructions, jump instructions, stack instructions, log instructions and system instructions.

[0017] In one implementation of the embodiment of the present application, after converting the EVM instruction set into a corresponding abstract semantic description based on the inductive definition method in the theorem prover, the following is further included:

[0018] In the theorem prover, recursive functions are used to complete the validity check of abstract semantic descriptions and instruction behavior.

[0019] A second aspect of an embodiment of the present application provides an EVM instruction set abstract semantic description device based on a theorem prover, comprising:

[0020] EVM instruction set acquisition module, used to obtain the EVM instruction set to be processed;

[0021] The abstract semantic description module is used to convert the EVM instruction set into the corresponding abstract semantic description based on the inductive definition method in the theorem prover.

[0022] A third aspect of an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the EVM instruction set abstract semantic description method based on theorem prover provided in the first aspect of the embodiment of the present application is implemented.

[0023] A fourth aspect of the embodiments of the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device executes the EVM instruction set abstract semantic description method based on theorem prover provided in the first aspect of the embodiments of the present application.

[0024] A fifth aspect of an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the EVM instruction set abstract semantic description method based on theorem prover as provided in the first aspect of the embodiment of the present application.

[0025] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 This is a flowchart of an EVM instruction set abstract semantic description method based on a theorem prover provided in an embodiment of the present application;

[0028] Figure 2 This is a schematic diagram of an overall technical framework adopted by the EVM instruction set abstract semantic description method based on theorem prover provided in an embodiment of the present application;

[0029] Figure 3 This is a schematic diagram of the structure of an EVM instruction set abstract semantic description device based on a theorem prover provided in an embodiment of the present application;

[0030] Figure 4 This is a schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system structures and technologies are provided to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obstructing the description of the present application with unnecessary details. In addition, in the description of the present application specification and the appended claims, the terms "first," "second," "third," etc. are only used to distinguish descriptions and are not to be understood as indicating or implying relative importance.

[0032] When executing smart contracts, Ethereum's virtual machine typically uses a compiler to translate the smart contract program into the underlying EVM instruction program. It then uses an execution engine, such as an interpreter, to interpret and execute the EVM instructions one by one. Therefore, accurately describing the behavior of EVM instructions is crucial for ensuring the smooth execution of smart contracts. However, existing EVM instruction set modeling methods often struggle to cover the entire EVM instruction set and its evolving versions. Furthermore, they lack high-reliability formal tools to ensure the correctness and verifiability of the modeling. This results in low accuracy in abstract semantic descriptions, which directly impacts the reliability of key operations such as smart contract security analysis and formal verification.

[0033] To address the above-mentioned technical problems in the prior art, the embodiments of this application provide a method, device, electronic device, and computer program product for describing the abstract semantics of the EVM instruction set based on a theorem prover. By introducing a highly reliable theorem prover, the accuracy of the abstract semantic description of the EVM instruction set can be improved, thereby ensuring the reliability of smart contract security analysis and formal verification. For more specific technical implementation details of the embodiments of this application, please refer to the various method embodiments described below.

[0034] It should be understood that the execution entities of the various method embodiments proposed in this application can be various types of electronic devices, such as mobile phones, tablet computers, desktop computers, wearable devices, augmented reality (AR) / virtual reality (VR) devices, laptop computers, ultra-mobile personal computers (UMPCs), netbooks, personal digital assistants (PDAs), large-screen televisions, etc. The embodiments of this application do not impose any restrictions on the specific types of electronic devices. For example, if applied in a blockchain technology scenario, the electronic device can be any blockchain node.

[0035] See also Figure 1, shows an EVM instruction set abstract semantic description method based on a theorem prover provided in an embodiment of the present application, including:

[0036] 101. Get the EVM instruction set to be processed;

[0037] First, obtain the EVM instruction set to be processed. This EVM instruction set can be any version of the EVM instruction set and can contain various types of EVM instructions. In practice, the EVM instruction set to be processed can be obtained from the latest version of the existing official EVM instruction set specification document or the actual EVM instruction set file in the industry. Subsequently, the EVM instruction set needs to be converted into the corresponding abstract semantic description to fully describe the instruction behavior of the EVM instruction set at runtime.

[0038] 102. In the theorem prover, the EVM instruction set is converted into the corresponding abstract semantic description based on the inductive definition method.

[0039] The technical core of the embodiment of the present application is to use a theorem prover to formally model the abstract semantics of the EVM instruction set based on the method of inductive definition, that is, to convert the EVM instruction set into a corresponding abstract semantic description. By using a high-reliability theorem prover, it is possible to mathematically accurately and completely describe the instruction behavior of the EVM instruction set during operation, thereby improving the accuracy of the abstract semantic description of the EVM instruction set. The theorem provers used here may include but are not limited to the following types: Isabelle / HOL, Coq, and Lean, etc., as long as the theorem prover has the function of inductive definition. The abstract semantic behavior of EVM is generally described by an EVM interpreter (such as EVM_interp), which mainly includes the formal modeling of EVM abstract type, EVM abstract state (EVM_state), and EVM instruction syntax. In the following text, the specific modeling method is mainly illustrated by the theorem prover Isabelle / HOL.

[0040] In one implementation of the embodiment of the present application, the EVM instruction set is converted into a corresponding abstract semantic description based on an inductive definition method in the theorem prover, including:

[0041] In the theorem prover, math data types are used to describe the integer data types of the EVM instruction set.

[0042] First, let's introduce the modeling of EVM abstract types. In the theorem prover, mathematical data types can be used to describe the integer data types of the EVM instruction set. For example, EVM smart contracts typically use 256-bit integer data types to process transaction data. In the theorem prover Isabelle / HOL, the mathematical data type word can be directly used to describe integer data types of any length. For example, the data type word256 can be used to accurately describe the 256-bit integer data type in EVM transactions. This setup allows for convenient and accurate conversion of EVM instruction set integer data types into corresponding abstract semantic descriptions.

[0043] In one implementation of the embodiment of the present application, the EVM instruction set is converted into a corresponding abstract semantic description based on an inductive definition method in the theorem prover, including:

[0044] In the theorem prover, the integer list type is used to describe the stack data structure of the EVM instruction set, and the function map type is used to describe the abstract memory mapping relationship of the EVM instruction set from the address space to a single byte.

[0045] To model EVM abstract types, the theorem prover can also use the integer list type to describe the EVM instruction set stack data structure, and the function mapping type to describe the EVM instruction set's abstract memory mapping relationship from the address space to a single byte. Specifically, for the data types used by the EVM virtual machine, taking the stack (EVM_stack) and memory (EVM_memory) as examples, the theorem prover Isabelle / HOL can use the 256-bit integer list type (word256list) to describe the EVM instruction set stack data structure, and use the function mapping type word256=>word8 to describe the EVM instruction set's abstract memory mapping relationship from the 256-bit address space to a single byte. Based on these abstract types, corresponding abstract operations can be modeled. For example, the EVM stack-based POP operation can be defined as: EVM_POP::EVM_stack=>(word256*EVM_stack)option. The optional type option is used to capture error information. The EVM_POP operation receives an EVM stack and returns the error message None if the stack is empty. If the stack is not empty, a word256 type of data is released from the top of the stack and returned along with the remaining EVM stack. This configuration allows for a convenient and accurate description of the EVM instruction set's stack data structure and the abstract semantics of its abstract memory mapping relationship.

[0046] In an implementation of an embodiment of the present application, based on the method of inductive definition in the theorem prover, the EVM instruction set is converted into the corresponding abstract semantic description, including:

[0047] In the theorem prover, the internal state of the contract and the cross - contract call state of the EVM instruction set are defined using n - tuples.

[0048] Here, the modeling of the EVM abstract state (EVM_state) is introduced. According to the above - mentioned definition of the EVM abstract type modeling, the abstract state modeling of the EVM instruction set can be divided into two cases: the internal state of the contract and the cross - contract call state. For the internal state of the contract InstructionContinue, it mainly includes information such as the EVM stack, memory, fuel (gas), and program counter (pc). In the theorem prover, n - tuples can be used to define this part of the information. For example, in the theorem prover Isabelle / HOL, the internal state of the contract InstructionContinue can be formally described as an n - tuple definition EVM_ctx::=<EVM_stack, EVM_memory, gas, pc, …>. For the cross - contract call state InstructionToEnvironment, on the basis of the internal state of the contract, it includes additional cross - contract call information, such as information recording the types and corresponding data of EVM function creation, call, or return. These additional information can be recorded after the information fields of the internal state of the contract defined by n - tuples, such as <EVM_stack, EVM_memory, gas, pc, additional information, …>. By setting it like this, the abstract semantic descriptions of the internal state of the contract and the cross - contract call state of the EVM instruction set can be obtained conveniently and accurately.

[0049] As an example, the mathematical description of the complete EVM abstract state definition in the theorem prover Isabelle / HOL is as follows:

[0050] datatype EVM_state=

[0051] InstructionContinue EVM_ctx

[0052] InstructionToEnvironment contract_action EVM_ctx…

[0053] Among them, contract_action records the information related to the operations of EVM functions.

[0054] In one implementation of the embodiment of the present application, the EVM instruction set is converted into a corresponding abstract semantic description based on an inductive definition method in the theorem prover, including:

[0055] In the theorem prover, the inst induction type is used to describe various EVM instructions of the EVM instruction set.

[0056] Next, we'll introduce the modeling of EVM instruction syntax. Based on the different functional behaviors of instructions, various EVM instructions can be modeled as inst inductive types in the theorem prover Isabelle / HOL. This means that the inst inductive type is used to describe the various EVM instructions in the EVM instruction set. By inductively defining datatypes, different EVM instructions can be modeled as different inst inductive types, allowing for convenient and accurate conversion of various EVM instructions in the EVM instruction set into corresponding abstract semantic descriptions.

[0057] In one implementation of the embodiment of the present application, various EVM instructions include arithmetic instructions, bit operation instructions, environment instructions, memory instructions, storage instructions, jump instructions, stack instructions, log instructions and system instructions.

[0058] The EVM instruction set includes various EVM instructions, including but not limited to arithmetic instructions, bit manipulation instructions, environment instructions, memory instructions, storage instructions, jump instructions, stack instructions, log instructions, and system instructions. In the theorem prover, these different types of EVM instructions can all be described using the induction type inst.Specifically, arithmetic instructions (Arith) include commonly used arithmetic instructions, such as integer addition, integer subtraction, integer multiplication, integer division, modulus operation, modulus addition operation, modulus multiplication operation, exponential operation and sign extension operation, etc., which can be summarized as datatype arith_inst = ADD | MUL | SUB | DIV | MOD | ADDMOD | MULMOD | EXP | ...; bit operation instructions (Bits) include logical AND, logical OR, logical NOT, logical XOR, logical left shift, logical right shift and arithmetic right shift operations, etc., which can be summarized as datatype bits_inst = inst_AND | inst_OR | inst_XOR | inst_NOT | inst_SHL | ...; environmental instructions (Info) include obtaining the current contract address (ADDRESS), balance (BALANCE), transaction sender (ORIGIN) and caller address (CALLER), etc., which can be summarized as datatype info_inst = ADDRESS | BALANCE | ORIGIN | CALLER | ...; Memory instructions (Memory) include reading 4 bytes of memory, writing 4 bytes of memory, and writing 1 byte of memory, etc., which can be summarized as datatype memory_inst = MLOAD | MSTORE | MSTORE8 | ...; Storage instructions (Storage) include reading 4 bytes of storage and writing 4 bytes of storage, etc., which can be summarized as datatype storage_inst = SLOAD | SSTORE | ...; Jump instructions (Pc) include unconditional jumps, conditional jumps, getting the current program counter value, and marking jump targets, etc., which can be summarized as datatype pc_inst = JUMP | JUMPI | PC | JUMPDEST | ...; Stack instructions (Stack) include pop and push operations, etc., where the pop operation only removes the top data of the stack, while the push operation involves 1-32 bytes of data, which can be summarized as datatype stack_inst = POP | PUSH_N"byte list"|…; Log instructions (Log) involve the creation of log record operations for five categories of topics (0-4), which can be summarized as datatype log_inst=LOG0|LOG1|LOG2|LOG3|LOG4; System instructions (Misc) include operations such as contract creation and different types of external contract calls, which can be summarized as datatype misc_inst=CREATE|CALL|CALLCODE|DELEGATECALL|….

[0059] As an example, the complete EVM instruction definition is mathematically described in the theorem prover Isabelle / HOL as follows:

[0060] datatype inst=

[0061] Arith"arith_inst"

[0062] Bits "bits_inst"

[0063] Info"info_inst"

[0064] Memory "memory_inst"

[0065] Storage "storage_inst"

[0066] Pc "pc_inst"

[0067] Stack "stack_inst"

[0068] Log "log_inst"

[0069] Misc"misc_inst"

[0070] Among them, Arith represents arithmetic instructions, Bits represents bit operation instructions, Info represents environment instructions, Memory represents memory instructions, Storage represents storage instructions, Pc represents jump instructions, Stack represents stack instructions, Log represents log instructions, and Misc represents system instructions.

[0071] See also Figure 2 , which is a schematic diagram of the overall technical framework adopted by the EVM instruction set abstract semantic description method based on theorem prover provided in the embodiment of this application. It can be seen that Figure 2 This paper provides an EVM abstract semantic modeling method based on the theorem prover Isabelle / HOL. By referring to the official EVM instruction set specification and the actual EVM instruction set implementation in the industry, the EVM abstract semantic behavior is described by the EVM interpreter, involving formal modeling of different aspects such as EVM abstract type, EVM abstract state and EVM instruction syntax.

[0072] After converting the EVM instruction set into the corresponding abstract semantic description, the EVM interpreter can also be semantically modeled to execute the instruction behavior corresponding to the abstract semantic description.

[0073] In one implementation of the embodiment of the present application, after converting the EVM instruction set into a corresponding abstract semantic description based on the inductive definition method in the theorem prover, the following is further included:

[0074] In the theorem prover, recursive functions are used to complete the validity check of abstract semantic descriptions and instruction behavior.

[0075] For the modeling of the EVM interpreter, the recursive function of the theorem prover can be used to complete the legality check and instruction behavior of the abstract semantic description of the EVM instruction. For example, in the theorem prover Isabelle / HOL, the EVM interpreter can be modeled as a recursive function program_sem, which accepts the initial EVM state and a termination counter. The program behavior of the recursive function program_sem can be defined as follows: when the counter is 0, the function stops executing; when the counter is not zero, the abstract semantic description of each EVM instruction is read sequentially and the legality check is performed on it (for example, whether there is sufficient remaining fuel gas, etc.). If the legality check fails, the execution of the corresponding instruction behavior is stopped; if the legality check passes, the sub-function instruction_sem can be used to execute the corresponding instruction behavior, and the abstract semantic description of the next EVM instruction is read based on the updated EVM state returned by the sub-function instruction_sem, until the abstract semantic description of all EVM instructions is recursively processed.

[0076] As an example, the definition of the recursive function program_sem is described as follows:

[0077] fun program_sem:: where

[0078] "program_sem 0st=st"

[0079] "program_sem(Suc fuel_pred)st=

[0080] if valid_check st then(*validity check*)

[0081] program_sem fuel_pred(instruction_sem st)

[0082] else st"

[0083] Using the above recursive function program_sem, the abstract semantic description of the EVM instruction set can be modeled as the EVM state transition relationship characterized by the EVM interpreter.

[0084] After obtaining the EVM instruction set to be processed, the technical solution of the embodiment of the present application converts the EVM instruction set into a corresponding abstract semantic description based on the inductive definition method in the theorem prover. The above process uses a high-reliability theorem prover to mathematically accurately and completely describe the instruction behavior of the EVM instruction set at runtime, thereby improving the accuracy of the abstract semantic description of the EVM instruction set and providing a solid mathematical foundation for automated reasoning and formal verification of smart contracts.

[0085] In summary, the embodiments of the present application propose an abstract semantic description method for the EVM instruction set based on a theorem prover. Since various types of EVM instructions can be converted into corresponding abstract semantic descriptions based on the inductive definition method in the theorem prover, this method supports the formal modeling of the complete EVM instruction set and can accurately describe the instruction behavior of various different versions of the EVM instruction set.

[0086] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0087] The above mainly describes an EVM instruction set abstract semantic description method based on a theorem prover. The following describes an EVM instruction set abstract semantic description device based on a theorem prover.

[0088] See also Figure 3 , shows an EVM instruction set abstract semantic description device based on a theorem prover provided in an embodiment of the present application, including:

[0089] An EVM instruction set acquisition module 301 is used to acquire an EVM instruction set to be processed;

[0090] The abstract semantic description module 302 is used to convert the EVM instruction set into a corresponding abstract semantic description based on the inductive definition method in the theorem prover.

[0091] In one implementation of the embodiment of the present application, the abstract semantic description module includes:

[0092] The integer type description unit is used to describe the integer data types of the EVM instruction set using mathematical data types in the theorem prover.

[0093] In one implementation of the embodiment of the present application, the abstract semantic description module includes:

[0094] The abstract type description unit is used in the theorem prover to describe the stack data structure of the EVM instruction set using the integer list type, and to describe the abstract memory mapping relationship of the EVM instruction set from the address space to a single byte using the function mapping type.

[0095] In one implementation of the embodiment of the present application, the abstract semantic description module includes:

[0096] Abstract state description unit, used in the theorem prover to define and describe the internal contract state and cross-contract call state of the EVM instruction set using n-tuples.

[0097] In one implementation of the embodiment of the present application, the abstract semantic description module includes:

[0098] The EVM instruction description unit is used in the theorem prover to describe various EVM instructions of the EVM instruction set using the inst induction type.

[0099] In one implementation of the embodiment of the present application, various EVM instructions include arithmetic instructions, bit operation instructions, environment instructions, memory instructions, storage instructions, jump instructions, stack instructions, log instructions and system instructions.

[0100] In one implementation of the embodiment of the present application, the EVM instruction set abstract semantic description device based on theorem prover further includes:

[0101] The interpreter modeling module is used to use recursive functions to complete the legality check and instruction behavior of abstract semantic descriptions in the theorem prover.

[0102] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the EVM instruction set abstract semantic description method based on the theorem prover described in any of the above embodiments.

[0103] An embodiment of the present application also provides a computer program product. When the computer program product is run on an electronic device, the electronic device executes the EVM instruction set abstract semantic description method based on theorem prover as described in any of the above embodiments.

[0104] Figure 4 Schematic diagram of an electronic device provided by an embodiment of the present application. Figure 4 As shown, the electronic device 4 of this embodiment includes: a processor 40, a memory 41, and a computer program 42 stored in the memory 41 and executable on the processor 40. When the processor 40 executes the computer program 42, the steps in the above-mentioned embodiments of the EVM instruction set abstract semantic description method based on the theorem prover are implemented, for example Figure 1Alternatively, when the processor 40 executes the computer program 42, the functions of the modules / units in the above-mentioned device embodiments are realized, for example, Figure 3 Functions of modules 301 and 302 of the illustrated apparatus.

[0105] The computer program 42 may be divided into one or more modules / units, which are stored in the memory 41 and executed by the processor 40 to implement the present application. The one or more modules / units may be a series of computer program instruction segments capable of performing specific functions, and the instruction segments are used to describe the execution process of the computer program 42 in the electronic device 4.

[0106] The processor 40 may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0107] The memory 41 may be an internal storage unit of the electronic device 4, such as a hard disk or memory of the electronic device 4. The memory 41 may also be an external storage device of the electronic device 4, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 4. Furthermore, the memory 41 may include both an internal storage unit of the electronic device 4 and an external storage device. The memory 41 is used to store the computer program and other programs and data required by the electronic device. The memory 41 may also be used to temporarily store data that has been output or is about to be output.

[0108] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0109] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0110] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0111] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0112] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the system embodiments described above are merely schematic. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0113] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0114] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0115] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and when the computer program is executed by the processor, it can implement the steps of the above-mentioned various method embodiments. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0116] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A method for abstract semantic description of EVM instruction set based on theorem prover, characterized in that: include: Get the EVM instruction set to be processed; In the theorem prover, the EVM instruction set is converted into a corresponding abstract semantic description based on the inductive definition method.

2. The method according to claim 1, wherein The method based on inductive definition in the theorem prover converts the EVM instruction set into a corresponding abstract semantic description, including: In the theorem prover, math data types are used to describe integer data types of the EVM instruction set.

3. The method according to claim 1, wherein The method based on inductive definition in the theorem prover converts the EVM instruction set into a corresponding abstract semantic description, including: In the theorem prover, an integer list type is used to describe the stack data structure of the EVM instruction set, and a function map type is used to describe the abstract memory mapping relationship of the EVM instruction set from the address space to a single byte.

4. The method according to claim 1, wherein The method based on inductive definition in the theorem prover converts the EVM instruction set into a corresponding abstract semantic description, including: In the theorem prover, n-tuple definitions are used to describe the contract internal state and cross-contract call state of the EVM instruction set.

5. The method according to claim 1, wherein The method based on inductive definition in the theorem prover converts the EVM instruction set into a corresponding abstract semantic description, including: In the theorem prover, the inst induction type is used to describe various EVM instructions of the EVM instruction set.

6. The method according to claim 5, wherein The various EVM instructions include arithmetic instructions, bit operation instructions, environment instructions, memory instructions, storage instructions, jump instructions, stack instructions, log instructions and system instructions.

7. The method according to any one of claims 1 to 6, wherein: After converting the EVM instruction set into a corresponding abstract semantic description based on the inductive definition method in the theorem prover, the method further includes: In the theorem prover, a recursive function is used to complete the legality check and instruction behavior of the abstract semantic description.

8. An EVM instruction set abstract semantic description device based on a theorem prover, characterized in that: include: EVM instruction set acquisition module, used to obtain the EVM instruction set to be processed; An abstract semantic description module is used to convert the EVM instruction set into a corresponding abstract semantic description based on an inductive definition method in a theorem prover.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the EVM instruction set abstract semantic description method based on theorem prover according to any one of claims 1 to 7 is implemented.

10. A computer program product, characterized in that When the computer program product is run on an electronic device, the electronic device executes the EVM instruction set abstract semantic description method based on theorem prover according to any one of claims 1 to 7.

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