FPGA BRAM reliability design method for resisting single event upset
Patent Information
- Application Number
- CN202510862185.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-25
- Publication Date
- 2025-10-03
Smart Images
Figure CN120745531A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of data storage, and in particular relates to a reliability design method for FPGA BRAM for resisting single-event upset. Background Art
[0002] Currently, FPGA chips are widely used in my country's aerospace sector due to their powerful interfaces, flexible programming, short development cycles, and compact size. However, FPGAs are susceptible to high-energy particles in space and are prone to single-event upsets (SEEs). This is particularly true for the BRAMs (Block RAMs) used to store user data within the FPGA. Mild SEEs can cause transient errors, while more severe SEEs can severely corrupt user data and cause critical functions to fail. For persistent storage devices, as the on-orbit power-up time increases, addressing the reduced data reliability caused by SEEs in FPGA BRAMs becomes crucial.
[0003] Existing technology uses triple-module redundancy to address single-event upsets. This technology implements triple-module redundancy by utilizing three FPGA BRAM modules, using voting logic to determine the final output, thereby achieving detection and error correction. However, this technology increases FPGA resource usage, resulting in increased chip power consumption. Summary of the Invention
[0004] In order to solve the above problems existing in the prior art, the present invention provides a reliability design method for FPGA BRAM for single event upset resistance. The technical problem to be solved by the present invention is achieved through the following technical solutions: In a first aspect, the present invention provides an FPGA BRAM reliability design method for single event upset resistance, comprising: Set up port control module trans_a and port control module trans_b; Using the port control module trans_a to control one of the two data read and write ports of the FPGA BRAM, and using the port control module trans_b to control the other of the two data read and write ports of the FPGA BRAM; Among them, the data read and write port controlled by the port control module trans_a is used for data reading and writing, and the data read and write port controlled by the port control module trans_b is used as a refresh port for monitoring the read and write operations of the data read and write port and automatically refreshing data when the data read and write port is not reading or writing.
[0005] In a second aspect, the present invention provides an FPGA BRAM reliability design device for resisting single event upset, the device comprising a port control module trans_a and a port control module trans_b; The port control module trans_a is used to control one of the two data read and write ports of the FPGA BRAM; The port control module trans_b is used to control the other of the two data read and write ports of the FPGA BRAM; Among them, the data read and write port controlled by the port control module trans_a is used for data reading and writing, and the data read and write port controlled by the port control module trans_b is used as a refresh port for monitoring the read and write operations of the data read and write port and automatically refreshing data when the data read and write port is not reading or writing.
[0006] Beneficial effects: The present invention provides a reliability design method for FPGA BRAM for resisting single-particle upsets, including: providing a port control module trans_a and a port control module trans_b, using the port control module trans_a to control one of the two data read / write ports of the FPGA BRAM, and the port control module trans_b to control the other; the data read / write port controlled by the port control module trans_a is used for data reading and writing, and the data read / write port controlled by the port control module trans_b is used as a refresh port for monitoring the read / write operations of the data read / write port and automatically refreshing data when the data read / write port is not reading or writing. The control and implementation of the present invention are relatively simple, occupy few resources, and can achieve high-reliability transmission of user data. The present invention has low power consumption when applied on a chip, can reduce the risk of firmware operation abnormalities caused by single-particle upsets, and can effectively improve the radiation resistance and reliability of solid-state storage devices.
[0007] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 This is a flow chart of a method for designing FPGA BRAM reliability for single event upset resistance provided by the present invention; Figure 2 This is a schematic diagram of the connection between the port control module trans_a, the port control module trans_b and the FPGA BRAM provided by the present invention. DETAILED DESCRIPTION
[0009] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.
[0010] First, combining Figure 1 and Figure 2 The present invention provides a FPGA BRAM reliability design method for resisting single event upset, including: S100, setting a port control module trans_a and a port control module trans_b; S200, using the port control module trans_a to control one of the two data read and write ports of the FPGA BRAM; using the port control module trans_b to control the other of the two data read and write ports of the FPGA BRAM; Among them, the data read and write port Port A controlled by the port control module trans_a is used for data reading and writing, and the data read and write port Port B controlled by the port control module trans_b is used as a refresh port, which is used to monitor the read and write operations of the data read and write port and automatically refresh data when the data read and write port is not reading or writing.
[0011] When the data read and write port reads and writes data, the data width is 42 bits, expressed as [41:0]; Bits [31:0] are data, bits [38:32] are ECC calculation results, and bits [41:39] are ECC flags. The data read / write port is specifically configured to perform read and write operations. The write operation involves padding the 32-bit data to be written to 42 bits and writing the padded 42-bit data to the BRAM. The read operation involves transmitting bits [31:0] of the 42-bit data from the BRAM to the port control module trans_a.
[0012] In a specific embodiment of the present invention, the refresh port is specifically used to: Monitoring the read and write operations of the data read and write port; When the data read / write port is not reading or writing, the following operations are performed to automatically refresh the data: Step 1: Read the data of BRAM to obtain 42-bit data; Step 2: Using the triple modular redundancy mechanism, select bits [41:39] from the 42-bit data read from the BRAM to obtain the ECC identifier; Step 3: Determine whether the ECC content is added based on the ECC identifier, and decide whether to perform error correction on the [31:0] bits based on the judgment result; Step 4: Recalculate the ECC calculation result of bits [31:0] in the current 42-bit data, and replace the original ECC calculation result in the current 42-bit data with the recalculated ECC calculation result to obtain updated 42-bit data; Step 5: Store the updated 42-bit data into the corresponding storage address, which is the next address of the address storing the updated 42-bit data after the last refresh.
[0013] In a specific embodiment of the present invention, Step 3 includes: Step 31, judging whether the ECC content has been added according to the ECC identifier to obtain a judgment result; This step determines whether the ECC content has been added based on the ECC identifier. If at least two bits of the ECC identifier are 0, it means that the ECC content has not been added. If at least two bits of the ECC identifier are 1, it means that the ECC content has been added.
[0014] Step 32: If the judgment result is that the ECC content has been added, the ECC error correction algorithm is used to correct the [31:0] bit position, and then the corrected data is used to replace the data of the [31:0] bit position before the error correction to obtain the current 42-bit data.
[0015] Step 33: If the judgment result is that the ECC content is not added, the 42-bit data read from the BRAM remains unchanged and the read 42-bit data is used as the current 42-bit data.
[0016] In a second aspect, the present invention provides an FPGA BRAM reliability design device for resisting single event upset, the device comprising a port control module trans_a and a port control module trans_b; The port control module trans_a is used to control one of the two data read and write ports of the FPGA BRAM; The port control module trans_b is used to control the other of the two data read and write ports of the FPGA BRAM; Among them, the data read and write port controlled by the port control module trans_a is used for data reading and writing, and the data read and write port controlled by the port control module trans_b is used as a refresh port for monitoring the read and write operations of the data read and write port and automatically refreshing data when the data read and write port is not reading or writing.
[0017] The data read and write port is specifically used to perform read data operations and write data operations. The write data operation includes filling the 32-bit data to be written into 42 bits and writing the filled 42-bit data into the BRAM; the read operation includes transmitting the bit data [31:0] in the 42-bit data from the BRAM to the port control module trans_a.
[0018] In a specific embodiment of the present invention, the refresh port is specifically used to: Monitoring the read and write operations of the data read and write port; When the data read / write port is not reading or writing, the following operations are performed to automatically refresh the data: Step 1: Read the data of BRAM to obtain 42-bit data; Step 2: Using the triple modular redundancy mechanism, select bits [41:39] from the 42-bit data read from the BRAM to obtain the ECC identifier; Step 3: Determine whether the ECC content is added based on the ECC identifier, and decide whether to perform error correction on the [31:0] bits based on the judgment result to obtain the current 42-bit data; Step 4: Recalculate the ECC identifier of the [31:0] bits in the current 42-bit data to obtain an ECC calculation result, and replace the original ECC calculation result in the current 42-bit data with the recalculated ECC calculation result to obtain an updated 42-bit data; Step 5: Store the updated 42-bit data into the corresponding storage address, which is the next address of the address storing the updated 42-bit data after the last refresh.
[0019] In a specific embodiment of the present invention, Step 3 includes: Step 31, judging whether the ECC content has been added according to the ECC identifier to obtain a judgment result; Step 32: If the judgment result is that the ECC content has been added, the ECC error correction algorithm is used to correct the [31:0] bit position, and then the corrected data is used to replace the data of the [31:0] bit position before the error correction to obtain the current 42-bit data.
[0020] Step 33: If the judgment result is that the ECC content is not added, the 42-bit data read from the BRAM remains unchanged and the read 42-bit data is used as the current 42-bit data.
[0021] The present invention provides a reliability design method for FPGA BRAMs (FPGA BRAMs) to resist single-event upsets (SEEs), including: providing a port control module trans_a and a port control module trans_b, wherein port control module trans_a controls one of the two data read / write ports of the FPGA BRAM, and port control module trans_b controls the other; the data read / write port controlled by port control module trans_a is used for data reading and writing, and the data read / write port controlled by port control module trans_b serves as a refresh port for monitoring the read / write operations of the data read / write port and automatically refreshing data when the data read / write port is not reading or writing. The present invention is relatively simple to control and implement, occupies few resources, and can achieve highly reliable transmission of user data. It can also reduce the risk of firmware operation anomalies caused by SEEs in the FPGA BRAM, effectively improving the radiation resistance and reliability of solid-state storage devices.
[0022] It is worth noting that the terms "first" and "second" in this disclosure are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of this disclosure, "plurality" means two or more, unless otherwise specifically defined.
[0023] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.
Claims
1. A FPGA BRAM reliability design method for single event upset resistance, characterized in that: include: Set up port control module trans_a and port control module trans_b; Using the port control module trans_a to control one of the two data read and write ports of the FPGA BRAM, and using the port control module trans_b to control the other of the two data read and write ports of the FPGA BRAM; Among them, the data read and write port controlled by the port control module trans_a is used for data reading and writing, and the data read and write port controlled by the port control module trans_b is used as a refresh port for monitoring the read and write operations of the data read and write port and automatically refreshing data when the data read and write port is not reading or writing.
2. The FPGA BRAM reliability design method for single event upset resistance according to claim 1, characterized in that: When the data read and write port reads and writes data, the data width is 42 bits, expressed as [41:0]; Among them, the bits [31:0] are data, the bits [38:32] are ECC calculation results, and the bits [41:39] are ECC flags.
3. The FPGA BRAM reliability design method for single event upset resistance according to claim 1, characterized in that: The data read and write port is specifically used to perform read data operations and write data operations. The write data operation includes filling the 32-bit data to be written into 42 bits and writing the filled 42-bit data into the BRAM; the read operation includes transmitting the bit data [31:0] in the 42-bit data from the BRAM to the port control module trans_a.
4. The FPGA BRAM reliability design method for single event upset resistance according to claim 1, characterized in that: The refresh port is specifically used for: Monitoring the read and write operations of the data read and write port; When the data read / write port is not reading or writing, the following operations are performed to automatically refresh the data: Step 1: Read the data of BRAM to get 42-bit data; Step 2: Using the triple modular redundancy mechanism, select bits [41:39] from the 42-bit data read from the BRAM to obtain the ECC identifier; Step 3: Determine whether the ECC content is added based on the ECC identifier, and decide whether to perform error correction on the [31:0] bits based on the judgment result to obtain the current 42-bit data; Step 4: Recalculate the ECC calculation result of bits [31:0] in the current 42-bit data, and replace the original ECC calculation result in the current 42-bit data with the recalculated ECC calculation result to obtain updated 42-bit data; Step 5: Store the updated 42-bit data into the corresponding storage address, which is the next address of the address storing the updated 42-bit data after the last refresh.
5. The FPGA BRAM reliability design method for single event upset resistance according to claim 4, characterized in that: Step 3 includes: Step 31, judging whether the ECC content has been added according to the ECC identifier to obtain a judgment result; Step 32: If the result of the judgment is that the ECC content has been added, the ECC error correction algorithm is used to correct the [31:0] bit, and then the corrected data is used to replace the data of the [31:0] bit before the error correction to obtain the current 42-bit data; Step 33: If the judgment result is that the ECC content is not added, the 42-bit data read from the BRAM remains unchanged and the read 42-bit data is used as the current 42-bit data.
6. The FPGA BRAM reliability design method for single event upset resistance according to claim 5, characterized in that: Step 31 includes: Whether the ECC content has been added is determined based on the ECC identifier. If at least two bits of the ECC identifier are 0, it means that the ECC content has not been added. If at least two bits of the ECC identifier are 1, it means that the ECC content has been added.
7. A FPGA BRAM reliability design device for single event upset resistance, characterized in that: The device includes a port control module trans_a and a port control module trans_b; The port control module trans_a is used to control one of the two data read and write ports of the FPGA BRAM; The port control module trans_b is used to control the other of the two data read and write ports of the FPGA BRAM; Among them, the data read and write port controlled by the port control module trans_a is used for data reading and writing, and the data read and write port controlled by the port control module trans_b is used as a refresh port for monitoring the read and write operations of the data read and write port and automatically refreshing data when the data read and write port is not reading or writing.
8. The FPGA BRAM reliability device for resisting single event upset according to claim 4, characterized in that: The data read and write port is specifically used to perform read data operations and write data operations. The write data operation includes filling the 32-bit data to be written into 42 bits and writing the filled 42-bit data into the BRAM; the read operation includes transmitting the bit data [31:0] in the 42-bit data from the BRAM to the port control module trans_a.
9. The FPGA BRAM reliability design device for single event upset resistance according to claim 8, characterized in that: The refresh port is specifically used for: Monitoring the read and write operations of the data read and write port; When the data read / write port is not reading or writing, the following operations are performed to automatically refresh the data: Step 1: Read the data of BRAM to get 42-bit data; Step 2: Using the triple modular redundancy mechanism, select bits [41:39] from the 42-bit data read from the BRAM to obtain the ECC identifier; Step 3: Determine whether the ECC content is added based on the ECC identifier, and decide whether to perform error correction on the [0:31] bits based on the judgment result to obtain the current 42-bit data; Step 4: Recalculate the ECC calculation result of bits [31:0] in the current 42-bit data, and replace the original ECC calculation result in the current 42-bit data with the recalculated ECC calculation result to obtain updated 42-bit data; Step 5: Store the updated 42-bit data into the corresponding storage address, which is the next address of the address storing the updated 42-bit data after the last refresh.
10. The FPGA BRAM reliability design device for single event upset resistance according to claim 9, characterized in that: Step 3 includes: Step 31, judging whether the ECC content has been added according to the ECC identifier to obtain a judgment result; Step 32: If the result of the judgment is that the ECC content has been added, the ECC error correction algorithm is used to correct the [31:0] bit, and then the corrected data is used to replace the data of the [31:0] bit before the error correction to obtain the current 42-bit data; Step 33: If the judgment result is that the ECC content is not added, the 42-bit data read from the BRAM remains unchanged and the read 42-bit data is used as the current 42-bit data.