Audio data processing system

Abstract

The invention relates to an audio data processing system, and relates to the technical field of audio processing. The system comprises a first storage module used for storing latest-level to-be-processed data corresponding to each received to-be-processed audio data; the filter is connected with the first storage module and is used for carrying out audio sampling rate conversion processing on each level of to-be-processed data to obtain each level of sampling rate converted data corresponding to each level of to-be-processed audio data; the second storage module is respectively connected with the filter and the first storage module and is used for storing the data after sampling rate conversion at each level; the data transmission module is also used for transmitting the data after sampling rate conversion of each level to the first storage module as the Nth-level to-be-processed data corresponding to each piece of to-be-processed audio data; the sampling rate converted data of each (N-1) th-level to-be-processed data output by the filter is processed target audio data corresponding to each to-be-processed audio data; the system is beneficial to reducing the hardware overhead of audio sampling rate conversion.

Description

Technical Field

[0001] The present application relates to the field of audio processing technology, and in particular to an audio data processing system. Background Art

[0002] Audio sampling rate conversion is the process of converting an audio signal from one sampling rate to another. In related technologies, low-pass filtering and phase compensation are performed on upsampled audio signals before downsampling. This audio sampling rate conversion method requires high storage and computational resources, placing significant hardware overhead on the audio processing system. Summary of the Invention

[0003] Based on this, it is necessary to provide an audio data processing system that can reduce hardware overhead during the process of performing sampling rate conversion on audio data.

[0004] The present application provides an audio data processing system, comprising:

[0005] a first storage module, configured to store first-level data to be processed corresponding to each received audio data to be processed, and, upon receiving N-level data to be processed corresponding to any of the first-level data to be processed, update the storage to store the N-level data to be processed; N ≥ 2, and N is a positive integer;

[0006] a filter, electrically connected to the first storage module, configured to perform audio sampling rate conversion processing on at least each level of the audio data to be processed, from the first level of the data to be processed to the N-1 level of the data to be processed, and obtain sampling rate converted data of each level corresponding to each level of the audio data to be processed;

[0007] a second storage module, electrically connected to the filter and the first storage module, respectively, for storing the sampling rate converted data at each level corresponding to each of the audio data to be processed; and further for transmitting the sampling rate converted data at each level corresponding to each of the audio data to be processed to the first storage module as the Nth level of data to be processed corresponding to each of the audio data to be processed;

[0008] The sampling rate converted data of the N-1th level of data to be processed corresponding to each of the audio data to be processed output by the filter is the processed target audio data corresponding to each of the audio data to be processed.

[0009] The audio data processing system provided by the present application involves at least a first storage module, a filter and a second storage module. The first storage module, the filter and the second storage module are electrically connected to each other. The first storage module in the system can be used to store the first-level data to be processed corresponding to each received audio data to be processed, and when the N-level data to be processed corresponding to any first-level data to be processed is received, it is updated to store the N-level data to be processed; the filter in the system is used to perform audio sampling rate conversion processing on at least the first-level data to be processed to the N-1-level data to be processed corresponding to each audio data to be processed, and obtain the sampling rate converted data of each level corresponding to each level of audio data to be processed; the second storage module can be used to store the sampling rate converted data of each level corresponding to each audio data to be processed; and is also used to convert the sampling rate converted data of each level corresponding to each audio data to be processed The data is transmitted to the first storage module as the Nth level of data to be processed corresponding to each audio data to be processed; it can be seen that the filter in the audio data processing system provided by the present application can obtain the processed target audio data corresponding to the audio data to be processed by performing multi-level audio processing operations on each audio data to be processed. The first storage module and the second storage module are set to store different data or different types of data in the processing stage of the audio data, respectively, and a filter is used to realize sequential polling processing of the multi-level data corresponding to the audio data to be processed, which is beneficial to reducing the number of devices required in the audio data processing system for converting the sampling rate of the audio data, that is, it is beneficial to reduce the hardware resource consumption of the audio data processing system, especially greatly reducing the number of required filters, which is beneficial to reducing the electrical structure complexity of the audio data processing system, and also beneficial to reducing the preparation cost of the audio data processing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 This is a schematic diagram of the architecture of the audio data processing system in the embodiment provided in this application;

[0012] Figure 2 This is another schematic diagram of the architecture of the audio data processing system in the embodiment provided by this application;

[0013] Figure 3This is another schematic diagram of the architecture of the audio data processing system in the embodiments provided in this application;

[0014] Figure 4 This is another schematic diagram of the architecture of the audio data processing system in the embodiment provided in this application;

[0015] Figure 5 A parameter design diagram of a filter in the embodiment provided in this application;

[0016] Figure 6 A schematic diagram of a process flow of an audio data processing system in an embodiment provided in this application;

[0017] Figure 7 This is a schematic diagram of the operation logic of the audio data processing system in the embodiment provided by this application. DETAILED DESCRIPTION

[0018] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0020] It will be understood that the terms "first," "second," etc. used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.

[0021] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0022] It is understood that “at least one” refers to one or more, “a plurality” refers to two or more, and “at least a portion of an element” refers to a portion or all of an element.

[0023] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0024] As described in the background, the methods for performing audio sampling rate conversion provided in related art require high storage and computational complexity, resulting in high hardware overhead for the audio processing system. Therefore, it is necessary to provide an audio data processing system that can reduce hardware overhead during the audio data sampling rate conversion process.

[0025] Please refer to Figure 1 , the present application provides an audio data processing system, comprising:

[0026] The first storage module 11 is configured to store the first level of data to be processed corresponding to each received audio data to be processed, and update the storage to the Nth level of data to be processed when the Nth level of data to be processed corresponding to any first level of data to be processed is received; N ≥ 2, and N is a positive integer;

[0027] The filter 12 is electrically connected to the first storage module 11 and is used to perform audio sampling rate conversion on at least each level of the to-be-processed data from the first level to the N-1 level of the to-be-processed data corresponding to each level of the to-be-processed audio data, and obtain the sampling rate converted data corresponding to each level of the to-be-processed audio data;

[0028] The second storage module 13 is electrically connected to the filter 12 and the first storage module 11, respectively, and is used to store the sampling rate converted data at each level corresponding to each audio data to be processed; and is also used to transmit the sampling rate converted data at each level corresponding to each audio data to be processed to the first storage module 11 as the Nth level of data to be processed corresponding to each audio data to be processed;

[0029] The sampling rate converted data of the N-1th level of the audio data to be processed corresponding to each of the audio data to be processed output by the filter 12 is the processed target audio data corresponding to each of the audio data to be processed.

[0030] Specifically, the audio data processing system 100 provided in the present application includes at least a first storage module 11, a filter 12 and a second storage module 13, wherein the first storage module 11 and the filter 12 may be electrically connected, and the first storage module 11 may be used to transmit the data stored in the first storage module 11 to the filter 12; the filter 12 and the second storage module 13 may also be electrically connected, and the filter 12 may be used to transmit the result obtained after processing the data to be processed (data after sampling rate conversion) to the second storage module 13; in addition, the second storage module 13 may also transmit the data stored in the second storage module 13 to the filter 12; the second storage module 13 may also be used to transmit the data stored in the second storage module 13 to the first storage module 11.

[0031] Exemplarily, the first storage module 11 provided in the present application can be used to store the received audio data to be processed, and the first to be received and stored is the first level of the audio data to be processed; after the first level of the audio data to be processed is transmitted to the filter 12 for the first time for audio sampling rate conversion processing, the first level of the data to be processed output by the filter 12 will be obtained. The first level of sampling rate converted data corresponding to the first level will be obtained; then, the filter 12 will transfer the first level of sampling rate converted data to the second storage module 13, and the second storage module 13 will store the first level of sampling rate converted data and simultaneously transmit the first level of sampling rate converted data to the first storage module 11. When the first storage module 11 receives the first-level sampling rate converted data, it will store the first-level sampling rate converted data as the second-level data to be processed, and before storing the second-level data to be processed, it will first delete the first-level data to be processed corresponding to the second-level data to be processed, so that the first storage module 11 always only stores a certain level of data to be processed corresponding to one audio data to be processed; further, the second-level data to be processed can be transmitted to the filter 12 through the first storage module 11, or the first-level sampling rate converted data can be transmitted to the filter 12 as the second-level data to be processed through the second storage module 13, so that the filter 12 Further, audio sampling rate conversion processing is performed on the second-level data to be processed corresponding to the first-level data to be processed of the audio data being processed; after the filter 12 processes the second-level data to be processed, the second-level sampling rate converted data corresponding to the second-level data to be processed output by the filter 12 is obtained; then, the filter 12 transmits the second-level sampling rate converted data to the second storage module 13, the second storage module 13 stores the second-level sampling rate converted data, and at the same time transmits the second-level sampling rate converted data to the first storage module 11. When the first storage module 11 receives the second-level sampling rate converted data, it uses the second-level sampling rate converted data as The third-level data to be processed is stored, and before the third-level data to be processed is stored, the second-level data to be processed corresponding to the third-level data to be processed is deleted, so that the first storage module 11 always only stores a certain level of data to be processed corresponding to one audio data to be processed; further, the third-level data to be processed can be transmitted to the filter 12 through the first storage module 11, or the second-level sampling rate converted data can be transmitted to the filter 12 as the third-level data to be processed through the second storage module 13, so that the filter 12 further performs audio sampling rate conversion processing on the third-level data to be processed corresponding to the second-level data to be processed of the audio data being processed.

[0032] By cooperating with the first storage module 11, the filter 12 and the second storage module 13, and referring to the above-mentioned cyclic processing method for the first to third levels of the audio data to be processed, multi-level filtering processing of the data to be processed at each level can be achieved.

[0033] Among them, the above-mentioned "each audio data to be processed" may refer to multiple different audio data to be processed. The current sampling rate values ​​of each audio data to be processed may be the same, or may be set to different values ​​of the current sampling rate of each audio data to be processed. This application does not make any specific restrictions on this.

[0034] An exemplary embodiment is provided in which, when a certain audio data to be processed only requires two levels of processing by the filter 12 to obtain the corresponding target audio data, referring to the above embodiment, the data after the second level sampling rate conversion, or the data after the sampling rate conversion of the (3-1) level of the data to be processed, is the processed target audio data corresponding to the audio data to be processed.

[0035] In summary, the filter 12 in the audio data processing system 100 provided in the present application can obtain processed target audio data corresponding to the audio data to be processed by performing multi-level audio processing operations on each audio data to be processed. By setting a first storage module 11 and a second storage module 13, different data or different types of data in the processing stage of the audio data are respectively stored, and a filter 12 is used to realize sequential polling processing of multi-level data corresponding to the audio data to be processed, which is beneficial to reducing the number of devices required in the audio data processing system 100 for converting the sampling rate of the audio data, that is, it is beneficial to reduce the hardware resource consumption of the audio data processing system 100, especially greatly reducing the number of required filters 12, which is beneficial to reducing the electrical structure complexity of the audio data processing system 100, and also beneficial to reducing the preparation cost of the audio data processing system 100.

[0036] Please refer to Figure 2 In an exemplary embodiment, the audio data processing system 100 provided in the present application further includes: a third storage module 17, electrically connected to the filter 12, for storing the number of taps of each level of filter 12 adapted to perform audio sampling rate conversion processing on each level of data to be processed.

[0037] Specifically, the audio data processing system 100 of the present application can be set to further include a third storage module 17 for providing the number of filter taps required for the operation of each level of filter 12. The third storage module 17 can store the number of filter taps corresponding to multiple filters 12; the third storage module 17 can be set to be directly electrically connected to the filter 12, and be used to provide it with an adapted number of taps (filter coefficients) according to the working requirements of the filter 12.

[0038] It can be seen that the present application can reduce the storage capacity requirements of the first storage module 11 and the second storage module 13 by separately setting up the third storage module 17, and can also avoid the high-frequency use of a storage module when storing multiple types of data in one storage module, thereby avoiding the problem of blockage during data storage and retrieval, and can also avoid the problem of cross-interference of data, which is beneficial to ensuring the stability and accuracy of data transmission in the audio data processing system 100.

[0039] Furthermore, the filter 12 provided in the present application can realize the multi-stage processing requirements for a to-be-processed audio data. For example, if a to-be-processed audio data needs to undergo 5-stage processing, there is no need to use 5 filters 12. Instead, only one filter 12 is needed to complete the 5-stage processing of the to-be-processed audio data, and the target audio data of the to-be-processed audio data can be obtained.

[0040] In addition, the filter 12 provided in the present application can perform multi-level processing on the relevant audio data to be processed based on the sequential requirements of the multi-level processing. During each level of processing, the third storage module 17 can also provide the filter 12 with adaptive filter coefficients, thereby ensuring that the audio data processing system 100 provided in the present application accurately processes the audio data to be processed, and realizes the processing of audio data using fewer components and modules, which is also beneficial to reducing the circuit complexity and preparation cost of the audio data processing system 100.

[0041] In an exemplary embodiment, the filter 12 includes a multiplier and an accumulator; wherein the output end of the multiplier is electrically connected to the input end of the accumulator, the input end of the multiplier is used to receive the data to be processed at each level, and the output end of the accumulator is used to output the sampling rate converted data of each level corresponding to the audio data to be processed at each level.

[0042] Specifically, the filter 12 may include at least an electrically connected multiplier and an accumulator, and the output end of the multiplier may be optionally set to be electrically connected to the input end of the accumulator. The input end of the multiplier is used to receive audio data to be processed at each level (level 1 to level N). After the audio data to be processed at each level is processed by the multiplier and the accumulator respectively and sequentially, the sampling rate converted data of each level corresponding to the audio data to be processed at each level can be output. Among them, the sampling rate converted data of the Nth level corresponding to the audio data to be processed output by the filter 12, or the sampling rate converted data of the N-1th level to be processed, is the processed target audio data corresponding to the audio data to be processed.

[0043] In an exemplary embodiment, please refer to Figure 2-Figure 4 The audio data processing system 100 provided in this application further includes:

[0044] The data receiving module 14 is electrically connected to the first storage module 11 and the filter 12, and includes a plurality of data receiving channels, each of which is used to receive different audio data to be processed and transmit them to the first storage module 11 and the filter 12 respectively;

[0045] The data output module 15 is electrically connected to the filter 12 and includes multiple data output channels; it is used to receive the sampling rate converted data of the N-1th level of data to be processed corresponding to each audio data to be processed output by the filter 12, and output the sampling rate converted data of the N-1th level of data to be processed corresponding to each audio data to be processed through each data output channel as the processed target audio data corresponding to each audio data to be processed.

[0046] Specifically, the data receiving channel included in the data receiving module 14 can be as follows: Figure 4 As shown in FIG. 1 , the data output channels included in the data output module 15 can be as follows: Figure 4 The eight data receiving channels shown in FIG. 1 and FIG. 2 can be used to simultaneously input eight different audio data to be processed. Similarly, the eight data output channels shown in FIG. 2 can be used to simultaneously output target audio data corresponding to the eight different audio data to be processed.

[0047] Among them, when the data receiving module 14 receives each audio data to be processed through the multiple data receiving channels it includes, it will transmit each audio data to be processed to the first storage module 11 and the filter 12 respectively, so that each audio data to be processed can be processed by the first storage module 11, and at the same time, each audio data to be processed (first-level data to be processed) can be subjected to first-level filtering processing through the filter 12.

[0048] Among them, the data output module 15 is used to obtain the sampling rate converted data of the N-1th level of audio data to be processed (Nth level sampling rate converted data) corresponding to each audio data to be processed through the multiple data output channels it includes, that is, to obtain the target audio data corresponding to each audio data to be processed, and then output the target audio data to the outside through each data output channel.

[0049] In an exemplary embodiment, the audio data processing system 100 provided in the present application further includes: a filter parameter control module 16, which is electrically connected to the data receiving module 14 and the filter 12 respectively; and is used to determine the conversion factor sequence of each level of filter 12 suitable for performing audio sampling rate conversion processing on each level of data to be processed based on the current sampling rate and target sampling rate of each level of audio data to be processed; and is used to determine the filter type parameter of the filter 12 based on at least one of the audio characteristics of the audio data to be processed, the signal index characteristics corresponding to the target sampling rate, and the audio processing resource characteristics of the local end; wherein the conversion factor sequence includes at least one conversion factor, and the conversion factor is used to characterize the change in data volume after the filter 12 performs audio sampling rate conversion processing on the audio data to be processed.

[0050] Specifically, if Figure 3 As shown, the filter parameter control module 16 can be optionally electrically connected between the data receiving module 14 and the filter 12. In addition, the filter parameter control module 16 can also be optionally integrated into the interior of the filter 12 as a unit inside the filter 12. The filter parameter control module 16 can be configured to receive each audio data to be processed (first-level audio data to be processed) to determine the number of levels of filters 12 required and the conversion factors of each level of filters 12 based on the current sampling rate and target sampling rate of each audio data to be processed, so as to obtain a conversion factor sequence corresponding to each level of filters 12 adapted to process each audio data to be processed; further, the filter parameter control module 16 can also be configured to determine the filter type of each level of filters 12 based on at least one of the audio characteristics of the audio data to be processed, the signal indicator characteristics corresponding to the target sampling rate, and the audio processing resource characteristics of the local end.

[0051] The conversion factor is used to represent the ratio of the amount of the to-be-processed audio data before being processed and the amount of the to-be-processed audio data after being processed by the filter 12 .

[0052] In an exemplary embodiment, please combine Figure 3 Reference Figure 4 The first storage module 11 includes data storage channels with the same number as the data receiving channels; each data storage channel is used to store the first-level data to be processed corresponding to the audio data to be processed received by each data receiving channel, and when the N-level data to be processed corresponding to any first-level data to be processed is received, it is updated to store the N-level data to be processed.

[0053] Specifically, the data storage channel is as follows Figure 4 As shown in ch_0, ch_1, ..., the number of data storage channels included in the first storage module 11 can be set to be the same as the number of data receiving channels. For example, if the number of data receiving channels is 8, the number of data storage channels can also be set to 8.

[0054] Each data storage channel can be optionally set to store the first-level data to be processed corresponding to the audio data to be processed received by each data receiving channel, and when the second-level data to be processed corresponding to the first-level data to be processed is subsequently received, the originally stored first-level data to be processed is deleted and updated to store the second-level data to be processed corresponding to the deleted first-level data to be processed; when the third-level data to be processed corresponding to the second-level data to be processed is subsequently received, the originally stored second-level data to be processed is deleted and updated to store the third-level data to be processed corresponding to the deleted second-level data to be processed.

[0055] That is, each data storage channel included in the first storage module 11 provided in the present application always stores only one piece of data.

[0056] like Figure 4 As shown, DHIS RAM is used to represent the aforementioned first storage module 11 , DOUT RAM is used to represent the aforementioned second storage module 13 , MUL ACC is used to represent the aforementioned filter 12 , and COEF RAM is used to represent the aforementioned third storage module 17 .

[0057] Please continue to combine Figure 3 Reference Figure 4 In an exemplary embodiment, the number of data receiving channels and data output channels is the same; the data output channel in a matched set of data receiving channels and data output channels is used to output target audio data corresponding to the audio data to be processed received by the matched data receiving channel.

[0058] Specifically, the data receiving channel and the data output channel can be set to a one-to-one matching correspondence. For example, when pcmfifo_0 and fltfifo_0 are set to match, pcmfifo_0 is used to receive the first audio data to be processed, and fltfifo_0 is used to receive the first target audio data corresponding to the first audio to be processed, and output the first target audio data to the outside of the audio data processing system 100.

[0059] Please continue to combine Figure 3 Reference Figure 4 In an exemplary embodiment, the number of data receiving channels and data output channels is M, M≥8, and M is a positive integer; the multiple data receiving channels and the multiple data output channels transmit data based on the first-in-first-out principle.

[0060] Specifically, on the same basis, in addition to setting the relevant number of data receiving channels and data output channels to 8 as mentioned above, the data receiving channels and data output channels can also be set to have a larger number based on demand, so that the audio data processing system 100 provided in this application can simultaneously receive a larger number of audio data to be processed.

[0061] It should be added that setting the number of data receiving channels and data output channels to at least 8 is only an optional implementation method provided by this application, but this application does not limit this. The number of data receiving channels and data output channels can be selected based on needs.

[0062] Among them, the multiple data receiving channels and multiple data output channels provided in this application can choose to transmit data based on the first-in-first-out principle.

[0063] Please continue to combine Figure 3 Reference Figure 4 In an exemplary embodiment, the audio data processing system 100 provided by the present application further includes:

[0064] a first multiplexing unit, wherein an input end of the first multiplexing unit is electrically connected to an output end of the data receiving module 14, and an output end of the first multiplexing unit is electrically connected to an input end of the first storage module 11 and an input end of the filter 12;

[0065] The second multiplexing unit has an input end electrically connected to the output end of the filter 12 , and an output end of the second multiplexing unit electrically connected to the input end of the data output module 15 .

[0066] Specifically, the first multiplexing unit may be as follows Figure 4 The output of MUX1, the second multiplexing unit can be as follows Figure 4wherein the first multiplexing unit is used to control which of the multiple audio data to be processed received by the data receiving module 14 is transmitted to the first storage module 11 and the filter 12 at the same time. The second multiplexing unit is used to transmit the target audio data of the audio data to be processed calculated by the filter 12 to the corresponding audio output channel.

[0067] Please continue to combine Figure 3 Reference Figure 4 In an exemplary embodiment, the audio data processing system 100 provided by the present application further includes:

[0068] a third multiplexing unit, wherein an input end of the third multiplexing unit is electrically connected to an output end of the first multiplexing unit, an output end of the first storage module 11, and an output end of the second storage module 13; and an output end of the third multiplexing unit is electrically connected to an input end of the filter 12;

[0069] The fourth multiplexing unit has an input end electrically connected to the output end of the filter 12 , and an output end of the fourth multiplexing unit electrically connected to the input end of the second storage module 13 and the input end of the second multiplexing unit respectively.

[0070] Specifically, the third multiplexing unit may be as follows Figure 4 The output of MUX3, the fourth multiplexing unit can be as follows Figure 4 The third multiplexing unit is used to control, at the same time, only one of the first multiplexing unit, the first storage module 11 and the second storage module 13 to transmit data to the filter 12; the fourth multiplexing unit is used to output the output result data of the filter 12 to the second storage module 13 and the second multiplexing unit respectively when necessary, or to select, at the same time, to output the output result data of the filter 12 to the second storage module 13 or the second multiplexing unit.

[0071] In summary, the first multiplexing unit, the second multiplexing unit, the third multiplexing unit and the fourth multiplexing unit provided in the present application are all used for performing multiplexing.

[0072] Please combine Figure 3 and Figure 4 The audio data processing system provided in this application can be used to perform sampling rate conversion on up to eight channels of audio data in PCM (Pulse Code Modulation) format. Before performing the sampling rate conversion, the appropriate data width of the audio data can be determined to maintain good data processing accuracy and reduce memory costs.

[0073] In one embodiment, after the audio data is sampled and converted, the SNR of the target audio is greater than 84dB (decibel). SNR is the full spelling of Signal to Noise Ratio. Figure 5 Correspondingly, the width of the filter tap coefficients of the multi-rate filter (such as the FIR filter) used to process audio data can be set to 21 bits; the width of the historical data is 18 bits; the width of the temporary result is 18 bits; the multiplication is 21 bits * 18 bits, and the output is 39 bits. Among them, "output 39 bits" is to ensure that the output result does not overflow. Among them, the FIR (Finite Impulse Response) filter: a finite-length unit impulse response filter, also known as a non-recursive filter, is the most basic component in the digital signal processing system. It can have a strict linear phase-frequency characteristic while ensuring arbitrary amplitude-frequency characteristics. At the same time, its unit sampling response is finite length, so the filter is a stable system.

[0074] Among them, the values ​​of the tap coefficients of the filter are predetermined; the historical data can be the output result of any filter group (which can be composed of multiple cascaded filters) after sampling rate conversion; the temporary data can be the result of the output of any filter, for example, it can be the result of the output of any filter in multiple cascaded filters.

[0075] like Figure 5 In the illustrated embodiment, when two-level interpolation is required, if both the results of the first-level interpolation and the second-level interpolation correspond to 39 bits, the result value after the two-level interpolation can also be retained as 39 bits of data. To reduce the amount of data in the result value, the present application provides an optional implementation method in which the lower 20 bits and the second-highest bit (the 38th bit) of the result value are discarded to obtain a final 18-bit data. The reason for discarding the lower 20 bits and the second-highest bit of the accumulated 39-bit data to ultimately obtain 18-bit audio data is dynamic range matching and quantization noise control.

[0076] Specifically, during the sampling rate conversion filtering operation, the accumulator outputs 39 bits of data (21-bit coefficients x 18-bit data), but the final output must meet the 18-bit width and SNR requirements of >84dB. The operation flow is as follows: the 39-bit accumulation result is: bit 38 (MSB, Most Significant Bit), bit 37, bit 36, ..., bit 1, bit 0 (LSB, Least Significant Bit); the lower 20 bits (bits 0-19) are discarded, and bits 38-20 (a total of 19 bits) are retained. Furthermore, the next highest bit (bit 37) is discarded, and bits 38 and bits 36-20 (a total of 18 bits) are retained.

[0077] The purpose of using a 39-bit accumulator is to prevent overflow, as the filter gain may be greater than 1. The purpose of using an 18-bit output is to match the input data range of downstream modules. Discarding the lower 20 bits eliminates catastrophic noise in the audio data, effectively eliminating fine quantization noise and reducing the SNR impact by a factor of 256. Discarding the second-highest bit can halve the signal power and reduce the SNR impact by at least 6dB. Discarding the second-highest bit (bit 37) is equivalent to dividing by 2, compressing the dynamic range, preventing 18-bit overflow, and facilitating gain calibration. Furthermore, while discarding the second-highest bit halves the signal power, this is offset by the noise reduction achieved by discarding the lower bits. Using an 18-bit output buffer also reduces the cost of associated storage hardware.

[0078] In summary, the embodiment provided by the present application above can retain high-bit information while suppressing noise by discarding the lower 20 bits; and can compensate for the filter gain and avoid saturation by discarding the second-highest bits.

[0079] After the data input end (data input module) of the 8 channels receives the PCM audio data, it is simultaneously transmitted to MUX1 for fractional multiplexing data processing, and then the selected audio data is output to DHIS RAM for storage, and at the same time transmitted to MUL ACC through MUX3 for further processing, and then the output processing result of MUL ACC is transmitted to DOUT RAM through MUX4 for storage. DOUT RAM simultaneously transmits the stored data to DHIS RAM. When DHIS RAM receives new data, it will delete the corresponding old data. Subsequently, the data to be processed by the next level of MUL ACC can be transmitted to it through DHIS RAM or DOUT RAM. Finally, MUL ACC will transmit the target audio data corresponding to each audio data to be processed to the audio output end (audio output module) through MUX4 and MUX2, that is, MUX4 can output the result to the data output end of the 8 channels through MUX2; the COEF RAM is used to store filter coefficients.

[0080] The audio data processing system provided in this application has the following construction requirements (multi-channel parallel processing and data width configuration) and can achieve the corresponding technical effects.

[0081] Multi-channel parallel processing: Channel independence allows each channel to independently perform sample rate conversion (interpolation / decimation) to avoid data crosstalk. Resource sharing is also enabled. All channels share the same set of 21-bit polyphase filter coefficients, reducing ROM (read-only memory) usage. The computation unit utilizes time-division multiplexing, with all eight channels sharing the same set of multiply-accumulate (MAC) units. Pipeline scheduling improves throughput.

[0082] Data width configuration: Coefficient bit width is 21 bits to ensure the accuracy of the filter frequency response (passband ripple ≤ 0.01dB, stopband attenuation ≥ 100dB). Historical data is 18 bits to store the previous input samples (such as the first 7 samples must be retained for three-level interpolation). Temporary results are 18 bits for storing intermediate values ​​of multi-level filtering. The truncation strategy uses saturation rounding to control quantization noise. The multiplier of the operation unit is 21 bits × 18 bits, retaining full precision. The accumulator of the operation unit is 39 bits and then truncated to 18 bits, with a dynamic range of ±2 17 , to avoid overflow.

[0083] The audio data processing system provided in this application has the following key performance optimization strategies, including SNR guarantee and RAM cost optimization.

[0084] SNR guarantee (>84dB): quantization noise control; coefficient quantization, the noise power introduced by the quantization error of the 21-bit coefficient is 2 42 , which can be ignored. The intermediate result is truncated, and the 18-bit truncated noise power is 2 36 The total SNR is calculated using a multi-level noise superposition formula. Anti-aliasing design uses strict filtering before decimation to ensure that the signal bandwidth is limited to the target Nyquist frequency (24kHz) to avoid aliasing noise.

[0085] RAM cost optimization: For historical data storage, the number of samples required for each channel is determined by the number of filter taps (e.g., three-level interpolation requires 7+5+3=15 samples, or 8+6+4=18 samples). For 8 channels, the total memory capacity is 8×15×18 bits = 2160 bits, approximately 0.26 KB. Intermediate result reuse: Intermediate results from multi-level interpolation (e.g., y(n)) are pipelined without additional storage, reducing buffering requirements.

[0086] Here is an example of audio sampling rate conversion:

[0087] First stage: 3x interpolation (phase = 3, taps = 8).

[0088] Input: original signal x(n), sampling rate Fs.

[0089] Output: interpolated signal y(n), sampling rate increased to 3Fs.

[0090] The implementation formula is as follows:

[0091] ;

[0092] ;

[0093] .

[0094] Key points include:

[0095] Each input sample generates 3 output samples (corresponding to an interpolation factor of 3).

[0096] An 8-tap filter is used, with different phases (0, 1, 2) corresponding to different coefficient groups hk_0, hk_1, hk_2, where the k value ranges from 0 to 7 and is used to suppress the image frequency.

[0097] Historical data storage: The first seven input samples (x(n−1) to x(n−7)) must be retained for calculation.

[0098] The audio data processing system provided in this application has the following operation unit implementation method.

[0099] Multiplier-Accumulator (MAC) Design: The architecture utilizes a single-cycle 21×18-bit multiplier and a 39-bit accumulator, supporting 8-channel time-division multiplexing. Each channel is allocated a fixed time slice (for example, processing a single tap calculation on one channel per clock cycle). The total latency of the 8-channel three-stage interpolation is 8×(8+6+4)=144 cycles (can be pipelined to 18 cycles).

[0100] Truncation and rounding strategy: Truncation position: retain the upper 18 bits of the accumulator output (discarding the lower 21 bits), combined with saturation to prevent overflow. Rounding method: add a rounding constant 2 to the power of 20 before truncation to reduce mean error.

[0101] For the audio data processing system provided in this application, an exemplary embodiment is provided as follows:

[0102] Input: 8-channel PCM data, sampling rate 11.025kHz, output: 48kHz;

[0103] Interpolation stage:

[0104] First stage (3x interpolation): 11.025kHz input per channel, 8-tap polyphase filter (21-bit coefficients), 33.075kHz output.

[0105] Second stage (2x interpolation): input 33.075kHz, 6-tap filter, output 66.15kHz.

[0106] Level 3 (4x interpolation): Input 66.15kHz, 4-tap filter, output 264.6kHz.

[0107] Extraction phase:

[0108] After anti-aliasing filtering, the signal is decimated by a factor of 5.5125 (264.6kHz converted to 48kHz) and merged into the final filtering operation.

[0109] As can be seen, by utilizing the Multi-Channel Shared Computing Unit (MUL ACC) and optimizing data width and truncation strategies, the system significantly reduces RAM and computing resource consumption while maintaining an SNR > 84dB. Core design features include: multi-level interpolation decomposition to balance computational complexity and accuracy; time-division multiplexing of the MAC to efficiently support 8-channel parallel processing; and dynamic range management to control quantization noise through 18-bit truncation and rounding.

[0110] In the audio data processing system provided by this application, the memory used includes the following Figures 1-4 The Coef RAM shown is used to store FIR coefficients; the DHIS RAM is used to store historical data for the 8-channel multi-filter steps; and the Dout RAM is used to save temporary results. These three types of memory (storage modules) are used to efficiently manage data and coefficients. The specific configuration is shown in Table 1 below.

[0111] Table 1

[0112]

[0113] The process of design rationality verification is as follows:

[0114] Coef RAM: Assuming a three-stage interpolation filter requires 8, 6, and 4 taps, respectively, there are 18 coefficient sets in total. A capacity of 256 entries supports multiple filter configurations (such as multi-channel sharing or adapting to different input sampling rates), and the redundant design allows for flexibility.

[0115] DHIS RAM: 8 channels × 128 historical data records per channel (1024 / 8), meeting multi-level filtering requirements (e.g., three-level interpolation requires storing the first 7+5+3=15 samples).

[0116] Dout RAM: 256 entries support caching of multi-level intermediate results to avoid pipeline blocking.

[0117] This application provides Figures 1-4The audio data processing system shown has an 8-channel synchronous FIFO input and a corresponding synchronous FIFO output; the main calculation process is multiplication and accumulation.

[0118] Data flow and synchronization control, involving input / output synchronization FIFO:

[0119] Function: 8-channel independent FIFO (fitffo_0 to fitffo_7) to ensure data continuity and real-time performance.

[0120] Depth requirement: Assuming 48 kHz output per channel, the input FIFO depth must cover the worst-case delay (such as the pipeline cycle of multi-stage filtering).

[0121] Bit width: Consistent with PCM data bit width (e.g., 16 / 24 bits). Not specified but must match the external interface.

[0122] Data flow and synchronization control also involves multiplexers (MUX):

[0123] Function: Time-division multiplexing of 8-channel data to the shared computing unit (MAC) to reduce hardware resource consumption.

[0124] Scheduling strategy: poll by channel, process one tap calculation of one channel per cycle, 8 channels × 18 taps = 144 cycles (can be pipelined).

[0125] Computational unit design, involving multiplication and accumulation units (MAC):

[0126] Bit width: 21-bit coefficient × 18-bit historical data; 39-bit product, accumulator bit width 39 bits (overflow prevention).

[0127] Truncation strategy: keep the high 18 bits of the accumulated result, combined with rounding (+2 20 ) Reduce quantization error and ensure SNR>84dB.

[0128] Throughput: A single MAC supports 8 channels of real-time processing (48 kHz × 8 = 384 kHz). The required clock frequency is ≥ 384 kHz × the number of taps (for example, 18 taps converts to 6.912 MHz).

[0129] The computational unit design also involves the implementation of polyphase filtering, where three-level interpolation examples include:

[0130] First stage: 3x interpolation, 8 taps, generating 3 phase outputs.

[0131] Second stage: 2x interpolation, 6 taps, generates 2 phase outputs.

[0132] The third stage: 4 times interpolation, 4 taps, generates 4 phase outputs.

[0133] Total interpolation factor: 3×2×4=24, supporting input sampling rate conversion from 2kHz to 48kHz (if higher rates are required, the number of stages must be expanded).

[0134] The key performance indicators of the audio data processing system provided in this application are shown in Table 2 below.

[0135] Table 2

[0136]

[0137] The audio data processing system provided in this application achieves real-time sampling rate conversion (to 48kHz) for 8-channel PCM data through multi-stage interpolation filtering, shared computing units, and efficient memory management. Key design features include: memory hierarchy: Coef RAM stores coefficients, DHIS RAM manages historical data, and Dout RAM caches intermediate results. Time-division multiplexing MAC: A single computing unit services 8 channels, balancing resources and performance. Synchronous FIFO: Ensures stable multi-channel data flow and prevents overflow.

[0138] Please refer to Figure 6 In the audio data processing system provided by this application, a state machine controls the sampling rate conversion process of 8-channel PCM data, and the functions of each state can be shown in Table 3 below.

[0139] Table 3

[0140]

[0141] Please refer to Figure 6 As shown in Table 3 above, the main process (single channel) in the state transition logic involves the following transition logic:

[0142] (1) S_IDLE to S_RDPCM:

[0143] Trigger condition: Input FIFO is not empty (pemffio_empty=0).

[0144] Action: Read the PCM data of the current channel.

[0145] (2) S_RDPCM to S_DHIS conversion:

[0146] Trigger condition: Read complete (status code 01 to 11).

[0147] Action: Store the data into DHIS RAM and update the history queue.

[0148] (3) The branch conditions for S_DHIS to S_RDDIN / S_MUL include:

[0149] Direct calculation (bypass): If no intermediate data is required, jump to S_MUL.

[0150] Intermediate data required: Jump to S_RDDIN to read Dout RAM data.

[0151] (4) S_RDDIN to S_MUL conversion:

[0152] Trigger condition: Intermediate data loading is completed (status code 21 to 02).

[0153] Action: Starts a multiply-accumulate calculation.

[0154] (5) S_MUL to S_SAVE conversion:

[0155] Trigger condition: Multiplication and accumulation completed (Imul_acc_finish=1).

[0156] Action: Save the result to Dout RAM or output FIFO.

[0157] (6) Trigger conditions for S_SAVE transition to S_IDLE / Next Channel:

[0158] If the output FIFO is full (outffio_full=1), it returns to S_IDLE and waits.

[0159] Otherwise, switch to the next channel (next_channel).

[0160] Polling mechanism for multi-channel scheduling: 8 channels are processed in a fixed order (such as ch_0 → ch_1 → ... → ch_7).

[0161] Switching timing of multi-channel scheduling: After S_SAVE is completed, the channel index is incremented through the next_channel signal and S_RDPCM is returned to process the next channel.

[0162] Obviously, the process processing of the audio data processing system provided by this application involves timing optimization, storage management and exception handling, among which:

[0163] (1) Timing optimization (S_MUL state):

[0164] Data registration: The input and output of the multiplier-accumulator (MAC) are inserted into registers to ensure that the critical path delay is controllable.

[0165] Input registers: store coefficients (Coef RAM) and historical data (DHIS RAM).

[0166] Output register: temporarily stores the accumulated results to prevent combinational logic delays from affecting the clock frequency.

[0167] Pipeline design: Multiplication and accumulation operations are divided into two stages to improve throughput.

[0168] (2) Storage management:

[0169] DHIS RAM: Each channel has an independent storage area to prevent data interference between channels.

[0170] Update strategy: In the S_DHIS state, new data overwrites the oldest historical sample (FIFO queue).

[0171] Dout RAM: Caches the intermediate results of multi-stage filtering (such as y(n)), partitioned by channel and step.

[0172] (3) Exception handling:

[0173] Input FIFO empty: Pause current channel processing (return S_IDLE) until data is ready.

[0174] Output FIFO full: Pause result writing and trigger flow control signal (such as notifying upstream to slow down).

[0175] The relevant performance and resource verification can be shown in Table 4 below.

[0176] Table 4

[0177]

[0178] In summary, the audio data processing system provided in this application utilizes a state machine that implements real-time sampling rate conversion for 8-channel PCM data through refined state partitioning and multi-channel round-robin scheduling. Key design advantages include: Low-latency processing: Pipelining of multiplication-accumulation operations and support for high-frequency clocks; Resource efficiency: Sharing of MAC units and storage interfaces reduces hardware overhead; and Robustness: An exception handling mechanism ensures data integrity.

[0179] Please refer to further Figure 6 The relevant pipeline design is shown in Table 5 below.

[0180] Table 5

[0181]

[0182] Based on Table 5 above, the design of a multi-channel sampling rate conversion pipeline is analyzed, including an overview of the pipeline process, detailed pipeline stage analysis, and performance advantages.

[0183] Pipeline Flow Overview: The pipeline table (Table 5) above shows the multiply-accumulate (MAC) operation flow of the multi-channel sample rate converter module, covering six clock cycles (Cycle 0 to Cycle 5), from data / coefficient reading to accumulation result generation. The core design achieves high throughput through a four-stage pipeline, with each stage focusing on a specific task. A detailed breakdown is shown in Table 6 below.

[0184] Table 6

[0185]

[0186] Detailed pipeline stage analysis includes stage 1 to stage 4.

[0187] Phase 1: Data and coefficient reading (Cycle0);

[0188] Operation: Read historical data from DHIS RAM (e.g. d0 corresponds to x(n-0), d1 corresponds to x(n-1), etc.) Read filter coefficients from Coef RAM (e.g. h0 corresponds to the coefficient of the current tap).

[0189] Design goal: Prepare data for subsequent computations and reduce latency through parallel reads. Support multi-channel time-division multiplexing, with each channel allocated an independent storage area.

[0190] Phase 2: Data register storage (Cycle 1);

[0191] Operation: Store the read data (d0) and coefficient (h0) into the input registers (Reg d0, Reg h0).

[0192] Design goal: Insert registers to isolate the combinational logic paths and improve timing performance. Ensure the multiplier input is stable and avoid timing violations caused by RAM read delays.

[0193] Stage 3: Multiplication operation (Cycle2);

[0194] Operation: Performs multiplication of the 21-bit coefficient (h0) and the 18-bit historical data (d0), and stores the result in the product register (r0). For example: r0 <= h0 * d0 (Cycle2), r1 <= h1 * d1 (Cycle3).

[0195] Design goal: Achieve high-speed computation through dedicated multiplication units (DSP blocks). Registers store results temporarily to facilitate pipeline advancement.

[0196] Phase 4: Accumulation operation (Cycle 3 to Cycle 5);

[0197] Operation: Add the product results to the accumulator (sum) in sequence. For example: Cycle3: sum <= sum + r0, Cycle4: sum <= sum + r1, Cycle5: sum <= sum + r2.

[0198] Design goal: Use step-by-step accumulation to avoid single-cycle long paths and increase clock frequency. Expand the accumulator bit width (e.g., 39 bits) to prevent overflow, and ultimately truncate to 18-bit output.

[0199] Performance advantages involve high throughput, low latency, and resource optimization, including:

[0200] High throughput: The pipeline design completes one tap multiplication-accumulation operation every six cycles, but multi-stage parallelism enables a valid output result per cycle (assuming the six-stage pipeline is fully populated). This supports eight channels of real-time processing (48 kHz × 8 = 384 kHz), requiring a clock frequency of only 384 kHz × 6, approximately 2.3 MHz.

[0201] Low latency: Inserting registers shortens critical paths (e.g., from multiplier input to accumulator output), allowing for higher clock frequencies (up to 100+ MHz in FPGAs).

[0202] Resource optimization: Shared multipliers and memory interfaces reduce DSP and RAM usage. Register insertion avoids complex combinational logic and improves timing closure.

[0203] Please refer to further Figure 7 The audio data processing system provided in this application involves the design of four arithmetic units. The functional unit arithmetic logic includes reading data from DDR and COEF RAM, registering data from RAM, and performing a product of a register multiplier and a cumulative total in a register. This pipeline design efficiently implements real-time sampling rate conversion for eight channels of PCM data through four-stage segmented operations (read, store, multiply, and accumulate) and multi-channel time-division multiplexing.

[0204] Exemplarily, the four operation units may involve an address generation and reading unit, a data reading and registering unit, and a multiplication and accumulation unit; wherein:

[0205] In the address generation and read unit, "1'b1" represents a constant 1, used for address counter addition operations. "+" represents the adder, which adds the input constant 1 to the current address (addr_dhis and addr_coef) to generate the next address. "D" represents the flip-flop (Rd), which stores the address. The input (D) receives the adder output, and the output (Q) outputs the current address, which is fed back to the adder for the next addition operation. addr_dhis and addr_coef are used to access the historical data RAM (DHIS) and coefficient RAM (COEF), respectively.

[0206] The dhis_in and coef_in in the data read and register unit represent the data read from the DHIS RAM and COEF RAM, respectively. DHIS RAM and COEF RAM store historical data and filter coefficients, respectively. "D" represents a trigger (Reg), which is used to register the read data. data_r and coef_r are the registered historical data and coefficients, respectively.

[0207] The multiplication unit, also known as the multiplier (Mul), where "×" represents the multiplier, multiplies the stored historical data data_r and the coefficient coef_r to obtain the multiplication result result_r.

[0208] The accumulation unit, also known as the adder (Add), where "+" represents the adder, adds the multiplication result result_r to the previous accumulation result sum_r to obtain a new accumulation result; "D" represents the trigger (Add), which is used to store the accumulation result; the input end (D) receives the output of the adder, and the output end (Q) outputs the current accumulation result sum_r and feeds it back to the adder for the next accumulation operation.

[0209] The overall workflow related to the four arithmetic units includes address generation, data reading, data storage, multiplication and accumulation operations, among which:

[0210] Address generation: The address counter is incremented continuously to generate the address for accessing DHIS RAM and COEF RAM;

[0211] Data reading: Read historical data and coefficients from DHIS RAM and COEF RAM according to the generated address;

[0212] Data storage: The read data is stored in the register and then sent to the multiplier;

[0213] Multiplication operation: The multiplier performs multiplication operation on the stored data to obtain the multiplication result;

[0214] Accumulation operation: The multiplication result is added to the previous accumulation result to obtain a new accumulation result, which is stored for the next accumulation.

[0215] With respect to the audio data processing system provided in the present application, based on the same inventive concept, the present application provides an audio signal processing method, comprising: obtaining an audio signal and determining a current sampling rate and a target sampling rate of the audio signal; determining a conversion factor sequence for the audio signal based on the current sampling rate and the target sampling rate, the conversion factor sequence including at least one conversion factor, the conversion factor being used to characterize a change in the amount of data after the filter converts and processes the input signal data; determining a filter type for the audio signal based on a filter constraint, the filter constraint being obtained based on at least one of an audio feature of the audio signal, a signal indicator feature corresponding to the target sampling rate, and a local audio processing resource feature; constructing a filter identification sequence for the audio signal according to the filter type; the filter identification sequence including filter identifications arranged in sequence, the number of which is the same as the number of conversion factors, the filter identification being used to characterize filters belonging to the filter type at the local end; performing output conversion configuration on the filters represented by the filter identifications in the filter identification sequence according to the conversion factors in the conversion factor sequence to obtain a filter configuration result; sequentially combining the local filters to obtain a filter group based on the filter configuration result, and performing sampling rate conversion processing on the audio signal through the filter group to obtain a target signal that meets the target sampling rate.

[0216] The filter bank is formed by sequentially combining the local filters. This means that the order in which the filters at each level appear during the audio processing is set according to the required order. The filter bank is also a virtual concept.

[0217] In an exemplary embodiment, a conversion factor sequence for an audio signal is determined based on a current sampling rate and a target sampling rate, including: determining an interpolation factor and a decimation factor for the audio signal based on the current sampling rate and the target sampling rate, and obtaining a conversion factor based on the interpolation factor and the decimation factor; and combining the conversion factors to obtain a conversion factor sequence for the audio signal.

[0218] In an exemplary embodiment, a filter identification sequence for an audio signal is constructed according to a filter type, including: determining the number of conversion factors included in a conversion factor sequence; determining, based on the filter type, filter identifications whose number is equal to the number of factors; and combining the filter identifications to obtain a filter identification sequence for the audio signal.

[0219] In an exemplary embodiment, the conversion factor includes an interpolation factor and a decimation factor, and the number of factors includes a first factor number of the interpolation factor and a second factor number of the decimation factor; the filter type includes an interpolation type and a decimation type; determining the filter identifiers whose number is the same as the number of factors based on the filter type includes: determining the first filter identifier whose number is the same as the number of first factors based on the interpolation type; determining the second filter identifier whose number is the same as the number of second factors based on the decimation type; and obtaining the filter identifiers whose number is the same as the number of factors based on the first filter identifier and the second filter identifier.

[0220] In an exemplary embodiment, the conversion factor includes an interpolation factor and a decimation factor, and the filter type includes an interpolation type and a decimation type; according to the conversion factors in the conversion factor sequence, the output conversion configuration is performed on the filters represented by the filter identifiers in the filter identification sequence to obtain a filter configuration result, including: when the interpolation factor indicates that the filter of the interpolation type meets the trigger configuration condition, the output conversion configuration is performed on the first filter according to the interpolation factor to obtain a first configuration result, and the first filter is the filter of the interpolation type represented by the filter identifier in the filter identification sequence; when the decimation factor indicates that the filter of the decimation type meets the trigger configuration condition, the output conversion configuration is performed on the second filter according to the decimation factor to obtain a second configuration result, and the second filter is the filter of the decimation type represented by the filter identifier in the filter identification sequence; according to the first configuration result and the second configuration result, the filter configuration result is obtained.

[0221] In an exemplary embodiment, the filter types include interpolation types and decimation types; based on the filter configuration result, the local filters are combined in sequence to obtain a filter group, including: determining the local target filter and the filter cascade order of the target filter according to the filter configuration result, the filter cascade order including the first cascade order of the first filter of the interpolation type and the second cascade order of the second filter of the decimation type in the target filter; cascading the first filter according to the first cascade order to obtain an interpolation filter group; cascading the second filter according to the second cascade order to obtain a decimation filter group; and connecting the interpolation filter group and the decimation filter group in a certain order to obtain a (virtual) filter group.

[0222] In an exemplary embodiment, sampling rate conversion processing is performed on an audio signal through a filter group, including: obtaining the number of taps of each target filter in the filter group; determining the audio processing algorithm corresponding to each target filter based on the number of taps of each target filter; and using each target filter to perform sampling rate conversion processing on the audio signal based on the cascade order of each target filter and the audio processing algorithm corresponding to each target filter.

[0223] In the description of this specification, reference to the terms "some embodiments" or "other embodiments" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0224] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0225] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A system for processing audio data, characterized in that: include: a first storage module, configured to store first-level data to be processed corresponding to each received audio data to be processed, and, upon receiving N-level data to be processed corresponding to any of the first-level data to be processed, update the storage to store the N-level data to be processed; N ≥ 2, and N is a positive integer; a filter, electrically connected to the first storage module, configured to perform audio sampling rate conversion processing on at least each level of the audio data to be processed, from the first level of the data to be processed to the N-1 level of the data to be processed, and obtain sampling rate converted data of each level corresponding to each level of the audio data to be processed; a second storage module, electrically connected to the filter and the first storage module, respectively, for storing the sampling rate converted data at each level corresponding to each of the audio data to be processed; and further for transmitting the sampling rate converted data at each level corresponding to each of the audio data to be processed to the first storage module as the Nth level of data to be processed corresponding to each of the audio data to be processed; The sampling rate converted data of the N-1th level of data to be processed corresponding to each of the audio data to be processed output by the filter is the processed target audio data corresponding to each of the audio data to be processed.

2. The audio data processing system according to claim 1, characterized in that Also includes: The third storage module is electrically connected to the filter and is used to store the number of taps of the filter at each level adapted to perform the audio sampling rate conversion processing on the data to be processed at each level.

3. The audio data processing system according to claim 1, wherein: The filter includes a multiplier and an accumulator; wherein the output end of the multiplier is electrically connected to the input end of the accumulator, the input end of the multiplier is used to receive the data to be processed at each level, and the output end of the accumulator is used to output the sampling rate converted data at each level corresponding to the audio data to be processed at each level.

4. The audio data processing system according to claim 1, wherein: Also includes: a data receiving module, electrically connected to the first storage module and the filter, respectively, comprising a plurality of data receiving channels, each of the data receiving channels being used to receive different audio data to be processed and transmit the data to the first storage module and the filter, respectively; a data output module, electrically connected to the filter and comprising a plurality of data output channels; Used to receive the sampling rate converted data of the N-1th level of data to be processed corresponding to each of the audio data to be processed output by the filter, and output the sampling rate converted data of the N-1th level of data to be processed corresponding to each of the audio data to be processed through each data output channel as the processed target audio data corresponding to each of the audio data to be processed.

5. The audio data processing system according to claim 4, characterized in that: Also includes: a filter parameter control module, the filter parameter control module being electrically connected to the data receiving module and the filter respectively; for determining, based on the current sampling rate and the target sampling rate of each of the audio data to be processed, a sequence of conversion factors for the filters at each level adapted to perform the audio sampling rate conversion processing on the data to be processed at each level; and for determining, based on at least one of the audio characteristics of the audio data to be processed, signal indicator characteristics corresponding to the target sampling rate, and characteristics of audio processing resources at the local end, a filter type parameter of the filter; The conversion factor sequence includes at least one conversion factor, and the conversion factor is used to represent a change in data volume after the filter performs the audio sampling rate conversion processing on the audio data to be processed.

6. The audio data processing system according to claim 4, characterized in that: The first storage module includes data storage channels with the same number as the data receiving channels; each data storage channel is used to store the first-level data to be processed corresponding to the audio data to be processed received by each data receiving channel, and when the N-level data to be processed corresponding to any of the first-level data to be processed is received, it is updated to store the N-level data to be processed.

7. The audio data processing system according to claim 4, characterized in that: The number of the data receiving channels and the number of the data output channels are the same; The data output channel in a matched set of the data receiving channels and the data output channels is configured to output the target audio data corresponding to the audio data to be processed received by the matched data receiving channel.

8. The audio data processing system according to claim 5, characterized in that: The number of the data receiving channels and the data output channels is M, M≥8, and M is a positive integer; The plurality of data receiving channels and the plurality of data output channels perform data transmission based on a first-in-first-out principle.

9. The audio data processing system according to claim 4, characterized in that: Also includes: a first multiplexing unit, wherein an input end of the first multiplexing unit is electrically connected to an output end of the data receiving module, and an output end of the first multiplexing unit is electrically connected to an input end of the first storage module and an input end of the filter respectively; A second multiplexing unit, wherein the input end of the second multiplexing unit is electrically connected to the output end of the filter, and the output end of the second multiplexing unit is electrically connected to the input end of the data output module.

10. The audio data processing system according to claim 9, characterized in that: Also includes: a third multiplexing unit, wherein an input end of the third multiplexing unit is electrically connected to an output end of the first multiplexing unit, an output end of the first storage module, and an output end of the second storage module; and an output end of the third multiplexing unit is electrically connected to an input end of the filter; A fourth multiplexing unit, wherein the input end of the fourth multiplexing unit is electrically connected to the output end of the filter, and the output end of the fourth multiplexing unit is electrically connected to the input end of the second storage module and the input end of the second multiplexing unit respectively.

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