Manufacturing method of semiconductor device

Abstract

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer on the substrate, the side wall structure and the pseudo gate, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer; oxidizing the hard mask layer, a part of the contact hole etching stop layer and a part of the side wall structure to form a surface oxide layer; synchronously removing the surface oxide layer and a part of the interlayer dielectric layer, wherein the surface of the dummy gate is flush with the surfaces of the interlayer dielectric layers on the two sides; and removing the dummy gate to form a metal gate. According to the manufacturing method of the semiconductor device provided by the invention, the height of the formed metal gate can be ensured, the manufacturing process is simple, and the controllability is high.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a method for manufacturing a semiconductor device. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing technology, integrated circuit chips are moving towards higher semiconductor device density and higher integration levels to achieve faster computing speeds, larger data storage capacities, and more functionality. As the feature sizes of semiconductor devices continue to shrink, polysilicon gate processes are unable to meet these requirements. Metal gates are being used to replace polysilicon gates to address issues such as threshold voltage drift, polysilicon gate depletion, excessive gate resistance, and Fermi level pinning.

[0003] During the metal gate fabrication process, a gate-last process is used. During the polysilicon dummy gate removal process, the polysilicon dummy gate is usually subjected to chemical mechanical polishing. The polishing stops at the hard mask layer on the polysilicon dummy gate, and then the hard mask layer and the polysilicon dummy gate are removed through dry / wet etching processes. However, when etching away the hard mask, defects such as the contact hole etch stop layer or the sidewall structure are etched, resulting in depressions. In subsequent processes, the depressions will be filled with work function metal, requiring the metal gate to increase the grinding amount to remove the metal in the depressions, resulting in insufficient metal gate height or insufficient metal gate polishing, resulting in metal residue. Excessive depressions can even lead to gate leakage and other problems. Summary of the Invention

[0004] The object of the present invention is to provide a method for manufacturing a semiconductor device. Through the method for manufacturing a semiconductor device provided by the present invention, the height of the formed metal gate can be ensured, problems such as gate leakage current can be avoided, and the manufacturing process is simple and highly controllable.

[0005] To solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: Providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming sidewall structures on both sides of the dummy gate; forming a contact hole etch stop layer on the substrate, the sidewall structure and the dummy gate, wherein the material of the contact hole etch stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etch stop layer, planarizing the interlayer dielectric layer to a remaining predetermined thickness of the hard mask layer; Oxidizing the hard mask layer, a portion of the contact hole etch stop layer, and a portion of the sidewall structure to form a surface oxide layer; Simultaneously removing the surface oxide layer and a portion of the interlayer dielectric layer, so that the surface of the dummy gate is flush with the surfaces of the interlayer dielectric layers on both sides; and The dummy gate is removed to form a metal gate.

[0006] In one embodiment of the present invention, the hard mask layer includes silicon nitride, and the interlayer dielectric layer includes silicon oxide.

[0007] In one embodiment of the present invention, the sidewall structure includes a stacked first sublayer, a second sublayer, a third sublayer and a fourth sublayer, starting from the side close to the dummy gate, the first sublayer and the third sublayer are silicon nitride layers, and the second sublayer and the fourth sublayer are silicon oxide layers.

[0008] In one embodiment of the present invention, the step of making the surface of the dummy gate flush with the surfaces of the interlayer dielectric layers on both sides includes: forming a first interlayer dielectric layer and a second interlayer dielectric layer in sequence on the contact hole etch stop layer; After planarizing the first interlayer dielectric layer, the second interlayer dielectric layer, the contact hole etch stop layer and a portion of the hard mask layer, the hard mask layer is flush with the first interlayer dielectric layer and the second interlayer dielectric layer on both sides; Oxidizing the hard mask layer, a portion of the contact hole etch stop layer, and a portion of the sidewall structure to form a surface oxide layer, wherein the surface oxide layer protrudes from surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer; forming a leveling layer on the first interlayer dielectric layer, the second interlayer dielectric layer and the surface oxide layer, wherein the leveling layer, the first interlayer dielectric layer and the second interlayer dielectric layer are made of the same material; and The leveling layer, the surface oxide layer, a portion of the first interlayer dielectric layer and a portion of the second interlayer dielectric layer are removed simultaneously, and the surface of the dummy gate is flush with the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer on both sides.

[0009] In one embodiment of the present invention, the first interlayer dielectric layer and the second interlayer dielectric layer are silicon oxide, the first interlayer dielectric layer is obtained by high aspect ratio chemical vapor deposition, the second interlayer dielectric layer is obtained by high density plasma chemical vapor deposition, and the second interlayer dielectric layer has compressive stress.

[0010] In one embodiment of the present invention, the step of making the surface of the dummy gate flush with the surfaces of the interlayer dielectric layers on both sides includes: forming a first interlayer dielectric layer and a second interlayer dielectric layer in sequence on the contact hole etch stop layer; planarizing the first interlayer dielectric layer, the second interlayer dielectric layer, the contact hole etch stop layer and a portion of the hard mask layer, wherein surfaces of the hard mask layer, a portion of the sidewall structure and the contact hole etch stop layer are lower than surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer on both sides; Oxidizing the hard mask layer, a portion of the contact hole etch stop layer, and a portion of the sidewall structure to form a surface oxide layer, wherein a surface of the surface oxide layer is flush with surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer; and The surface oxide layer, part of the first interlayer dielectric layer and part of the second interlayer dielectric layer are removed simultaneously, and the surface of the dummy gate is flush with the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer on both sides.

[0011] In one embodiment of the present invention, the method for manufacturing the surface oxide layer includes: placing the substrate after planarizing the interlayer dielectric layer into a plasma chamber; and The chamber is controlled to operate at a preset temperature and a preset power, and oxygen-containing gas and auxiliary gas are introduced to perform oxidation.

[0012] In one embodiment of the present invention, the preset temperature is 350° C. to 550° C., and the preset power is 3000W to 14000W.

[0013] In one embodiment of the present invention, the total flow rate of the oxygen-containing gas and the auxiliary gas is 300 sccm-900 sccm, and the flow rate ratio of the oxygen-containing gas to the auxiliary gas is 1:1-2:1.

[0014] In one embodiment of the present invention, the remaining preset thickness of the hard mask layer is 3 nm to 5 nm.

[0015] In summary, the present invention provides a method for manufacturing a semiconductor device. The unexpected technical effect of the present application is that it can ensure that after the hard mask layer is removed, the interlayer dielectric layer, the side wall structure and the contact hole etch stop layer are not recessed, thereby ensuring the height of the formed metal gate and avoiding problems such as gate leakage current; it can control the thickness of the surface oxide layer to obtain surface oxide layers of different depths. After the surface oxide layer reaches a certain thickness, the oxidation rate drops significantly and does not affect the underlying side wall structure and the contact hole etch stop layer; it can ensure the height of the metal gate finally formed and improve the height consistency of subsequent metal gates; it can neutralize the lateral stress generated when the surface oxide layer is formed and reduce the influence of the lateral stress generated by the surface oxide layer on the device performance; the manufacturing process is highly controllable and the manufacturing process is simple, so it is easy to control the height of the metal gate and improve the electrical performance of the semiconductor device.

[0016] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 FIG. 1 is a schematic diagram of forming a pad oxide layer and a pad nitride layer on a substrate according to an embodiment of the present invention.

[0019] Figure 2 FIG. 4 is a schematic diagram of forming a first photoresist layer in one embodiment of the present invention.

[0020] Figure 3 FIG. 1 is a schematic diagram of forming a shallow trench isolation structure in one embodiment of the present invention.

[0021] Figure 4 FIG. 1 is a schematic diagram of forming a well region in one embodiment of the present invention.

[0022] Figure 5 FIG. 1 is a schematic diagram of forming a gate material layer and a hard mask layer in one embodiment of the present invention.

[0023] Figure 6 FIG. 1 is a schematic diagram of forming a dummy gate according to an embodiment of the present invention.

[0024] Figure 7 FIG. 1 is a schematic diagram of forming a lightly doped region in one embodiment of the present invention.

[0025] Figure 8 FIG. 1 is a schematic diagram of forming a sidewall structure and a heavily doped region in one embodiment of the present invention.

[0026] Figure 9 Schematic diagram of forming a metal silicide layer, a contact hole etch stop layer and an interlayer dielectric layer in one embodiment of the present invention.

[0027] Figure 10 Schematic diagram of planarizing the interlayer dielectric layer and a portion of the hard mask layer in one embodiment of the present invention.

[0028] Figure 11 FIG. 1 is a schematic diagram of a surface oxide layer formed in one embodiment of the present invention.

[0029] Figure 12 Schematic diagram showing the effect of oxidation time on the thickness of the surface oxide layer in one embodiment of the present invention.

[0030] Figure 13Schematic diagram of forming a leveling layer on a surface oxide layer and an interlayer dielectric layer in one embodiment of the present invention.

[0031] Figure 14 This is a schematic diagram after removing the leveling layer, the surface oxide layer and part of the interlayer dielectric layer in one embodiment of the present invention.

[0032] Figure 15 FIG. 1 is a schematic diagram of removing a dummy gate according to an embodiment of the present invention.

[0033] Figure 16 FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0034] Figure 17 FIG. 4 is a schematic diagram of planarizing the interlayer dielectric layer in another embodiment of the present invention.

[0035] Figure 18 FIG. 1 is a schematic diagram of another embodiment of the present invention after a surface oxide layer is formed.

[0036] Figure 19 This is a schematic diagram of another embodiment of the present invention after the surface oxide layer and part of the interlayer dielectric layer are removed.

[0037] Description of labels: 10. Substrate; 101. Well region; 11. Pad oxide layer; 12. Pad nitride layer; 13. First photoresist layer; 131. Opening; 14. Shallow trench isolation structure; 15. Gate oxide layer; 16. Gate dielectric layer; 17. Barrier layer; 18. Gate material layer; 181. Dummy gate; 182. Recess; 19. Hard mask layer; 20. Second photoresist layer; 21. Lightly doped region; 22. Sidewall structure; 221. First sublayer; 222. Second sublayer; 223. Third sublayer; 224. Fourth sublayer; 23. Heavily doped region; 24. Metal silicide layer; 25. Contact hole etch stop layer; 26. First interlayer dielectric layer; 27. Second interlayer dielectric layer; 28. Surface oxide layer; 29. ​​Leveling layer; 30. Metal gate. DETAILED DESCRIPTION

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0040] In the description of this specification, it should be understood that the directions or positional relationships indicated by terms such as "center," "upper," "lower," "front," "back," "left," and "right" are based on the directions or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this solution and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific direction, be constructed, or operate in a specific direction. Therefore, they should not be construed as limitations on this solution. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0041] The present invention provides a method for fabricating a semiconductor device. During metal gate formation, the interlayer dielectric layer, sidewall structure, and contact hole etch stop layer are prevented from being recessed, thereby ensuring the height of the formed metal gate and avoiding problems such as gate leakage current. The method also ensures the height of the final metal gate and improves the height consistency of subsequent metal gates, thereby enhancing the electrical performance of the semiconductor device. Furthermore, the semiconductor device fabricated by the present invention can be widely used in various fields, including optical communications, digital displays, image reception, optical integration, transportation, energy, medicine, household appliances, and aerospace.

[0042] See also Figure 1 As shown, in one embodiment of the present invention, a substrate 10 is first provided. Substrate 10 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, a silicon wafer, or other semiconductor materials formed from III / V compounds, including stacked structures composed of these semiconductor materials, or silicon-on-insulator (SOI), stacked silicon-on-insulator (SiOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In this embodiment, substrate 10 is, for example, a silicon wafer semiconductor substrate, and can be either an N-type substrate or a P-type substrate. In other embodiments, the type of substrate 10 is selected based on the semiconductor device being fabricated. The present invention is not limited to the type of semiconductor device; for example, the semiconductor device includes a gate structure. In this embodiment, a MOS transistor is used as an example to illustrate the method for fabricating a semiconductor device.

[0043] See also Figure 1As shown, in one embodiment of the present invention, a pad oxide layer 11 is formed on a substrate 10. The pad oxide layer 11 acts as a buffer layer to improve the stress between the substrate 10 and the subsequently formed pad nitride layer 12. The pad oxide layer 11 is, for example, a dense silicon oxide or other material, and the pad oxide layer 11 can be formed, for example, by any one of a dry oxygen oxidation method, a wet oxygen oxidation method, or an in-situ steam growth method (ISSG). In this embodiment, the pad oxide layer 11 is formed, for example, by a dry oxygen oxidation method. Specifically, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen is introduced. The surface of the substrate 10 reacts with the oxygen at high temperature to generate a dense pad oxide layer 11, and the quality of the generated pad oxide layer 11 is good. The pad oxide layer 11 is, for example, silicon oxide, and the thickness of the pad oxide layer 11 is, for example, 10nm to 40nm, specifically, for example, 10nm, 20nm, 30nm, or 40nm.

[0044] See also Figures 1 to 3 As shown, in one embodiment of the present invention, a pad nitride layer 12 is formed on the pad oxide layer 11. The pad nitride layer 12 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. In this embodiment, the pad nitride layer 12 is, for example, silicon nitride, and can be formed, for example, by a method such as low pressure chemical vapor deposition (LPCVD). Specifically, for example, the substrate 10 with the pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia, and reacts at a pressure of, for example, 2T~10T and a temperature of, for example, 700°C~900°C to deposit the pad nitride layer 12. The thickness of the pad nitride layer 12 can be adjusted by controlling the heating time. The thickness of the pad nitride layer 12 is, for example, 50 nm to 80 nm, specifically 50 nm, 60 nm, or 70 nm. Providing the pad nitride layer 12 protects the substrate 10 from planarization processes such as chemical mechanical polishing (CMP) involved in fabricating the shallow trench isolation structure 14. Furthermore, during the subsequent shallow trench isolation structure formation process, the pad nitride layer 12 can serve as a mask to protect the substrate 10 outside the shallow trench isolation structure from damage during etching.

[0045] See also Figures 1 to 3As shown, in one embodiment of the present invention, after forming the pad nitride layer 12, a first photoresist layer 13 is formed on the pad nitride layer 12, and a plurality of openings 131 are formed on the first photoresist layer 13 through exposure and development processes. The openings 131 are used to define the position of the shallow trench isolation structure 14. Using the first photoresist layer 13 as a mask, etching is performed to remove the pad nitride layer 12, the pad oxide layer 11 and a portion of the substrate 10 exposed by the openings 131 to form a shallow trench. In this embodiment, for example, dry etching is used to form a shallow trench (not shown in the figure). After the etching is completed, the first photoresist layer 13 is removed. After the shallow trench is formed, an insulating dielectric is deposited in the shallow trench until the insulating dielectric in the shallow trench protrudes from the surface of the pad nitride layer 12. The present invention does not limit the deposition method of the insulating medium. For example, high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect ratio chemical vapor deposition (HARP-CVD) can be used to form a high-quality insulating medium. In this embodiment, the insulating medium is, for example, silicon oxide. In other embodiments, the insulating medium can also be other insulating materials suitable for isolation.

[0046] See also Figures 1 to 3 As shown, in one embodiment of the present invention, after the insulating medium is prepared, the insulating medium is planarized, for example, by using CMP to planarize the insulating medium. For example, a portion of the insulating medium and a portion of the pad nitride layer 12 are removed by grinding, and then the pad nitride layer 12 is removed to obtain a shallow trench isolation structure 14, and the shallow trench isolation structure 14 is, for example, higher than the pad oxide layer 11 on both sides. The present invention does not limit the method for removing the pad nitride layer 12, for example, dry etching, wet etching, or a combination of dry etching and wet etching are used for removal. In this embodiment, for example, hot phosphoric acid is used to remove the pad nitride layer 12 to form a shallow trench isolation structure 14 to isolate adjacent semiconductor devices.

[0047] See also Figures 3 and 4As shown, in one embodiment of the present invention, after the shallow trench isolation structure 14 is prepared, ion implantation is performed on the substrate 10 using the pad oxide layer 11 as an ion implantation buffer layer to form a well region 101. In one embodiment of the present invention, the semiconductor device is, for example, a PMOS transistor, and the dopant ions in the well region 101 are, for example, N-type dopant ions, such as phosphorus (P) or arsenic (As). In another embodiment of the present invention, the semiconductor device is, for example, an NMOS transistor, and the dopant ions in the well region 101 are, for example, P-type dopant ions, such as boron (B) or gallium (Ga). After the ion implantation, a rapid thermal annealing (RTA) process is performed on the well region 101 to diffuse the implanted ions to an appropriate depth and improve the avalanche breakdown resistance of the semiconductor device. For example, wet etching is used to remove the pad oxide layer 11, and the wet etching solution used is, for example, hydrofluoric acid or buffered oxide etchant (BOE).

[0048] See also Figures 4 to 5 As shown, in one embodiment of the present invention, after removing the pad oxide layer, a gate oxide layer 15 is formed on the substrate 10. The gate oxide layer 15 is, for example, a silicon oxide layer, and is formed, for example, by an in-situ water vapor growth method. The thickness of the gate oxide layer 15 is, for example, 8 Å to 15 Å. After forming the gate oxide layer 15, a gate dielectric layer 16 is deposited on the gate oxide layer 15 and the shallow trench isolation structure 14. The gate dielectric layer 16 is, for example, one or a mixture of high-k dielectrics such as hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), zirconium oxynitride (ZrON), zirconium oxynitride (ZrSiON), hafnium silicate (HfSiO), hafnium oxynitride (HfSiON), hafnium lanthanum oxynitride (HfLaON), or hafnium aluminum oxide (HfAlO). The thickness of the gate dielectric layer 16 is, for example, 12 Å to 20 Å. The gate dielectric layer 16 can be formed, for example, by atomic layer deposition (ALD). By forming the gate oxide layer 15, the poor interface quality between the gate dielectric layer 16 and the substrate 10 can be improved, thereby improving the performance of the semiconductor device.

[0049] See also Figure 5As shown, in one embodiment of the present invention, after forming the gate dielectric layer 16, a barrier layer 17 is formed on the gate dielectric layer 16. The barrier layer 17 is, for example, titanium nitride or titanium, and is prepared by methods such as DC magnetron sputtering or atomic layer deposition. The thickness of the barrier layer 17 is, for example, 15Å to 25Å. By providing the barrier layer 17, it can serve as a barrier layer for dummy gate etching and a work function layer for the metal gate during the subsequent preparation process, preventing the gate dielectric layer 16 from being contaminated or damaged, thereby improving the performance of the subsequently prepared metal gate. A gate material layer 18 is then formed on the barrier layer 17. The gate material layer 18 is, for example, polysilicon. In this embodiment, the gate material layer 18 is prepared by methods such as chemical vapor deposition, and the thickness of the gate material layer 18 is, for example, 50nm to 200nm, which is selected based on the thickness of the final metal gate.

[0050] See also Figure 5 As shown, in one embodiment of the present invention, after forming the gate material layer 18, a hard mask layer 19 is formed on the gate material layer 18, wherein the hard mask layer 19 is, for example, a silicon nitride layer, and has a thickness of, for example, 15nm to 30nm. By providing the hard mask layer, it is possible to prevent the dummy gate from being etched prematurely when subsequently forming structures such as sidewall structures, heavily doped regions, or contact hole etch stop layers, resulting in a loss of dummy gate height and affecting the height of the final metal gate. This ensures the height of the dummy gate, thereby ensuring the height of the final metal gate and improving the height consistency of the subsequent metal gates.

[0051] See also Figures 5 and 6 As shown, in one embodiment of the present invention, after the hard mask layer 19 is formed, a second photoresist layer 20 is formed on the hard mask layer 19. The second photoresist layer 20 is then exposed and developed to remove the second photoresist layer 20 in areas other than where the dummy gate is to be formed. The hard mask layer 19, gate material layer 18, barrier layer 17, and gate dielectric layer 16 are then etched using the second photoresist layer 20 as a mask and the gate oxide layer 15 as an etch stop layer, for example, by a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process, leaving the remaining gate material layer 18 as a dummy gate 181.

[0052] See also Figures 6 and 7As shown, in one embodiment of the present invention, after forming the dummy gate 181, lightly doped regions 21 are formed in the well region 101 on both sides of the dummy gate 181. The doping ions in the lightly doped regions 21 are formed, for example, by ion implantation, and the type of the implanted ions is opposite to the type of ions in the well region 101. In this embodiment, when the semiconductor device is a PMOS transistor, the doping ions in the lightly doped regions 21 are, for example, P-type impurities such as boron or gallium. When the semiconductor device is an NMOS transistor, the doping ions in the lightly doped regions 21 are, for example, N-type impurities such as phosphorus or arsenic. In addition, during the implantation of the doping ions, the lightly doped regions 21 formed partially overlap with the dummy gate.

[0053] See also Figures 7 and 8 As shown, in one embodiment of the present invention, after forming the lightly doped region 21, spacer structures 22 are formed on both sides of the dummy gate, wherein the spacer structure 22 is, for example, a stacked structure. In this embodiment, the spacer structure 22, starting from the side close to the dummy gate 181, includes, for example, a stacked first sublayer 221, a second sublayer 222, a third sublayer 223, and a fourth sublayer 224. The first sublayer 221 and the third sublayer 223 are, for example, silicon nitride layers, and the second sublayer 222 and the fourth sublayer 224 are, for example, silicon oxide layers. By setting the first sublayer 221 as a silicon nitride layer, the occurrence of cracks in the spacer structure during the patterning process during the subsequent formation of the heavily doped region can be reduced. At the same time, the stability of the spacer structure 22 after the dummy gate is removed can be improved. In other embodiments, the spacer structure 22 is, for example, another stacked structure. By setting the spacer structure 22 as a stacked structure, the uniformity of the dummy gate is improved, thereby improving the stability of the threshold voltage of the semiconductor device.

[0054] See also Figure 8 As shown, in one embodiment of the present invention, after forming the spacer structure 22, a heavily doped region 23 is formed in the substrate 10 on the side of the spacer structure 22 away from the dummy gate 181. The edge of the heavily doped region 23 is aligned with the side of the spacer structure 22 away from the dummy gate 181. A photoresist process is used to expose the area where the heavily doped region 23 is to be formed. For example, the heavily doped region 23 is formed by ion implantation. The implanted ions are of the opposite type to the ions in the well region 101, i.e., the same type as the ions in the lightly doped region 21. The doping concentration of the heavily doped region 23 is greater than the doping concentration of the lightly doped region 21, and the doping depth of the heavily doped region 23 is greater than the doping depth of the lightly doped region 21. After forming the heavily doped region 23, the heavily doped region 23 and the lightly doped region 21 are activated, for example, by subjecting the substrate 10 to rapid thermal annealing. Rapid thermal annealing can repair lattice defects generated during the fabrication process and activate doped ions, thereby activating the heavily doped region 23 and the lightly doped region 21.

[0055] See also Figures 8 and 9As shown, in one embodiment of the present invention, after forming the heavily doped region 23, the gate oxide layer 15 is removed from the area outside the dummy gate 181 and the spacer 22, for example by etching, to form a fully covering metal layer (not shown) on the substrate 10. Through heat treatment, the metal reacts with the exposed substrate 10 to form a metal silicide layer 24 on the heavily doped region 23. The unreacted metal layer is then removed. The formed metal silicide layer 24 is used to improve the contact resistance of the conductive plugs subsequently formed on the source and drain electrodes. After forming the metal silicide layer 24, a contact etch stop layer (CESL) 25 is formed on the substrate 10. The CESL 25 is made of the same material as the hard mask layer 19, such as silicon nitride. The CESL 25 is formed, for example, by chemical vapor deposition and has a thickness of, for example, 5 nm to 25 nm. The contact hole etch stop layer 25, for example, covers the spacer structure 22, the dummy gate 181, the metal silicide layer 24, and the shallow trench isolation structure 14, thereby preventing damage to the substrate 10 during subsequent fabrication processes, thereby improving the performance of the semiconductor device. In the present application, the hard mask layer 19 is partially removed during the formation of the lightly doped region 21, the spacer structure 22, the heavily doped region 23, and the metal silicide layer 24. In one specific embodiment, after forming the metal silicide layer 24, for example, one-third to two-thirds of the hard mask layer 19 is removed.

[0056] See also Figures 9 and 10As shown, in one embodiment of the present invention, after forming the contact hole etch stop layer 25, an interlayer dielectric layer is formed on the contact hole etch stop layer 25. The interlayer dielectric layer includes a first interlayer dielectric layer 26 and a second interlayer dielectric layer 27. The first interlayer dielectric layer 26, for example, covers the dummy gate 181, the sidewall structure 22, the shallow trench isolation structure 14, and the substrate 10. The second interlayer dielectric layer 27 is formed on the first interlayer dielectric layer 26. The first and second interlayer dielectric layers 26, 27 are, for example, silicon oxide. The first interlayer dielectric layer 26 is deposited, for example, by HARP-CVD to improve deposition quality and filling performance and prevent voids in the interlayer dielectric layer. The second interlayer dielectric layer 27 is deposited, for example, by HDP-CVD to obtain an oxide layer with compressive stress. After forming the second interlayer dielectric layer 27, the second interlayer dielectric layer 27 and the first interlayer dielectric layer 26 are planarized, for example, by chemical mechanical polishing. During the polishing process, for example, non-selective polishing is employed, and the polishing time is controlled to remove the second interlayer dielectric layer 27, the first interlayer dielectric layer 26, the contact hole etch stop layer 25, and a portion of the hard mask layer 19 on the dummy gate 181. Polishing is stopped until a predetermined thickness of the hard mask layer 19 remains. After planarization, the surface of the hard mask layer 19 is flush with the surfaces of the second interlayer dielectric layer 27, the first interlayer dielectric layer 26, and the contact hole etch stop layer 25 on either side thereof. In this embodiment, after polishing, the remaining predetermined thickness of the hard mask layer 19 is, for example, 3 nm to 5 nm. By stopping the planarization process on the hard mask layer 19, the dummy gate is prevented from being partially exposed while remaining partially unexposed due to uneven polishing during the polishing process, thereby preventing the dummy gate from being completely removed. This also prevents the interlayer dielectric layer from experiencing large depressions, thereby preventing metal residue from remaining in the interlayer dielectric layer during subsequent manufacturing processes.

[0057] See also Figures 10 and 11As shown, in one embodiment of the present invention, after planarizing the interlayer dielectric layer, the hard mask layer 19, the surface contact hole etch stop layer 25, and a portion of the sidewall structure 22 are oxidized to obtain a surface oxide layer 28. In this embodiment, for example, a high-density plasma treatment process is used for oxidation, wherein the substrate after the interlayer dielectric layer is planarized is placed in a plasma chamber, and the chamber is controlled to introduce oxygen-containing gas and auxiliary gas at a preset temperature and preset power for oxidation, and the oxidation time is, for example, 30s to 60s. In this embodiment, the preset temperature is, for example, 350°C to 550°C, the preset power is, for example, 3000W to 14000W, the total flow rate of the oxygen-containing gas and the auxiliary gas is, for example, 300sccm to 900sccm, and the flow ratio of the oxygen-containing gas to the auxiliary gas is, for example, 1:1 to 2:1. The oxygen-containing gas includes, for example, oxygen or nitrous oxide, and the auxiliary gas includes, for example, an inert gas such as argon. The oxygen-containing gas and the auxiliary gas are plasmatized in the chamber. The auxiliary gas can increase the density of the excited plasma and enhance the process effect. During the oxidation process, in the sidewall structure 22, the surface first sublayer 221 and the third sublayer 223 are oxidized from silicon nitride to silicon oxide, the surface contact hole etch stop layer 25 is oxidized to silicon oxide, and the hard mask layer 19 is oxidized to silicon oxide, thereby forming a surface oxide layer 28. During the oxidation process, when the silicon nitride layer is oxidized to form a silicon oxide layer, the surface oxide layer 28 protrudes from the surface of the first interlayer dielectric layer 26 and the second interlayer dielectric layer 27, and the thickness of the surface oxide layer 28 increases by 40% to 80% relative to the thickness of the hard mask layer 19 before oxidation. Furthermore, the surface oxide layer 28 formed by oxidation expands and generates lateral stress, and the stress generated by the second interlayer dielectric layer 27 can neutralize the lateral stress, thereby reducing the influence of the lateral stress generated by the surface oxide layer 28 on the device performance.

[0058] See also Figures 11 to 12 As shown in FIG. 1 , in one embodiment of the present invention, the temperature and power of the plasma chamber are fixed, and a fixed flow rate of oxygen-containing gas and auxiliary gas is introduced, and the effect of oxidation time on oxidation depth is shown. Figure 12 The figure shows the effect of oxidation time on oxidation depth under the conditions of O2 flow rate of 300 sccm, Ar flow rate of 250 sccm, and chamber temperature of 400°C. Figure 12As can be seen in the figure, as the oxidation time increases, the thickness of the contact etch stop layer 25 tends to stabilize, that is, the oxidation depth tends to stabilize. Therefore, by controlling the remaining thickness of the hard mask layer 19 and then controlling the oxidation conditions, it is possible to ensure that the hard mask layer 19 is completely oxidized. At the same time, the oxidation depth of the sidewall structure 22 and the contact etch stop layer 25 is consistent with the oxidation depth of the hard mask layer 19. On the one hand, it can avoid incomplete oxidation of the hard mask layer 19 on the dummy gate, resulting in incomplete removal. On the other hand, it can control the thickness of the surface oxide layer to obtain surface oxide layers of different depths. When the surface oxide layer reaches a certain thickness, the oxidation rate decreases significantly, which can prevent the oxidation depth of the sidewall structure 22 and the contact etch stop layer 25 from being too deep, without affecting the underlying sidewall structure and contact etch stop layer. It can also avoid problems such as recessing caused by excessive removal of the sidewall structure and contact etch stop layer in subsequent processes, thereby ensuring the height of the formed metal gate and avoiding problems such as gate leakage current.

[0059] See also Figure 11 and Figure 13 As shown, in one embodiment of the present invention, after forming the surface oxide layer 28, a leveling layer 29 is formed on the interlayer dielectric layer and the surface oxide layer 28. The leveling layer 29 is, for example, a silicon oxide layer, and is deposited, for example, by a method such as HARP-CVD. After deposition, a CMP planarization process is performed to obtain a smooth surface of the leveling layer 29, thereby preventing height inconsistencies between the dummy gate 181 and the interlayer dielectric layer during subsequent etching.

[0060] See also Figure 13 and Figure 14 As shown, in one embodiment of the present invention, after the leveling layer 29 is formed, the leveling layer 29, the surface oxide layer 28 and part of the interlayer dielectric layer are removed simultaneously. Since the leveling layer 29, the surface oxide layer 28 and the interlayer dielectric layer are made of the same material, there is no difference in etching rate caused by material difference. Therefore, after removal, the surface of the pseudo gate 181 is flush with the surfaces of the sidewall structures 22 on both sides, the contact hole etch stop layer 25, the first interlayer dielectric layer 26 and the second interlayer dielectric layer 27. The leveling layer 29, the surface oxide layer 28, and the interlayer dielectric layer are removed by, for example, wet etching, dry etching, or a combination of dry and wet etching. In this embodiment, wet etching is used for removal, and the wet etching solution is, for example, dilute hydrofluoric acid or a buffered oxide etchant, wherein the mass fraction of dilute hydrofluoric acid is, for example, 5% to 15%. The time is controlled to ensure that the surface oxide layer 28 is just removed, and the etching rate is controlled to prevent the interlayer dielectric layer from being recessed due to excessive etching speed, thereby improving the performance of the semiconductor device. By first performing oxidation, the top layer material is unified, the removal process is simplified, the manufacturing process is highly controllable, and the manufacturing process is simple, thereby making it easy to control the height of the metal gate and improving the electrical performance of the semiconductor device.

[0061] See also Figure 14 and Figure 15 As shown, in one embodiment of the present invention, after removing the surface oxide layer 28, the gate material layer of the dummy gate 181 is removed to form a recess 182 at the position of the dummy gate 181. When removing the dummy gate 181, dry etching, wet etching, or a combination of dry etching and wet etching can be used. When dry etching is used, chlorine, bromine, helium, hydrogen bromide, or a mixture of at least one of these gases and oxygen can be selected. Dry etching has good anisotropy, selectivity, and etching efficiency to ensure that the dummy gate 181 is free of residue. During the etching process, after etching to expose the barrier layer 17, etching is stopped, and the sidewall structure 22 is retained as the sidewall structure of the metal gate prepared later.

[0062] See also Figure 15 and Figure 16 As shown, in one embodiment of the present invention, after forming the recess 182, multiple metal work function layers and metal conductive layers (not shown) are deposited on the second interlayer dielectric layer 27, the first interlayer dielectric layer 26, and the bottom and sidewalls of the recess 182. The metal conductive layers are disposed on the multiple metal work function layers until the recess 182 is completely filled. The metal conductive layers and the metal work function layers are then planarized until they are flush with the surfaces of the first interlayer dielectric layer 26 and the second interlayer dielectric layer 27, thereby forming a metal gate 30. The metal work function layers may be made of, for example, one or more stacks of tantalum nitride (TaN), titanium nitride, titanium aluminide (TiAl), titanium aluminum nitride (TiAIN), or tungsten nitride (WN), and may be formed, for example, by methods such as plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition, or physical vapor deposition. The number of metal work function layers and the materials used are selected based on the type of semiconductor device to meet the threshold voltage requirements of different semiconductor devices. The metal conductive layer may be made of a metal material with good conductivity, such as aluminum, tungsten, copper, or silver, and may be a single metal layer, a multilayer metal layer, or a stack of metal compounds. After forming the metal gate 30, for example, conductive plugs and metal wiring layers are fabricated, which will not be elaborated here. In this application, the metal gate formation process can be applied to the fabrication of any semiconductor device containing a metal gate to stabilize the height of the metal gate, prevent gate leakage current, and improve the performance of the semiconductor device.

[0063] Please participate Figure 9 and Figure 17In another embodiment of the present invention, after forming the second interlayer dielectric layer 27, the second interlayer dielectric layer 27 and the first interlayer dielectric layer 26 are planarized, for example, by chemical mechanical polishing. During the planarization process, the polishing process is controlled to increase the polishing speed of the silicon nitride layer. After the polishing stops, the surfaces of the second interlayer dielectric layer 27 and the first interlayer dielectric layer 26 are flush, and the surfaces of the hard mask layer 19, the contact hole etch stop layer 25, and the silicon nitride within the sidewall structure 22 are lower than the surface of the interlayer dielectric layer. The polishing process is controlled to ensure that the height difference between the silicon oxide and the silicon nitride is equal to the expansion height of the silicon nitride during the subsequent oxidation process. In this embodiment, after polishing, the remaining predetermined thickness of the hard mask layer 19 is, for example, 3 nm to 5 nm.

[0064] Please participate Figures 17 to 19 In another embodiment of the present invention, after the planarization layer is processed, the hard mask layer 19 and the surface contact hole etch stop layer 25 and part of the sidewall structure 22 are oxidized to obtain a surface oxide layer 28. In this embodiment, the oxidation conditions are the same as those in the previous embodiment and will not be elaborated here. During the planarization process, since the surface of the silicon nitride in the hard mask layer 19, the contact hole etch stop layer 25 and the sidewall structure 22 is lower than the surface of the interlayer dielectric layer, the volume expansion of the silicon nitride during the oxidation process can compensate for the height difference, and the surface of the obtained surface oxide layer 28 is flush with the surface of the interlayer dielectric layer. After obtaining the surface oxide layer 28, the surface oxide layer 28 and part of the interlayer dielectric layer can be directly etched away so that the dummy gate 181 is flush with the structures on both sides, and then the metal gate is prepared, which is the same as the previous embodiment and will not be elaborated here. In this embodiment, the production of the leveling layer can be avoided, the production process can be further simplified, and the process speed can be improved.

[0065] In summary, the present invention provides a method for manufacturing a semiconductor device. By improving the method for manufacturing a semiconductor device, the unexpected technical effect of the present application is that it can ensure that after the hard mask layer is removed, the interlayer dielectric layer, the sidewall structure and the contact hole etch stop layer do not sink, thereby ensuring the height of the formed metal gate and avoiding problems such as gate leakage current. The thickness of the surface oxide layer can be controlled to obtain surface oxide layers of different depths. After the surface oxide layer reaches a certain thickness, the oxidation rate drops significantly without affecting the underlying sidewall structure and the contact hole etch stop layer. The height of the metal gate finally formed can be ensured, and the height consistency of subsequent metal gates can be improved. The lateral stress generated when the surface oxide layer is formed can be neutralized, reducing the impact of the lateral stress generated by the surface oxide layer on the device performance. The manufacturing process is highly controllable and the manufacturing process is simple, so it is easy to control the height of the metal gate and improve the electrical performance of the semiconductor device.

[0066] The above description of the illustrated embodiments of the present invention (including that described in the Abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes only, as those skilled in the art will recognize and appreciate, various equivalent modifications are possible within the spirit and scope of the present invention. As noted, modifications may be made to the present invention in light of the above description of the illustrated embodiments of the present invention, and such modifications will be within the spirit and scope of the present invention.

[0067] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, such as the technical solutions formed by replacing the above features with (but not limited to) technical features with similar functions disclosed in this application. In addition to the technical features described in the specification, the remaining technical features are known technologies to those skilled in the art. In order to highlight the innovative features of the present invention, the remaining technical features will not be repeated here.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming sidewall structures on both sides of the dummy gate; forming a contact hole etch stop layer on the substrate, the sidewall structure and the dummy gate, wherein the material of the contact hole etch stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etch stop layer, planarizing the interlayer dielectric layer to a remaining predetermined thickness of the hard mask layer; Oxidizing the hard mask layer, a portion of the contact hole etch stop layer, and a portion of the sidewall structure to form a surface oxide layer; The surface oxide layer and a portion of the interlayer dielectric layer are removed simultaneously, so that the surface of the dummy gate is flush with the surfaces of the interlayer dielectric layers on both sides; as well as The dummy gate is removed to form a metal gate.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The hard mask layer includes silicon nitride, and the interlayer dielectric layer includes silicon oxide.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The sidewall structure includes a stacked first sublayer, a second sublayer, a third sublayer and a fourth sublayer starting from the side close to the dummy gate. The first sublayer and the third sublayer are silicon nitride layers, and the second sublayer and the fourth sublayer are silicon oxide layers.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of making the surface of the dummy gate flush with the surfaces of the interlayer dielectric layers on both sides include: forming a first interlayer dielectric layer and a second interlayer dielectric layer in sequence on the contact hole etch stop layer; After planarizing the first interlayer dielectric layer, the second interlayer dielectric layer, the contact hole etch stop layer and a portion of the hard mask layer, the hard mask layer is flush with the first interlayer dielectric layer and the second interlayer dielectric layer on both sides; Oxidizing the hard mask layer, a portion of the contact hole etch stop layer, and a portion of the sidewall structure to form a surface oxide layer, wherein the surface oxide layer protrudes from surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer; forming a leveling layer on the first interlayer dielectric layer, the second interlayer dielectric layer and the surface oxide layer, wherein the leveling layer, the first interlayer dielectric layer and the second interlayer dielectric layer are made of the same material; and The leveling layer, the surface oxide layer, a portion of the first interlayer dielectric layer and a portion of the second interlayer dielectric layer are removed simultaneously, and the surface of the dummy gate is flush with the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer on both sides.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The first interlayer dielectric layer and the second interlayer dielectric layer are silicon oxide. The first interlayer dielectric layer is obtained by high aspect ratio chemical vapor deposition, and the second interlayer dielectric layer is obtained by high density plasma chemical vapor deposition. The second interlayer dielectric layer has compressive stress.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of making the surface of the dummy gate flush with the surfaces of the interlayer dielectric layers on both sides include: forming a first interlayer dielectric layer and a second interlayer dielectric layer in sequence on the contact hole etch stop layer; planarizing the first interlayer dielectric layer, the second interlayer dielectric layer, the contact hole etch stop layer and a portion of the hard mask layer, wherein surfaces of the hard mask layer, a portion of the sidewall structure and the contact hole etch stop layer are lower than surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer on both sides; Oxidizing the hard mask layer, a portion of the contact hole etch stop layer, and a portion of the sidewall structure to form a surface oxide layer, wherein a surface of the surface oxide layer is flush with surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer; and The surface oxide layer, part of the first interlayer dielectric layer and part of the second interlayer dielectric layer are removed simultaneously, and the surface of the dummy gate is flush with the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer on both sides.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for manufacturing the surface oxide layer comprises: placing the substrate after planarizing the interlayer dielectric layer into a plasma chamber; and The chamber is controlled to operate at a preset temperature and a preset power, and oxygen-containing gas and auxiliary gas are introduced to perform oxidation.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The preset temperature is 350° C. to 550° C., and the preset power is 3000W to 14000W.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: The total flow rate of the oxygen-containing gas and the auxiliary gas is 300 sccm to 900 sccm, and the flow rate ratio of the oxygen-containing gas to the auxiliary gas is 1:1 to 2:

1.

10. The method for manufacturing a semiconductor device according to claim 1, wherein: The remaining preset thickness of the hard mask layer is 3 nm to 5 nm.

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