Preparation method of shield gate groove type power device

Abstract

The invention discloses a preparation method of a shield gate groove type power device, a semiconductor structure used for the shield gate groove type power device and the shield gate groove type power device. The method comprises the steps that a semiconductor substrate is provided, a groove is formed in the semiconductor substrate, and first oxide layers are formed on the surface of the substrate and the side wall of the groove; filling polycrystalline silicon in the groove, wherein the surface of the polycrystalline silicon is lower than the upper surface of the first oxide layer on the surface of the substrate; forming a side wall on the side wall of the groove above the polycrystalline silicon; etching the polycrystalline silicon in the groove to a first depth by taking the side wall as a hard mask; etching the first oxide layer on the side wall of the groove to a second depth, wherein the second depth is smaller than the first depth; removing the side wall, executing thermal oxidation, and forming an oxide layer on the exposed part in the groove; and filling polycrystalline silicon in the first depth part and the second depth part of the groove. According to the scheme provided by the invention, the gate-source capacitance can be reduced, so that the starting speed of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a shielded gate trench power device, a semiconductor structure for a shielded gate trench power device, and a shielded gate trench power device. Background Art

[0002] SGT MOSFET (Shielded Gate Trench Metal-Oxide-Semiconductor Field-Effect Transistor) is a high-performance power semiconductor device designed to provide lower on-resistance and smaller switching losses than traditional normal trench MOSFET. SGT MOSFET technology mainly relies on thermal oxide growth process to form the inter-gate dielectric layer, which can produce high-quality silicon dioxide on the silicon surface. ), used as a gate insulation layer. In addition, by introducing a shielded gate structure, SGT MOSFET can reduce on-resistance and switching losses, improving the overall performance of the device.

[0003] However, SGT MOSFET devices have various parasitic capacitances between the source, drain, and gate, which will affect the turn-on speed of the device. Therefore, how to improve the turn-on speed of the device has become a technical problem that needs to be solved urgently. Summary of the Invention

[0004] This application provides a method for preparing a shielded-gate trench power device, a semiconductor structure for a shielded-gate trench power device, and a shielded-gate trench power device, which can reduce the integrated capacitance between the gate and source, thereby improving the turn-on speed of the device. The specific solution is as follows: In a first aspect, an embodiment of the present application provides a method for preparing a shielded gate trench power device, the method comprising: providing a semiconductor substrate, wherein a trench is formed on the semiconductor substrate, and a first oxide layer is formed on the substrate surface and the sidewalls of the trench; filling the trench with polysilicon, and the surface of the polysilicon is lower than the upper surface of the first oxide layer on the substrate surface; forming a sidewall on the sidewall of the trench above the polysilicon; using the sidewall as a hard mask, etching the polysilicon in the trench to a first depth; etching the first oxide layer on the sidewall of the trench to a second depth, and the second depth is less than the first depth; removing the sidewall, and performing thermal oxidation to form an oxide layer in the exposed portion of the trench; and filling the first depth portion and the second depth portion of the trench with polysilicon.

[0005] Optionally, the filling of polysilicon in the groove, wherein the surface of the polysilicon is lower than the upper surface of the first oxide layer on the surface of the substrate, includes: depositing polysilicon on the surface of the substrate and in the groove until the trench is completely filled with polysilicon; grinding the polysilicon and the first oxide layer deposited on the surface of the substrate until the thickness of the first oxide layer on the surface of the substrate is 1000A~2000A; etching the polysilicon in the groove so that the surface of the polysilicon is lower than the upper surface of the first oxide layer on the surface of the substrate.

[0006] Optionally, forming a sidewall on the trench sidewall above the polysilicon includes: depositing a barrier layer on the first oxide layer on the surface of the substrate, the upper surface of the polysilicon, and the trench sidewall above the polysilicon; removing the barrier layer on the surface of the substrate and the barrier layer on the upper surface of the polysilicon, retaining the barrier layer on the trench sidewall above the polysilicon, so as to form a sidewall on the trench sidewall above the polysilicon.

[0007] Optionally, etching the polysilicon in the trench to a first depth includes: anisotropically etching the polysilicon in the trench to the first depth using a dry method to retain the polysilicon under the sidewall.

[0008] Optionally, the method for preparing the shielded gate trench power device also includes: during or after the process of using dry anisotropic etching of the polysilicon in the trench, using a set proportion of isotropic etching to remove part of the polysilicon under the side wall to form a trumpet-shaped opening between the polysilicon under the side wall.

[0009] Optionally, etching the first oxide layer of the trench sidewall to a second depth includes: covering the area that does not need to be etched through a photolithography process; performing wet etching to remove the first oxide layer exposed on the surface of the semiconductor substrate, and etching the first oxide layer of the trench sidewall so that the depth of the area between the trench sidewall and the polysilicon sidewall formed below the sidewall is the second depth; and removing the photoresist in the photolithography process.

[0010] Optionally, the removing of the sidewall, performing thermal oxidation, and forming an oxide layer on the exposed portion in the trench include: removing the sidewall by etching, performing thermal oxidation, forming an oxide layer on the polysilicon sidewall formed below the sidewall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewall above the first oxide layer in the trench, and partially oxidizing the polysilicon sidewall formed below the sidewall in the trench; removing the oxide layer on the trench sidewall above the first oxide layer in the trench and the oxide layer on the substrate surface; performing thermal oxidation, forming an oxide layer on the polysilicon sidewall formed below the sidewall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewall above the first oxide layer in the trench, and completely oxidizing the polysilicon sidewall formed below the sidewall in the trench.

[0011] Optionally, the removing of the sidewall and performing thermal oxidation to form an oxide layer in the exposed portion of the trench include: cleaning the trench sidewall above the first oxide layer in the trench and the surface of the substrate to remove impurities on the trench sidewall above the first oxide layer in the trench and impurities on the surface of the substrate; performing thermal oxidation to form an oxide layer on the polysilicon sidewall formed below the sidewall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewall above the first oxide layer in the trench, and completely oxidizing the polysilicon sidewall formed below the sidewall in the trench.

[0012] Optionally, filling the first depth portion and the second depth portion of the trench with polysilicon includes: depositing polysilicon on the first depth portion, the second depth portion of the trench and the oxide layer on the surface of the substrate; and grinding and / or etching the deposited polysilicon to form three sub-gates separated from each other.

[0013] Optionally, after forming three mutually separated sub-gates, the method further includes: implanting source regions and body regions, depositing an interlayer dielectric layer, and etching contact holes on the semiconductor substrate to form a source electrode, a gate electrode, and a drain electrode.

[0014] Optionally, the thickness of the first oxide layer formed on the substrate surface and the trench sidewall is 1000Å~20000Å.

[0015] Optionally, the polysilicon surface is lower than the upper surface of the first oxide layer on the substrate surface, including: the polysilicon surface is lower than the upper surface of the first oxide layer on the substrate surface, and the height difference between the polysilicon surface and the upper surface of the first oxide layer on the substrate surface is 1500A~2000A.

[0016] Optionally, the barrier layer is one of SIN, SION, and SIHN.

[0017] In a second aspect, an embodiment of the present application provides a semiconductor structure for a shielded gate trench-type power device, comprising: a semiconductor substrate having a trench formed therein and a gate oxide layer formed on the sidewalls of the trench; a shielding gate arranged in the bottom area of ​​the trench on the gate oxide layer; mutually discrete sub-gates arranged in the upper area of ​​the trench and located above the shielding gate; the mutually discrete sub-gates are divided by an oxide layer; wherein at least one sub-gate is staggered a set distance relative to the shielding gate in a direction perpendicular to the depth.

[0018] Optionally, there are three mutually separated sub-grids, the sub-grid located in the middle is opposite to the shielding grid, and the other two sub-grids are arranged on both sides of the sub-grid located in the middle.

[0019] Optionally, there are two separate sub-grids, which are placed side by side.

[0020] In a third aspect, the present application also provides a shielded gate trench power device, which is prepared by the method described in the first aspect.

[0021] Compared with the prior art, this application has the following advantages: It can be seen that the preparation method of the shielded gate trench type power device provided by the embodiment of the present application is to fill the source polysilicon with a surface lower than the upper surface of the first oxide layer on the surface of the substrate in the trench, so that a groove with a polysilicon bottom and a first oxide layer on the sidewall can be formed in the trench; then, by forming a sidewall on the sidewall of the groove, the sidewall is used as a hard mask, and the polysilicon in the trench can be etched to form a first depth portion in the trench while protecting the polysilicon below the sidewall from being etched, so that a polysilicon sidewall can be formed below the sidewall; then, based on the sidewall and the polysilicon sidewall below it, the first oxide layer on the sidewall of the trench can be etched, and the first oxide layer on the sidewall of the trench can be etched. The second depth to which the oxide layer is etched is less than the first depth to which the polysilicon in the trench is etched. In this way, a second depth portion can be formed on both sides of the first depth portion in the trench, with the depth of the first depth portion being greater than the depth of the second depth portion. Subsequently, the sidewall spacers are removed, and thermal oxidation is performed to oxidize the polysilicon sidewalls in the trench to form an oxide layer. Finally, the first depth portion and the second depth portion are filled with polysilicon, thereby forming a floating polysilicon in the first depth portion and two sub-gates in the second depth portion. In this way, a tri-gate structure is formed, located in the upper region of the trench and above the shield gate, and having two left and right sub-gates and a floating polysilicon in the middle. It can be seen that due to the reduction in the facing area between the left and right sub-gates and the shield gate, the integrated capacitance between the gate and the source can be effectively reduced, thereby improving the turn-on speed of the device.

[0022] In addition, the preparation method of the shielded gate trench type power device provided in the embodiment of the present application has no gate-source leakage problem because the gate polysilicon (two left and right sub-gates) and the shielding gate are staggered and there is no inter-gate oxide layer in between. Therefore, it can ensure that the gate-source leakage is no longer affected by the interlayer oxide layer between the shielding gate and the control gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a flow chart of a method for preparing a shielded gate trench power device provided in this application.

[0024] Figure 2 It is a schematic diagram of an example of a semiconductor substrate provided in the method for preparing a shielded gate trench power device provided in an embodiment of the present application.

[0025] Figure 3 This is a schematic diagram of an example of forming a first oxide layer on the substrate surface and the trench sidewall in the method for preparing a shielded gate trench power device provided in the present application.

[0026] Figure 4 This is a schematic diagram of an example of filling polysilicon in a trench in a method for preparing a shielded gate trench power device provided in an embodiment of the present application.

[0027] Figure 5 This is a schematic diagram of an example of filling polysilicon in a trench in a method for preparing a shielded gate trench power device provided in an embodiment of the present application.

[0028] Figure 6 This is a schematic diagram of an example of etching polysilicon filled in a trench in a method for preparing a shielded gate trench power device provided in an embodiment of the present application.

[0029] Figure 7 It is a schematic diagram of an example of depositing a barrier layer in the method for preparing a shielded gate trench power device provided in an embodiment of the present application.

[0030] Figure 8 This is a schematic diagram of an example of removing the barrier layer outside the trench in the method for preparing the shielded gate trench power device provided in an embodiment of the present application.

[0031] Figure 9 This is a schematic diagram of an example of etching polysilicon using a sidewall as a hard mask in the method for preparing a shielded gate trench power device provided in an embodiment of the present application.

[0032] Figure 10 This is a schematic diagram of an example of etching the first oxide layer on the trench sidewall in the method for preparing a shielded gate trench power device provided in an embodiment of the present application.

[0033] Figure 11, which is a three-dimensional schematic diagram of an example of the polysilicon sidewall and the source polysilicon below in the shielded gate trench power device provided by an embodiment of the present application.

[0034] Figure 12 This is a schematic diagram of an example of removing the sidewall in the method for preparing the shielded gate trench power device provided in an embodiment of the present application.

[0035] Figure 13 This is a schematic diagram of an example of performing a thermal oxidation step for the first time on the exposed portion in the trench in the method for preparing a shielded gate trench power device provided by an embodiment of the present application.

[0036] Figure 14 This is a schematic diagram of an example of removing the oxide layer on the surface of the polysilicon in the trench and the oxide layer on the surface of the substrate in the method for preparing the shielded gate trench power device provided in an embodiment of the present application.

[0037] Figure 15 This is a schematic diagram of an example of performing a second thermal oxidation step on the exposed portion in the trench in the method for preparing a shielded gate trench power device provided by an embodiment of the present application.

[0038] Figure 16 This is a schematic diagram of an example of filling polysilicon in a first depth portion and a second depth portion of a trench in a method for preparing a shielded gate trench power device provided in an embodiment of the present application.

[0039] Figure 17 This is a schematic diagram of an example of processing gate polysilicon in the method for preparing a shielded gate trench power device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The following description sets forth many specific details to facilitate a thorough understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the scope of the present application. Therefore, the present application is not limited to the specific implementations disclosed below.

[0041] It should be noted that the terms "first", "second", "third", etc. in the claims, description and drawings of the present application are used to distinguish similar objects and are not used to describe a specific order or sequence. The data used in this way are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than that illustrated or described herein. In addition, the terms "including", "having" and their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0042] It should be understood that in the embodiments of the present application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "Including A, B and / or C" means including any one, any two, or any three of A, B, and C.

[0043] It should be understood that in the embodiments of the present application, "B corresponding to A," "B corresponding to A," "A corresponds to B," or "B corresponds to A" means that B is associated with A and B can be determined based on A. Determining B based on A does not mean determining B based solely on A; B can also be determined based on A and / or other information.

[0044] Existing SGT MOSFET technology mainly relies on thermal oxygen growth process to form the inter-gate dielectric layer. This method can produce high-quality silicon dioxide on the silicon surface ( ), used as a gate insulating layer. In addition, by introducing a shielded gate structure, the SGT MOSFET effectively reduces the on-resistance and switching loss, and improves the overall performance of the device. However, on the one hand, there are various parasitic capacitances between the source, drain, and gate, which will increase the input capacitance and reduce the turn-on speed of the device; on the other hand, due to the changes in the morphology and thickness of the inter-gate dielectric layer formed by thermal oxidation, a large gate-source leakage current will be generated, which reduces the reliability of the device and limits its performance in high-performance application scenarios. Therefore, there is an urgent need for a method that can reduce the gate-source capacitance while ensuring that the gate-source leakage is no longer affected by the interlayer oxide layer between the shielded gate and the control gate.

[0045] Based on the above reasons, the first embodiment of the present application provides a method for preparing a shielded gate trench power device, which can ensure that the gate-source leakage is no longer affected by the interlayer oxide layer between the shielding gate and the control gate while reducing the integrated capacitance between the gate and the source.

[0046] The technical solution of the present application is described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0047] The following, combined Figures 1 to 17 The present invention introduces a method for preparing a shielded gate trench power device provided in an embodiment of the present application.

[0048] like Figure 1 , which is a flow chart of a method for preparing a shielded gate trench power device provided by the present application, including the following steps S101 to S107.

[0049] Step S101: providing a semiconductor substrate, wherein a trench is formed on the semiconductor substrate, and a first oxide layer is formed on the surface of the substrate and the sidewalls of the trench.

[0050] In semiconductor manufacturing, a semiconductor substrate refers to the fundamental material used to construct semiconductor devices. Semiconductor substrates can include, but are not limited to, pure single-crystalline silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC). The choice of semiconductor substrate material can be tailored to actual needs during the manufacturing process.

[0051] like Figure 2 , which is a schematic diagram of an example of a semiconductor substrate provided in the method for preparing a shielded gate trench power device provided in an embodiment of the present application, wherein the semiconductor substrate may include an epitaxial layer 02 and a substrate layer 01 , wherein a trench 03 is formed in the epitaxial layer 02 .

[0052] An epitaxial layer is a new material layer with a specific doping concentration and crystal structure grown on an original semiconductor substrate through a process called epitaxial growth (epitaxy, or simply Epi). This process allows the composition, thickness, and doping type and concentration of the new layer to be controlled to achieve specific electrical properties. The epitaxial layer can perfectly match the substrate at the atomic level, forming a continuous crystal structure. The epitaxial layer can be made of the same material as the substrate (homoepitaxy) or a different material (heteroepitaxy); specifically, the epitaxial layer can be based on silicon or silicon carbide.

[0053] It should be noted that the epitaxial layer, which supports the device's current transmission, typically has higher purity and fewer defects than the original substrate. Through epitaxial growth, the dopant type and concentration in the epitaxial layer can be precisely controlled, thereby customizing the desired electrical properties. For example, in a power MOSFET, the breakdown voltage and on-resistance can be optimized by adjusting the doping of the epitaxial layer. Furthermore, during the epitaxial growth process, materials with different doping concentrations or types can be grown layer by layer as needed to form complex multilayer structures. This capability is crucial for the manufacture of high-performance integrated circuits (ICs) and power devices.

[0054] like Figure 3 , which is a schematic diagram of an example of forming a first oxide layer on the substrate surface and the trench sidewalls in the method for preparing a shielded gate trench power device provided by the present application, wherein a first oxide layer 04 is formed on the surface of the epitaxial layer 02 and the sidewalls of the trench 03 .

[0055] The oxide layer refers to a layer of insulating material (usually silicon dioxide) grown or deposited on the sidewalls of the trench (that is, the inner surface of the trench) and the surface of the epitaxial layer after the trench is etched on the semiconductor substrate. ).

[0056] It should be noted that the oxide layer, as a dielectric, provides the necessary electrical isolation, preventing current from flowing directly from the gate to the source or drain. This helps control and manage the current through the channel, ensuring that current flows only under appropriate voltage conditions. Furthermore, forming an oxide layer inside the trench can help optimize the electric field distribution in the channel region. Especially in high-voltage applications, good electric field management can increase the breakdown voltage and enhance device reliability and performance.

[0057] In a specific implementation, the following steps may be performed to form a trench and a first oxide layer in a semiconductor substrate to be processed where the trench and the first oxide layer are not formed: Etching the epitaxial layer 02 of the semiconductor substrate to be processed to form a trench 03; A first oxide layer 04 is formed on the sidewalls of the trench 03 and the surface of the epitaxial layer 02 .

[0058] In this implementation, the thickness of the first oxide layer 04 is 1000A~20000A. This thickness range covers the different requirements of the field oxide layer from low voltage to medium and high voltage MOSFET devices, and can adapt to the application of various voltage platforms. Specifically, the oxide layer can be formed on the sidewalls of the trench and the upper surface of the epitaxial layer by methods such as thermal oxidation or chemical vapor deposition (CVD). Among them, thermal oxidation is a method of growing silicon dioxide ( ) process, thermal oxidation includes dry oxygen oxidation and wet oxygen oxidation. Dry oxygen oxidation refers to the use of pure oxygen as an oxidant to generate a high-quality, dense oxide layer. Wet oxygen oxidation refers to the use of water vapor to react with silicon to generate an oxide layer. The growth rate of wet oxygen oxidation is faster than that of dry oxygen oxidation, but the density of the oxide layer is lower than that of dry oxygen oxidation. Chemical vapor deposition is a technology that uses chemical reactions to deposit thin films on the surface of a substrate.

[0059] Step S102: filling the trench with polysilicon, with the surface of the polysilicon being lower than the upper surface of the first oxide layer on the surface of the substrate.

[0060] This step is used to fill the trench with source polysilicon, and the upper surface of the filled source polysilicon is lower than the upper surface of the first oxide layer on the substrate surface, thereby forming a groove in the trench with the sidewall being the oxide layer and the bottom being the polysilicon.

[0061] In the manufacturing process, step S102 can be specifically implemented through the following steps S201, S202 and S203.

[0062] Step S201: depositing polysilicon on the substrate surface and in the trench until the trench is completely filled with polysilicon.

[0063] like Figure 4 Figure 1 is a schematic diagram illustrating an example of filling a trench with polysilicon in a method for fabricating a shielded gate trench power device according to an embodiment of the present invention. After forming a first oxide layer 04 on the sidewalls of trench 03 and the surface of epitaxial layer 02, source polysilicon is deposited on trench 03 and the surface of epitaxial layer 02 to completely fill trench 03 with source polysilicon 05.

[0064] Step S202: grinding the polysilicon and the first oxide layer deposited on the surface of the substrate until the thickness of the first oxide layer on the surface of the substrate is 1000 Å to 2000 Å.

[0065] like Figure 5 Figure 1 is a schematic diagram illustrating an example of filling a trench with polysilicon in a method for fabricating a shielded gate trench power device according to an embodiment of the present invention. After depositing source polysilicon 05 in trench 03 and on the surface of epitaxial layer 02, chemical mechanical masking is performed on the source polysilicon 05 and first oxide layer 04 deposited on the surface of epitaxial layer 02 until the thickness of first oxide layer 04 on the surface of epitaxial layer 02 reaches 1000 Å to 2000 Å.

[0066] As can be seen from the above introduction, when the first oxide layer is formed on the substrate surface and the trench sidewalls, the thickness of the first oxide layer is 1000A~20000A, and the thickness of the first oxide layer ground to the substrate surface in step S202 is 1000A~2000A. Specifically, if the thickness of the first oxide layer is 1000A~2000A, then the grinding of the polysilicon deposited on the substrate surface and the first oxide layer in step S202 can be stopped at the first oxide layer 04; if the thickness of the first oxide layer is greater than 2000A, then the grinding of the polysilicon deposited on the substrate surface and the first oxide layer in step S202 essentially thins the first oxide layer on the substrate surface. Specifically, the grinding setting can be based on the actual thickness of the first oxide layer formed on the substrate surface and the trench sidewalls, and this application is not limited to this.

[0067] It should be noted that since the first oxide layer on the surface of the substrate is a portion that needs to be removed in subsequent processes, if the thickness of the first oxide layer is greater than 2000 Å (for example, the first oxide layer is 5000 Å, 10000 Å, or 20000 Å), the cost of removing the first oxide layer on the surface of the substrate in subsequent processes will be high. In addition, a large step height difference will be formed between the termination region and the cell region of the device in subsequent processes. As a result, when the polysilicon in the trench is subsequently removed, the step difference will lead to uneven removal rates, which may easily lead to polysilicon residue in low-step regions (such as the cell region), affecting device reliability. If the thickness of the first oxide layer is less than 1000 Å, it will be difficult to effectively protect the underlying epitaxial silicon layer during the subsequent polysilicon etching process, which may cause the epitaxial layer to be over-etched or damaged, thereby affecting device reliability. Therefore, by maintaining the first oxide layer thickness between 1000 Å and 2000 Å in this step, the cost of removing the first oxide layer on the surface of the substrate in subsequent processes can be effectively reduced, and device reliability can be improved.

[0068] Step S203: etching the polysilicon in the trench so that the surface of the polysilicon is lower than the upper surface of the first oxide layer on the surface of the substrate.

[0069] like Figure 6 FIG. 1 is a schematic diagram illustrating an example of etching the polysilicon filled in the trench in a method for fabricating a shielded gate trench power device according to an embodiment of the present invention. After grinding the source polysilicon 05 and the first oxide layer deposited on the surface of the epitaxial layer 02, the source polysilicon 05 in the trench 03 is etched so that the surface of the source polysilicon in the trench 03 is lower than the upper surface of the first oxide layer 04 on the surface of the epitaxial layer 02. This forms a recess in the trench 03 with the first oxide layer 04 as the sidewall and the source polysilicon 05 as the bottom.

[0070] In this implementation, after etching the source polysilicon 05 in the trench 03, the height difference between the surface of the source polysilicon 05 in the trench 03 and the upper surface of the first oxide layer 04 on the surface of the epitaxial layer 02 is 1500A~2000A. The height difference between the surface of the source polysilicon and the upper surface of the first oxide layer on the surface of the epitaxial layer is the vertical height of the sidewall to be formed in the subsequent steps. The height difference here can reserve sufficient vertical height for the sidewall to be formed, so that when the sidewall to be formed is used as a hard mask, the polysilicon directly below the sidewall can be effectively prevented from being etched. That is, Figure 6 The depth of the recess formed in the trench 03 with the sidewall of the first oxide layer 04 and the bottom of the source polysilicon 05 is 1500A~2000A.

[0071] Etching usually includes dry etching and wet etching. Among them, dry etching is to generate plasma by radio frequency power supply under low pressure environment, so that the reaction gas (such as 、 etc.) into active substances such as active ions and free radicals, and remove polysilicon through chemical reaction between active substances and polysilicon. Dry etching has high selectivity and anisotropy; wet etching uses nitric acid ( ), hydrofluoric acid (HF), acetic acid ( ) mixture to dissolve and remove polysilicon, usually using isotropic etching.

[0072] Step S103: forming sidewall spacers on the trench sidewalls above the polysilicon.

[0073] This step is used to form a barrier layer on the sidewall of the groove formed in the trench 03. The barrier layer is used to protect the polysilicon located directly below it, so as to retain the polysilicon located directly below the sidewall when the polysilicon in the trench 03 is subsequently etched for the second time.

[0074] In a specific implementation, step S103 can be implemented through the following steps S204 and S205.

[0075] Step S204: depositing a barrier layer on the first oxide layer on the surface of the substrate, the upper surface of the polysilicon, and the sidewalls of the trench above the polysilicon.

[0076] like Figure 7 FIG2 is a schematic diagram illustrating an example of depositing a barrier layer in a method for fabricating a shielded gate trench power device according to an embodiment of the present invention. After etching the source polysilicon 05 in the trench 03, a barrier layer 06 can be deposited on the first oxide layer 04 on the surface of the epitaxial layer 02, the upper surface of the source polysilicon 05, and the trench sidewalls above the source polysilicon 05.

[0077] It should be noted that the barrier layer 06 is a film layer made of a different material from the first oxide layer 04. For example, the barrier layer 06 can be a nitride film, including but not limited to SIN (silicon nitride), SION (silicon oxynitride), SIHN (silicon hydrogen nitride) and other nitride film layers. In the embodiment of the present application, the thickness of the barrier layer 06 is twice less than the width of the source polysilicon 05, so as to avoid the groove formed in the trench 03 from being blocked. In addition, the thickness of the barrier layer 06 is less than the thickness of the polysilicon that can be consumed in the subsequent S106 thermal oxidation step, so as to ensure that the polysilicon retained below the barrier layer 06 ( Figure 9 When the thermal oxidation step is performed on the polysilicon sidewalls 08 in the barrier layer 06, the polysilicon remaining under the barrier layer 06 can be completely oxidized.

[0078] Step S205: removing the barrier layer on the surface of the substrate and the barrier layer on the upper surface of the polysilicon, and retaining the barrier layer on the trench sidewall above the polysilicon to form a sidewall on the trench sidewall above the polysilicon.

[0079] like Figure 8 FIG. 1 is a schematic diagram illustrating an example of removing a barrier layer outside the trench in a method for fabricating a shielded gate trench power device according to an embodiment of the present invention. After depositing a barrier layer 06 on the first oxide layer 04 on the surface of the epitaxial layer 02, the upper surface of the source polysilicon 05, and the trench sidewalls above the source polysilicon 05, the barrier layer 06 can be etched to remove the barrier layer on the surface of the epitaxial layer 02 and the upper surface of the source polysilicon 05 in the trench 03, leaving the barrier layer 07 on the trench sidewalls above the source polysilicon 05, thereby forming a sidewall on the trench sidewalls above the source polysilicon 05.

[0080] Step S104: using the sidewall spacer as a hard mask, etching the polysilicon in the trench to a first depth.

[0081] This step is used to protect the polysilicon directly below the sidewall from being etched while etching the polysilicon in the trench.

[0082] like Figure 9 Figure 1 is a schematic diagram illustrating an example of etching polysilicon using a sidewall as a hard mask in a method for fabricating a shielded gate trench power device according to an embodiment of the present application. After forming sidewalls 07 on the trench sidewalls above the source polysilicon 05, the source polysilicon 05 in the trench 03 is etched using sidewalls 07 as a hard mask. This protects the source polysilicon directly below sidewalls 07 from being etched while etching the source polysilicon 05, forming polysilicon sidewalls 08.

[0083] In a specific embodiment, dry anisotropic etching of the polysilicon in the trench can be performed to a first depth. Anisotropic etching is a technique that primarily etches in a vertical direction. By using the sidewalls as a hard mask, the source polysilicon in the trench can be etched while retaining the polysilicon beneath the sidewalls, thereby forming polysilicon sidewalls beneath the sidewalls.

[0084] It should be noted that during or after dry anisotropic etching of the polysilicon in the trench, isotropic etching at a set ratio may be used to remove a portion of the polysilicon below the sidewalls to form a trumpet-shaped opening between the polysilicon below the sidewalls. The set ratio may be set based on actual needs. Unlike anisotropic etching, isotropic etching proceeds at the same rate in all directions. In isotropic etching mode, etching occurs not only downward but also laterally, thereby adjusting the thickness of the residual polysilicon on the sidewalls.

[0085] The set ratio of isotropic etching is smaller than that of anisotropic etching. In this way, the thickness of the residual polysilicon on the sidewall can be fine-tuned on the basis of forming the polysilicon sidewall below the sidewall, and the etching angle can be adjusted between 85° and 95° to form a trumpet-shaped opening, which is convenient for filling the gate polysilicon in the subsequent steps, ensuring good coverage and reducing gaps.

[0086] Step S105: etching the first oxide layer on the sidewall of the trench to a second depth, wherein the second depth is smaller than the first depth.

[0087] like Figure 10 FIG2 is a schematic diagram illustrating an example of etching the first oxide layer on the trench sidewalls in a method for fabricating a shielded gate trench power device according to an embodiment of the present invention. After forming polysilicon sidewalls 08 on the trench sidewalls, the first oxide layer 04 on the trench sidewalls can be etched. The second depth to which the first oxide layer 04 on the trench sidewalls 03 is etched is less than the first depth to which the source polysilicon 05 filling the trench 03 is etched.

[0088] Furthermore, etching the first oxide layer on the trench sidewall to the second depth in step S105 can be achieved by the following steps: Cover the area that does not need to be etched by photolithography; Performing wet etching to remove the first oxide layer exposed on the surface of the semiconductor substrate and etching the first oxide layer on the sidewall of the trench so that the depth of the area between the sidewall of the trench and the polysilicon sidewall formed below the sidewall is the second depth; Remove photoresist in the photolithography process.

[0089] It should be noted that the semiconductor substrate also includes an area that does not need to be etched. The area that does not need to be etched can be protected from being etched by coating a photoresist on its surface.

[0090] Combined with attachment Figure 9 To explain, Figure 9 The semiconductor substrate shown includes three trenches 05. The leftmost trench may be an area that does not require etching. A photoresist 06 may be coated on it to protect it from etching during photolithography, thereby playing a role in electric field regulation and improving withstand voltage.

[0091] By applying photoresist in the area that does not need to be etched, wet etching is performed. Wet etching is a process that uses liquid chemical reagents to remove specific parts of the material surface. In this way, the first oxide layer exposed on the surface of the semiconductor substrate can be removed. Figure 9 As shown, the first oxide layer 04 exposed on the surface of the semiconductor substrate not covered by the photoresist 06 is removed by wet etching, and then the first oxide layer on the sidewall of the trench 03 can be further etched so that the depth of the area between the sidewall of the trench 03 and the polysilicon sidewall 08 formed under the sidewall 07 is the second depth. Figure 10 As shown, the photoresist 06 is removed and the subsequent process is continued.

[0092] It should be noted that the attached Figure 10 The cross-sectional view of the shielded gate trench power device is shown in FIG. 8 . The polysilicon sidewall 08 is not a structure standing alone in the trench. Figure 11 As shown, it is a three-dimensional schematic diagram of an example of the polysilicon side wall and the source polysilicon below in the shielded gate trench power device provided by an embodiment of the present application. It can be seen that the polysilicon side wall 08 forms a hollow ring structure connected together on all sides, and its mutual support structure is stable and firm and will not collapse. The source polysilicon 05 below it is a solid structure.

[0093] Step S106: removing the sidewall spacer and performing thermal oxidation to form an oxide layer on the exposed portion in the trench.

[0094] The exposed portion in the groove can be understood as an attached Figure 12 The polysilicon sidewall 08 formed in the trench 03 is completely oxidized into an oxide layer in this step.

[0095] In an optional specific implementation, the polysilicon sidewalls 08 can be completely oxidized by performing a thermal oxidation step. Specifically, thermal oxidation is performed to form an oxide layer on the polysilicon sidewalls formed below the sidewalls in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewalls above the first oxide layer in the trench, and the polysilicon sidewalls formed below the sidewalls in the trench are completely oxidized.

[0096] In another optional specific implementation, considering that an oxide layer is naturally formed on the surface of a semiconductor substrate when it is exposed to air, but this oxide layer is usually not dense enough and may contain many defects and impurities, which may affect the quality of subsequent processes and device performance, an oxide layer can be formed in the exposed portion of the trench by at least the following two implementations: Implementation method 1 includes the following steps S206 to S209: Step S206: removing the sidewalls by etching; like Figure 12 FIG. 1 is a schematic diagram of an example of removing a sidewall in a method for preparing a shielded gate trench power device according to an embodiment of the present invention. After etching the first oxide layer of the trench sidewall to a second depth, the sidewall 07 can be removed by wet etching.

[0097] Step S207: Perform thermal oxidation to form an oxide layer on the polysilicon sidewall formed below the sidewall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewall above the first oxide layer in the trench, and partially oxidize the polysilicon sidewall formed below the sidewall in the trench.

[0098] like Figure 13 FIG. 1 is a schematic diagram illustrating an example of a first thermal oxidation step performed on the exposed portion of a trench in a method for fabricating a shielded gate trench power device according to an embodiment of the present application. After removing the sidewall spacers 07 by etching, thermal oxidation is performed to form an oxide layer 13 on the polysilicon sidewalls 08 in the trench 03, the surface of the polysilicon 05 below the first depth portion of the trench 03, the surface of the epitaxial layer 02, and the trench sidewalls above the first oxide layer 04 in the trench 03.

[0099] Through the above step S207 , the polysilicon sidewall 08 in the trench can be partially oxidized.

[0100] Step S208: removing the oxide layer on the trench sidewall above the first oxide layer in the trench and the oxide layer on the surface of the substrate.

[0101] like Figure 14, which is a schematic diagram of an example of removing the oxide layer on the surface of the polysilicon in the trench and the oxide layer on the surface of the substrate in the method for preparing a shielded gate trench power device provided by an embodiment of the present application. After the oxide layer 13 is formed on the polysilicon sidewall 08 in the trench 03, the surface of the polysilicon 05 below the first depth portion of the trench 03, the surface of the epitaxial layer 02, and the trench sidewall above the first oxide layer 04 in the trench 03, the oxide layer on the trench sidewall above the first oxide layer 04 in the trench 03 and the oxide layer on the surface of the epitaxial layer 02 are completely removed, leaving only the oxide layer on the surface of the polysilicon sidewall 08 in the trench 03. In this way, impurities on the trench sidewall above the first oxide layer 04 in the trench 03 and impurities on the surface of the substrate can be removed.

[0102] Step S209: Perform thermal oxidation to form an oxide layer on the polysilicon sidewall formed below the sidewall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewall above the first oxide layer in the trench, and completely oxidize the polysilicon sidewall formed below the sidewall in the trench.

[0103] This step is used to completely oxidize the polysilicon sidewalls in the trench into an oxide layer.

[0104] like Figure 15 , which is a schematic diagram of an example of performing a second thermal oxidation step on the exposed portion of the trench in the method for preparing a shielded gate trench power device provided by an embodiment of the present application. After completely removing the oxide layer on the trench sidewall above the first oxide layer 04 in the trench 03 and the oxide layer on the surface of the epitaxial layer 02, a thermal oxidation step is performed on the polysilicon sidewall 08 in the trench 03, the surface of the polysilicon 05 below the first depth portion in the trench 03, the surface of the epitaxial layer 02, and the trench sidewall above the first oxide layer 04 in the trench 03, so as to completely oxidize the polysilicon sidewall 08 in the trench 03 into an oxide layer 14, and form an oxide layer on the surface of the polysilicon 05 below the first depth portion in the trench 03, the surface of the epitaxial layer 02, and the trench sidewall above the first oxide layer 04 in the trench 03.

[0105] Optionally, after step S208, the thermal oxidation step in step S209 may not be performed, and a chemical vapor deposition step may be performed to form an oxide layer on the surface of the polysilicon sidewall formed below the sidewall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewall above the first oxide layer in the trench, and the polysilicon sidewall formed below the sidewall in the trench is partially oxidized; or a thermal oxidation step and a chemical vapor deposition step may be performed to form an oxide layer on the surface of the polysilicon sidewall formed below the sidewall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewall above the first oxide layer in the trench, and the polysilicon sidewall formed below the sidewall in the trench is completely oxidized.

[0106] It should be noted that if dry oxygen oxidation is selected as the thermal oxidation method in the present application, the oxidation temperature is generally between 900°C and 1100°C, and the oxidation time depends on the thickness of the oxide layer to be generated. For example, it may take about 2 hours to grow a 100-nanometer-thick oxide layer by dry oxygen oxidation at 1000°C. If wet oxygen oxidation is selected as the thermal oxidation method in the present application, the oxidation temperature is generally between 700°C and 1000°C, and the oxidation time also depends on the thickness of the oxide layer to be generated. However, the speed of wet oxygen oxidation is greater than that of dry oxygen oxidation. For example, it may take about 10 to 15 minutes to grow a 100-nanometer-thick oxide layer by wet oxygen oxidation at 1000°C. It should be noted that the oxidation temperature and oxidation time herein are merely examples and are not intended to limit the present application.

[0107] The second embodiment includes the following steps S210 and S211: Step S210: cleaning the trench sidewalls above the first oxide layer in the trench and the substrate surface to remove impurities on the trench sidewalls above the first oxide layer in the trench and impurities on the substrate surface; Step S211 (same as step S209 in embodiment 1): perform thermal oxidation to form an oxide layer on the polysilicon sidewall formed below the sidewall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewall above the first oxide layer in the trench, and completely oxidize the polysilicon sidewall formed below the sidewall in the trench.

[0108] In order to generate a denser, higher-quality oxide layer on the substrate surface and the trench sidewall, the substrate surface and the trench sidewall may be typically cleaned in step S210 to remove contaminants and naturally formed incomplete oxides. Specifically, the trench sidewall above the first oxide layer in the trench and the substrate surface may be cleaned using one of a hydrofluoric acid (HF) solution, an ammonia-hydrogen peroxide solution (SC-1 cleaning solution), a hydrochloric acid-hydrogen peroxide solution (SC-2 cleaning solution), etc., thereby removing impurities on the trench sidewall above the first oxide layer in the trench and impurities on the substrate surface.

[0109] Then, thermal oxidation is performed to form an oxide layer on the polysilicon sidewalls formed below the trench sidewalls, the polysilicon surface below the first depth portion of the trench, the substrate surface, and the trench sidewalls above the first oxide layer in the trench. Furthermore, the polysilicon sidewalls formed below the trench sidewalls are completely oxidized. Step S211 can refer to the description of step S209 and is not repeated here.

[0110] In the embodiment of the present application, the specific method of forming the gate oxide can be selected based on actual needs and is not specifically limited here.

[0111] Step S107: filling polysilicon in the first depth portion and the second depth portion of the trench.

[0112] This step is used to deposit gate polysilicon.

[0113] like Figure 16 FIG. 1 is a schematic diagram illustrating an example of filling polysilicon at a first depth portion and a second depth portion of a trench in a method for fabricating a shielded gate trench power device according to an embodiment of the present invention. After the polysilicon sidewalls 08 in trench 03 are completely oxidized to form an oxide layer 14, and an oxide layer is formed on the surface of the epitaxial layer and on the trench sidewalls above the first oxide layer 04 in trench 03, gate polysilicon 09 is deposited at the first depth portion and the second depth portion of trench 03.

[0114] In a specific implementation, step S108 can be implemented by the following steps: Depositing polysilicon on the first depth portion, the second depth portion of the trench and the oxide layer on the surface of the substrate; The deposited polysilicon is ground and / or etched to form three sub-gates separated from each other.

[0115] After forming three mutually separated sub-gates, the method for preparing the shielded gate trench device provided in the embodiment of the present application may further include the following steps: The semiconductor substrate is subjected to implantation of source regions and body regions, deposition of an interlayer dielectric layer, and etching of contact holes to form a source electrode, a gate electrode, and a drain electrode.

[0116] like Figure 17 FIG. 1 is a schematic diagram illustrating an example of processing gate polysilicon in a method for fabricating a shielded gate trench power device according to an embodiment of the present application. After depositing gate polysilicon 09, gate polysilicon 09 is ground and / or etched to form three mutually separated sub-gates, namely sub-gate 10, sub-gate 11, and sub-gate 12. Subsequently, the semiconductor substrate is implanted with source and body regions. Ion implantation introduces impurity atoms into specific regions to change the conductivity type (N-type or P-type) of these regions, thereby defining the functional regions of the transistor. An interlayer dielectric layer is then deposited. After the source and body regions are implanted, a layer of insulating material is deposited to isolate the different conductive layers and provide a foundation for subsequent contact hole etching. Contact holes are then etched to form contact holes at locations corresponding to sub-gate 10 and sub-gate 12, respectively, so that the subsequent metal interconnect layer can establish electrical connection with the electrode through the contact holes.

[0117] It can be seen that the preparation method of the shielded gate trench type power device provided by the embodiment of the present application is to fill the source polysilicon with a surface lower than the upper surface of the first oxide layer on the surface of the substrate in the trench, so that a groove with a polysilicon bottom and a first oxide layer on the sidewall can be formed in the trench; then, by forming a sidewall on the sidewall of the groove, the sidewall is used as a hard mask, and the polysilicon in the trench can be etched to form a first depth portion in the trench while protecting the polysilicon below the sidewall from being etched, so that a polysilicon sidewall can be formed below the sidewall; then, based on the sidewall and the polysilicon sidewall below it, the first oxide layer on the sidewall of the trench can be etched, and the sidewall of the trench can be etched. The second depth to which the first oxide layer of the sidewall is etched is less than the first depth to which the polysilicon in the trench is etched, so that a second depth portion can be formed on both sides of the first depth portion in the trench, and the depth of the first depth portion is greater than the depth of the second depth portion; thereafter, the sidewall is removed, and a thermal oxidation step is performed to oxidize the polysilicon sidewall in the trench to form an oxide layer; finally, polysilicon is filled in the first depth portion and the second depth portion, thereby forming a floating polysilicon in the first depth portion and forming two sub-gates in the second depth portion, thus forming a layer located in the upper area of ​​the trench and above the shield gate and having two left and right sub-gates (i.e., attached Figure 17 The sub-gates 10 and 12 in the middle and the floating polysilicon in the middle (also known as the attached Figure 17 The floating polysilicon 11 in the triple gate structure. Figure 17 The sub-grid 10 and sub-grid 12) and the shield grid (also attached Figure 17 The facing area between the source polysilicon 05) under the floating polysilicon 11 is reduced, which can effectively reduce the integrated capacitance between the gate and the source, thereby improving the turn-on speed of the device.

[0118] In addition, the preparation method of the shielded gate trench type power device provided in the embodiment of the present application has no gate-source leakage problem because the gate polysilicon (two left and right sub-gates) and the shielding gate are staggered and there is no inter-gate oxide layer in between. Therefore, it can ensure that the gate-source leakage is no longer affected by the interlayer oxide layer between the shielding gate and the control gate.

[0119] The second embodiment of the present application provides a semiconductor structure for a shielded gate trench power device, comprising: a semiconductor substrate, a trench formed in the semiconductor substrate, a gate oxide layer formed on the sidewalls of the trench; a shielding gate arranged in the bottom area of ​​the trench on the gate oxide layer; mutually separated sub-gates arranged in the upper area of ​​the trench and located above the shielding gate; the mutually separated sub-gates are divided by an oxide layer; wherein at least one sub-gate is staggered relative to the shielding gate by a set distance in a direction perpendicular to the depth. The gate oxide layer in this embodiment is attached Figure 17 The first oxide layer 04 on the sidewall of the middle trench, in this embodiment, the shield gate arranged on the bottom area of ​​the trench on the gate oxide layer is the attached Figure 17 The source polysilicon 05 below the floating polysilicon 11 is shown in FIG. 1 . In this embodiment, the separate sub-gates disposed in the upper region of the trench and above the shielding gate are attached. Figure 17 The sub-gates 10 and 12 shown in FIG. 1 are formed by the oxide layer between the separate sub-gates in this embodiment. Figure 17 The oxide layer 14 in the.

[0120] In an optional embodiment, the number of the mutually separated sub-grids is 3, specifically including the attached Figure 17 The sub-gate 10, sub-gate 12 and floating polysilicon 11 shown in FIG, the sub-gate in the middle (also attached Figure 17 The floating polysilicon 11 shown in FIG. Figure 17 The source polysilicon 05 under the floating polysilicon 11 shown in FIG is opposite, and the other two sub-gates (i.e., the attached Figure 17 The sub-gates 10 and 12 shown in FIG are arranged on both sides of the sub-gate located in the middle.

[0121] The semiconductor structure for the shielded gate trench type power device provided in this embodiment can be obtained by the preparation method of the shielded gate trench type power device provided in the first embodiment of the present application. For details, please refer to the detailed introduction of the preparation method of the shielded gate trench type power device provided in the first embodiment of the present application, which will not be repeated here.

[0122] In another optional embodiment, the number of the mutually separated sub-grids is 2 (i.e. Figure 17 The sub-gates 10 and 12 shown in FIG are placed side by side. In this embodiment, the semiconductor structure does not include any additional Figure 17 The floating polysilicon 11 is shown in FIG.

[0123] It can be seen that the second embodiment of the present application provides a semiconductor structure for a shielded gate trench type power device, comprising: a semiconductor substrate, a trench formed in the semiconductor substrate, and a gate oxide layer formed on the sidewall of the trench; a shielding gate arranged in the bottom area of ​​the trench on the gate oxide layer; mutually discrete sub-gates arranged in the upper area of ​​the trench and located above the shielding gate; the mutually discrete sub-gates are divided by an oxide layer; since at least one sub-gate is staggered by a set distance relative to the shielding gate in the direction perpendicular to the depth, the facing area between the mutually discrete sub-gates arranged in the upper area of ​​the trench and located above the shielding gate and the shielding gate arranged in the bottom area of ​​the trench on the gate oxide layer is reduced, which can effectively reduce the integrated capacitance between the gate and the source, thereby improving the turn-on speed of the device.

[0124] The third embodiment of the present application provides a shielded gate trench type power device, which can be prepared by the preparation method of the shielded gate trench type power device provided by the first embodiment of the present application. For details, please refer to the detailed introduction of the preparation method of the shielded gate trench type power device provided by the first embodiment of the present application, which will not be repeated here.

[0125] Although the present application is disclosed as above with the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims of the present application.

Claims

1. A method for preparing a shielded gate trench power device, characterized in that: The method comprises: Providing a semiconductor substrate, wherein a trench is formed on the semiconductor substrate, and a first oxide layer is formed on the surface of the substrate and the sidewalls of the trench; Filling polysilicon in the trench, with a surface of the polysilicon being lower than an upper surface of the first oxide layer on the surface of the substrate; forming sidewalls on the trench sidewalls above the polysilicon; Using the sidewall as a hard mask, etching the polysilicon in the trench to a first depth; Etching the first oxide layer on the sidewall of the trench to a second depth, wherein the second depth is less than the first depth; removing the sidewall spacer and performing thermal oxidation to form an oxide layer on the exposed portion in the trench; Polysilicon is filled in the first depth portion and the second depth portion of the trench.

2. The method according to claim 1, characterized in that The step of filling the trench with polysilicon, wherein the surface of the polysilicon is lower than the upper surface of the first oxide layer on the surface of the substrate, comprises: Depositing polysilicon on the substrate surface and in the trench until the trench is completely filled with polysilicon; Grinding the polysilicon and the first oxide layer deposited on the surface of the substrate until the thickness of the first oxide layer on the surface of the substrate is 1000 Å to 2000 Å; The polysilicon in the trench is etched so that the surface of the polysilicon is lower than the upper surface of the first oxide layer on the surface of the substrate.

3. The method according to claim 1, characterized in that The step of forming a sidewall on the trench sidewall above the polysilicon comprises: Depositing a barrier layer on the first oxide layer on the surface of the substrate, the upper surface of the polysilicon, and the sidewalls of the trench above the polysilicon; The barrier layer on the surface of the substrate and the barrier layer on the upper surface of the polysilicon are removed, and the barrier layer on the sidewall of the trench above the polysilicon is retained to form a sidewall on the sidewall of the trench above the polysilicon.

4. The method according to any one of claims 1 to 3, characterized in that: The etching of the polysilicon in the trench to a first depth comprises: The polysilicon in the trench is anisotropically etched to a first depth by dry etching to retain the polysilicon below the sidewall.

5. The method according to claim 4, characterized in that Also includes: During or after the dry anisotropic etching of the polysilicon in the trench, isotropic etching with a set ratio is used to remove a portion of the polysilicon below the sidewalls to form a trumpet-shaped opening between the polysilicon below the sidewalls.

6. The method according to claim 1, characterized in that Etching the first oxide layer on the sidewall of the trench to a second depth, comprising: Cover the area that does not need to be etched by photolithography; Performing wet etching to remove the first oxide layer exposed on the surface of the semiconductor substrate and etching the first oxide layer on the sidewall of the trench so that the depth of the area between the sidewall of the trench and the polysilicon sidewall formed below the sidewall is the second depth; Remove photoresist in the photolithography process.

7. The method according to claim 1, 5 or 6, characterized in that: The step of removing the sidewall spacer and performing thermal oxidation to form an oxide layer on the exposed portion of the trench comprises: removing the sidewalls by etching; Performing thermal oxidation to form an oxide layer on the polysilicon sidewall formed below the sidewall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewall above the first oxide layer in the trench, and oxidizing the polysilicon sidewall formed below the sidewall in the trench; removing the oxide layer on the trench sidewall above the first oxide layer in the trench and the oxide layer on the surface of the substrate; Thermal oxidation is performed to form an oxide layer on the polysilicon sidewall formed below the sidewall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewall above the first oxide layer in the trench, and the polysilicon sidewall formed below the sidewall in the trench is completely oxidized.

8. The method according to claim 1, 5 or 6, characterized in that: The performing thermal oxidation to form an oxide layer on the exposed portion of the trench comprises: Cleaning the trench sidewalls above the first oxide layer in the trench and the substrate surface to remove impurities on the trench sidewalls above the first oxide layer in the trench and impurities on the substrate surface; Thermal oxidation is performed to form an oxide layer on the polysilicon sidewall formed below the sidewall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewall above the first oxide layer in the trench, and the polysilicon sidewall formed below the sidewall in the trench is completely oxidized.

9. The method according to claim 1, characterized in that Filling polysilicon in the first depth portion and the second depth portion of the trench comprises: Depositing polysilicon on the first depth portion, the second depth portion of the trench and the oxide layer on the surface of the substrate; The deposited polysilicon is ground and / or etched to form three sub-gates separated from each other.

10. The method according to claim 9, characterized in that After forming three mutually separated sub-grids, it also includes: The semiconductor substrate is subjected to implantation of source regions and body regions, deposition of an interlayer dielectric layer, and etching of contact holes to form a source electrode, a gate electrode, and a drain electrode.

11. The method according to claim 1, wherein The thickness of the first oxide layer formed on the substrate surface and the trench sidewall is 1000Å~20000Å.

12. The method according to claim 1, characterized in that The polysilicon surface is lower than the upper surface of the first oxide layer on the substrate surface, including: the polysilicon surface is lower than the upper surface of the first oxide layer on the substrate surface, and the height difference between the polysilicon surface and the upper surface of the first oxide layer on the substrate surface is 1500A~2000A.

13. The method according to claim 1, wherein The barrier layer is one of SIN, SION and SIHN.

14. A semiconductor structure for a shielded gate trench power device, characterized in that: include: A semiconductor substrate having a trench formed therein and a gate oxide layer formed on sidewalls of the trench; a shielding gate disposed in the bottom region of the trench on the gate oxide layer; Separate sub-gates disposed in the upper region of the trench and located above the shielding gate; The mutually separated sub-gates are divided by an oxide layer; Wherein, at least one sub-grid is staggered with a set distance relative to the shielding grid in a direction perpendicular to the depth direction.

15. The semiconductor structure according to claim 14, wherein: There are three mutually separated sub-grids, the sub-grid located in the middle is opposite to the shielding grid, and the other two sub-grids are arranged on both sides of the sub-grid located in the middle.

16. The semiconductor structure according to claim 14, wherein: There are two mutually independent sub-grids, and the two sub-grids are placed side by side.

17. A shielded gate trench power device, characterized in that: It is prepared by the method according to any one of claims 1 to 13.

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