Input / output driver

Abstract

The invention provides an input / output driver which comprises an electrostatic discharge protection circuit. The electrostatic discharge protection circuit is provided with a silicon controlled rectifier and comprises first to fourth heavily doped regions which are respectively arranged in surface layer regions of first to fourth well regions of a substrate. The first well region to the fourth well region are sequentially arranged along the first direction and are adjacent to each other. The first well region, the third well region, the first heavily doped region and the third heavily doped region have a first conductivity type. The second well region, the fourth well region, the second heavily doped region and the fourth heavily doped region have a second conductivity type. The second heavily doped region further extends into the first well region and the third well region and is next to the first heavily doped region and the third heavily doped region, and the fourth heavily doped region further extends into the third well region and is next to the third heavily doped region.

Description

Technical Field

[0001] The present invention relates to an input / output driver, and in particular to an input / output driver capable of forming an embedded silicon controlled rectifier (SCR) structure. Background Art

[0002] Input / output (I / O) drivers receive input voltages from memory device I / O terminals that vary between high and low logic voltages associated with specific core voltage regions. Traditionally, I / O drivers require additional layout area for each I / O terminal to configure on-chip electrostatic discharge (ESD) diodes and resistors to protect the driver circuits. Given the significant layout area already consumed, further improvements in ESD protection are difficult. Summary of the Invention

[0003] The present invention provides an input / output driver capable of providing better electrostatic protection capability in a manner of effectively utilizing layout area.

[0004] The input / output driver of the present invention includes an electrostatic discharge protection circuit. The electrostatic discharge protection circuit has a silicon-controlled rectifier connected between the input / output terminal and the power supply terminal, and includes a first heavily doped region, a second heavily doped region, a third heavily doped region, and a fourth heavily doped region disposed in the surface region of a first well region, a second well region, a third well region, and a fourth well region, respectively. The first well region to the fourth well region are arranged in sequence along a first direction and are adjacent to each other. The first well region, the third well region, the first heavily doped region, and the third heavily doped region have a first conductivity type. The second well region, the fourth well region, the second heavily doped region, and the fourth heavily doped region have a second conductivity type. The second heavily doped region further extends into the first well region and the third well region, adjacent to the first and third heavily doped regions, and the fourth heavily doped region further extends into the third well region, adjacent to the third heavily doped region.

[0005] Based on the above, the present invention can form a silicon-controlled rectifier in an input / output driver in a manner that effectively utilizes layout area. In this way, it can save layout area while increasing the discharge path and providing better ESD protection, thereby achieving miniaturization and cost reduction requirements.

[0006] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a circuit diagram of an input / output driver according to an embodiment of the present invention;

[0008] Figure 2A yes Figure 1 A partial three-dimensional schematic diagram of an electrostatic discharge protection circuit;

[0009] Figure 2B and Figure 2C It is along Figure 2A A schematic cross-sectional view of the tangent line X-X';

[0010] Figure 2D It is along Figure 2A A schematic cross-sectional view of the tangent line Y-Y';

[0011] Figure 3 An embodiment of the present invention shows how an input / output driver is configured in a memory chip. DETAILED DESCRIPTION

[0012] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0013] Please refer to Figure 1 The input / output driver 100 is, for example, an off-chip driver for a memory device. The input / output driver 100 includes an electrostatic discharge (ESD) protection circuit 110 and a driver circuit 120. The ESD protection circuit 110 includes a diode circuit 112_1, a diode circuit 112_2, a silicon-controlled rectifier 114_1, a silicon-controlled rectifier 114_2, and multiple protection resistors Rp. The diode circuit 112_1 includes multiple diodes connected between the input / output terminal 130 and the power supply terminal 140. The diode circuit 112_2 includes multiple diodes connected between the input / output terminal 130 and the power supply terminal 150. The power supply terminal 140 is configured to receive a ground voltage VSS, and the power supply terminal 150 is configured to receive a power supply voltage VDD. Furthermore, the input / output terminal 130 can be coupled to other memory peripheral circuits or devices via a resistor Re. The resistor Re can, for example, prevent current from flowing to the memory peripheral circuits or devices when the discharge path is insufficient or the current is too high. The resistance value of the resistor Re can be adjusted according to the type and specification of the memory device to which the I / O driver 100 is applicable.

[0014] The silicon-controlled rectifier 114_1 and the diode circuit 112_1 are connected in parallel between the input / output terminal 130 and the power supply terminal 140. The silicon-controlled rectifier 114_2 and the diode circuit 112_2 are connected in parallel between the input / output terminal 130 and the power supply terminal 150. It should be noted that the silicon-controlled rectifiers 114_1 and 114_2 of this embodiment are embedded and formed due to parasitic effects. In other words, the silicon-controlled rectifiers 114_1 and 114_2 are formed between electronic components or circuit modules in the input / output driver 100. Because they are close to each other, they can perform rectification operations without applying a gate voltage. A detailed formation example is described below.

[0015] exist Figure 1 In the embodiment, the driving circuit 120 includes a first driving circuit 120_1 and a second driving circuit 120_2. The first driving circuit 120_1 includes a plurality of driving transistors TD1 connected between corresponding protection resistors Rp and a power supply terminal 140. The second driving circuit 120_2 includes a plurality of driving transistors TD2 connected between corresponding protection resistors Rp and a power supply terminal 150. The protection resistors Rp can prevent current from flowing to the corresponding driving transistors, thereby protecting the driving circuit 120.

[0016] Figure 2A yes Figure 1 A partial three-dimensional schematic diagram of the electrostatic discharge protection circuit 110 is shown. Figure 2B and Figure 2C It is along Figure 2A Schematic diagram of the cross section of the tangent line XX'. Figure 2D It is along Figure 2A Schematic diagram of the cross section of the tangent line Y-Y'.

[0017] Please also refer to Figures 2A to 2D The ESD protection circuit 110 includes a first well 202, a second well 204, a third well 206, a fourth well 208, and a fifth well 210, respectively disposed in a substrate 200, and a first heavily doped region 212, a second heavily doped region 214, a third heavily doped region 216, a fourth heavily doped region 218, and a fifth heavily doped region 220, respectively disposed in surface regions of the first well 202, the second well 204, the third well 206, the fourth well 208, and the fifth well 210. The substrate 200 includes a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.

[0018] The first to fourth well regions 202 to 208 are sequentially arranged along the first direction D1 and are adjacent to each other. The first well region 202 is adjacent to the second well region 204 and the fifth well region 210 on opposite sides. Furthermore, the first heavily doped region 212 and the third heavily doped region 216 are coupled to the input / output terminal 130, and the second heavily doped region 214, the fourth heavily doped region 218, and the fifth heavily doped region 220 are coupled to the power terminal 222.

[0019] The first well region 202, the third well region 206, the first heavily doped region 212, and the third heavily doped region 216 may be doped to have a first conductivity type, and the second well region 204, the fourth well region 208, the fifth well region 210, the second heavily doped region 214, the fourth heavily doped region 218, and the fifth heavily doped region 220 may be doped to have a second conductivity type. In some embodiments, the first conductivity type may be N-type, and the second conductivity type may be P-type. In this case, Figures 2A to 2C The power supply terminal 222 in the Figure 1 The power terminal 140 in the embodiment can be used to receive the ground voltage VSS. In other embodiments, the first conductivity type can also be P type, and the second conductivity type can be N type. In this case, Figures 2A to 2C The power supply terminal 222 in the Figure 1 The power terminal 150 in the circuit can be used to receive a power supply voltage VDD. For example, N-type dopants include phosphorus or arsenic, and P-type dopants may include boron. The dopant concentration of the heavily doped region is greater than the dopant concentration of the well region of the same conductivity type.

[0020] In this embodiment, the second heavily doped region 214 further extends along the first direction D1 into the first well region 202 and the third well region 206 and is adjacent to the first heavily doped region 212 and the third heavily doped region 216. The fourth heavily doped region 218 further extends along the first direction D1 into the third well region 206 and is adjacent to the third heavily doped region 216. The fifth heavily doped region 220 further extends along the first direction D1 into the first well region 202 and is adjacent to the first heavily doped region 212. Therefore, the avalanche breakdown effect of the PN junction can be enhanced, the reverse bias current of the PN junction can be increased, and the threshold voltage between the well region and the heavily doped region can be reduced. In this way, Figure 2B As shown, the first heavily doped region 212 to the fourth heavily doped region 218 of the electrostatic discharge protection circuit 110 can form an embedded silicon controlled rectifier 224 connected between the input / output terminal 130 and the power supply terminal 222 along the first direction D1 due to parasitic effects, thereby increasing the discharge path and providing better electrostatic protection capabilities. It should be noted that when the first conductivity type is N-type and the second conductivity type is P-type, the silicon controlled rectifier 224 can correspond to Figure 1In the case where the first conductivity type is P type and the second conductivity type is N type, the silicon controlled rectifier 224 may correspond to Figure 1 The silicon controlled rectifier 114_2 in the circuit.

[0021] The input / output driver 100 further includes a first diode Did1, a second diode Did2, a third diode Did3, and a fourth diode Did4 connected to the input / output terminal 130 and the power terminal 222. Figure 2C As shown, the first diode Did1 is defined along the first direction D1 at the interface between the first well region 202 and the second well region 204. The second diode Did2 is defined along the first direction D1 at the interface between the second well region 204 and the third well region 206. The third diode Did3 is defined along the first direction D1 at the interface between the third well region 206 and the fourth well region 208. The fourth diode Did4 is defined along the first direction D1 at the interface between the first well region 202 and the fifth well region 210. It should be noted that, in Figure 2C In the embodiment, the direction from the anode to the cathode of the first diode Did1 to the fourth diode Did4 is described by taking the case where the first conductivity type is N type and the second conductivity type is P type as an example. The first diode Did1 to the fourth diode Did4 can be used as Figure 1 If the first conductivity type is P type and the second conductivity type is N type, the direction from the anode to the cathode of the first diode Did1 to the fourth diode Did4 will be the same as Figure 2C The opposite of what is shown in Figure 1 The diode circuit 112_2 includes a diode.

[0022] The first heavily doped region 212 and the third heavily doped region 216 are further connected to the driving circuit 120. Specifically, the first heavily doped region 212 to the fifth heavily doped region 220 extend along the second direction D2 that intersects the first direction D1. In addition, the first heavily doped region 212 and the third heavily doped region 216 are connected to the input / output terminal 130 and the driving circuit 120 at opposite ends. Taking the third heavily doped region 216 as an example, Figure 2D As shown, protection resistors Rp connected between the input / output terminal 130 and the driving circuit 120 may be formed in the third heavily doped region 216 along the second direction D2 .

[0023] Please refer to Figure 3The I / O driver circuit area 300 in the chip includes an ESD protection circuit area 310, a driver circuit area 320, and an I / O terminal area 330. By employing the two-dimensional concept of forming the silicon-controlled rectifier and diode along the first direction D1 and the protection resistor along the second direction D2 in the ESD protection circuit, as described in the above embodiment, the silicon-controlled rectifier, diode, and protection resistor can all be integrated into the ESD protection circuit area 310. This saves approximately 50% of the layout area, achieving miniaturization and cost reduction.

[0024] In summary, the present invention allows for the formation of silicon-controlled rectifiers within input / output drivers while effectively utilizing layout area. Furthermore, the protective resistors used to protect the driver circuits can be integrated into the same area as the silicon-controlled rectifiers. This reduces layout area while increasing the discharge path, providing enhanced ESD protection, and ultimately achieving miniaturization and cost reduction.

[0025] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An input / output driver, characterized in that: include: An electrostatic discharge protection circuit having a silicon-controlled rectifier connected between an input / output terminal and a power supply terminal, comprising: A first heavily doped region, a second heavily doped region, a third heavily doped region and a fourth heavily doped region are respectively arranged in the surface areas of the first well region, the second well region, the third well region and the fourth well region of the substrate, wherein the first well region to the fourth well region are arranged in sequence along a first direction and are adjacent to each other, the first well region, the third well region, the first heavily doped region and the third heavily doped region have a first conductivity type, the second well region, the fourth well region, the second heavily doped region and the fourth heavily doped region have a second conductivity type, the second heavily doped region further extends into the first well region and the third well region and is adjacent to the first heavily doped region and the third heavily doped region, and the fourth heavily doped region further extends into the third well region and is adjacent to the third heavily doped region.

2. The input / output driver according to claim 1, wherein: The first heavily doped region and the third heavily doped region are coupled to the input / output terminal, and the second heavily doped region and the fourth heavily doped region are coupled to the power terminal.

3. The input / output driver according to claim 2, wherein: The power terminal receives a ground voltage.

4. The input / output driver according to claim 2, wherein: The power terminal receives a power voltage.

5. The input / output driver according to claim 1, wherein: The invention also includes a driving circuit, wherein the driving circuit includes a plurality of driving transistors, and the first heavily doped region and the third heavily doped region are further connected to the driving circuit respectively.

6. The input / output driver according to claim 5, wherein: The first to fourth heavily doped regions extend along a second direction intersecting the first direction, and the first heavily doped region and the third heavily doped region are connected to the input / output terminal and the driving circuit at opposite ends, respectively.

7. The input / output driver according to claim 6, wherein: Protection resistors connected between the input / output terminal and the driving circuit are formed in the first heavily doped region and the third heavily doped region, respectively.

8. The input / output driver according to claim 1, wherein: Also included are a plurality of diodes connected between the input / output terminal and the power supply terminal.

9. The input / output driver according to claim 8, wherein: The plurality of diodes include: a first diode defined at an interface between the first well region and the second well region; a second diode defined at an interface between the second well region and the third well region; and The third diode is defined at the interface between the third well region and the fourth well region.

10. The input / output driver according to claim 8, wherein The electrostatic discharge protection circuit further includes a fifth well region having the second conductivity type arranged in the substrate and a fifth heavily doped region arranged in the surface area of ​​the fifth well region. The first well region is adjacent to the second well region and the fifth well region on two opposite sides. The fifth heavily doped region further extends to the first well region and is adjacent to the first heavily doped region. The multiple diodes include a fourth diode defined at the interface between the first well region and the fifth well region.

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