Etching method of semiconductor device and semiconductor device

Abstract

The invention relates to an etching method of a semiconductor device and the semiconductor device, the semiconductor device has a laminated structure and comprises a lower electrode layer, a resistive layer, an upper electrode layer, an organic dielectric layer and a mask layer which are sequentially arranged from bottom to top; the etching method comprises the following steps: etching the organic dielectric layer until the upper electrode layer is exposed to form a patterned organic dielectric layer; etching the upper electrode layer and the resistive layer in sequence until the lower electrode layer is exposed; wherein in the process of etching the upper electrode layer and the resistive layer, at least part of the thickness of the patterned organic dielectric layer is not etched. Taking the semiconductor device as a resistive random access memory as an example, according to the etching method of the semiconductor device provided by the invention, in the process of etching the upper electrode layer and the resistive random access layer, at least part of the thickness of the patterned organic dielectric layer is not etched, so that the thickness of the upper electrode layer is protected to improve the performance and reliability of the resistive random access memory.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an etching method for a semiconductor device and a resistive random access memory. Background Art

[0002] With the rapid development of semiconductor technology, conventional memory can no longer meet people's needs. To meet people's growing demands, non-volatile memory has gradually come into people's view, such as ferroelectric RAM (FeRAM), magnetic RAM (MRAM), phase change RAM (PRAM), and resistive random access RAM (RRAM). Among them, RRAM mainly consists of an upper electrode layer, a resistive switching layer, and a lower electrode layer. It has the advantages of simple structure, high integration density, good fatigue resistance, long data retention time, and compatibility with CMOS.

[0003] In the related art, an inorganic hard mask is used in the etching process of resistive random access memory (PRAM). However, the thickness of the inorganic hard mask cannot be protected during the etching process, resulting in insufficient thickness of the inorganic hard mask after etching. The etchant may penetrate the inorganic mask layer and directly attack the upper electrode layer below, causing loss of the upper electrode layer. The loss of the upper electrode layer will lead to increased contact resistance and uneven current distribution, and may even cause perforation of the upper electrode layer and cause short circuit failure, affecting the performance and reliability of the resistive random access memory. Summary of the Invention

[0004] The present invention aims to solve the problems existing in the related art and proposes an etching method for a semiconductor device, which can protect the thickness of the upper electrode layer and avoid the loss of the thickness of the upper electrode layer, so as to improve the performance and reliability of the semiconductor device.

[0005] The present invention provides an etching method for a semiconductor device, wherein a resistive switching memory has a stacked structure, and the stacked structure includes a lower electrode layer, a resistive switching layer, an upper electrode layer, an organic dielectric layer, and a mask layer arranged in sequence from bottom to top;

[0006] The etching method comprises the following steps:

[0007] Etching the organic dielectric layer until the upper electrode layer is exposed to form a patterned organic dielectric layer;

[0008] The upper electrode layer and the resistive switching layer are sequentially etched until the lower electrode layer is exposed; wherein, during the etching of the upper electrode layer and the resistive switching layer, at least a portion of the patterned organic dielectric layer is not etched.

[0009] Optionally, a bottom anti-reflection layer is provided between the mask layer and the organic dielectric layer;

[0010] Before the step of etching the organic dielectric layer, the etching method includes:

[0011] Etching the bottom anti-reflection layer until the organic dielectric layer is exposed to form a patterned bottom anti-reflection layer;

[0012] The step of etching the organic dielectric layer further includes: completely removing the mask layer to expose the patterned bottom anti-reflection layer.

[0013] Optionally, a dielectric anti-reflection layer is provided between the organic dielectric layer and the upper electrode layer;

[0014] The steps after etching the bottom anti-reflection layer and before sequentially etching the top electrode layer and the resistive switching layer include:

[0015] Etching the organic dielectric layer until the dielectric anti-reflection layer is exposed to form the patterned organic dielectric layer;

[0016] The dielectric anti-reflection layer is etched until the upper electrode layer is exposed to form the patterned dielectric anti-reflection layer, and the patterned bottom anti-reflection layer is completely removed.

[0017] Optionally, the step of etching the dielectric anti-reflection layer includes:

[0018] Mainly etch the dielectric anti-reflection layer to a thickness of the portion;

[0019] Over-etching the remaining thickness of the dielectric anti-reflection layer until the upper electrode layer is exposed;

[0020] During the main etching and the over-etching process, at least a portion of the thickness of the patterned organic dielectric layer is not etched.

[0021] Optionally, the main material of the bottom anti-reflection layer is silicon dioxide;

[0022] The process parameters in the step of etching the bottom anti-reflection layer include:

[0023] a first process gas, wherein the first process gas includes trifluoromethane and tetrafluoromethane, the flow rate of trifluoromethane is 0-200 sccm, the flow rate of tetrafluoromethane is 0-200 sccm, the ratio of trifluoromethane to tetrafluoromethane is 1.5-2.5:1, and trifluoromethane can form a polymer on the sidewall of the patterned bottom anti-reflection layer; or the first process gas includes difluoromethane and tetrafluoromethane, the flow rate of difluoromethane is 0-200 sccm, the flow rate of tetrafluoromethane is 0-200 sccm, the ratio of difluoromethane to tetrafluoromethane is 0.8-1.5:1, and difluoromethane can form a polymer on the sidewall of the patterned bottom anti-reflection layer;

[0024] The chamber pressure is 3-10 mToR; the upper electrode power is 500-1000 W; the lower electrode power is 50-200 W; and the chuck temperature is 30-40°C.

[0025] Optionally, the main material of the organic dielectric layer is organic spin-on carbon;

[0026] The process parameters in the step of etching the organic dielectric layer include:

[0027] a second process gas comprising oxygen, hydrogen bromide, and an inert gas, wherein the flow rate of the oxygen is 20-200 sccm, the flow rate of the hydrogen bromide is 0-100 sccm, the flow rate of the inert gas is 0-200 sccm, and the ratio of the oxygen, hydrogen bromide, and the inert gas is 1:0.5-1.0:1. The hydrogen bromide can form a polymer on the sidewall of the patterned organic dielectric layer;

[0028] The chamber pressure is 3-15 mToor; the upper electrode power is 200-800 W; the lower electrode power is 50-200 W; and the chuck temperature is 30-40°C.

[0029] Optionally, the main material of the dielectric anti-reflection layer is silicon oxycarbide;

[0030] The process parameters in the step of etching the dielectric anti-reflection layer of the main etching portion thickness include:

[0031] a third process gas, wherein the third process gas includes tetrafluoromethane, trifluoromethane, and an inert gas, wherein the flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of trifluoromethane is 20-200 sccm, the flow rate of inert gas is 50-200 sccm, and the ratio of trifluoromethane to tetrafluoromethane is 0.2-0.5:1. Trifluoromethane can form a polymer on the sidewall of the patterned dielectric anti-reflection layer; or, wherein the third process gas includes tetrafluoromethane, difluoromethane, and an inert gas, wherein the flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of difluoromethane is 20-200 sccm, and the ratio of difluoromethane to tetrafluoromethane is 0.1-0.2:1. Difluoromethane can form a polymer on the sidewall of the patterned dielectric anti-reflection layer;

[0032] The chamber pressure is 5-20 mToor; the upper electrode power is 300-1000 W; the lower electrode power is 50-150 W; the chuck temperature is 30-40 ° C;

[0033] The process parameters in the step of over-etching the remaining dielectric anti-reflection layer include:

[0034] The fourth process gas includes tetrafluoromethane and trifluoromethane, the flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of trifluoromethane is 20-200 sccm, trifluoromethane can form a polymer on the side wall of the patterned dielectric anti-reflection layer, and the ratio of trifluoromethane to tetrafluoromethane is: 0.8-1.2:1; or, the fourth process gas includes tetrafluoromethane and difluoromethane, the flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of difluoromethane is 20-200 sccm, the ratio of difluoromethane to tetrafluoromethane is: 0.5-0.8:1, and difluoromethane can form a polymer on the side wall of the patterned dielectric anti-reflection layer.

[0035] Optionally, after the step of sequentially etching the upper electrode layer and the resistive layer until the lower electrode layer is exposed, the etching method further comprises: removing the remaining thickness of the patterned organic dielectric layer until the patterned dielectric anti-reflection layer is exposed.

[0036] Optionally, the process parameters of the step of removing the remaining thickness of the patterned organic dielectric layer until the patterned dielectric anti-reflection layer is exposed include:

[0037] Oxygen, wherein the flow rate of the oxygen is between 300-400 sccm;

[0038] The chamber pressure is 10-20 mToor; the upper electrode power is 1000-1500 W; the lower electrode power is 80-100 W; and the chuck temperature is 30-40°C.

[0039] Optionally, the upper electrode layer includes a first upper electrode layer and a second upper electrode layer arranged sequentially from top to bottom;

[0040] The step of sequentially etching the upper electrode layer and the resistive switching layer until the lower electrode layer is exposed comprises:

[0041] The first upper electrode layer, the second upper electrode layer and the resistive switching layer are sequentially etched until the lower electrode layer is exposed, thereby sequentially forming a patterned first upper electrode layer, a patterned second upper electrode layer and a patterned resistive switching layer.

[0042] Optionally, the process parameters in the step of etching the first top electrode layer include: a fifth process gas, the fifth process gas including chlorine, methane, and an inert gas, the chlorine flow rate being 50-300 sccm, the methane flow rate being 0-200 sccm, the inert gas flow rate being 0-200 sccm, and the ratio of chlorine to methane being 4-8:1; methane being capable of forming a polymer on the sidewall of the patterned first top electrode layer; a chamber pressure being 3-20 mTorr; an upper electrode power being between 600-1000 W; a lower electrode power being between 50-150 W; and a chuck temperature being 30-40° C.;

[0043] And / or, the process parameters of the step of etching the second upper electrode layer and the resistive layer include: a sixth process gas, the sixth process gas including chlorine, boron trichloride and an inert gas, the flow rate of chlorine is 50-150sccm, the flow rate of boron trichloride is between 100-300sccm, the flow rate of the inert gas is between 0-200sccm, and boron trichloride and the inert gas can enhance the physical bombardment effect; the ratio of boron trichloride to chlorine is: 2-4:1; the chamber pressure is 3-20mTorr; the upper electrode power is 800-1200W; the lower electrode power is 50-200W.

[0044] Taking a resistive random access memory as an example, the present invention provides an etching method for a semiconductor device, which has at least the following beneficial technical effects:

[0045] An organic dielectric layer is provided between the upper electrode layer and the mask layer, the organic dielectric layer is preferentially etched to form a patterned organic dielectric layer, and then the upper electrode layer and the resistive switching layer are sequentially etched using the patterned organic dielectric layer as a mask. During the etching of the upper electrode layer and the resistive switching layer, at least a portion of the thickness of the patterned organic dielectric layer is not etched, thereby protecting the thickness of the upper electrode layer and avoiding thickness loss of the upper electrode layer, thereby improving the performance and reliability of the resistive switching memory. At least a portion of the thickness of the patterned organic dielectric layer is not etched, and during the etching process, anisotropic etching in the vertical direction can be achieved, thereby protecting the sidewalls of the patterned upper electrode layer and the patterned resistive switching layer, reducing secondary bombardment of the sidewalls of the patterned upper electrode layer and the patterned resistive switching layer by process gases, avoiding depression of the sidewalls of the patterned upper electrode layer and the patterned resistive switching layer, and ensuring the verticality of the sidewalls of the patterned upper electrode layer and the patterned resistive switching layer.

[0046] The present invention also provides a semiconductor device, including the semiconductor device formed by the etching method described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1( a ) is a schematic structural diagram of a semiconductor device before etching provided by an embodiment of the present invention;

[0048] FIG1( b ) is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention after etching of the bottom anti-reflection layer is completed;

[0049] FIG1( c ) is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention after etching of the organic dielectric layer is completed;

[0050] FIG1( d ) is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention after the main etching of the dielectric anti-reflection layer is completed;

[0051] FIG1(e) is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention after over-etching of the dielectric anti-reflection layer;

[0052] FIG1( f ) is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention after etching of the first upper electrode layer is completed;

[0053] FIG1( g ) is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention after etching of the barrier layer and the second top electrode layer is completed;

[0054] Figure 2 Flowchart 1 of a semiconductor device etching method provided by an embodiment of the present invention;

[0055] Figure 3 A process of etching a semiconductor device provided by an embodiment of the present invention Figure 2 ;

[0056] Figure 4 A process of etching a semiconductor device provided by an embodiment of the present invention Figure 3 .

[0057] Description of reference numerals:

[0058] 1. Mask layer; 2. Bottom anti-reflection layer; 21. Patterned bottom anti-reflection layer; 3. Organic dielectric layer; 31. Patterned organic dielectric layer; 4. Dielectric anti-reflection layer; 41. Patterned dielectric anti-reflection layer; 5. First upper electrode layer; 51. Patterned first upper electrode layer; 6. Second upper electrode layer; 61. Patterned second upper electrode layer; 7. Blocking layer; 71. Patterned blocking layer; 8. Lower electrode layer; 9. First dielectric layer; 10. Second dielectric layer. DETAILED DESCRIPTION

[0059] A related art method for manufacturing a resistive random access memory includes the following steps: forming a stacked structure, the stacked structure including a lower electrode layer, a resistive random access layer, and an upper electrode layer arranged in sequence from bottom to top; forming a mask layer with a predetermined pattern on the above-mentioned stacked structure, the mask layer including a hard mask such as a silicon oxide layer; etching the upper electrode layer using a first plasma etching method; the first process gas used in the first plasma etching method includes a main etching gas and a protective gas that can form by-products on the sidewalls of the pattern (i.e., the sidewalls of the upper electrode formed by etching); etching the resistive random access layer using a second plasma etching method; etching the lower electrode layer using a third plasma etching method; the third process gas used in the third plasma etching method includes a main etching gas and a protective gas. During the etching process of the resistive random access memory, the use of strong bombardment gas (for example, Cl2 / BCl3 / Ar) may result in insufficient hard mask thickness. The strong bombardment gas may penetrate the inorganic mask layer and directly attack the upper electrode layer below, causing loss of the upper electrode layer. The loss of the upper electrode layer will lead to increased contact resistance and uneven current distribution, and may even cause perforation of the upper electrode layer and cause short-circuit failure, affecting the performance and reliability of the resistive random access memory.

[0060] The embodiment of the present invention provides an etching method for a semiconductor device, which can protect the thickness of the upper electrode layer and avoid the loss of the thickness of the upper electrode layer, so as to improve the performance and reliability of the resistive random access memory. The details are as follows. Figure 1(a)-Figure 1(g) as well as Figure 2-Figure 4 The specific embodiments of the present invention are described in detail.

[0061] An embodiment of the present invention provides a semiconductor device. Referring to FIG1 , the semiconductor device has a stacked structure, which includes, from bottom to top, a bottom electrode layer (BEL) 8, a resistive layer (RL) 7, a top electrode layer (TEL), an organic dielectric layer (ODL) 3, and a mask layer (ML) 1; the mask layer 1 is a patterned photoresist (PR).

[0062] Taking a semiconductor device as a resistive random access memory as an example, an embodiment of the present invention provides an etching method for a semiconductor device. For example, an inductively coupled plasma (ICP) etching device can be used to etch the corresponding film layer. The etching device includes a process chamber, an air inlet device, an upper electrode device, and a lower electrode device. The process parameters involved include process gas, chamber pressure, upper electrode power, lower electrode power, and chuck temperature. See Appendix. Figures 1(a)-1(g) And attached Figure 2 , the etching method comprises the following steps:

[0063] S110, etching the organic dielectric layer 3 until the upper electrode layer is exposed, thereby forming a patterned organic dielectric layer 31;

[0064] S130, etching the upper electrode layer and the resistive layer 7 in sequence until the lower electrode layer 8 is exposed; wherein, in the process of etching the upper electrode layer and the resistive layer 7, at least a portion of the thickness of the patterned organic dielectric layer 31 is not etched. In this way, an organic dielectric layer 3 is set between the upper electrode layer and the mask layer 1, and the organic dielectric layer 3 serves as an intermediate buffer layer. On the one hand, the organic dielectric layer 3 can be etched preferentially by adjusting the proportion of process gases to form a patterned organic dielectric layer 31, and then the upper electrode layer and the resistive layer 7 are etched in sequence using the patterned organic dielectric layer 31 as a mask. In the process of etching the upper electrode layer and the resistive layer 7, the upper electrode layer and the resistive layer 7 can be etched preferentially by adjusting the proportion of process gases, while maintaining a low etching rate for the patterned organic dielectric layer 31, so that at least a portion of the thickness of the patterned organic dielectric layer 31 is not etched. The organic dielectric layer 31 is not etched, thereby protecting the upper electrode layer and avoiding thickness loss of the upper electrode layer, thereby improving the performance and reliability of the resistive memory. On the other hand, at least part of the thickness of the patterned organic dielectric layer 31 is not etched. During the etching process, anisotropic etching in the vertical direction can be achieved, which can protect the side walls of the patterned upper electrode layer and the patterned resistive layer 71, reduce the secondary bombardment of the process gas on the side walls of the patterned upper electrode layer and the patterned resistive layer 71, avoid the side walls of the patterned upper electrode layer and the patterned resistive layer from being recessed, and ensure the verticality of the etched side walls.

[0065] 1 , in an embodiment of the present invention, a bottom anti-reflection layer 2 is provided between the mask layer 1 and the organic dielectric layer 3;

[0066] See attached Figures 1(a)-1(g) And attached Figure 2 Before the step of etching the organic dielectric layer 3 until the upper electrode layer is exposed, the etching method includes: S100, etching the bottom anti-reflection layer 2 until the organic dielectric layer 3 is exposed to form a patterned bottom anti-reflection layer 21;

[0067] S110, the step of etching the organic dielectric layer 3 also includes: completely removing the mask layer 1 to expose the patterned bottom anti-reflection layer 21. In this step, the organic dielectric layer 3 is etched using the patterned bottom anti-reflection layer 21 as a mask until the upper electrode layer is exposed, thereby forming a patterned organic dielectric layer 31. In this configuration, a bottom anti-reflection layer 2 is provided between the mask layer 1 and the organic dielectric layer 3. On the one hand, the bottom anti-reflection layer 2 can make the exposure of the patterned photoresist more uniform, reduce the thickness variation and pattern deformation of the photoresist caused by reflection, and thus improve the performance and reliability of the photoresist; on the other hand, the bottom anti-reflection layer 2 can absorb or reduce reflected light, so that the incident light can be better focused on the patterned photoresist, further improving the edge clarity of the pattern after the photoresist is developed, and providing a more accurate mask foundation for subsequent etching.

[0068] 1( a ), in an embodiment of the present invention, a dielectric anti-reflective coating (DARC) 4 is provided between the organic dielectric layer 3 and the upper electrode layer;

[0069] See attached Figures 1(a)-1(g) And attached Figure 3 The steps of etching the bottom anti-reflection layer 2 in step S100 and etching the top electrode layer and the resistive switching layer 7 in step S130 include:

[0070] S110′, etching the organic dielectric layer 3 until the dielectric anti-reflection layer 4 is exposed, thereby forming a patterned organic dielectric layer 31. In this step, the organic dielectric layer 3 is etched using the patterned bottom anti-reflection layer 21 as a mask until the dielectric anti-reflection layer 4 is exposed, thereby forming a patterned organic dielectric layer 31.

[0071] S120: The dielectric anti-reflection layer 4 is etched until the top electrode layer is exposed, forming a patterned dielectric anti-reflection layer 41. The patterned bottom anti-reflection layer 21 is completely removed to expose the patterned organic dielectric layer 31. Thus, the dielectric anti-reflection layer 4 is provided between the organic dielectric layer 3 and the top electrode layer, which can effectively absorb multiple reflections of incident light between the multi-layer interfaces, thereby improving the transfer accuracy of the pattern.

[0072] See attached Figure 1(d)-1(e) And attached Figure 4 In the embodiment of the present invention, S120, the step of etching the dielectric anti-reflection layer 4 includes:

[0073] S121, mainly etching a portion of the dielectric anti-reflection layer 4 to form a patterned dielectric anti-reflection layer 41 with a portion of the thickness, and completely removing the patterned bottom anti-reflection layer 21 to expose the patterned organic dielectric layer 31;

[0074] S122, over-etching the remaining thickness of the dielectric anti-reflection layer 4 until the upper electrode layer is exposed, thereby forming a patterned dielectric anti-reflection layer 41 of the remaining thickness;

[0075] During the main etching and overetching processes, at least a portion of the patterned organic dielectric layer 31 remains unetched. With this configuration, the main etching is used to quickly vertically penetrate the dielectric anti-reflection layer 4; the overetching reduces the etching rate and increases the selectivity between the dielectric anti-reflection layer 4 and the organic dielectric layer 3, preferentially etching the dielectric anti-reflection layer 4 while maintaining a lower etching rate for the patterned organic dielectric layer 31. This ensures that at least a portion of the patterned organic dielectric layer 31 remains unetched, allowing the etching to precisely stop at the top electrode layer, preventing the formation of pits or residues in the top electrode layer.

[0076] 1 (a), in the embodiment of the present invention, the main material of the bottom anti-reflective coating (BRAC) 2 is silicon dioxide (SiO2);

[0077] S120, process parameters in the step of etching the bottom anti-reflection layer 2 include:

[0078] The first process gas is a fluorine-based gas suitable for etching silicon dioxide. The type of the first process gas is not limited, and is as follows:

[0079] For example, the first process gas includes tetrafluoromethane (CF4) and trifluoromethane (CHF3). Tetrafluoromethane, as the main etching gas, decomposes in a plasma environment to produce highly active substances such as fluorine radicals, which react with silicon dioxide to produce volatile products such as silicon tetrafluoride (SiF4) and carbon dioxide (CO2), thereby achieving directional etching of silicon dioxide. Trifluoromethane, as the protective gas, can form a polymer on the sidewalls of the patterned bottom anti-reflection layer 21. Specifically, it decomposes in a plasma environment to produce carbon-containing radicals (such as CF2). During the etching process, the carbon-containing radicals are deposited on the sidewalls of silicon dioxide to form a fluorocarbon polymer film. Since the fluorocarbon polymer has high chemical stability and a higher chemical strength than the etching product silicon tetrafluoride, the deposition of the fluorocarbon polymer on the sidewalls of silicon dioxide can reduce lateral etching, thereby protecting the sidewalls of the patterned bottom anti-reflection layer 21 and forcing the etching to proceed primarily in the vertical direction. That is, while achieving anisotropic etching, the problem of sidewall recess is avoided. Among them, the flow rate of tetrafluoromethane is 0-200 sccm, the flow rate of trifluoromethane is 0-200 sccm, and the ratio of trifluoromethane to tetrafluoromethane is: 1.5-2.5:1. By adjusting the flow rate and ratio of tetrafluoromethane and trifluoromethane, the etching rate and sidewall protection can be balanced.

[0080] For another example, the first process gas includes tetrafluoromethane (CF4) and difluoromethane (CH2F2), wherein tetrafluoromethane is used as the main etching gas, which decomposes in the plasma environment to produce highly active substances such as fluorine free radicals, which react with silicon dioxide to generate volatile products such as silicon tetrafluoride (SiF4) and carbon dioxide (CO2), thereby achieving directional etching of silicon dioxide; difluoromethane is used as the protective gas, and difluoromethane can form a polymer on the side wall of the patterned bottom anti-reflection layer 21; specifically, in the plasma environment The carbon-containing radicals (e.g., CF2) are decomposed in the silicon dioxide sidewalls during the etching process, forming a fluorocarbon polymer film. Since the fluorocarbon polymer has high chemical stability and a higher chemical strength than the etching product, silicon tetrafluoride, the deposition of the fluorocarbon polymer on the silicon dioxide sidewalls can reduce lateral etching, thereby protecting the sidewalls of the patterned bottom anti-reflective layer 21 and forcing the etching to proceed primarily in the vertical direction. This achieves anisotropic etching while avoiding sidewall depression. The difluoromethane flow rate is 0-200 sccm, the tetrafluoromethane flow rate is 0-200 sccm, and the ratio of difluoromethane to tetrafluoromethane is 0.8-1.5:1. By adjusting the flow rates and ratio of tetrafluoromethane to difluoromethane, a balance between etching rate and sidewall protection can be achieved.

[0081] In this step, the process parameters also include: chamber pressure of 3-10 mToR; upper electrode power of 500-1000 W; lower electrode power of 50-200 W; and chuck temperature of 30-40°C. By limiting the chamber pressure within a certain range, uniform plasma distribution is achieved, thereby ensuring uniform etching of the bottom anti-reflection layer 2; limiting the upper electrode power within a certain range can increase the plasma density; limiting the lower electrode power within a certain range can adjust the ion bombardment energy, thereby controlling the directionality of etching and reducing damage; and limiting the chuck temperature within a certain range prevents excessively high temperatures from causing structural deformation of the resistive random access memory, or excessively low temperatures from causing condensation contamination of the resistive random access memory.

[0082] In the embodiment of the present invention, the main material of the organic dielectric layer 3 is organic spin-on-carbon (SOC);

[0083] S110, the process parameters in the step of etching the organic dielectric layer 3 include:

[0084] The second process gas includes oxygen (O2), hydrogen bromide (HBr), and an inert gas. Hydrogen bromide can form polymers on the sidewalls of the patterned organic dielectric layer 31. Oxygen, the primary etching gas, generates plasma that reacts with the organic spin-on carbon (OSC), producing products such as carbon dioxide that are then pumped away. Hydrogen bromide, a gas that hardens the OSC, reacts with hydroxyl groups in the OSC of the organic dielectric layer 3 during the etching process to produce bromide and water, thereby etching the organic dielectric layer 3 and forming the patterned organic dielectric layer 31. Simultaneously, it reacts with silicon dioxide in the patterned dielectric anti-reflective layer 21 to form volatile silicon tetrabromide (SiBr4), which forms a protective layer on the sidewalls of the patterned organic dielectric layer 31 and reduces lateral etching. The inert gas, which can be nitrogen, argon, or helium, acts as a diluent to slow the etching rate and prevent excessive etching due to overreaction. Among them, the flow rate of oxygen is 20-200sccm, the flow rate of hydrogen bromide is 0-100sccm, the flow rate of inert gas is 0-200sccm, and the ratio of oxygen, hydrogen bromide and inert gas is: 1:0.5-1.0:1. By adjusting the flow rate and ratio of oxygen, hydrogen bromide and inert gas, the balanced etching rate and sidewall protection can be achieved.

[0085] In this step, the process parameters also include: chamber pressure of 3-15 mTorr; upper electrode power of 200-800 W; lower electrode power of 50-200 W; and chuck temperature of 30-40°C. By limiting the chamber pressure within a certain range, uniform plasma distribution is achieved, thereby ensuring uniform etching of the organic dielectric layer 3. By limiting the upper electrode power within a certain range, the plasma density can be increased. By limiting the lower electrode power within a certain range, the ion bombardment energy can be adjusted, thereby controlling the directionality of the etching and reducing semiconductor damage. By limiting the chuck temperature within a certain range, excessively high temperatures can be prevented from causing structural deformation of the resistive random access memory, or excessively low temperatures from causing condensation contamination of the resistive random access memory.

[0086] In the embodiment of the present invention, the main material of the dielectric anti-reflection layer 4 is silicon oxycarbide (SiOC);

[0087] S121, the process parameters in the step of etching the dielectric anti-reflection layer 4 to a certain thickness include:

[0088] The third process gas includes a fluorine-based gas and an inert gas, wherein the type of the fluorine-based gas is not limited, and is specifically as follows:

[0089] For example, the third process gas includes tetrafluoromethane (CF4), trifluoromethane (CHF3) and an inert gas, wherein tetrafluoromethane is used as the main etching gas, and the generated plasma reacts with silicon oxycarbide to form volatile gases, such as silicon tetrafluoride (SiF4) and carbon dioxide (CO2), which are extracted; trifluoromethane is used as a protective gas, which can form a polymer on the side wall of the patterned dielectric anti-reflection layer 41, thereby protecting the side wall of the patterned dielectric anti-reflection layer 41; the inert gas can be nitrogen, argon or helium inert gas, which mainly plays the role of dilution gas and auxiliary ignition. Among them, the flow rate of tetrafluoromethane is 20-200sccm, the flow rate of trifluoromethane is 20-200sccm, the flow rate of inert gas is 50-200sccm, and the ratio of trifluoromethane to tetrafluoromethane is: 0.2-0.5:1. With such setting, in the main etching stage, the ratio of tetrafluoromethane is higher than that of trifluoromethane, thereby providing a higher concentration of fluorine free radicals, and the fluorine free radicals react with silicon oxycarbide to achieve rapid etching; trifluoromethane provides a small amount of carbon source to generate a polymer deposited on the side wall of the patterned dielectric anti-reflection layer 41.

[0090] For another example, the third process gas includes tetrafluoromethane (CF4), difluoromethane (CH2F2) and an inert gas, wherein tetrafluoromethane is used as the main etching gas, and the generated plasma reacts with silicon oxycarbide to form volatile gases, such as silicon tetrafluoride (SiF4) and carbon dioxide (CO2), which are extracted; difluoromethane is used as a protective gas, which can form a polymer on the sidewall of the patterned dielectric anti-reflection layer 41 of a partial thickness, thereby protecting the sidewall of the patterned dielectric anti-reflection layer 41; the inert gas can be nitrogen, argon or helium, which mainly plays the role of a dilution gas and assists in ignition. Among them, the flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of difluoromethane is 20-200 sccm, and the ratio of difluoromethane to tetrafluoromethane is: 0.1-0.2:1; with such an arrangement, in the main etching stage, the ratio of tetrafluoromethane is higher than that of difluoromethane, thereby providing a higher concentration of fluorine free radicals, which react with silicon oxycarbide to achieve rapid etching; difluoromethane provides a small amount of carbon source to generate a polymer deposited on the sidewalls of the patterned dielectric anti-reflection layer 41.

[0091] In this step, the process parameters also include: chamber pressure of 5-20mToor; upper electrode power of 300-1000W; lower electrode power of 50-150W; chuck temperature of 30-40°C; by setting it in this way, by limiting the chamber pressure within a certain range, uniform distribution of plasma is achieved, thereby ensuring the uniformity of etching the medium anti-reflection layer 4; by limiting the upper electrode power within a certain range, the plasma density can be increased; by limiting the lower electrode power within a certain range, the ion bombardment energy can be adjusted, thereby controlling the directionality of etching and reducing semiconductor damage; by limiting the chuck temperature within a certain range, the structural deformation of the resistive random access memory due to excessively high temperature, or the condensation contamination of the resistive random access memory due to excessively low temperature is prevented.

[0092] S122, the process parameters in the step of over-etching the remaining dielectric anti-reflection layer 4 include:

[0093] The fourth process gas includes a fluorine-based gas, wherein the type of the fluorine-based gas is not limited, and is specifically as follows:

[0094] For example, the fourth process gas includes tetrafluoromethane (CF4) and trifluoromethane (CHF3). Tetrafluoromethane, serving as the main etching gas, generates plasma that reacts with silicon oxycarbide to form volatile gases, such as silicon tetrafluoride (SiF4) and carbon dioxide (CO2), which are then pumped away. Trifluoromethane, serving as a protective gas, can form a polymer on the sidewalls of the patterned dielectric anti-reflection layer 41, thereby protecting the sidewalls of the patterned dielectric anti-reflection layer 41. The flow rates of tetrafluoromethane and trifluoromethane are 20-200 sccm and 20-200 sccm, respectively. Trifluoromethane can form a polymer on the sidewalls of the patterned dielectric anti-reflection layer 41, and the ratio of trifluoromethane to tetrafluoromethane is 0.8-1.2:1. With this setting, compared with the main etching, the proportion of trifluoromethane in the over-etching is increased, the increase of carbon source promotes the deposition of polymer; the proportion of tetrafluoromethane is reduced, the concentration of fluorine free radicals is reduced, the etching rate is reduced, and the etching is stopped accurately at the upper electrode layer, avoiding the formation of pits or residues in the upper electrode layer.

[0095] For another example, the fourth process gas includes tetrafluoromethane (CF4) and difluoromethane (CH2F2). The tetrafluoromethane serves as the main etching gas, and the generated plasma reacts with silicon oxycarbide to form volatile gases, such as silicon tetrafluoride (SiF4) and carbon dioxide (CO2), which are then pumped away. The difluoromethane serves as the protective gas, and can form a polymer on the sidewalls of the patterned dielectric anti-reflection layer 41 over a certain thickness, thereby protecting the sidewalls of the patterned dielectric anti-reflection layer 41. The flow rates of the tetrafluoromethane and difluoromethane are 20-200 sccm, and the ratio of difluoromethane to tetrafluoromethane is 0.5-0.8:1. The difluoromethane can form a polymer on the sidewalls of the patterned dielectric anti-reflection layer 41. With this setting, compared with the main etching, the proportion of difluoromethane in the over-etching is increased, the increase of carbon source promotes the deposition of polymer; the proportion of tetrafluoromethane is reduced, the concentration of fluorine free radicals is reduced, the etching rate is reduced, and the etching is stopped accurately at the upper electrode layer, avoiding the formation of pits or residues in the upper electrode layer.

[0096] See Figure (g) and Figure 3 In the embodiment of the present invention, after the steps of sequentially etching the upper electrode layer and the resistive layer 7 , the etching method further includes: S140 , removing the remaining thickness of the patterned organic dielectric layer 31 until the patterned dielectric anti-reflection layer 41 is exposed.

[0097] In an embodiment of the present invention, in step S140, the process parameters for removing the remaining thickness of the patterned organic dielectric layer 31 include: oxygen, which is used as the main etching gas, and the generated plasma reacts with the organic spin-on carbon of the patterned organic dielectric layer 41 to form volatile gases such as carbon dioxide, which are then extracted; and an etching selectivity ratio of greater than 10:1 for the patterned dielectric anti-reflection layer 41, the patterned top electrode layer, and the patterned resistive layer 71, thereby ensuring that only the patterned organic dielectric layer 31 is removed without damaging the patterned dielectric anti-reflection layer 41, the patterned top electrode layer, and the patterned resistive layer 71. The oxygen flow rate is between 300 and 400 seem;

[0098] This step also includes process parameters: chamber pressure is 10-20mToor; upper electrode power is 1000-1500W; lower electrode power is 80-100W; chuck temperature is 30-40°C.

[0099] 1( a ), in the embodiment of the present invention, the upper electrode layer includes a first upper electrode layer 5 and a second upper electrode layer 6 arranged sequentially from top to bottom;

[0100] S130, the step of sequentially etching the upper electrode layer and the resistive switching layer 7 includes: sequentially etching the first upper electrode layer 5, the second upper electrode layer 6, and the resistive switching layer 7 until the lower electrode layer 8 is exposed, and sequentially forming a patterned first upper electrode layer 51, a patterned second upper electrode layer 61, and a patterned resistive switching layer 71. Figures 1(e)-1(g) And attached Figure 3 , S130, the steps of etching the upper electrode layer and the resistive layer 7 in sequence include: S131, etching the first upper electrode layer 5 until the second upper electrode layer 6 is exposed, forming a patterned first upper electrode layer 51; S132, etching the second upper electrode layer 6 and the resistive layer 7 until the lower electrode layer 9, the patterned second upper electrode layer 61 and the patterned resistive layer 71 are exposed.

[0101] In an embodiment of the present invention, the main material of the first top electrode layer 5 is one or a combination of titanium nitride (TiN), aluminum (Al), and tungsten (W); for example, the main material of the first top electrode layer 5 is titanium nitride. S131, the process parameters in the step of etching the first top electrode layer 5 include: a fifth process gas, the fifth process gas including chlorine (Cl2), methane (CH4), and an inert gas, wherein chlorine is used as the main etching gas, and the generated plasma reacts with titanium nitride to generate volatile titanium tetrachloride and nitrogen, which are extracted to achieve the etching of the first top electrode layer 5 and form a patterned first top electrode layer 51; methane is used as a protective gas, and methane can form a polymer on the sidewall of the patterned first top electrode layer 51. Specifically, methane is decomposed in the plasma to generate a carbon-containing polymer, which adheres to the sidewall of the patterned first top electrode layer 5, protecting the sidewall from being lateral etching and preventing the sidewall from being concave. The inert gas can be nitrogen, argon, or helium, and mainly serves as a dilution gas and assists in ignition. The chlorine flow rate is 50-300 sccm, the methane flow rate is 0-200 sccm, and the inert gas flow rate is 0-200 sccm, with a chlorine to methane ratio of 4-8:1. This configuration, by limiting the chlorine to methane ratio, provides a certain concentration of chlorine radicals, which dominates the etching rate; methane, under the action of plasma, generates carbon-based polymers to passivate the sidewalls; limiting the chlorine flow rate prevents excessive chlorine flow from increasing the roughness of the sidewalls of the first top electrode layer 5; limiting the methane flow rate prevents excessive methane flow from causing residue accumulation on the top; and limiting the inert gas flow rate assists plasma ignition and dilutes the concentration of the reactive gas.

[0102] In this step, the process parameters also include: chamber pressure of 3-20mTorr; upper electrode power of 600-1000W; lower electrode power of 50-150W; and chuck temperature of 30-40°C. By setting the chamber pressure within a certain range, a uniform distribution of plasma is achieved, thereby ensuring uniform etching of the first upper electrode layer 5; by limiting the upper electrode power within a certain range, the plasma density can be increased; by limiting the lower electrode power within a certain range, the ion bombardment energy can be adjusted, thereby controlling the directionality of etching and reducing semiconductor damage; by limiting the chuck temperature within a certain range, excessively high temperatures can be prevented from causing structural deformation of the resistive random access memory, or excessively low temperatures from causing condensation contamination of the resistive random access memory.

[0103] In the embodiment of the present invention, the main material of the second top electrode layer 6 is one or a combination of tantalum (Ta), titanium (Ti), aluminum (Al) and tungsten (W); the main material of the resistive layer 7 is a metal oxide with resistive switching properties, and the metal oxide is hafnium dioxide (HfO2) or nickel oxide (NiO) or zirconium dioxide (ZrO2) or titanium oxide (TiO2) or aluminum oxide (Al2O3);

[0104] Taking the second top electrode layer 6 as an example of a material of tantalum and the resistive layer 7 as an example of a material of hafnium dioxide; S312, the process parameters in the step of etching the second top electrode layer 6 and the resistive layer 7 include:

[0105] The sixth process gas includes chlorine (Cl2), boron trichloride (BCl3) and an inert gas, wherein chlorine is used as the main etching gas, and the generated plasma first reacts with the tantalum of the second upper electrode layer 6 to generate volatile tantalum tetrachloride, which is extracted; boron trichloride is used as an auxiliary etching gas, which has stronger bombardment. After etching the second upper electrode layer 6 to form a patterned second upper electrode layer 61, a combination of chlorine, boron chloride and an inert gas is used for etching. Boron trichloride and an inert gas can enhance the physical bombardment effect and ensure the opening of the hafnium dioxide film layer. At the same time, during the etching process, due to the presence of the patterned organic dielectric layer 31, a non-volatile attachment will be formed that adheres to the sidewalls of the patterned second top electrode layer 61 and the patterned resistive layer 71, preventing the second top electrode layer 6 and the resistive layer 7 from being etched laterally and causing depressions. In addition, due to the presence of the patterned organic dielectric layer 31, during the heavy bombardment process, it can provide a certain degree of protection for the patterned dielectric anti-reflection layer 41, preventing excessive consumption of the patterned dielectric anti-reflection layer 41 during the etching process. The inert gas can be nitrogen, argon, or helium, and mainly serves as a dilution gas and assists in ignition. The flow rate of chlorine is 50-150 sccm, the flow rate of boron trichloride is between 100-300 sccm, the flow rate of the inert gas is between 0-200 sccm, and the ratio of boron trichloride to chlorine is 2-4:1. In this configuration, the chlorine gas mainly reacts chemically with the second electrode layer 6 to form a patterned second electrode layer 61 ; the boron trichloride has a stronger bombardment ability, which can enhance the etching ability of the resistive layer and increase the etching rate of the resistive layer.

[0106] In this step, the process parameters also include: chamber pressure of 3-20mTorr; upper electrode power of 800-1200W; lower electrode power of 50-200W; and chuck temperature of 30-40°C. By limiting the chamber pressure within a certain range, a uniform distribution of plasma is achieved, thereby ensuring uniform etching of the second upper electrode layer 6 and the resistive switching layer 7; limiting the upper electrode power within a certain range can increase the plasma density; limiting the lower electrode power within a certain range can adjust the ion bombardment energy, thereby controlling the directionality of etching and reducing semiconductor damage; and limiting the chuck temperature within a certain range prevents excessively high temperatures from causing structural deformation of the resistive switching memory, or excessively low temperatures from causing condensation contamination of the resistive switching memory.

[0107] An embodiment of the present invention further provides a semiconductor device, including a semiconductor device formed by the etching method described above.

[0108] Referring to Figure 1(a), in an embodiment of the present invention, the semiconductor device has a stacked structure, which includes, from bottom to top, a bottom electrode layer (BEL) 8, a resistive layer (RL) 7, a top electrode layer (TEL), a dielectric anti-reflective coating (DARC) 4, an organic dielectric layer (ODL) 3, a bottom anti-reflective coating (BRAC) 2 and a mask layer (ML) 1; wherein the mask layer 1 is a patterned photoresist (PR).

[0109] Referring to Figure 1(a), in an embodiment of the present invention, the stacked structure further includes a first dielectric layer 9 and a second dielectric layer 10. The first dielectric layer 9 is located below the resistive layer 7, the lower electrode layer 8 is located on the first dielectric layer 9, and the mask layer 1 and the lower electrode layer 8 are positioned relative to each other; the second dielectric layer 10 is located below the first dielectric layer 9.

[0110] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for etching a semiconductor device, characterized in that: The semiconductor device has a stacked structure, which comprises a lower electrode layer (8), a resistive switching layer (7), an upper electrode layer, an organic medium layer (3), and a mask layer (1) arranged in sequence from bottom to top; The etching method comprises the following steps: Etching the organic dielectric layer (3) until the upper electrode layer is exposed, thereby forming a patterned organic dielectric layer (31); The upper electrode layer and the resistive switching layer (7) are sequentially etched until the lower electrode layer (8) is exposed; wherein, during the etching of the upper electrode layer and the resistive switching layer (7), at least a portion of the thickness of the patterned organic dielectric layer (31) is not etched.

2. The etching method of a semiconductor device according to claim 1, wherein: A bottom anti-reflection layer (2) is provided between the mask layer (1) and the organic medium layer (3); Before the step of etching the organic dielectric layer (3), the etching method comprises: Etching the bottom anti-reflection layer (2) until the organic medium layer (3) is exposed, thereby forming a patterned bottom anti-reflection layer (21); The step of etching the organic dielectric layer (3) further comprises: completely removing the mask layer (1) to expose the patterned bottom anti-reflection layer (21).

3. The etching method of a semiconductor device according to claim 2, wherein: A dielectric anti-reflection layer (4) is provided between the organic dielectric layer (3) and the upper electrode layer; The steps after etching the bottom anti-reflection layer (2) and before sequentially etching the upper electrode layer and the resistive switching layer (7) include: Etching the organic dielectric layer (3) until the dielectric anti-reflection layer (4) is exposed, thereby forming the patterned organic dielectric layer (31); The dielectric anti-reflection layer (4) is etched until the upper electrode layer is exposed to form the patterned dielectric anti-reflection layer (41), and the patterned bottom anti-reflection layer (21) is completely removed to expose the patterned organic dielectric layer (31).

4. The etching method of a semiconductor device according to claim 3, wherein: The step of etching the dielectric anti-reflection layer (4) comprises: The dielectric anti-reflection layer (4) is mainly etched to a thickness of the portion; Over-etching the remaining thickness of the dielectric anti-reflection layer (4) until the upper electrode layer is exposed; Wherein, during the main etching and the over-etching process, at least a portion of the thickness of the patterned organic dielectric layer (31) is not etched.

5. The etching method for a semiconductor device according to any one of claims 2 to 4, characterized in that: The main material of the bottom anti-reflection layer (2) is silicon dioxide; The process parameters in the step of etching the bottom anti-reflection layer (2) include: a first process gas, wherein the first process gas comprises trifluoromethane and tetrafluoromethane, the flow rate of trifluoromethane is 0-200 sccm, the flow rate of tetrafluoromethane is 0-200 sccm, the ratio of trifluoromethane to tetrafluoromethane is 1.5-2.5:1, and trifluoromethane can form a polymer on the sidewall of the patterned bottom anti-reflection layer (21); or the first process gas comprises difluoromethane and tetrafluoromethane, the flow rate of difluoromethane is 0-200 sccm, the flow rate of tetrafluoromethane is 0-200 sccm, the ratio of difluoromethane to tetrafluoromethane is 0.8-1.5:1, and difluoromethane can form a polymer on the sidewall of the patterned bottom anti-reflection layer (21); The chamber pressure is 3-10 mToR; the upper electrode power is 500-1000 W; the lower electrode power is 50-200 W; and the chuck temperature is 30-40°C.

6. The etching method for a semiconductor device according to any one of claims 1 to 4, characterized in that: The main material of the organic dielectric layer (3) is organic spin-on carbon; The process parameters in the step of etching the organic dielectric layer (3) include: a second process gas, wherein the second process gas comprises oxygen, hydrogen bromide and an inert gas, wherein the flow rate of the oxygen is 20-200 sccm, the flow rate of the hydrogen bromide is 0-100 sccm, the flow rate of the inert gas is 0-200 sccm, and the ratio of the oxygen, hydrogen bromide and the inert gas is 1:0.5-1.0:1, and the hydrogen bromide can form a polymer on the sidewall of the patterned organic dielectric layer (31); The chamber pressure is 3-15 mToor; the upper electrode power is 200-800 W; the lower electrode power is 50-200 W; and the chuck temperature is 30-40°C.

7. The etching method of a semiconductor device according to claim 4, wherein: The main material of the dielectric anti-reflection layer (4) is silicon oxycarbide; The process parameters in the step of mainly etching the thickness of the dielectric anti-reflection layer (4) include: a third process gas, wherein the third process gas comprises tetrafluoromethane, trifluoromethane and an inert gas, wherein the flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of trifluoromethane is 20-200 sccm, the flow rate of inert gas is 50-200 sccm, the ratio of trifluoromethane to tetrafluoromethane is 0.2-0.5:1, and trifluoromethane can form a polymer on the sidewall of the patterned dielectric anti-reflection layer (41); or, wherein the third process gas comprises tetrafluoromethane, difluoromethane and an inert gas, wherein the flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of difluoromethane is 20-200 sccm, the ratio of difluoromethane to tetrafluoromethane is 0.1-0.2:1, and difluoromethane can form a polymer on the sidewall of the patterned dielectric anti-reflection layer (41); The chamber pressure is 5-20 mToor; the upper electrode power is 300-1000 W; the lower electrode power is 50-150 W; the chuck temperature is 30-40 ° C; The process parameters in the step of over-etching the remaining dielectric anti-reflection layer (4) include: A fourth process gas, wherein the fourth process gas includes tetrafluoromethane and trifluoromethane, the flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of trifluoromethane is 20-200 sccm, the trifluoromethane can form a polymer on the side wall of the patterned dielectric anti-reflection layer (41), and the ratio of trifluoromethane to tetrafluoromethane is 0.8-1.2:1; or, the fourth process gas includes tetrafluoromethane and difluoromethane, the flow rate of tetrafluoromethane is 20-200 sccm, the flow rate of difluoromethane is 20-200 sccm, the ratio of difluoromethane to tetrafluoromethane is 0.5-0.8:1, and difluoromethane can form a polymer on the side wall of the patterned dielectric anti-reflection layer (41).

8. The etching method for a semiconductor device according to any one of claims 3 to 4, characterized in that: After the steps of sequentially etching the upper electrode layer and the resistive switching layer (7), the etching method further comprises: removing the remaining thickness of the patterned organic dielectric layer (31) until the patterned dielectric anti-reflection layer (41) is exposed.

9. The etching method of a semiconductor device according to claim 8, wherein: The process parameters in the step of removing the remaining thickness of the patterned organic dielectric layer (31) include: Oxygen, the flow rate of the oxygen is between 300-400 sccm; The chamber pressure is 10-20 mToor; the upper electrode power is 1000-1500 W; the lower electrode power is 80-100 W; and the chuck temperature is 30-40°C.

10. The etching method for a semiconductor device according to any one of claims 1 to 4, characterized in that: The upper electrode layer comprises a first upper electrode layer (5) and a second upper electrode layer (6) arranged in sequence from top to bottom; The step of sequentially etching the upper electrode layer and the resistive switching layer (7) comprises: The first upper electrode layer (5), the second upper electrode layer (6) and the resistive switching layer (7) are sequentially etched until the lower electrode layer (8) is exposed, thereby sequentially forming a patterned first upper electrode layer (51), a patterned second upper electrode layer (61) and a patterned resistive switching layer (71).

11. The etching method of a semiconductor device according to claim 10, wherein: The process parameters in the step of etching the first upper electrode layer (5) include: a fifth process gas, the fifth process gas including chlorine, methane and an inert gas, the flow rate of chlorine being 50-300 sccm, the flow rate of methane being 0-200 sccm, the flow rate of the inert gas being 0-200 sccm, and the ratio of chlorine to methane being 4-8:1; methane being capable of forming a polymer on the sidewall of the patterned first upper electrode layer (51); a chamber pressure being 3-20 mTorr; an upper electrode power being between 600-1000 W; a lower electrode power being between 50-150 W; and a chuck temperature being 30-40°C; And / or, the process parameters in the step of etching the second upper electrode layer (6) and the resistive layer (7) include: a sixth process gas, the sixth process gas including chlorine, boron trichloride and an inert gas, the flow rate of chlorine being 50-150 sccm, the flow rate of boron trichloride being between 100-300 sccm, the flow rate of the inert gas being between 0-200 sccm, and the boron trichloride and the inert gas being capable of enhancing the physical bombardment effect; the ratio of boron trichloride to chlorine being 2-4:1; the chamber pressure being 3-20 mTorr; the upper electrode power being 800-1200 W; and the lower electrode power being 50-200 W.

12. A semiconductor device, characterized in that: A semiconductor device formed by the etching method according to any one of claims 1 to 11.

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