Layout design method and device, electronic equipment and storage medium

Abstract

The invention provides a layout design method and device, electronic equipment and a storage medium, and is applied to the technical field of computers. According to the method, after candidate risk graphic samples are obtained, sample parameters of the candidate risk graphic samples are adjusted according to production process parameters of an integrated circuit; a target risk graph sample matched with an integrated circuit production process is obtained, a layout and wiring constraint rule is customized based on the target risk graph sample, an initial layout of the integrated circuit is generated according to the layout and wiring constraint rule, the target risk graph is prevented from appearing in the initial layout, and therefore the success rate of layout design is increased. Layout wiring constraint rules are customized before layout wiring, the probability of iterative modification after layout wiring can be effectively reduced, layout design efficiency can be improved, manpower and material resource consumption is saved, the research and development cycle of an integrated circuit is shortened, and actual application requirements are met.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a layout design method, device, electronic device and storage medium. Background Art

[0002] During the integrated circuit (IC) design and manufacturing process, risky patterns within the layout, such as metal tip coupling and sudden changes in via density, have become a key bottleneck restricting chip yield. To address the impact of risky patterns on chip yield, technologies primarily rely on design rule checking and rule pattern matching to verify IC layouts.

[0003] However, based on the existing design process, the design rule check and rule pattern matching check of the integrated circuit layout are performed after layout and routing. Once a risky pattern is found during the check process, the layout and routing must be repeated, and then the design rule check and rule pattern matching check must be performed again. Only after multiple iterations can the final layout be obtained. Not only is the layout design efficiency low, but it also takes up a lot of manpower and material resources, resulting in a long overall R&D cycle for integrated circuits and difficulty in meeting actual application needs. Summary of the Invention

[0004] In view of this, the present application is committed to providing a layout design method, device, electronic device and storage medium to solve the problems in related technologies such as low layout design efficiency, high consumption of manpower and material resources, long integrated circuit R&D cycle, and difficulty in meeting actual application needs.

[0005] In a first aspect, the present application provides a layout design method, comprising:

[0006] Obtaining a candidate risk graph sample, where the candidate risk graph sample is any one of a plurality of risk graph samples in a preset risk graph sample library;

[0007] Adjusting the sample parameters of the candidate risk pattern sample according to the production process parameters of the integrated circuit to obtain a target risk pattern sample that matches the production process of the integrated circuit;

[0008] Customizing layout and routing constraint rules based on the target risk graphic sample;

[0009] An initial layout of the integrated circuit is generated according to the layout and routing constraint rules to avoid the target risk pattern from appearing in the initial layout.

[0010] In an optional embodiment, adjusting the sample parameters of the candidate risk pattern sample according to the production process parameters of the integrated circuit includes:

[0011] Based on the historical data of the layout design, counting the cumulative number of occurrences of the candidate risk graphic samples;

[0012] If the cumulative number of occurrences is greater than a preset number threshold, the sample parameters of the candidate risk pattern sample are adjusted according to the production process parameters of the integrated circuit.

[0013] In an optional implementation, customizing placement and routing constraint rules based on the target risk pattern sample includes:

[0014] Determining a risk assessment index of the target risk pattern sample based on a production process parameter of the integrated circuit, wherein the risk assessment index is used to characterize the impact of the target risk pattern on the layout of the integrated circuit, the target risk pattern being a risk pattern corresponding to the target risk pattern sample;

[0015] If the risk assessment indicator indicates that the target risk pattern affects the generation of the layout of the integrated circuit, a layout and routing constraint rule is customized based on the target risk pattern sample.

[0016] In an optional embodiment, the risk assessment index includes at least one of failure probability, repair complexity and timing margin, wherein:

[0017] The failure probability is used to characterize the possibility that the target risk pattern will cause the layout of the integrated circuit to fail;

[0018] The repair complexity is used to represent the human resources required to repair the target risk pattern in the layout of the integrated circuit;

[0019] The timing margin is used to characterize an allowable range of timing deviation of the integrated circuit.

[0020] In an optional embodiment, the risk assessment indicators include failure probability, repair complexity and timing margin;

[0021] The priority of the failure probability is higher than the priority of the repair complexity and the timing margin;

[0022] If the failure probability is greater than or equal to a preset probability threshold, it is determined that the target risk pattern affects the generation of the layout of the integrated circuit.

[0023] In an optional implementation, if the failure probability is less than the preset probability threshold, the method further includes:

[0024] Calculating a comprehensive evaluation index based on the failure probability, the repair complexity, and the timing margin;

[0025] If the comprehensive evaluation index is greater than or equal to a preset comprehensive index threshold, it is determined that the target risk pattern affects the layout of the integrated circuit.

[0026] In an optional implementation, the initial layout is verified based on the target risk pattern sample;

[0027] If the initial layout includes the target risk pattern, the layout and routing constraint rules are adjusted and the layout of the integrated circuit is regenerated until a target layout that does not include the target risk pattern is obtained.

[0028] In a second aspect, the present application provides a layout design device, comprising:

[0029] An acquisition unit is configured to acquire a candidate risk pattern sample, the candidate risk pattern sample being any one of a plurality of risk pattern samples in a preset risk pattern sample library;

[0030] A matching unit is configured to adjust sample parameters of the candidate risk pattern sample according to production process parameters of an integrated circuit, to obtain a target risk pattern sample matched with the production process of the integrated circuit;

[0031] A customization unit is configured to customize layout and routing constraint rules based on the target risk pattern sample;

[0032] A generation unit is configured to generate an initial layout of the integrated circuit according to the layout and routing constraint rules, to avoid the target risk pattern from appearing in the initial layout.

[0033] In a third aspect, the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, wherein the processor executes the computer program to implement the steps of the layout design method provided in any of the embodiments of the first aspect of the present application.

[0034] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the steps of the layout design method provided in any of the embodiments of the first aspect of the present application.

[0035] Based on the above content, the layout design method provided by the present application, after obtaining the candidate risk graphic sample, adjusts the sample parameters of the candidate risk graphic sample according to the production process parameters of the integrated circuit, obtains the target risk graphic sample that matches the integrated circuit production process, customizes the layout and routing constraint rules based on the target risk graphic sample, and generates the initial layout of the integrated circuit according to the layout and routing constraint rules, thereby avoiding the appearance of the target risk graphic in the initial layout. It can be seen that the layout design method provided by the present application creates customized layout and routing constraint rules based on the target risk graphic sample. The layout and routing constraint rules can avoid the appearance of the target risk graphic in the integrated circuit layout, thereby improving the success rate of the layout design. Moreover, the layout and routing constraint rules are customized before layout and routing, which can effectively reduce the probability of iterative modification after layout and routing, help improve the efficiency of layout design, and thus save manpower and material resources, shorten the integrated circuit research and development cycle, and meet actual application needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 This is a flowchart of a layout design method provided in an embodiment of the present application.

[0038] Figure 2a-2d This is a schematic diagram of the effect of applying the layout design method provided in an embodiment of the present application to avoid a metal bridging risk pattern.

[0039] Figure 3a-3c This is a schematic diagram of the effect of applying the layout design method provided in an embodiment of the present application to avoid another metal bridging risk pattern.

[0040] Figure 4a-4d This is a schematic diagram of the effect of applying the layout design method provided in an embodiment of the present application to avoid another metal bridging risk pattern.

[0041] Figure 5a-5d This is a schematic diagram of the effect of applying the layout design method provided in an embodiment of the present application to avoid a metal open risk pattern.

[0042] Figure 6a-6d This is a schematic diagram of the effect of applying the layout design method provided in an embodiment of the present application to avoid another metal open circuit risk pattern.

[0043] Figure 7a-7dIt is a schematic diagram of the effect of applying the layout design method provided in the embodiment of the present application to avoid risk graphics caused by platform migration.

[0044] Figure 8a-8e It is a schematic diagram of the effect of applying the layout design method provided in the embodiment of the present application to avoid the risk of through-hole failure and thermal resistance bottleneck.

[0045] Figure 9 This is a flowchart of another layout design method provided in an embodiment of the present application.

[0046] Figure 10 This is a structural block diagram of a layout design device provided in an embodiment of the present application.

[0047] Figure 11 This is a structural block diagram of another layout design device provided in an embodiment of the present application.

[0048] Figure 12 This is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0050] As mentioned above, in order to solve the impact of risky graphics on chip yield during the layout design process, the relevant technology is based on the existing design process. After completing the layout and routing processing, the integrated circuit layout is subjected to design rule checking and rule pattern matching checking. Once a risky pattern is found during the inspection process, the layout and routing must be re-performed, and then the design rule checking and rule pattern matching checking must be performed again. Only after multiple iterations can the final layout be obtained. It can be seen that the layout design process in the relevant technology is not only inefficient in layout design, but also occupies a lot of manpower and material resources, resulting in a long overall R&D cycle for integrated circuits, which is difficult to meet actual application needs.

[0051] In order to solve the above technical problems, the present application provides a layout design method, which creates customized layout and routing constraint rules based on target risk graphic samples. Through the layout and routing constraint rules, the target risk graphics can be avoided from appearing in the integrated circuit layout, thereby improving the success rate of layout design. Moreover, the layout and routing constraint rules are customized before layout and routing, which can effectively reduce the probability of iterative modification after layout and routing, help improve layout design efficiency, thereby saving manpower and material resources, shortening the integrated circuit R&D cycle, and meeting actual application needs.

[0052] The layout design method provided in this application is applied to electronic devices, which may be laptops, personal computers (PCs), tablet computers, and other electronic devices that can run the application corresponding to the integrated circuit timing optimization method provided in this application. These are not listed here one by one. In some cases, it can also be applied to servers on the network side. Figure 1 As shown, the layout design method provided in this application includes the following steps.

[0053] S100: Obtain candidate risk graph samples.

[0054] A risk pattern refers to a specific layout structure within an integrated circuit layout that is prone to causing defects or failures and is part of the complete integrated circuit layout. This application provides a preset risk pattern sample library, which includes multiple risk pattern samples. Each risk pattern sample corresponds to a typical risk pattern in a practical application. Based on this, this step obtains any risk pattern sample in the risk pattern sample library as a candidate risk pattern sample.

[0055] Any risk graph sample in the risk graph sample library can be obtained by following the following process:

[0056] First, risk patterns that occur during the integrated circuit layout design process are obtained.

[0057] In an optional embodiment, a risk graph can be obtained based on the yield and defect coordinate positioning report of the tape-out wafer under the same generation process or a similar production process. Specifically, the yield loss point can be accurately associated with the defect coordinates through electrical testing and physical failure analysis, and the defect position can be mapped to the specific layout structure in combination with the design layout database; then the recurring systematic defect coordinates (such as specific metal layer spacing violation areas) are screened, and non-graphic related failure points such as random particles are excluded. Subsequently, the key graphic clips (Clips) around the defect point are extracted, and their topological commonalities (such as dense line ends, minimum spacing corners, etc.) are analyzed. Finally, the risk graph is confirmed through yield correlation statistics (such as a certain graphic appears more than 10 times and the defect rate is >80%).

[0058] In another alternative implementation, the risk patterns can be identified according to the LFD (Litho-friendly Design) photolithography simulation hotspot map in the related art. Specifically, first, key quantitative indicators in the hotspot map are extracted, including edge placement error (EPE), critical dimension deviation, process window sensitivity (such as mask error enhancement factor (MEEF)), light intensity distribution abnormality, and hotspot label confidence, and further, by setting threshold values of the corresponding quantitative indicators, high-risk areas are screened, and positions in the layout where bridging, disconnection, or deformation are prone to occur are located. Then, a layout picture segment containing local environment patterns is intercepted with the hotspot as the center, and finally, actual failure patterns are confirmed through silicon verification and other technologies, and the corresponding risk patterns are obtained.

[0059] In another alternative implementation, the risk patterns can also be obtained according to transmission electron microscope slice data of failed devices in the integrated circuit. Specifically, first, a failed device in yield testing is selected, and a nanometer-precision vertical / horizontal slice sample is prepared at the defect coordinates by a focused ion beam; the microstructure of the failure interface (such as gate oxide breakdown hole, metal electromigration cavity, via misalignment, etc.) is analyzed by high-resolution imaging of the transmission electron microscope, and the material composition anomaly is analyzed by a synchronous correlation energy spectrometer. Subsequently, the transmission electron microscope pattern is superimposed and compared with the original design layout, and the specific layout topology causing the failure is located, after the layout picture segment of the structure is extracted, the causal relationship between the failure mechanism and the pattern sensitivity is verified by three-dimensional topography reconstruction (such as tomography), and finally, the pattern with typical failure physical characteristics is taken as the risk pattern.

[0060] It should be noted that in actual applications, the risk patterns can also be obtained by other means, which will not be described one by one here. As for the specific implementation process of the above three alternative implementations, the parts not described in detail in the present application can be implemented with reference to the related art, and will not be described here.

[0061] Secondly, the common characteristics of each risk pattern are summarized, and a risk pattern sample is constructed. As an alternative implementation, after obtaining a plurality of risk patterns through the foregoing steps, the obtained risk patterns can be divided into different pattern groups according to the structure of the risk patterns, the structures of the risk patterns in the same pattern group are similar, for each pattern group, the common characteristics of the risk patterns in the pattern group are extracted, and the corresponding risk pattern sample is obtained. As for the specific implementation of creating a risk pattern sample according to the common characteristics of the risk patterns, it can be implemented with reference to the related art, and the present application does not make specific limitations thereto.

[0062] All the obtained risk graph samples are centrally managed and stored, that is, the aforementioned preset risk graph sample library is obtained. When executing this step, the risk graph sample library is accessed to obtain candidate risk graph samples.

[0063] S110 , adjusting sample parameters of the candidate risk pattern sample according to the production process parameters of the integrated circuit to obtain a target risk pattern sample that matches the production process of the integrated circuit.

[0064] Based on the creation process of the aforementioned risk pattern samples, it can be seen that the risk pattern samples reflect the common characteristics of the same type of risk patterns, and there must be certain differences between them and the risk patterns generated under a specific production process in actual applications. Based on this, after obtaining the candidate risk pattern samples, it is first necessary to adjust the sample parameters of the candidate risk pattern samples according to the current integrated circuit production process parameters to obtain the target risk pattern samples that match the integrated circuit production process. For example, while ensuring that the overall proportional relationship of each component in the reference risk pattern sample remains unchanged, the width of the metal line and / or the spacing between adjacent metal lines in the reference risk pattern sample is adjusted according to the current integrated circuit production process parameters. For example, the pin layout in the reference risk pattern sample is adjusted according to the integrated circuit production process parameters. In actual applications, it is necessary to adjust the sample parameters of the reference risk pattern sample in combination with the integrated circuit production process parameters until a target risk pattern sample that matches the integrated circuit production process is obtained.

[0065] It is understandable that in the layout of the same integrated circuit, different risk patterns may appear at different times. In other words, some risk patterns may appear multiple times, while some risk patterns may only appear a few times. Considering various factors such as the overall design cycle of the integrated circuit and the time required to avoid risk patterns, the impact of risk patterns that appear less frequently on the effectiveness of the integrated circuit layout is very small, or even negligible. Therefore, such risk patterns can be temporarily left unprocessed, and the subsequent design process will determine whether to further avoid or repair them based on actual test results. For risk patterns that appear multiple times, the need for avoidance design is correspondingly greater.

[0066] Based on the above content, as an optional implementation method, after obtaining the candidate risk graphic samples, the cumulative number of occurrences of the candidate risk graphic samples can be first counted based on the historical data of the layout design. If the obtained cumulative number of occurrences is greater than the preset number threshold, it means that the candidate risk graphic samples have a greater impact on the layout design. In this case, the sample parameters of the candidate risk graphic samples are adjusted according to the production process parameters of the integrated circuit to obtain the corresponding target risk graphic samples; accordingly, if the obtained cumulative number is less than or equal to the preset number threshold, it means that the candidate risk graphic samples have a small impact on the layout design, then the impact of the candidate risk graphic samples can be temporarily ignored, and the subsequent design process will no longer be executed. Furthermore, it can return to S100 to obtain the next candidate risk graphic sample, and so on until the design process for all risk graphic samples is completed.

[0067] As for the specific value of the preset number threshold, it needs to be comprehensively considered in combination with factors such as the requirements for integrated circuit layout quality, chip yield requirements, and the overall situation of the cumulative number of occurrences of each risk graphic sample. This application does not make specific restrictions on this.

[0068] In practical applications, metal bridges and metal opens are two common risk patterns in integrated circuit layout design.

[0069] The primary cause of metal bridging is that, in ultra-deep submicron processes, the feature sizes of integrated circuits are approaching or even smaller than the wavelengths of extreme ultraviolet (EUV) or deep ultraviolet (DUV) lithography. Light diffraction is significant, and the discrepancy between the lithographic pattern and the mask pattern on the silicon wafer is significant. Closely spaced parallel narrow metal lines, metal protrusions, and surface contamination by particles can easily cause metal line bridges during chip manufacturing, ultimately reducing chip yield.

[0070] Figure 2a 、 Figure 3a as well as Figure 4a Three different risk graphics that may cause metal bridging are shown. Figure 2a The risk pattern of double pattern allocation may lead to Figure 2b The second mask shown in red cannot be assigned; Figure 3a The risk graph shown is two adjacent parallel narrow metal lines. If there is particle contamination or foreign matter on the surface during the chip manufacturing process, the following may occur: Figure 3b The situation shown is that two adjacent metal wires are bridged (the yellow part is the bridge point); Figure 4aThe risk graph shown is when two adjacent metal wires are interlaced and the distance between the metal wire endpoints is relatively close. Due to the optical proximity effect during the manufacturing process, the metal wire shape is not completely consistent with the designed shape, which is as shown in the following figure. Figure 4b The bone shape shown could cause a short circuit between two connected metal wires.

[0071] Furthermore, the main causes of metal open circuits are: 1. Insufficient metal filling: In high aspect ratio through holes or trenches, the metal coverage of physical vapor deposition or electroplating is low, forming voids. 2. Over-etching: Deviations in the etching process window lead to local breakage of metal lines, especially in thin layers or narrow line width areas. 3. Stress cracking: The thermal expansion coefficients of different materials (such as copper and other dielectrics) do not match, and the interface separates after thermal cycling. 4. Resistive open: The metal line becomes locally thinner (such as a dish-shaped defect), the resistance increases but is not completely disconnected. Such metal lines will fail under high loads.

[0072] See also Figure 5a as well as Figure 6a As shown in the figure, both risk graphs have the risk of metal open circuit. In practical applications, due to the effect of metal over-etching, the following Figure 5a The wide metal line-narrow metal line-wide metal line pattern shown appears as Figure 5b The defect shown in red is the local thinning of the metal wire; correspondingly, due to the same reason, such as Figure 6a The bone-shaped wire shown in the figure may also have the following appearance during the manufacturing process: Figure 6b The red part in the middle shows the local thinning. In practical applications, the thinner metal wire part is prone to metal open circuit or resistive open circuit, which in turn affects the reliable operation of the integrated circuit.

[0073] Based on the above content, when the respective cumulative times are greater than the corresponding cumulative times threshold, Figure 2a 、 Figure 3a 、 Figure 4a 、 Figure 5a as well as Figure 6a All of them can be used as target risk graph samples to execute subsequent steps. It should be noted that in actual applications, the cumulative number thresholds corresponding to different risk graph samples can be the same or different, and can be determined based on actual design requirements.

[0074] S120 , customizing layout and routing constraint rules based on the target risk graphic sample.

[0075] Based on the above content, it can be seen that if a target risk pattern appears in the layout (i.e., a risk pattern corresponding to the target risk pattern sample), it is very likely to cause integrated circuit abnormalities during the production process. The original intention of this application is to avoid the target risk pattern in the integrated circuit layout as much as possible. In other words, try to ensure that the target risk pattern does not appear in the integrated circuit layout.

[0076] Based on the above content, after determining the target risk pattern sample, layout and routing constraint rules are further customized according to the target risk pattern sample, so as to avoid the target risk pattern from appearing in the integrated circuit layout through the layout and routing constraint rules.

[0077] Following the previous example, for Figure 2a The target risk graph shown in the figure can customize two types of layout and routing constraint rules, namely Figure 2c As shown, increase the spacing between the two metal lines in the layout and routing constraints, or, as shown in Figure 2d As shown, the layout and routing constraint rules prohibit the generation of U-shaped metal lines (i.e., prohibit the appearance of Figure 2d dotted part of Figure 3a The target risk graph shown can increase the distance between adjacent metal lines in the layout and routing constraint rules to avoid the situation where the metal spacing is too small. Furthermore, it can also be required to insert filling cells between adjacent metal lines as a transition. Figure 4a The target risk graph shown in the figure can increase the routing requirements in the layout and routing constraint rules to increase the parallel length of the adjacent metal wire ends, such as Figure 4c As shown, or, as Figure 4d As shown, the spacing between adjacent metal lines in such target risk patterns is increased in the placement and routing constraint rules.

[0078] Further, for Figure 5a The target risk graph shown can be used to add restrictions in the layout and routing constraint rules, requiring that during the first wiring process of the integrated circuit, Figure 5c As shown, increase the width of the thin metal, or, use Figure 5d The method shown in the figure increases the spacing between thin metal lines and wide metal lines, thereby effectively avoiding over-etching during the manufacturing process. Figure 6a The target risk pattern of the bone shape shown can be restricted in the layout and routing constraint rules by filling the concave part (such as Figure 6c as shown) or cutting the raised portion (as Figure 6d The method shown in the figure ensures that the metal wire has a rectangular shape and avoids the shape of bones.

[0079] It is understandable that the possibility of different risk patterns causing integrated circuit layout failure is different, and the complexity of repairing different risk patterns and the integrated circuit timing changes caused by repairing risk patterns are also different. Therefore, in actual applications, whether to customize layout and routing constraint rules based on target risk pattern samples needs to be comprehensively considered in combination with at least the aforementioned factors in order to strike a balance between the repair cost and the beneficial improvements brought about by the repair.

[0080] Based on the above content, the present application provides a preferred implementation method. After obtaining the target risk graphic sample, the risk evaluation index of the target risk graphic sample is first determined based on the production process parameters of the integrated circuit, wherein the risk evaluation index described in this embodiment is used to characterize the impact of the target risk graphic on the layout of the integrated circuit. Furthermore, if the obtained risk evaluation index characterizes that the target risk graphic affects the layout of the generated integrated circuit, then refer to the above content and customize the layout and routing constraint rules based on the target risk graphic sample. On the contrary, if the obtained risk evaluation index characterizes that the target risk graphic will not affect the layout of the generated integrated circuit, the current execution process can be exited.

[0081] In an optional embodiment, the risk assessment index includes at least one of failure probability, repair complexity and timing margin. Of course, in practical applications, other risk assessment indicators can be set in combination with actual design requirements to evaluate the impact of the target risk graph on the integrated circuit layout generation process. They are not listed one by one here. As long as they do not exceed the core idea of ​​this application, they also fall within the scope of protection of this application.

[0082] Specifically, the failure probability is used to characterize the possibility that the target risk pattern will cause the layout of the integrated circuit to fail. In an optional embodiment, the failure probability can be calculated according to the following formula:

[0083]

[0084] Among them, P fail represents the probability of failure;

[0085] A0 represents the preset coefficient, which can be selected according to actual conditions in practical applications;

[0086] DSI stands for Design Sensitivity Index, a key parameter used to quantitatively evaluate the sensitivity of graphics in a layout to process fluctuations.

[0087] It should be noted that DSI is a dimensionless number, and its specific value is related to multiple parameters in the integrated circuit production process parameters, such as line width spacing, metal density, and topological complexity. It can be used to measure the amplification effect of the aforementioned parameters on small fluctuations in the etching process. The larger the DSI value, the more likely the corresponding graphic is to be severely deformed or fail due to small process deviations during the etching process. In practical applications, DSI can be extracted based on etching simulation models or silicon wafer test data. This application does not limit the specific value of DSI.

[0088] Based on this, when determining the failure probability corresponding to the target risk pattern sample, it is first necessary to determine the specific value of DSI in combination with the production process parameters of the integrated circuit, and then calculate the specific value of the corresponding failure probability according to formula (1). It can be understood that the larger the value of the failure probability, the greater the possibility that the target risk pattern will affect the generation of the integrated circuit layout. In practical applications, a preset probability threshold can be provided. When the obtained failure probability is greater than the preset probability threshold, it is determined that the target risk pattern affects the generation of the integrated circuit layout. As for the specific value of the preset probability threshold, it can be determined in combination with factors such as the design requirements of the integrated circuit layout and the application scenario of the integrated circuit. This application does not make specific restrictions on this.

[0089] Furthermore, the repair complexity is used to characterize the human resources required to repair the target risk pattern in the layout of the integrated circuit. In an optional embodiment, the repair complexity can be expressed in man-hours. Based on this, the repair complexity can be calculated according to the following formula:

[0090] T repair =A1L 2 +C0 (2)

[0091] Among them, Trepair represents the repair complexity;

[0092] A1 represents the preset coefficient, for example, it can be 0.8;

[0093] L represents the logical depth of the repair path of the integrated circuit, which specifically refers to the topological distance from the defect point to the nearest available repair resource (such as spare cells and redundant metal lines). It is also a comprehensive quantitative value of the number of layout layers and physical spans that the repair process needs to traverse. The specific value of L is related to the actual situation such as the defect area of ​​the integrated circuit layout and the depth of the inter-layer connection. 2 The nonlinear variation constituted is used to dynamically characterize the impact of L on the final calculation result. The increase of L will lead to an exponential increase in the repair complexity.

[0094] C0 is a preset constant, used to represent the basic workload required for repairing the target risk pattern, in actual application, can be combined with design experience to select flexibly, the specific value of C0 is not limited in the present application.

[0095] With reference to the foregoing failure probability, a complexity threshold can also be set for the repair complexity, and whether to repair the target risk pattern is comprehensively evaluated based on the size relationship between the calculated repair complexity and the complexity threshold. It can be understood that in actual application, the repair complexity is not used as the only risk evaluation index in most cases, and is usually used in combination with the foregoing failure probability, for example, in the case where the failure probability is greater than the preset probability threshold, whether the repair complexity is greater than the complexity threshold can be determined to determine whether the target risk pattern affects the layout generation of the integrated circuit.

[0096] The timing margin is used to represent the timing deviation allowed range of the integrated circuit, used to measure the dynamic change of the design margin, and the timing margin anomaly is likely to cause metal bridging and exacerbate the capacitive coupling effect. With reference to the foregoing two risk evaluation indexes, a timing margin threshold can also be set, and it needs to be explained that if the timing margin is less than the timing margin threshold, it means that repairing the target risk pattern has less impact on the timing of the integrated circuit, and on the contrary, if the timing margin is greater than the timing margin threshold, it means that repairing the target risk pattern has greater impact on the timing of the integrated circuit. Based on this, in actual application, whether to customize the layout and wiring constraint conditions according to the target risk pattern needs to be determined in combination with the timing requirements of the integrated circuit and other risk evaluation indexes such as the foregoing failure probability, so as to avoid the target risk pattern in the subsequent layout and wiring process.

[0097] In an optional implementation, the risk evaluation indexes of the target risk pattern sample can include failure probability, repair complexity and timing margin at the same time, in which case, the priority of each risk evaluation index can be set, for example, the priority of the failure probability is higher than the priority of the repair complexity and the timing margin, and of course, the priority of the timing margin can be further limited to be higher than the priority of the repair complexity.

[0098] Based on the foregoing premise, as an optional determination method, if the failure probability is greater than or equal to the preset probability threshold, at this time, the size relationship between the repair complexity and the complexity threshold does not need to be considered, and the size relationship between the timing margin and the timing margin threshold also does not need to be considered, and the target risk pattern can be directly determined to affect the layout generation of the integrated circuit.

[0099] In another optional determination method, the failure probability and the timing margin can also be combined, for example, in the case where the failure probability is greater than or equal to the preset probability threshold, and the timing margin is less than the timing margin threshold, it is determined that the target risk pattern affects the layout generation of the integrated circuit, and the layout and wiring constraint conditions need to be customized based on the target risk pattern.

[0100] Further, based on the foregoing definitions of the three risk evaluation indexes, it can be known that the three risk evaluation indexes measure the influence of the risk pattern on the integrated circuit layout generation from different dimensions respectively. In actual application, the influence of each risk evaluation index on the layout generation is different. Based on this, as another optional determination manner, in the case that the obtained failure probability is less than the preset probability threshold, a comprehensive evaluation index can be further calculated based on the failure probability, the repair complexity and the timing margin, and whether the target risk pattern influences the generation of the integrated circuit layout is determined by the size relationship between the comprehensive evaluation index and a preset comprehensive index threshold.

[0101] Specifically, first, the corresponding weight coefficients of the failure probability, the repair complexity and the timing margin are set. Since the failure probability can more directly represent the influence of the risk pattern on the integrated circuit layout generation, the weight coefficient of the failure probability can be set to a relatively large value, such as 40%. The weight coefficients of the other two risk evaluation indexes can be set to relatively small values, such as 30% respectively. For example, the weight coefficient corresponding to the repair complexity is set to 35%, and the weight coefficient corresponding to the timing margin is set to 25%. Of course, there are other weight coefficient setting manners. The selection of the specific weight coefficients mainly depends on the influence degree of the corresponding risk evaluation index on the layout generation and the attention degree of the user to each risk evaluation index in actual application. The specific values of the weight coefficients of each risk evaluation index are not limited in the present application, as long as the sum of the weight coefficients of each risk evaluation index is equal to 100%.

[0102] According to the calculation manner of each risk evaluation index described in the foregoing embodiments, the index values of the failure probability, the repair complexity and the timing margin are calculated. The specific calculation process can be referred to the foregoing content, which is not repeated here.

[0103] After obtaining the index values of each risk evaluation index and the corresponding weight coefficients, the product of the index value of each risk evaluation index and the weight coefficient corresponding to the risk evaluation index is calculated respectively to obtain the weight value of each risk evaluation index. Finally, the sum of the weight values of each risk evaluation index is calculated, and the obtained result is the comprehensive evaluation index.

[0104] It should be noted that the above calculation process is only described by taking three risk evaluation indexes as an example. When other number of risk evaluation indexes are included, the same calculation process can be used to determine the comprehensive evaluation index. Specifically, the comprehensive evaluation index can be calculated according to the following formula:

[0105] P s =C1×P1+C2×P2+…+C n ×P n (3)

[0106] Wherein, Ps represents comprehensive evaluation index;

[0107] P1-P n represents n risk assessment indicators, n≥1;

[0108] C1-C n Indicates the weight coefficient corresponding to n risk assessment indicators, n≥1, C1+C2+…+C n =100%.

[0109] Furthermore, if the resulting comprehensive evaluation index is greater than or equal to a preset comprehensive index threshold, determining that the target risk pattern affects the generated integrated circuit layout requires customizing layout and routing constraints based on the target risk pattern. Conversely, if the resulting comprehensive evaluation index is less than the preset comprehensive index threshold, determining that the target risk pattern does not affect the generated integrated circuit layout. The specific value of the preset comprehensive index threshold can be determined in practical applications based on factors such as the distribution of values ​​of each risk assessment index, the configuration of weight coefficients for each risk assessment index, and integrated circuit performance requirements. This application does not limit the specific value of the preset comprehensive index threshold.

[0110] S130 , generating an initial layout of the integrated circuit according to layout and routing constraint rules to avoid target risk patterns appearing in the initial layout.

[0111] After customizing the layout and routing constraints based on the target risk pattern, the initial layout of the integrated circuit can be generated according to the resulting layout and routing constraints. As can be understood, since the layout and routing constraints have already been specifically limited to avoid the target risk pattern, generating the initial layout of the integrated circuit according to the customized layout and routing constraints can effectively avoid the target risk pattern in the initial layout. The specific layout and routing process can be implemented by referring to related technologies and will not be detailed here.

[0112] It should be noted that, in combination with the layout and routing operations of related technologies, the layout and routing constraint rules described in this application not only involve the modification and limitation of the automatic layout and routing (Auto Place and Routing, APR) process technology rules, but also include the modification of the layout and routing scripts.

[0113] To sum up, the layout design method provided in this application creates customized layout and routing constraint rules based on target risk graphic samples. Through these layout and routing constraint rules, the target risk graphics can be avoided from appearing in the integrated circuit layout, thereby improving the success rate of layout design. Moreover, the layout and routing constraint rules are customized before layout and routing, which can effectively reduce the probability of iterative modification after layout and routing, help improve layout design efficiency, thereby saving manpower and material resources, shortening the integrated circuit R&D cycle, and meeting actual application needs.

[0114] Furthermore, when facing the migration of different production processes, the layout and routing avoidance mechanism provided by the layout design method provided by this application is applied, that is, the layout and routing constraint rules are customized before automatic layout and routing, and the integrated circuit layout is generated according to the customized layout and routing constraint rules. This can also solve the migration of different production processes, especially the risk graphic problems that arise when migrating layout design from advanced production processes to relatively backward production processes. While improving the layout generation efficiency, it can effectively improve the chip yield of backward production processes.

[0115] Based on the aforementioned embodiments, other forms of risk graphics may also appear in the layout design, such as risk graphics caused by process platform migration and risk graphics in scenarios such as through-hole failure and thermal resistance bottleneck, etc., which can also be avoided by applying the layout design method provided in this application.

[0116] Specifically, the process platform migration leads to physical and electrical mismatch of integrated circuits, which is mainly caused by the different sensitivity of units with different fin numbers to etching rates. Figure 7a As shown, the dense fin array of a 5Fin unit blocks the etching ion flow, causing over-etching of the fins of adjacent 3Fin units, forming a "dishing" shape. The dense fin array of the 5Fin unit restricts the lateral growth of the epitaxial material, while the epitaxial layer of the 3Fin unit over-expands, causing interface dislocations, which in turn increases contact resistance and drive current fluctuation.

[0117] With reference to the above, Figure 7a If the target risk graph shown affects the generation of the integrated circuit layout, it may cause Figure 7b The risk graph shown is based on this, according to Figure 7a The target risk graphic is shown in the preset rules for customized layout and routing: 1. Requires 5fin units and 3fin units to be used as concentrated as possible, that is, using Figure 7c 2. If 5fin units and 3fin units must be mixed, they should be filled with 3fin units (such as Figure 7d ), increase the length of the 3fin diffusion region to weaken the impact of over-etching during manufacturing.

[0118] Furthermore, the main causes of via failure and thermal resistance bottlenecks are: when a single via carries high current, the copper or cobalt interconnect metal ions migrate in a directional manner, forming voids or hillocks, which ultimately lead to open or shorted metal lines. In areas of excessively high current density, the temperature rises sharply, accelerating electromigration and inducing thermal runaway. Furthermore, the large fluctuations in doping concentration within a single via can affect chip timing.

[0119] In addition, chemical mechanical polishing over-grinds the dielectric layer around the single hole, causing metal protrusions or cracks, affecting the chip yield. Advanced processes avoid the above situation by adding additional constraint levels to ensure that every pin of the multi-output standard unit can be connected. However, backward processes lack the above constraints, and there may be multiple output metals, but only one of them is connected.

[0120] Combine Figure 8a As shown in the figure, a cell is configured with one input pin (I) and two output pins (Z). In the existing layout and routing process, it is easy to have the following Figure 8b as well as Figure 8d The example shown here shows that only one of the pins is connected, which is not allowed in actual applications.

[0121] Referring to the above embodiment, when determining Figure 8a When the target risk pattern sample shown affects the generation of the integrated circuit layout, the layout and routing constraint rules are customized according to the target risk pattern sample, that is, each standard unit output pin is forced to be connected to the subsequent metal wire to ensure sufficient through holes. When the wiring allows, the number of through holes is increased, the resistance is reduced, the through hole density is increased, and the yield is finally improved. The effect of generating the layout according to the layout and routing constraint rules provided by this application can be seen in Figure 8c as well as Figure 8e As shown, no further details are given here.

[0122] Furthermore, the present invention also provides another layout design method, see Figure 9 As shown, based on the layout design method provided in the previous embodiment, the layout design method provided in this embodiment further includes the following steps:

[0123] S140: Verify the initial layout based on the target risk graphic sample.

[0124] After the initial layout of the integrated circuit is generated according to the customized placement and routing constraint rules, in order to further avoid possible risk patterns in the initial layout, this step verifies the initial layout based on the target risk patterns.

[0125] In practical applications, the verification method is mainly to match the risk pattern of the initial layout of the integrated circuit with the target risk pattern as a reference, that is, to check whether there is a risk pattern in the initial layout that is consistent or similar to the target risk pattern. If so, it can be determined that the corresponding risk pattern exists in the initial layout, and the initial layout cannot be taped out yet. On the contrary, if there is no risk pattern in the initial layout that is consistent or similar to the target risk pattern, it can be confirmed that the initial layout of the integrated circuit has passed the verification and can be taped out.

[0126] S150 , when the initial layout includes the target risk pattern, adjusting the layout and routing constraint rules and regenerating the layout of the integrated circuit until a target layout that does not include the target risk pattern is obtained.

[0127] If the target risk graphic is included in the initial layout, that is, if it fails the verification, the layout and routing constraint rules are further adjusted to adjust the constraint conditions in the rules that may lead to the appearance of the target risk graphic, and the layout of the integrated circuit is regenerated according to the adjusted layout and routing rules. Accordingly, the regenerated layout is continuously verified according to the target risk graphic, and this iteration is repeated until a layout that does not include the target risk graphic is obtained as the final target layout of the integrated circuit.

[0128] As a preferred implementation, after obtaining the target layout, the aforementioned preset risk pattern sample library is updated based on the tape-out test results and test data of the integrated circuit layout, that is, the new risk images that appear in the aforementioned process and the risk patterns that are similar to the target risk patterns but have certain differences are processed as risk pattern samples in accordance with the relevant contents of the aforementioned embodiment, and the risk sample patterns stored in the preset risk sample library are updated.

[0129] In the related art, the process factory will provide a static risk library, but the static risk library has a slow update speed and cannot meet the fast iteration cycle and customization requirements of integrated circuits. Compared with the existing technology, this embodiment updates the preset risk graphic sample library after each layout design, establishes an experience-driven dynamic rule engine, realizes the automatic update and improvement of the risk graphics, and continuously enriches the preset risk graphic sample library in actual applications, breaking through the limitations of the static risk library in the related art.

[0130] In summary, the layout design method provided in this embodiment, based on the previous embodiments, realizes closed-loop verification of the integrated circuit layout, iteratively designs the integrated circuit layout according to the target risk image samples, and ultimately achieves effective avoidance of target risk graphics in the target layout by continuously improving the layout and routing constraint rules, thereby improving the success rate of layout design, shortening the integrated circuit R&D cycle, and meeting actual application needs.

[0131] It should be noted that during the integrated circuit layout design process, various types of risk graphics may appear. In practical applications, the aforementioned layout design method can be used for various risk graphics during one layout design process, thereby improving layout design efficiency.

[0132] The following describes the layout design device provided by the present invention. The layout design device provided by the present invention and the layout design method provided in the embodiments of this application are based on the same application concept. It can execute the layout design method provided in any embodiment of this application and has the corresponding functional modules and beneficial effects of executing the layout design method. For technical details not fully described in this embodiment, please refer to the layout design method provided in the embodiments of this application and will not be repeated here.

[0133] See also Figure 10 The layout design device provided in the embodiment of the present application includes: an acquisition unit 10, a matching unit 20, a customization unit 30 and a generation unit 40, wherein:

[0134] An acquiring unit 10 is configured to acquire a candidate risk pattern sample, where the candidate risk pattern sample is any one of a plurality of risk pattern samples in a preset risk pattern sample library;

[0135] A matching unit 20 is configured to adjust sample parameters of the candidate risk pattern sample according to the production process parameters of the integrated circuit to obtain a target risk pattern sample that matches the production process of the integrated circuit;

[0136] A customization unit 30, configured to customize layout and routing constraint rules based on a target risk pattern sample;

[0137] The generating unit 40 is configured to generate an initial layout of the integrated circuit according to the layout and routing constraint rules, so as to avoid the appearance of target risk patterns in the initial layout.

[0138] Furthermore, the present invention also provides another layout design device, see Figure 11 As shown, based on the above embodiment, the layout design device provided in this embodiment further includes:

[0139] A verification unit 50 is used to verify the initial layout based on the target risk pattern sample;

[0140] The optimization unit 60 is configured to adjust the layout and routing constraint rules and regenerate the layout of the integrated circuit if the initial layout includes the target risk pattern, until a target layout that does not include the target risk pattern is obtained.

[0141] Below, reference Figure 12 To describe the electronic device provided by the embodiment of the present invention, the electronic device provided by this embodiment may include: at least one processor 100, at least one communication interface 200, at least one memory 300 and at least one communication bus 400;

[0142] In the embodiments of the present application, the number of the processor 100, the communication interface 200, the memory 300 and the communication bus 400 is at least one, and the processor 100, the communication interface 200 and the memory 300 complete the communication with each other through the communication bus 400. Obviously, Figure 12 The communication connection shown by the processor 100, the communication interface 200, the memory 300 and the communication bus 400 is only optional.

[0143] Optionally, the communication interface 200 can be the interface of the communication module, such as the interface of the GSM module; the processor 100 can be a central processing unit CPU, or an application specific integrated circuit ASIC, or one or more integrated circuits configured to implement the embodiments of the present application.

[0144] The memory 300 can include a high-speed RAM memory, and can also include a non-volatile memory, for example, at least one disk memory.

[0145] The processor 100 is specifically configured to execute the application program in the memory, so as to realize the steps of the layout design method described above.

[0146] In some embodiments, the embodiments also provide a computer readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a U disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., and the computer readable storage medium stores one or more instructions for realizing the above steps. When the one or more instructions are executed by one or more processors, the processor executes the layout design method described above. For related specific implementation, please refer to the foregoing description, which will not be described here.

[0147] In addition to the above method and device, the embodiments of the present application can also be a computer program product, which includes computer program instructions, and the computer program instructions make the processor execute the steps of the layout design method according to various embodiments of the present application described in the foregoing description when the processor runs.

[0148] The computer program product may be written in any combination of one or more programming languages ​​to implement the program code for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0149] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented through hardware, software, firmware, or a combination of some or all of the three.

[0150] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0151] Flowcharts are used in this disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the preceding or following steps do not necessarily need to be performed in exact order. Instead, the various steps may be performed in reverse order or simultaneously. Furthermore, other operations may be added to these processes.

[0152] Those skilled in the art will appreciate that all or part of the steps in the above method can be performed by instructing the relevant hardware using a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Alternatively, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of software functional modules. The present disclosure is not limited to any particular combination of hardware and software.

[0153] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or highly formal sense unless expressly defined as such herein.

[0154] The above is an illustration of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure have been described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the above is an illustration of the present disclosure and should not be considered as limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A layout design method, characterized in that: include: Obtaining a candidate risk graph sample, where the candidate risk graph sample is any one of a plurality of risk graph samples in a preset risk graph sample library; Adjusting the sample parameters of the candidate risk pattern sample according to the production process parameters of the integrated circuit to obtain a target risk pattern sample that matches the production process of the integrated circuit; Customizing layout and routing constraint rules based on the target risk graphic sample; An initial layout of the integrated circuit is generated according to the layout and routing constraint rules to avoid the target risk pattern from appearing in the initial layout.

2. The method according to claim 1, characterized in that Adjusting the sample parameters of the candidate risk pattern sample according to the production process parameters of the integrated circuit includes: Based on the historical data of the layout design, counting the cumulative number of occurrences of the candidate risk graphic samples; If the cumulative number of occurrences is greater than a preset number threshold, the sample parameters of the candidate risk pattern sample are adjusted according to the production process parameters of the integrated circuit.

3. The method according to claim 1, characterized in that Customizing placement and routing constraint rules based on the target risk pattern sample, including: Determining a risk assessment index of the target risk pattern sample based on a production process parameter of the integrated circuit, wherein the risk assessment index is used to characterize the impact of the target risk pattern on the layout of the integrated circuit, the target risk pattern being a risk pattern corresponding to the target risk pattern sample; If the risk assessment indicator indicates that the target risk pattern affects the generation of the layout of the integrated circuit, a layout and routing constraint rule is customized based on the target risk pattern sample.

4. The method according to claim 3, characterized in that The risk assessment index includes at least one of failure probability, repair complexity and timing margin, wherein: The failure probability is used to characterize the possibility that the target risk pattern will cause the layout of the integrated circuit to fail; The repair complexity is used to represent the human resources required to repair the target risk pattern in the layout of the integrated circuit; The timing margin is used to characterize an allowable range of timing deviation of the integrated circuit.

5. The method according to claim 4, characterized in that The risk assessment indicators include failure probability, repair complexity and timing margin; The priority of the failure probability is higher than the priority of the repair complexity and the timing margin; If the failure probability is greater than or equal to a preset probability threshold, it is determined that the target risk pattern affects the generation of the layout of the integrated circuit.

6. The method according to claim 5, characterized in that If the failure probability is less than the preset probability threshold, the method further includes: Calculating a comprehensive evaluation index based on the failure probability, the repair complexity, and the timing margin; If the comprehensive evaluation index is greater than or equal to a preset comprehensive index threshold, it is determined that the target risk pattern affects the generation of the layout of the integrated circuit.

7. The method according to any one of claims 1 to 6, characterized in that Verifying the initial layout based on the target risk graphic sample; If the initial layout includes the target risk pattern, the layout and routing constraint rules are adjusted and the layout of the integrated circuit is regenerated until a target layout that does not include the target risk pattern is obtained.

8. A layout design device, characterized in that: include: an acquiring unit, configured to acquire a candidate risk pattern sample, wherein the candidate risk pattern sample is any one of a plurality of risk pattern samples in a preset risk pattern sample library; a matching unit, configured to adjust sample parameters of the candidate risk pattern sample according to production process parameters of the integrated circuit to obtain a target risk pattern sample that matches the production process of the integrated circuit; A customization unit, configured to customize layout and routing constraint rules based on the target risk pattern sample; A generating unit is configured to generate an initial layout of the integrated circuit according to the layout and routing constraint rules, so as to avoid the target risk pattern appearing in the initial layout.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, wherein: When the processor executes the computer program, the steps of the layout design method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the layout design method according to any one of claims 1 to 7 are implemented.

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