Current proportion mirror image circuit and electronic product

Abstract

The invention provides a current proportion mirror image circuit and an electronic product. The current proportion mirror image circuit comprises a current mirror module composed of a first transistor, a second transistor, a third transistor, a first capacitor, an operational amplifier and a mode switching unit; wherein the first ends of the first and second transistors are connected with working voltage, the control ends are connected with driving voltage, and the second end of the third transistor is connected with a CS end; the mode switching unit is used for switching an input signal of the operational amplifier and a control end signal of the third transistor based on different working modes; the second end of the third transistor outputs detection current having a preset proportion with the load current, and the second end of the second transistor is connected with a load; and the offset compensation module is used for sampling and compensating the input offset voltage of the operational amplifier. The offset compensation module is constructed by utilizing a self-zero-setting technology, so that the input offset voltage of the operational amplifier in the current mirror module is reduced, and the detection precision of the current proportion mirror circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and particularly to a current proportional mirror circuit and an electronic product. BACKGROUND

[0002] In the current proportional mirror circuit, the virtual short-virtual open characteristic of the operational amplifier is often used to make the voltage of the two set nodes equal, and then make the output current and the input current satisfy a specific proportional relationship, to realize the current proportional mirror function. However, in actual application, the operational amplifier has an input offset voltage, which causes the voltage of the two set nodes to be unable to be equal, and the current detection precision is poor (especially in the case of small current), which cannot meet the design requirements.

[0003] Therefore, how to overcome the influence of the input offset voltage of the operational amplifier on the current detection precision has become one of the problems to be solved by the person skilled in the art.

[0004] It should be noted that the above introduction to the technical background is only to facilitate the clear and complete description of the technical scheme of the present application, and to facilitate the understanding of the person skilled in the art. The above technical scheme cannot be considered as known to the person skilled in the art only because it is described in the background section of the present application. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a current proportional mirror circuit and an electronic product, which is used to solve the problem of poor current detection precision in the prior art.

[0006] To achieve the above object and other related objects, the present application provides a current proportional mirror circuit, which at least comprises:

[0007] a current mirror module and an offset compensation module;

[0008] The current mirror module comprises a first transistor, a second transistor, a third transistor, a first capacitor, an operational amplifier and a mode switching unit; the first end of the first transistor and the second transistor is connected with a working voltage, and the control end is connected with a driving voltage; the mode switching unit is connected between the second end of the first transistor and the second transistor and the differential input end of the operational amplifier, and is also connected between the control end of the third transistor and the output end of the operational amplifier, and based on different working modes, the input end of the operational amplifier is switched to the second end of the first transistor and the second transistor or to a common-mode voltage, and the on-off relationship between the control end of the third transistor and the output end of the operational amplifier is controlled; the second end of the second transistor is connected with an external load; the second end of the first transistor is connected with the first end of the third transistor, and the second end of the third transistor outputs a detection current having a preset proportion of the current of the load; one end of the first capacitor is connected with the working voltage, and the other end is connected with the control end of the third transistor.

[0009] The input end of the offset compensation module is connected with the output end of the operational amplifier, for sampling the input offset voltage of the operational amplifier, and feeding back an output signal to the operational amplifier to compensate the input offset voltage of the operational amplifier.

[0010] Optionally, the first transistor and the second transistor are NMOS tubes, and the third transistor is a PMOS tube.

[0011] Optionally, the mode switching unit comprises a first switch, a second switch, a third switch, a fourth switch and a fifth switch.

[0012] One end of the first switch and the second switch receives the common-mode voltage, and the other end is connected with the differential input end of the operational amplifier respectively.

[0013] One end of the third switch is connected with the second end of the first transistor, and the other end is connected with the reverse input end of the operational amplifier; one end of the fourth switch is connected with the second end of the second transistor, and the other end is connected with the forward input end of the operational amplifier.

[0014] One end of the fifth switch is connected with the control end of the third transistor, and the other end is connected with the output end of the operational amplifier.

[0015] More optionally, the offset compensation module comprises a sixth switch, a seventh switch, a second capacitor, a third capacitor and a transconductance amplifier.

[0016] The first input end of the transconductance amplifier is connected with the output end of the operational amplifier via the sixth switch, the second input end receives a bias voltage via the seventh switch, and the output end is fed back to the operational amplifier.

[0017] One end of the second capacitor is connected with the working voltage, and the other end is connected with the first input end of the transconductance amplifier;

[0018] One end of the third capacitor is connected with the working voltage, and the other end is connected with the second input end of the transconductance amplifier.

[0019] More optionally, the offset compensation module further comprises a bias voltage generating unit, and the bias voltage generating unit comprises a fourth transistor, a fifth transistor, a first resistor, a first bias current source and a second bias current source.

[0020] The fourth transistor is in diode connection, the first end is connected with the working voltage, and the second end is grounded via the first bias current source; the first end of the fifth transistor is connected with the working voltage, the second end is grounded via the first resistor and the second bias current source in sequence, the control end is connected with the second end of the fourth transistor; and the connection node of the first resistor and the second bias current source outputs the bias voltage.

[0021] More optionally, the fourth transistor is a PMOS transistor, and the fifth transistor is an NMOS transistor.

[0022] Optionally, the current proportional mirror circuit further comprises a follower arranged between the output end of the operational amplifier and the input end of the offset compensation module, and the follower comprises a second resistor, a sixth transistor and a third bias current source.

[0023] One end of the second resistor is connected with the working voltage, and the other end is grounded via the sixth transistor and the third bias current source in sequence; the control end of the sixth transistor is connected with the output end of the operational amplifier, and the connection node of the sixth transistor and the third bias current source serves as the output end of the follower.

[0024] Optionally, the operational amplifier adopts a two-stage amplification structure; wherein the first-stage amplification unit adopts a resistor load, and the second-stage amplification unit adopts a folded cascode structure.

[0025] More optionally, the second-stage amplification unit adopts the folded cascode structure, and the output end of the offset compensation module is connected between two load transistors in series in the second-stage amplification unit.

[0026] To achieve the above object and other related objects, the application provides an electronic product, which at least comprises the current proportional mirror circuit.

[0027] As described above, the current proportional mirror circuit and the electronic product have the following beneficial effects:

[0028] The current proportional mirror circuit and the electronic product utilize the self-zeroing technology to construct the offset compensation module, so as to reduce the input offset voltage of the operational amplifier in the current mirror module, and improve the detection precision of the current proportional mirror circuit. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 A structural schematic diagram of a current mirror circuit is shown.

[0030] Figure 2 A structural schematic diagram of a current mirror circuit with input offset voltage is shown. Figure 1

[0031] Figure 3 A structural schematic diagram of a current proportional mirror circuit is shown.

[0032] Figure 4 A structural schematic diagram of an operational amplifier is shown.

[0033] Figure 5 A structural schematic diagram of a mode switching unit and an offset compensation module is shown.

[0034] Figure 6 A structural schematic diagram of a bias voltage generating unit and a follower is shown.

[0035] Figure 7 A structural schematic diagram of a transconductance amplifier is shown.

[0036] Figure 8 A simulation schematic diagram before offset compensation is shown.

[0037] Figure 9 A simulation schematic diagram after offset compensation is shown.

[0038] ELEMENT NUMBER EXPLANATION

[0039] 1 current mirror circuit

[0040] 11 operational amplifier

[0041] 2 current proportional mirror circuit

[0042] 21 current mirror module

[0043] 211 operational amplifier

[0044] 21a first-stage amplification unit

[0045] 21b second-stage amplification unit

[0046] 21c bias unit

[0047] 212 mode switching unit ​

[0048] 22 mismatch compensation module

[0049] 221 transconductance amplifier

[0050] 22a biasing and voltage reduction unit

[0051] 22b transconductance amplification unit

[0052] 222 bias voltage generation unit

[0053] 23 follower DETAILED DESCRIPTION

[0054] The present application is herein described, by way of example only, with the

[0055] Reference will now be made to the drawings, wherein: Figures 1-9 It is to be understood that the drawings are to be used only for illustrating the preferred embodiments and should not be used to limit the present application. The specific embodiments shown are merely illustrative of the present application and should not be considered as limiting the scope of the application as there can be numerous variations and modifications which will readily occur to those skilled in the art, but which are not described herein. It is to be understood that the phraseology and terminology employed herein are for the purpose of description and not of limitation. Any and all variations and modifications thereof that are apparent to those skilled in the art are intended to be included within the scope of the present application.

[0056] As shown in Figure 1 Fig. 1 is a current mirror circuit 1, which can be used to achieve the function of current detection. The current mirror circuit includes NMOS transistors Q1 and Q2, a PMOS transistor Q3 and an operational amplifier 11. The drain of the NMOS transistor Q1 is connected to a battery voltage Vbat, and the source of the NMOS transistor Q1 is connected to the source of the PMOS transistor Q3. The drain of the NMOS transistor Q2 is connected to the battery voltage Vbat, and the source of the NMOS transistor Q2 is connected to an output terminal OUT (for connecting an external load). The gates of the NMOS transistors Q1 and Q2 are connected to a driving voltage V G . The drain of the PMOS transistor Q3 is connected to a detection output terminal CS. The input terminals of the operational amplifier 11 are connected to the sources of the NMOS transistors Q1 and Q2, and the output terminal of the operational amplifier 11 is connected to the gate of the PMOS transistor Q3. When the current mirror circuit 1 is working normally, the NMOS transistors Q1 and Q2 work in the linear region, and their currents satisfy the following equation:

[0057]

[0058] where I OUT is the load current, I CS is the output detection current, I DS2 is the drain-source current of the NMOS transistor Q2, and I DS1is the drain-source current of NMOS tube Q1, V DS2 is the drain-source voltage of NMOS tube Q2, V DS1 is the drain-source voltage of NMOS tube Q1, (W / L)2 is the width-to-length ratio of NMOS tube Q2, (W / L)1 is the width-to-length ratio of NMOS tube Q1, V dsat2 is the overdrive voltage of NMOS tube Q2, V dsat1 is the overdrive voltage of NMOS tube Q1, μ n is the carrier mobility of the NMOS tube, C ox It is the gate oxide capacitance per unit area of ​​the MOS tube.

[0059] Ideally, the source voltages of NMOS tubes Q1 and Q2 are equal, V DS1 =V DS2 , V dsat1 =V dsat2 , load current I OUT and the detection current I CS The ratio is only related to the ratio of width to length:

[0060]

[0061] In actual applications, the limited gain and mismatch of the operational amplifier 11 will produce an input offset voltage Vos, which is equivalent to the input terminal of the operational amplifier 11 (equivalent to the inverting input terminal in this example), such as Figure 2 As shown, the load current I OUT and the detection current I CS The relationship is:

[0062]

[0063] It can be seen from formula (3) that the change of input offset voltage Vos will affect the load current I OUT and the detection current I CS Especially when detecting small current, that is, V DS1 ≤V OS , at this time the current detection accuracy is greatly reduced.

[0064] Based on the above reasons, the present invention provides a current proportional mirror circuit 2, which includes a current mirror module 21 and an offset compensation module 22. The offset compensation module 22 samples and compensates the input offset voltage of the operational amplifier in the current mirror module 21.

[0065] like Figure 3As shown, the current mirror module 21 receives a load current (input through port OUT) and generates a detection current (output through port CS) with a preset proportion of the load current through current proportional mirroring; the current mirror module 21 comprises a first transistor M1, a second transistor M2, a third transistor M3, a first capacitor C1, an operational amplifier 211 and a mode switching unit 212.

[0066] Specifically, the first ends of the first transistor M1 and the second transistor M2 are connected to a working voltage V BAT ; in the present example, the working voltage is provided by a battery, and in actual use, the working voltage of the current proportional mirroring circuit 2 of the present application can be obtained based on any approach, not limited to the present example. The control ends of the first transistor M1 and the second transistor M2 are connected together and receive a driving voltage V G . The mode switching unit 212 is connected between the second ends of the first transistor M1 and the second transistor M2 and the differential input ends of the operational amplifier 211, and is also connected between the control end of the third transistor M3 and the output end of the operational amplifier 211, and switches the input ends of the operational amplifier 211 to the second ends of the first transistor M1 and the second transistor M2 or to a common-mode voltage V CM based on different working modes and controls the on-off relationship between the control end of the third transistor M3 and the output end of the operational amplifier 211; that is, the mode switching unit 212 connects the differential input ends of the operational amplifier 211 to the second ends of the first transistor M1 and the second transistor M2 respectively or simultaneously connects the differential input ends of the operational amplifier 211 to the common-mode voltage V CM , and also controls the connection or disconnection of the control end of the third transistor M3 and the output end of the operational amplifier 211 (when connected, the output end of the operational amplifier 211 adjusts the current flowing through the third transistor M3; when disconnected, the output end of the operational amplifier 211 does not affect the current flowing through the third transistor M3). The second end of the second transistor M2 serves as the OUT end and is connected to an external load; the second end of the first transistor M1 is connected to the first end of the third transistor M3, and the second end of the third transistor M3 outputs a detection current with a preset proportion of the load current (i.e., the detection current is obtained through the detection end CS). One end of the first capacitor C1 is connected to the working voltage V BAT , and the other end is connected to the control end of the third transistor M3.

[0067] More specifically, in this example, the first transistor M1 and the second transistor M2 are NMOS transistors. In this case, the first end of the first transistor M1 and the second transistor M2 is the drain, the second end is the source, and the control end is the gate. The third transistor M3 is a PMOS transistor. In this case, the source of the third transistor M3 is connected to the source of the first transistor M1, the drain is connected to the detection terminal CS, and the gate is connected to the output end of the operational amplifier 211. In actual use, the type of each transistor can be set as needed, and the connection relationship of each port can be adaptively adjusted, which will not be described one by one here. As an example, the first transistor M1, the second transistor M2 and the third transistor M3 are high-voltage transistors. It should be noted that there is no absolutely unified numerical standard for the voltage range division of high-voltage transistors and low-voltage transistors. It mainly depends on the application scenario, industry specifications and device design goals. Generally, "low voltage" refers to transistors suitable for low-power, low-voltage scenarios, while "high voltage" is for scenarios with high power and high voltage requirements.

[0068] More specifically, the operational amplifier 211 adopts a two-stage amplification structure; wherein the first-stage amplification unit adopts a resistive load to reduce the RC time constant and increase the speed; the second-stage amplification unit adopts a folded cascode structure to increase the output impedance of the operational amplifier 211. Furthermore, the second-stage amplification unit adopts a folded cascode structure, and the output end of the offset compensation module 22 is connected between the two load transistors connected in series in the second-stage amplification unit. As an example, Figure 4 As shown, the operational amplifier 211 includes a first-stage amplifying unit 21a, a second-stage amplifying unit 21b and a bias unit 21c. The bias unit 21c includes a fourth bias current source I B4 , a seventh transistor M7 and an eighth transistor M8. In this example, the seventh transistor M7 and the eighth transistor M8 are both NMOS transistors; a fourth bias current source I B4 One end is connected to the working voltage V BAT , the other end is connected to the drain of the seventh transistor M7; the gate of the seventh transistor M7 is connected to the bias signal bias_n1; the drain of the eighth transistor M8 is connected to the source of the seventh transistor M7, the gate is connected to the drain of the seventh transistor M7, and the source is grounded (the ground terminal of the operational amplifier 211 in this example is V BAT -5V). The first-stage amplifying unit 21a includes a third resistor R3, a fourth resistor R4, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. In this example, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are all NMOS transistors; one end of the third resistor R3 is connected to the operating voltage V BAT , the other end is connected to the drain of the ninth transistor M9; one end of the fourth resistor R4 is connected to the operating voltage V BAT, the other end of which is connected to the drain of the tenth transistor M10; the gates of the ninth transistor M9 and the tenth transistor M10 are respectively the differential input terminals inn and inp, and the sources are both connected to the drain of the eleventh transistor M11; the gate of the eleventh transistor M11 is connected to the bias signal bias_n1, and the source is connected to the drain of the twelfth transistor M12; the gate of the twelfth transistor M12 is connected to the gate of the eighth transistor M8, and the source is grounded. The second-stage amplification unit 21b includes the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21, the twenty-second transistor M22, the twenty-third transistor M23, and the twenty-fourth transistor M24. In this example, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the twenty-first transistor M21, the twenty-second transistor M22, the twenty-third transistor M23, and the twenty-fourth transistor M24 are all NMOS transistors, and the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, and the twentieth transistor M20 are all PMOS transistors; the gates of the thirteenth transistor M13 and the fourteenth transistor M14 are respectively connected to the differential output terminals of the first-stage amplification unit 21a as the differential input terminals, and the sources are both connected to the drain of the fifteenth transistor M15; the gate of the fifteenth transistor M15 is connected to the bias signal bias_n1, and the source is connected to the drain of the sixteenth transistor M16; the gate of the sixteenth transistor M16 is connected to the gate of the eighth transistor M8, and the source is grounded; the sources of the seventeenth transistor M17 and the eighteenth transistor M18 are connected to the working voltage Vdd, and the gates are both connected to the output terminal of the first-stage amplification unit 21a; the drain of the seventeenth transistor M17 is connected to the drain of the nineteenth transistor M19, and the drain of the eighteenth transistor M18 is connected to the drain of the twentieth transistor M20; the gate of the nineteenth transistor M19 is connected to the drain of the fifteenth transistor M15, and the gate of the twentieth transistor M20 is connected to the drain of the sixteenth transistor M16; the sources of the nineteenth transistor M19 and the twentieth transistor M20 are both connected to the drain of the twenty-first transistor M21; the gate of the twenty-first transistor M21 is connected to the bias signal bias_n1, and the source is connected to the drain of the twenty-second transistor M22; the gate of the twenty-second transistor M22 is connected to the gate of the eighth transistor M8, and the source is grounded; the drain of the twenty-first transistor M21 is connected to the drain of the twenty-third transistor M23, and the drain of the twenty-second transistor M22 is connected to the drain of the twenty-fourth transistor M24; the gate of the twenty-third transistor M23 is connected to the drain of the fifteenth transistor M15, and the gate of the twenty-fourth transistor M24 is connected to the drain of the sixteenth transistor M16; the sources of the twenty-third transistor M23 and the twenty-fourth transistor M24 are both connected to the output terminal of the second-stage amplification unit 21b. BAT, the drains are respectively connected to the drains of the thirteenth transistor M13 and the fourteenth transistor M14; the source of the nineteenth transistor M19 is connected to the drain of the seventeenth transistor M17, the gate is connected to the bias signal bias_p1, and the drain is connected to the gates of the seventeenth transistor M17 and the eighteenth transistor M18; the source of the twentieth transistor M20 is connected to the drain of the eighteenth transistor M18, and the gate is connected to the bias signal bias_p1; the drain of the twenty-first transistor M21 is connected to the drain of the nineteenth transistor M19, the gate is connected to the bias signal bias_n1, and the source is connected to the drain of the twenty-third transistor M23 (and serves as a feedback input point); the gate of the twenty-third transistor M23 is connected to the gate of the eighth transistor M8, and the source is grounded; the drain of the twenty-second transistor M22 is connected to the drain of the twentieth transistor M20 and serves as the output terminal Vo, the gate is connected to the bias signal bias_n1, the source is connected to the The drain of the twenty-fourth transistor M24; the gate of the twenty-fourth transistor M24 is connected to the gate of the eighth transistor M8, and the source is grounded; in this example, the offset compensation module 22 samples the offset voltage of the operational amplifier 211 and connects the output current signal out_ib of the offset compensation module 22 to the connection node between the twenty-first transistor M21 and the twenty-third transistor M23 of the operational amplifier 211, thereby converting the sampled offset voltage signal of the operational amplifier 211 into a current signal and feeding the current signal back to the operational amplifier 211 to form negative feedback; in actual use, any node that can feed back the current signal to the operational amplifier 211 to form negative feedback can be used as the connection node for the feedback signal (out_ib) of the offset compensation module 22, including but not limited to the differential input terminal, differential output terminal or other connection node of the corresponding polarity of the operational amplifier 211, which are not detailed here. In actual use, any amplifier structure is applicable, and is not limited to this embodiment.

[0069] It should be noted that, as another example, the offset compensation module 22 outputs a voltage signal. Then, the output signal of the offset compensation module 22 can be connected in series to the differential input terminal and differential output terminal of the corresponding polarity of the operational amplifier 211 (it cannot be directly connected to the differential input terminal or the differential output terminal), which can also constitute negative feedback to achieve the purpose of compensating for the input offset voltage. This is not elaborated here.

[0070] More specifically, if Figure 5 As shown, in this example, the mode switching unit 212 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4 and a fifth switch S5. One end of the first switch S1 and the second switch S2 receives a common mode voltage V CM, one end of the third switch S3 is connected to the second end (point A) of the first transistor M1, and the other end is connected to the reverse input end of the operational amplifier 211; one end of the fourth switch S4 is connected to the second end (point B) of the second transistor M2, and the other end is connected to the forward input end of the operational amplifier 211; one end of the fifth switch S5 is connected to the control end of the third transistor M3, and the other end is connected to the output end (in this example, the forward output end) of the operational amplifier 211. Any circuit structure that can switch the input end of the operational amplifier 211 to the second end of the second transistor M2 and the third transistor M3, or to the common-mode voltage, and realize the on-off of the control end of the third transistor M3 and the output end of the operational amplifier 211, is applicable to the present application, and is not limited to this embodiment.

[0071] As shown in Figure 3 , the input end of the offset compensation module 2 is connected to the output end of the operational amplifier 211, for sampling the input offset voltage of the operational amplifier, and feeding back the output signal to the operational amplifier 211 for compensating the input offset voltage Vos of the operational amplifier 211.

[0072] Specifically, as shown in Figure 5 , in this example, the offset compensation module 22 includes a sixth switch S6, a seventh switch S7, a second capacitor C2, a third capacitor C3, and a transconductance amplifier 221. The first input end of the transconductance amplifier 221 is connected to the output end Vo of the operational amplifier 211 via the sixth switch S6, the second input end receives a bias voltage V B via the seventh switch S7, and the output end is fed back to the operational amplifier 211. One end of the second capacitor C2 is connected to the working voltage V BAT , and the other end is connected to the first input end of the transconductance amplifier 221. One end of the third capacitor C3 is connected to the working voltage V BAT , and the other end is connected to the second input end of the transconductance amplifier 221. In this embodiment, the input offset voltage Vos is equivalent to the reverse input end of the operational amplifier 211, the forward output end of the operational amplifier 211 is connected to the forward input end of the transconductance amplifier 221 via the switch, and the output signal of the transconductance amplifier 221 is fed back to the operational amplifier 211 to form a negative feedback loop; in actual use, the output end polarity of the operational amplifier 211, the input end polarity of the transconductance amplifier 221, and the polarity of the feedback point can be adjusted as needed, as long as a negative feedback is formed to achieve the compensation function, and is not limited to this embodiment. In addition, as an example, the capacitance values of the second capacitor C2 and the third capacitor C3 are equal; the size relationship can also be configured as needed.

[0073] More specifically, as shown in Figure 7As shown, as an example, the transconductance amplifier 221 includes a bias and voltage reduction unit 22a and a (unipolar) transconductance amplifier unit 22b. The bias and voltage reduction unit 22a includes a fifth bias current source I B5 , a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a Zener diode Z1, a twenty-fifth transistor M25, a twenty-sixth transistor M26, a twenty-seventh transistor M27, a twenty-eighth transistor M28, a twenty-ninth transistor M29, a thirtieth transistor M30, a thirty-first transistor M31, a thirty-second transistor M32, and a thirty-third transistor M33. In this example, the twenty-fifth transistor M25, the twenty-sixth transistor M26, the twenty-seventh transistor M27, the twenty-ninth transistor M29, and the thirtieth transistor M30 are all NMOS transistors, and the twenty-eighth transistor M28, the thirty-first transistor M31, the thirty-second transistor M32, and the thirty-third transistor M33 are all PMOS transistors; a fifth bias current source I B5 One end is connected to the working voltage V BAT , the other end is connected to the drain and gate of the twenty-fifth transistor M25; the source of the twenty-fifth transistor M25 is grounded; the sources of the twenty-sixth transistor M26 and the twenty-ninth transistor M29 are grounded, and their gates are connected to the gate of the twenty-fifth transistor M25; the source of the twenty-seventh transistor M27 is connected to the drain of the twenty-sixth transistor M26, the gate is connected to the high-voltage signal VDDA, and the drain is connected to the drain and gate of the twenty-eighth transistor M28 via the fifth resistor R5; the source of the twenty-eighth transistor M28 is connected to the operating voltage V BAT The source of the thirtieth transistor M30 is connected to the drain of the twenty-ninth transistor M29, the gate is connected to the high voltage signal VDDA, and the drain is connected to the operating voltage V through the seventh resistor R7 and the sixth resistor R6. BAT The anode of the Zener diode Z1 is connected to the connection node of the sixth resistor R6 and the seventh resistor R7, and the cathode is connected to the operating voltage V BAT The 31st transistor M31, the 32nd transistor M32 and the 33rd transistor M33 are connected in series with the operating voltage V BAT and the anode of the Zener diode Z1; the transconductance amplifying unit 22b includes a 34th transistor M34, a 35th transistor M35, a 36th transistor M36, a 37th transistor M37, and a 38th transistor M38. In this example, the 34th transistor M34, the 35th transistor M35, and the 36th transistor M36 are all PMOS transistors, and the 37th transistor M37 and the 38th transistor M38 are all NMOS transistors; the source of the 34th transistor M34 is connected to the operating voltage V BAT, the gate of the twenty-eighth transistor M28, the drain of the thirty-fifth transistor M35 and the source of the thirty-sixth transistor M36; the gates of the thirty-fifth transistor M35 and the thirty-sixth transistor M36 as differential input terminals; the drain and the gate of the thirty-seventh transistor M37 connecting the drain of the thirty-fifth transistor M35, and the source connecting the anode of the voltage stabilizing diode Z1; the drain of the thirty-eighth transistor M38 connecting the drain of the thirty-sixth transistor M36 and as the output terminal of the trans-impedance amplifier 221, the gate connecting the gate of the thirty-seventh transistor M37, and the source connecting the anode of the voltage stabilizing diode Z1 and outputting V BAT -5V. In actual use, any trans-impedance amplifier structure is applicable, which is not described one by one here.

[0074] Further, as shown in Figure 6 , the offset compensation module 22 further includes a bias voltage generating unit 222, which includes, as an example, a fourth transistor M4, a fifth transistor M5, a first resistor R1, a first bias current source I B1 , and a second bias current source I B2 . Among them, the fourth transistor M4 is in diode connection, the first end connecting the working voltage V BAT , and the second end grounding through the first bias current source I B1 ; the first end of the fifth transistor M5 connecting the working voltage V BAT , and the second end grounding through the first resistor R1 and the second bias current source I B2 in turn, and the control end connecting the second end of the fourth transistor M4; the connection node of the first resistor R1 and the second bias current source I B2 outputs the bias voltage V B . In this example, the fourth transistor M4 is a PMOS tube, at this time, the first end of the fourth transistor M4 is the source, the second end is the drain, and the gate and the drain are connected together to constitute the diode connection; the fifth transistor M5 is an NMOS tube, at this time, the first end of the fifth transistor M5 is the drain, the second end is the source, and the control end is the gate. In this example, the bias voltage V B is equal to V BAT -V gs4 -V gs5 -I B2 *R1. In actual use, the types of transistors can be set as needed, and the port connection relationship can be adaptively adjusted, which is not described one by one here.

[0075] As shown in Figure 6 , as another implementation manner of the present application, the current proportional mirror circuit 2 further includes a follower 23 arranged between the output terminal of the operational amplifier 211 and the input terminal of the offset compensation module 22. As an example, the follower 23 includes a second resistor R2, a sixth transistor M6, and a third bias current source IB3 ; one end of the second resistor R2 is connected to the working voltage V BAT , and the other end is connected to the ground via the sixth transistor M6 and the third bias current source I B3 in sequence; the control end of the sixth transistor M6 is connected to the output end of the operational amplifier 211, and the connection node of the sixth transistor M6 and the third bias current source I B3 serves as the output end of the follower 23. In the present example, the sixth transistor M6 is an NMOS transistor, and at this time, the drain of the sixth transistor M6 is connected to the second resistor R2, the source is connected to the third bias current source I B3 , and the gate is connected to the output end of the operational amplifier 211. In actual use, the type of transistor can be set as needed, and the connection relationship of each port is adjusted adaptively, which is not described here.

[0076] As shown in Figure 5 , it is assumed that there is an input offset voltage V OS at the input end of the operational amplifier 211, and the differential mode gain is AV, which satisfies AV=G m1 ×R O (4), where G m1 is the transconductance of the operational amplifier 211, and R O is the output impedance of the operational amplifier 211. The current proportional mirror circuit 2 has two working states, which are offset sampling and offset compensation, respectively; when the circuit enters the offset sampling stage, i.e., the switches S1, S2, S6, and S7 are closed, and the switches S3, S4, and S5 are disconnected, at this time, the connection between the input end of the operational amplifier 211 and points A and B is disconnected, and the input end of the operational amplifier 211 is shorted to the common-mode voltage V CM , the output end of the operational amplifier 211 is disconnected from the gate of the third transistor M3, and the first capacitor C1 stores the gate voltage information of the third transistor M3, ensuring that the current proportional mirror circuit can also output the detection current I CS in the offset sampling stage. The input offset voltage V OS of the operational amplifier 211 is amplified to the output end V O , the transconductance amplifier 221 samples the voltage difference between the voltage V O at the output end of the operational amplifier 211 and the bias voltage V B and generates a feedback current Is, thereby completing the sampling of the input offset voltage of the operational amplifier 211, wherein the voltage V O at the output end of the operational amplifier 211 satisfies the following relationship:

[0077] (V OS G m1 -V O G m2 )×R O =V O (5)

[0078] The calculation is as follows:

[0079]

[0080] Wherein, G m2 is the transconductance of the transconductance amplifier 221. When the circuit enters the offset compensation stage, i.e. switches S1, S2, S6 and S7 are open, and switches S3, S4 and S5 are closed, in this stage, the current detection loop containing the third transistor M3 works normally, the input end of the transconductance amplifier 221 saves the input offset voltage information of the operational amplifier 211 through the second capacitor C2 and the third capacitor C3, and generates a sampling current Is fed back to the input stage of the transconductance amplifier 221 through the amplification of the transconductance amplifier 221, thereby completing the compensation of the input offset voltage of the transconductance amplifier 221, and making V OS,all is the input offset voltage of the transconductance amplifier 221 after compensation, and the detailed calculation is as follows:

[0081]

[0082] The calculation is as follows:

[0083] As can be seen from equation (9), after adding the offset compensation circuit, setting appropriate R O and G m2 , the input offset voltage can be reduced.

[0084] As an example, the current ratio is set to 300:1, and the value of the load current I OUT is 5mA. The simulation is compared whether there is an offset compensation module. Figure 8 The simulation result without the offset compensation module is shown in the figure, and from the figure, it can be seen that the load current I OUT is 4.999mA, the detection current I CS is 22.497μA, and the current ratio is 222.24:1. Figure 9 The simulation result containing the offset compensation module is shown in the figure, and from the figure, it can be seen that the load current I OUT is 4.999mA, the detection current I CS is 17.301μA, and the ratio is 288.98:1. It can be seen that based on the offset compensation module 22 of the application, the detection accuracy is improved.

[0085] The application also provides an electronic product, which at least comprises the current proportional mirror circuit 2 of the application, for obtaining higher detection accuracy. The electronic product includes but is not limited to mobile phones, watches, computers, tablets and other electronic products, which will not be described one by one here.

[0086] In summary, the application provides a current proportional mirror circuit and electronic product, comprising: a current mirror module and a offset compensation module; the current mirror module comprises a first transistor, a second transistor, a third transistor, an operational amplifier and a mode switching unit; the first end of the first transistor and the second transistor is connected with a working voltage, and the control end is connected with a driving voltage; the mode switching unit is connected between the second end of the first transistor and the second transistor and the differential input end of the operational amplifier, and the input end of the operational amplifier is switched to the second end of the first transistor and the second transistor or to a common mode voltage based on different working modes; the output end of the operational amplifier is connected with the control end of the third transistor; the second end of the second transistor is connected with an external load; the second end of the first transistor is connected with the first end of the third transistor, and the second end of the third transistor outputs a detection current with a preset proportion of the current of the load; the input end of the offset compensation module is connected with the output end of the operational amplifier, and the output signal is fed back to the third input end of the operational amplifier, for sampling and compensating the input offset voltage of the operational amplifier. The current proportional mirror circuit and electronic product of the application use the self-zeroing technology to construct the offset compensation module, so as to reduce the input offset voltage of the operational amplifier in the current mirror module and improve the detection accuracy of the current proportional mirror circuit. Therefore, the application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0087] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought of the application should be covered by the claims of the application.

Claims

1. A current proportional mirror circuit, characterized in that: The current proportional mirror circuit at least includes: Current mirror module and offset compensation module; The current mirror module includes a first transistor, a second transistor, a third transistor, a first capacitor, an operational amplifier, and a mode switching unit; the first ends of the first transistor and the second transistor are connected to an operating voltage, and the control ends are connected to a driving voltage; the mode switching unit is connected between the second ends of the first transistor and the second transistor and the differential input end of the operational amplifier, and is also connected between the control end of the third transistor and the output end of the operational amplifier, and switches the input end of the operational amplifier to the second ends of the first transistor and the second transistor or to a common mode voltage based on different operating modes and controls the on-off relationship between the control end of the third transistor and the output end of the operational amplifier; the second end of the second transistor is connected to an external load; the second end of the first transistor is connected to the first end of the third transistor, and the second end of the third transistor outputs a detection current having a preset ratio to the current of the load; one end of the first capacitor is connected to the operating voltage, and the other end is connected to the control end of the third transistor; The input end of the offset compensation module is connected to the output end of the operational amplifier, and is used to sample the input offset voltage of the operational amplifier and feed back the output signal to the operational amplifier to compensate for the input offset voltage of the operational amplifier.

2. The current proportional mirror circuit according to claim 1, wherein: The first transistor and the second transistor are NMOS transistors, and the third transistor is a PMOS transistor.

3. The current proportional mirror circuit according to claim 1, wherein: The mode switching unit includes a first switch, a second switch, a third switch, a fourth switch and a fifth switch; One end of the first switch and the second switch receives the common mode voltage, and the other end is connected to the differential input terminal of the operational amplifier respectively; One end of the third switch is connected to the second end of the first transistor, and the other end is connected to the inverting input terminal of the operational amplifier; one end of the fourth switch is connected to the second end of the second transistor, and the other end is connected to the positive input terminal of the operational amplifier; One end of the fifth switch is connected to the control end of the third transistor, and the other end is connected to the output end of the operational amplifier.

4. The current proportional mirror circuit according to any one of claims 1 to 3, wherein: The offset compensation module includes a sixth switch, a seventh switch, a second capacitor, a third capacitor and a transconductance amplifier; The first input terminal of the transconductance amplifier is connected to the output terminal of the operational amplifier via the sixth switch, the second input terminal receives a bias voltage via the seventh switch, and the output terminal is fed back to the operational amplifier; One end of the second capacitor is connected to the operating voltage, and the other end is connected to the first input terminal of the transconductance amplifier; One end of the third capacitor is connected to the operating voltage, and the other end is connected to the second input end of the transconductance amplifier.

5. The current proportional mirror circuit according to claim 4, wherein: The offset compensation module further includes a bias voltage generating unit, wherein the bias voltage generating unit includes a fourth transistor, a fifth transistor, a first resistor, a first bias current source, and a second bias current source; The fourth transistor is diode-connected, with a first end connected to the operating voltage and a second end connected to ground via the first bias current source. The fifth transistor has a first end connected to the operating voltage, a second end connected to ground via the first resistor and the second bias current source in sequence, and a control end connected to the second end of the fourth transistor. The bias voltage is output from a connection node between the first resistor and the second bias current source.

6. The current proportional mirror circuit according to claim 5, wherein: The fourth transistor is a PMOS transistor, and the fifth transistor is an NMOS transistor.

7. The current proportional mirror circuit according to claim 1, wherein: The current proportional mirror circuit further includes a follower arranged between the output terminal of the operational amplifier and the input terminal of the offset compensation module, wherein the follower includes a second resistor, a sixth transistor and a third bias current source; One end of the second resistor is connected to the operating voltage, and the other end is connected to the ground via the sixth transistor and the third bias current source in sequence; the control end of the sixth transistor is connected to the output end of the operational amplifier, and the connection node between the sixth transistor and the third bias current source serves as the output end of the follower.

8. The current proportional mirror circuit according to claim 1, wherein: The operational amplifier adopts a two-stage amplification structure; wherein the first-stage amplification unit adopts a resistive load, and the second-stage amplification unit adopts a folded common-source common-gate structure.

9. The current proportional mirror circuit according to claim 8, wherein: The second-stage amplifying unit adopts a folded cascode structure, and the output end of the offset compensation module is connected between two load tubes connected in series in the second-stage amplifying unit.

10. An electronic product, characterized in that: The electronic product at least includes: the current proportional mirror circuit according to any one of claims 1-9.

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