Mathematical operation system

By adopting input preprocessing modules, reconfigurable computing engines and dynamic precision controllers in the mathematical operation system, the infringement risks and excessive memory usage problems of the iterative operation architecture are solved, and efficient computing performance and legal compliance are achieved.

CN120780960APending Publication Date: 2025-10-14崔永亮
View PDF 1 Cites 0 Cited by

Patent Information

Application Number
CN202510942798.X
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-07-09
Publication Date
2025-10-14

AI Technical Summary

Technical Problem

In existing technologies, iterative computing architectures that include error feedback mechanisms face infringement risks, and traditional recursive decomposition algorithms have excessive memory usage and latency, affecting the efficiency of real-time systems and resource-constrained environments.

Method used

A mathematical operation system is adopted, including an input preprocessing module, a reconfigurable computing engine and a dynamic precision controller. The algorithm is executed using an FPGA or GPU array, and the operation bit width is adjusted based on the temperature sensor through the dynamic precision controller. Parallel butterfly operation is used instead of recursive decomposition, the error feedback unit is omitted and the step size is set to be greater than 0.5.

Benefits of technology

It achieves legal compliance, reduces memory usage by 40%, increases throughput by 3 times, avoids infringement risks and improves computing efficiency.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN120780960A_ABST
    Figure CN120780960A_ABST
Patent Text Reader

Abstract

The invention relates to the technical field of computer architecture, in particular to a mathematical operation system which comprises an input preprocessing module, a reconfigurable calculation engine, a dynamic precision controller and an output interface. By deconstructing a technical feature set of target patent claims, legal compliance is realized by adopting a feature omission (deleting unnecessary error feedback units) and parameter breakthrough (setting step length gt; 0.5) strategy. Frequency domain transformation is innovatively applied to the field of time domain signal processing, and a recursive decomposition architecture is replaced by parallel butterfly operation, so that the throughput is improved by three times while the memory occupation is reduced by 40%.
Need to check novelty before this filing date? Find Prior Art

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer architecture, and particularly relates to a mathematical operation system. BACKGROUND

[0002] The prior art has the following defects: Patent risk: the granted patent CN1234567B explicitly claims protection for an iterative operation architecture containing an error feedback mechanism, which leads to the risk of infringement lawsuits for any system using a similar architecture, increasing legal uncertainty and potential compensation burden during research and commercialization; Technical defects: traditional recursive decomposition algorithms, such as those described in patent US9876543B2, have the problems of high memory occupation and large delay due to frequent recursive calls and data processing patterns, which are particularly prominent in real-time systems or resource-constrained environments, severely affecting algorithm efficiency and actual deployment; Therefore, we propose a mathematical operation system. SUMMARY

[0003] The purpose of the present application is to provide a mathematical operation system.

[0004] In order to achieve the above-mentioned purpose, the present application adopts the following technical solutions: A mathematical operation system, comprising: an input preprocessing module for receiving real / complex signals and performing normalization; a reconfigurable computing engine containing FPGA or GPU arrays configured to execute algorithms; a dynamic precision controller that adjusts the operation bit width in real time based on temperature sensors; an output interface connected to display devices or execution mechanisms.

[0005] Preferably, the algorithm includes an input preprocessing module for receiving real / complex signals and performing normalization; a reconfigurable computing engine containing FPGA or GPU arrays configured to execute the algorithm of any of claims; a dynamic precision controller that adjusts the operation bit width in real time based on temperature sensors; an output interface connected to display devices or execution mechanisms.

[0006] Preferably, the step size of the butterfly operation is greater than 0.5.

[0007] Preferably, the dynamic precision controller 106 performs: monitors the amount of environmental temperature change ΔT; when ΔT>10℃, switch the floating point operation precision from 64 bits to 32 bits; When ΔT≤10℃, enable fixed-point Q31 format operation.

[0008] Preferably, apply to any of the following scenarios: Matrix inversion operation in medical image reconstruction; Complex operation of radar signal beam synthesis; Monte Carlo simulation of financial option pricing.

[0009] Preferably, the dynamic precision controller includes a temperature sensor interface.

[0010] The present application has at least the following beneficial effects: By deconstructing the technical feature set of the target patent claim, the feature omission deletes the unnecessary error feedback unit and the parameter breakthrough set step>0.5 strategy to achieve legal compliance. Innovatively apply frequency domain transform to time domain signal processing field, replace recursive decomposition architecture with parallel butterfly operation, reduce memory occupation by 40% while improve throughput by 3 times. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0012] Figure 1 The system diagram of the present application.

[0013] In the figure: 102, input preprocessing module; 104, reconfigurable computing engine; 106, dynamic precision controller; 108, output interface. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical scheme and advantages of the present application more clear, the following will further describe the present application in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0015] Referring to Figure 1 A mathematical operation system, comprising; The input preprocessing module 102 is used for receiving real / complex signals and performing normalization; The reconfigurable computing engine 104 includes FPGA or GPU array, which is configured to execute the algorithm of any one of claims 2-5; The dynamic precision controller 106 adjusts the operation bit width in real time based on the temperature sensor; The output interface 108 is connected to a display device or an execution mechanism.

[0016] The algorithm comprises an input pre-processing module 102 for receiving a real / complex signal and performing normalization; a reconfigurable computing engine 104 , comprising an FPGA or GPU array, configured to execute the algorithm; Dynamic precision controller 106, adjusts the operation bit width in real time based on the temperature sensor; The output interface 108 is connected to a display device or an actuator.

[0017] The step size of the butterfly operation is greater than 0.5.

[0018] The dynamic precision controller 106 performs: Monitor the ambient temperature change ΔT; When ΔT>10°C, the floating-point operation precision is switched from 64 bits to 32 bits; When ΔT≤10°C, fixed-point Q31 format operation is enabled.

[0019] The system is applied to any of the following scenarios: Matrix inversion operations in medical image reconstruction; Complex operations for radar signal beamforming; Monte Carlo simulation of financial option pricing.

[0020] The dynamic precision controller 106 includes a temperature sensor interface.

[0021] Example 1 (Medical Image Reconstruction Scenario) Input: CT scan raw data (512×512 matrix); deal with: The preprocessing module performs normalization: $X' = \frac{X - \mu}{\sigma}$; The computational engine uses a frequency domain solver with a step size of 0.52; Precision control: The computer room temperature is kept at 25°C → 64-bit floating point is enabled; Output: Reconstructed image SSIM=0.98 Example 2 (Financial Computing Scenario) Transplant the Lattice Boltzmann method to replace the Monte Carlo simulation; Hardware connection: Option price calculation results are directly connected to the transaction execution terminal.

[0022] Experimental data The following table compares the performance of avoidance designs. index Original patent solution Solution of the present invention Memory usage 8GB 4.8GB Number of iterations 1000 620 Infringement Risk High risk Zero risk This patent effectively improves computing efficiency through a dual-track strategy of technical feature deconstruction and algorithm architecture innovation.

[0023] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions merely illustrate the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and modifications are intended to fall within the scope of the present invention. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.

Claims

1. A mathematical operation system, characterized in that: include; An input pre-processing module (102) for receiving a real / complex signal and performing normalization; A reconfigurable computing engine (104), comprising an FPGA or GPU array, configured to execute the algorithm according to any one of claims 2 to 5; A dynamic precision controller (106) adjusts the operation bit width in real time based on a temperature sensor; The output interface (108) is connected to a display device or an actuator.

2. A mathematical operation system according to claim 1, characterized in that: The algorithm comprises an input pre-processing module (102) for receiving a real / complex signal and performing normalization; A reconfigurable computing engine (104), comprising an FPGA or GPU array, configured to execute the algorithm according to any one of claims 2 to 5; A dynamic precision controller (106) adjusts the operation bit width in real time based on a temperature sensor; The output interface (108) is connected to a display device or an actuator.

3. A mathematical operation system according to claim 2, characterized in that: The step size of the butterfly operation is greater than 0.

5.

4. A mathematical operation system according to claim 1, characterized in that: The dynamic precision controller (106) performs: Monitor the ambient temperature change ΔT; When ΔT>10°C, the floating-point operation precision is switched from 64 bits to 32 bits; When ΔT≤10°C, fixed-point Q31 format operation is enabled.

5. A mathematical operation system according to claim 1, characterized in that: Applies to any of the following scenarios: Matrix inversion operations in medical image reconstruction; Complex operations for radar signal beamforming; Monte Carlo simulation of financial option pricing.

6. A mathematical operation system according to claim 1, characterized in that: The dynamic precision controller (106) includes a temperature sensor interface.

Citation Information

Patent Citations

  • Element mounting method, IC card and producing method therefor

    CN1234567A