Clock control system and method

Abstract

The invention relates to the technical field of signal processing, and discloses a clock control system and method.A first clock module and a second clock module have the same structure; the input end of the phase discriminator is connected with the first clock module and the second clock module, the output end of the phase discriminator is connected with the controller, and the phase discriminator compares and determines the phase difference of clock signals output by the first clock module and the second clock module and feeds back the phase difference to the controller; the controller is connected with the first clock module and the second clock module, and outputs an adjustment signal to the first clock module or the second clock module based on the phase difference; and the combiner is connected with the first clock module and the second clock module, and combines and outputs clock signals output by the first clock module and the second clock module. Self-calibration is achieved through the main clock link and the compensation clock link, the phase difference of clock signals of the main clock link and the compensation clock link is reduced, interference of the external environment is eliminated, and therefore phase noise is reduced, and stability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing, in particular to a clock control system and method. BACKGROUND

[0002] The precision and stability of the clock module directly affect the overall performance of the spectrum analyzer and the accuracy of the measurement results. In the clock module, the phase noise generated by the crystal oscillator directly affects the detection ability of the spectrum analyzer for weak signals, reduces the resolution, signal-to-noise ratio and other performances of the spectrum analyzer; and with the passage of time, the aging of the crystal oscillator, the influence of the phase noise of the crystal oscillator on the performance of the spectrum analyzer will further deteriorate. In addition, the reference signal of the clock module will also be affected by environmental factors such as temperature and vibration, thereby causing problems such as frequency drift. The superposition of the above multiple factors results in the current clock module having high phase noise interference and low stability. SUMMARY

[0003] Therefore, the present application provides a clock control system and method to solve the problem of high phase noise interference and low stability of the clock module.

[0004] In a first aspect, the present application provides a clock control system, which comprises: a first clock module, a second clock module, a phase detector, a controller and a combiner; Wherein, the first clock module and the second clock module have the same structure; The input end of the phase detector is connected with the first clock module and the second clock module, and the output end is connected with the controller. The phase detector determines the phase difference of the clock signals output by the first clock module and the second clock module, and feeds back to the controller; The controller is connected with the first clock module and the second clock module. The controller outputs an adjustment signal to the first clock module or the second clock module based on the phase difference; The combiner is connected with the first clock module and the second clock module. The combiner combines and outputs the clock signals output by the first clock module and the second clock module.

[0005] In an optional embodiment, the first clock module comprises a first digital-to-analog converter, a first crystal oscillator and a first coupler; The first digital-to-analog converter is connected with the controller and the first crystal oscillator respectively, converts the signal output by the controller into an analog signal, and outputs the analog signal to the first crystal oscillator; The first crystal oscillator is connected with the first coupler. The first coupler couples the first clock signal output by the first crystal oscillator to the phase detector.

[0006] In an alternative embodiment, the first clock module further comprises a first phase-locked loop and a first power divider; The first power divider is connected with the first phase-locked loop, the first crystal oscillator and the first coupler respectively, and the first power divider divides the first clock signal output by the first crystal oscillator into two paths and feeds back to the first phase-locked loop and the first coupler respectively. The first phase-locked loop is connected with the first crystal oscillator, and the first phase-locked loop receives a reference signal input from outside and synchronizes the first clock signal with the reference signal.

[0007] In an alternative embodiment, the first clock module further comprises a first switch; The first switch is connected with the first phase-locked loop, the first digital-to-analog converter and the first crystal oscillator respectively.

[0008] In an alternative embodiment, the system further comprises a third power divider; The third power divider is connected with the first phase-locked loop and the second phase-locked loop of the second clock module respectively, and the third power divider divides the reference signal input from outside into two paths and feeds back to the first phase-locked loop and the second phase-locked loop respectively.

[0009] In an alternative embodiment, the system further comprises an analog-to-digital converter; The analog-to-digital converter is connected with the phase detector and the controller respectively, and the analog-to-digital converter converts the phase difference output by the phase detector into a digital signal and outputs to the controller.

[0010] In a second aspect, the application provides a clock control method applied to the clock control system of the first aspect or any of the corresponding embodiments, and the method comprises: The first clock module generates and outputs the first clock signal based on the initial configuration signal, and the second clock module generates and outputs the second clock signal based on the initial configuration signal; The phase detector determines the phase difference between the first clock module and the second clock module based on the first clock signal and the second clock signal and feeds back to the controller; The controller determines the adjustment signal based on the phase difference and outputs the adjustment signal to the first clock module or the second clock module; The first clock module or the second clock module adjusts the corresponding clock signal based on the adjustment signal.

[0011] In an alternative embodiment, the first clock module generates and outputs the first clock signal based on the initial configuration signal, and the second clock module generates and outputs the second clock signal based on the initial configuration signal, which comprises: If the initial configuration signal is a signal output by the controller, in the first clock module, the first switch controls the first digital-to-analog converter to be connected with the first crystal oscillator, so that the first digital-to-analog converter controls the first crystal oscillator to generate and output the first clock signal based on the initial configuration signal. In the second clock module, the second switch controls the second digital-to-analog converter to be connected with the second crystal oscillator, so that the second digital-to-analog converter controls the second crystal oscillator to generate and output the second clock signal based on the initial configuration signal.

[0012] In an optional embodiment, the first clock module generates and outputs the first clock signal based on the initial configuration signal, and the second clock module generates and outputs the second clock signal based on the initial configuration signal, including: If the initial configuration signal is a signal input externally, in the first clock module, the first switch controls the first phase-locked loop to be connected with the first crystal oscillator, so that the first phase-locked loop controls the first crystal oscillator to generate and output the first clock signal based on the initial configuration signal. In the second clock module, the second switch controls the second digital-to-analog converter to be connected with the second crystal oscillator, so that the second digital-to-analog converter controls the second crystal oscillator to generate and output the second clock signal based on the reference signal output by the controller, wherein the reference signal is generated by the controller based on the initial configuration signal input externally.

[0013] In an optional embodiment, the controller determines the adjustment signal based on the phase difference, including: The controller looks up the corresponding relationship between the phase difference and the adjustment signal based on the phase difference, to determine the adjustment signal corresponding to the phase difference, wherein the corresponding relationship between the phase difference and the adjustment signal is calculated based on a gradient descent manner.

[0014] The clock control system provided by the embodiment of the application has the following advantages: by setting two clock modules with the same structure, one of the clock modules is used as a main clock link and the other clock module is used as a compensation clock link, so that self-calibration is performed in the clock system through the main clock link and the compensation clock link, thereby excluding the interference of external environment and improving stability; the phase difference between the clock signals output by the two clock modules is determined by the phase detector, the adjustment signal corresponding to the phase difference is determined by the controller, and the clock module serving as the compensation clock link is controlled based on the adjustment signal, so as to adjust the clock signal output by the clock module serving as the compensation clock link, thereby reducing the phase difference between the clock signals of the main clock link and the compensation clock link, and thus reducing the phase noise. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0016] Figure 1 is a schematic diagram of the architecture of a clock control system provided by an embodiment of the present application; Figure 2 is a schematic diagram of the architecture of a clock control system provided by an embodiment of the present application; Figure 3 is a schematic diagram of the architecture of a clock control system provided by an embodiment of the present application; Legend: 1, first clock module; 2, second clock module; 3, phase discriminator; 4, controller; 5, combiner. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0018] The precision and stability of the clock module directly affect the overall performance of the spectrum analyzer and the accuracy of the measurement results. In the clock module, the phase noise generated by the crystal oscillator directly affects the detection ability of the spectrum analyzer for weak signals, reduces the resolution, signal-to-noise ratio and other performances of the spectrum analyzer; and as the use time elapses and the crystal oscillator ages, the influence of the phase noise of the crystal oscillator on the performance of the spectrum analyzer will further deteriorate. In addition, the reference signal of the clock module will also be affected by environmental factors such as temperature and vibration, resulting in problems such as frequency drift. The superposition of the above multiple factors results in high phase noise interference and low stability of the current clock module.

[0019] Based on this, the application provides a clock control system, comprising: a first clock module, a second clock module, a phase detector, a controller and a combiner; wherein the first clock module and the second clock module have the same structure; the input end of the phase detector is connected with the first clock module and the second clock module, the output end is connected with the controller, the phase detector compares and determines the phase difference of the clock signals output by the first clock module and the second clock module, and feeds back to the controller; the controller is connected with the first clock module and the second clock module, the controller outputs an adjustment signal to the first clock module or the second clock module based on the phase difference; the combiner is connected with the first clock module and the second clock module, and the combiner combines and outputs the clock signals output by the first clock module and the second clock module. The application sets two clock modules with the same structure, takes one of the clock modules as a main clock link and the other as a compensation clock link, so that the clock system is self-calibrated internally through the main clock link and the compensation clock link, thereby excluding the interference of the external environment and improving the stability; the phase detector determines the phase difference of the clock signals output by the two clock modules, the controller determines the adjustment signal corresponding to the phase difference, and controls the clock module as the compensation clock link based on the adjustment signal, so as to adjust the clock signal output by the clock module as the compensation clock link, thereby reducing the phase difference of the clock signals of the main clock link and the compensation clock link, and reducing the phase noise.

[0020] It should be noted that the terms "first", "second" and the like in the present application are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or server including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0021] According to an embodiment of the application, a clock control system embodiment is provided. As shown in the figure, the system comprises: a first clock module 1, a second clock module 2, a phase detector 3, a controller 4 and a combiner 5. Wherein the first clock module 1 and the second clock module 2 have the same structure, one of the first clock module 1 and the second clock module 2 as a main clock link, the other as a compensation clock link, through the comparison and adjustment of the clock signals of the main clock link and the compensation clock link, the clock signal self-calibration of the clock control system is realized. Figure 1

[0022] ​In the embodiment of the present application, the input end of the phase detector 3 is connected with the first clock module 1 and the second clock module 2, and the output end is connected with the controller 4. The phase detector 3 compares and determines the phase difference of the clock signals output by the first clock module 1 and the second clock module 2, and feeds back to the controller 4.

[0023] In the embodiment of the present application, the controller 4 is connected with the first clock module 1 and the second clock module 2. The controller 4 outputs an adjustment signal to the first clock module 1 or the second clock module 2 based on the phase difference. The combiner 5 is connected with the first clock module 1 and the second clock module 2. The combiner 5 combines and outputs the clock signals output by the first clock module 1 and the second clock module 2.

[0024] In an alternative embodiment, Figure 2 is a structural schematic diagram of a clock control system provided by the embodiment of the present application, as Figure 2 shown, the first clock module 1 includes a first digital-to-analog converter, a first crystal oscillator and a first coupler.

[0025] The first digital-to-analog converter is used to convert a digital signal into an analog signal. The controller 4 and the first crystal oscillator are connected respectively. The signal output by the controller 4 is a digital signal. The first digital-to-analog converter converts the signal output by the controller 4 into an analog signal and outputs it to the first crystal oscillator. It should be noted that if the first clock module 1 is a master clock link, then only when the reference clock is an internal reference source, the controller 4 outputs a signal to the first digital-to-analog converter of the first clock module 1. At this time, the reference clock is generated by the controller 4 and output to the first clock module 1 and the second clock module 2. If the first clock module 1 is a compensation clock link, then regardless of whether the reference clock is an internal reference source or an external reference source, the controller 4 outputs an adjustment signal to the first digital-to-analog converter of the first clock module 1.

[0026] In an alternative embodiment, as Figure 2 shown, the first crystal oscillator is connected with the first coupler. The first coupler couples the first clock signal output by the first crystal oscillator to the phase detector 3.

[0027] In an alternative embodiment, as Figure 2As shown, the first clock module 1 further comprises a first phase-locked loop and a first power divider. The first power divider is connected with the first phase-locked loop, the first crystal oscillator and the first coupler respectively. The first power divider divides the first clock signal output by the first crystal oscillator into two paths, and feeds back to the first phase-locked loop and the first coupler respectively. The first phase-locked loop is connected with the first crystal oscillator. The first phase-locked loop receives the reference signal input from outside, and synchronizes the first clock signal with the reference signal. When the external reference source is used as the reference clock, in order to ensure that the clock signal generated by the crystal oscillator in the clock module is consistent with the reference clock, the first phase-locked loop is used in cooperation with the first power divider. The first power divider divides the first clock signal output by the first crystal oscillator into two paths. One path is fed back to the first coupler, so that the first coupler couples the first clock signal to the phase detector 3, so as to ensure that the phase detector 3 can determine the phase difference of the clock signals output by the first clock module 1 and the second clock module 2. The other path is fed back to the first phase-locked loop. The first phase-locked loop compares the reference signal input from outside with the first clock signal, and controls the first crystal oscillator to adjust the generated first clock signal when the two are inconsistent, so as to make the first clock signal consistent with the reference clock input from outside.

[0028] In an optional embodiment, as shown in Figure 2 The first clock module 1 further comprises a first switch. The first switch is used to select and switch the signal for controlling the first crystal oscillator under different conditions of the internal reference source and the external reference source, and under different conditions of the first clock module 1 as the master clock link and the compensation clock link. The selection and switching of the signal by the first switch can be implemented according to the method embodiments described below. The first switch is connected with the first phase-locked loop, the first digital-to-analog converter and the first crystal oscillator respectively.

[0029] In an optional embodiment, as shown in Figure 2 The second clock module 2 has the same structure as the first clock module 1, that is, the second clock module 2 comprises a second digital-to-analog converter, a second crystal oscillator, a second coupler, a second phase-locked loop, a second power divider and a second switch. The connection relationship and the function of each component in the second clock module 2 can be referred to the description of the first clock module 1 above, and will not be repeated here.

[0030] In an alternative embodiment, the system further comprises a third power divider; the third power divider is connected with the first phase-locked loop and the second phase-locked loop of the second clock module 2 respectively, the third power divider divides the externally input reference signal into two paths and feeds back to the first phase-locked loop and the second phase-locked loop respectively, and then selects the signal for controlling the crystal oscillator through the first switch in the first clock module 1 and the second switch in the second clock module 2, so that the externally input reference signal can be input into both clock modules, and both clock modules can serve as the master clock link, thereby improving the flexibility of the clock control system.

[0031] In an alternative embodiment, as shown in Figure 2 the system further comprises an analog-to-digital converter. The analog-to-digital converter is connected with the phase detector 3 and the controller 4 respectively, because the output of the phase detector 3 is an analog signal and the controller 4 needs to receive a digital signal, so the analog-to-digital converter is connected between the phase detector 3 and the controller 4, and the analog-to-digital converter converts the phase difference output by the phase detector 3 into a digital signal and outputs the digital signal to the controller 4.

[0032] The clock control system provided by the embodiment of the present application has the following advantages: by arranging two clock modules with the same structure, one of the clock modules serves as the master clock link and the other clock module serves as the compensation clock link, so that the self-calibration of the clock system is performed through the master clock link and the compensation clock link, thereby excluding the interference of the external environment and improving the stability; the phase difference of the clock signals output by the two clock modules is determined by the phase detector, the adjustment signal corresponding to the phase difference is determined by the controller, and the clock module serving as the compensation clock link is controlled based on the adjustment signal to adjust the clock signal output by the clock module serving as the compensation clock link, thereby reducing the phase difference of the clock signals of the master clock link and the compensation clock link and reducing the phase noise.

[0033] According to the embodiment of the present application, a clock control method is provided, and it should be noted that the steps shown in the flowchart can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described herein can be executed in a different order.

[0034] In the embodiment, a clock control method is provided, which can be used in the clock control system described above, Figure 3 is a flowchart of a clock control method provided by the embodiment of the present application, as shown in Figure 3 the flowchart comprises the following steps: Step S301, the first clock module 1 generates and outputs the first clock signal based on the initial configuration signal, and the second clock module 2 generates and outputs the second clock signal based on the initial configuration signal.

[0035] In the embodiment of the present application, the initial configuration signal is the reference signal, that is, the reference clock; the initial configuration signal can be externally input, that is, an external reference source, or can be internally generated, that is, an internal reference source. Wherein, for the clock module as the master clock link, the initial configuration signal varies with the reference source, and for the clock module as the compensation clock link, the initial configuration signal is internally generated, that is, generated by the controller 4.

[0036] In an optional embodiment, taking the first clock module 1 as the master clock link and the second clock module 2 as the compensation clock link as an example, step S301 is described in detail: If the initial configuration signal is the signal output by the controller 4, that is, the internal reference source, in the first clock module 1, the first switch controls the first digital-to-analog converter to be connected with the first crystal oscillator, so as to output the initial configuration signal output by the controller 4 to the first crystal oscillator, thereby making the first digital-to-analog converter control the first crystal oscillator to generate and output the first clock signal based on the initial configuration signal. In the second clock module 2, the second switch controls the second digital-to-analog converter to be connected with the second crystal oscillator, so as to output the initial configuration signal output by the controller 4 to the first crystal oscillator, thereby making the second digital-to-analog converter control the second crystal oscillator to generate and output the second clock signal based on the initial configuration signal.

[0037] If the initial configuration signal is the externally input signal, that is, the external reference source, in the first clock module 1, the first switch controls the first phase-locked loop to be connected with the first crystal oscillator, so as to output the externally input initial configuration signal to the first crystal oscillator, thereby making the first phase-locked loop control the first crystal oscillator to generate and output the first clock signal based on the initial configuration signal; in the second clock module 2, the second switch controls the second digital-to-analog converter to be connected with the second crystal oscillator, so as to output the initial configuration signal output by the controller 4 to the first crystal oscillator, thereby making the second digital-to-analog converter control the second crystal oscillator to generate and output the second clock signal based on the reference signal output by the controller 4, wherein the reference signal output by the controller 4 is generated by the controller 4 based on the externally input initial configuration signal.

[0038] Wherein, in the case of internal reference source, the initial configuration signal generated by the controller 4 is generated based on the configuration information set by the user, and the user pre-configures the signal performance parameters such as the frequency, phase and amplitude of the clock signal. The controller 4 generates the initial configuration signal based on the configuration. In the case of external reference source, the reference signal generated by the controller 4 based on the initial configuration signal input from the outside can be generated based on the analysis of the initial configuration signal input from the outside, or can be generated based on the configuration information set by the user as shown in the case of the internal reference source. Similarly, the initial configuration signal input from the outside is also generated based on the configuration information set by the user.

[0039] It should be noted that the above examples are only illustrative of the embodiments of the present application, and are not limited to the main clock link and the compensation clock link. In actual application, the second clock module 2 can also be used as the main clock link, and the first clock module 1 can be used as the compensation clock link.

[0040] In step S302, the phase detector 3 determines the phase difference between the first clock module 1 and the second clock module 2 based on the first clock signal and the second clock signal, and feeds back to the controller 4.

[0041] In the embodiment of the present application, the phase detector 3 compares the first clock signal and the second clock signal to determine the phase difference between the first clock signal and the second clock signal, and outputs the phase difference after obtaining the phase difference. The analog phase difference is converted into digital quantity by the analog-to-digital converter, and is fed back to the controller 4, so that the controller 4 determines the adjustment signal based on the phase difference.

[0042] In step S303, the controller 4 determines the adjustment signal based on the phase difference, and outputs the adjustment signal to the first clock module 1 or the second clock module 2.

[0043] In the embodiment of the present application, the controller 4 determines the adjustment signal corresponding to the phase difference by looking up the corresponding relationship between the phase difference and the adjustment signal based on the phase difference, and outputs the adjustment signal to the first clock module 1 or the second clock module 2. Specifically, it is output to the clock module as a compensation clock link; wherein the corresponding relationship between the phase difference and the adjustment signal is calculated based on the gradient descent method.

[0044] In an optional embodiment, when the correspondence between the phase difference and the adjustment signal is calculated in a gradient descent based manner, the variation function of the phase noise power can be measured by an external phase noise meter, or obtained by digital signal processing, such as FFT analysis of phase jitter; the phase difference parameter and the learning rate are initialized, and in the iteration process, the gradient of the variation function is calculated based on the current phase difference parameter, and the learning rate is set to move one step along the negative gradient direction to update the phase difference, and through multiple iterations until the gradient tends to zero, the phase adjustment corresponding to the current phase difference is obtained. Thus, the correspondence between the phase adjustment and the phase difference is calculated, and at the same time, since the controller 4 outputs a digital signal, a correspondence between the phase adjustment and the signal voltage value output by the controller 4 is established, and thus the correspondence between the phase difference and the signal voltage value is obtained, that is, the correspondence between the phase difference and the adjustment signal.

[0045] In step S304, the first clock module 1 or the second clock module 2 adjusts the corresponding clock signal based on the adjustment signal.

[0046] In the embodiment of the application, as the compensation clock module, the corresponding clock signal is adjusted based on the adjustment signal. Through the cyclic iteration of the above steps, the phase difference between the first clock signal and the second clock signal meets the phase difference requirement, or the iteration number reaches the threshold value, at which time the first clock signal and the second clock signal are combined and output by the combiner 5.

[0047] In an optional embodiment, the signal output by the controller 4, that is, the initial configuration signal and the adjustment signal, can be output to the first clock module 1 and the second clock module 2, and selected by the first switch and the second switch in the first clock module 1 and the second clock module 2 before being output to the corresponding crystal oscillator. Specifically, if the first clock module 1 is the main clock link and the second clock module 2 is the compensation clock link, in the case of an internal reference source, the first switch is switched to connect the first digital-to-analog converter with the first crystal oscillator, and the second switch is switched to connect the second digital-to-analog converter with the second crystal oscillator; in the case of an external reference source, the first switch is switched to connect the first phase-locked loop with the first crystal oscillator, and the second switch is switched to connect the second digital-to-analog converter with the second crystal oscillator; if the first clock module 1 is the compensation clock link and the second clock module 2 is the main clock link, in the case of an internal reference source, the first switch is switched to connect the first digital-to-analog converter with the first crystal oscillator, and the second switch is switched to connect the second digital-to-analog converter with the second crystal oscillator; in the case of an external reference source, the first switch is switched to connect the first digital-to-analog converter with the first crystal oscillator, and the second switch is switched to connect the second phase-locked loop with the second crystal oscillator.

[0048] The clock control method provided by the embodiment of the present application sets two clock modules with the same structure, uses one of the clock modules as a main clock link and the other as a compensation clock link, thereby performing self-calibration within the clock system through the main clock link and the compensation clock link, thus eliminating the interference of the external environment and improving stability; the phase difference of the clock signals output by the two clock modules is determined by a phase discriminator, the adjustment signal corresponding to the phase difference is determined by a controller, and the clock module serving as the compensation clock link is controlled based on the adjustment signal to adjust the clock signal output by the clock module serving as the compensation clock link, thereby reducing the phase difference of the clock signals of the main clock link and the compensation clock link, thus reducing phase noise.

[0049] Although the embodiments of the present application are described in conjunction with the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the present application.

Claims

1. A clock control system, characterized in that: The system comprises: A first clock module (1), a second clock module (2), a phase detector (3), a controller (4) and a combiner (5); Wherein, the first clock module (1) and the second clock module (2) have the same structure; The input end of the phase detector (3) is connected to both the first clock module (1) and the second clock module (2), and the output end is connected to the controller (4). The phase detector (3) compares and determines the phase difference between the clock signals output by the first clock module (1) and the second clock module (2), and feeds back the phase difference to the controller (4). The controller (4) is connected to both the first clock module (1) and the second clock module (2), and the controller (4) outputs an adjustment signal to the first clock module (1) or the second clock module (2) based on the phase difference; The combiner (5) is connected to both the first clock module (1) and the second clock module (2), and the combiner (5) combines the clock signals output by the first clock module (1) and the second clock module (2) and outputs the combined signals.

2. The system according to claim 1, wherein: The first clock module (1) comprises a first digital-to-analog converter, a first crystal oscillator and a first coupler; The first digital-to-analog converter is connected to the controller (4) and the first crystal oscillator respectively, converts the signal output by the controller (4) into an analog signal, and outputs it to the first crystal oscillator; The first crystal oscillator is connected to the first coupler, and the first coupler couples the first clock signal output by the first crystal oscillator to the phase detector (3).

3. The system according to claim 2, characterized in that The first clock module (1) further comprises a first phase-locked loop and a first power divider; The first power divider is connected to the first phase-locked loop, the first crystal oscillator and the first coupler respectively, and the first power divider divides the first clock signal output by the first crystal oscillator into two paths, and feeds the two paths back to the first phase-locked loop and the first coupler respectively; The first phase-locked loop is connected to the first crystal oscillator, receives an external reference signal, and synchronizes the first clock signal with the reference signal.

4. The system according to claim 3, characterized in that The first clock module (1) further comprises a first switch; The first switch is connected to the first phase-locked loop, the first digital-to-analog converter, and the first crystal oscillator respectively.

5. The system according to claim 3, wherein: The system further includes a third power divider; The third power divider is connected to the first phase-locked loop and the second phase-locked loop of the second clock module (2) respectively, and the third power divider divides the external input reference signal into two paths and feeds them back to the first phase-locked loop and the second phase-locked loop respectively.

6. The system according to claim 1, wherein: The system also includes an analog-to-digital converter; The analog-to-digital converter is connected to the phase detector (3) and the controller (4) respectively. The analog-to-digital converter converts the phase difference output by the phase detector (3) into a digital signal and outputs it to the controller (4).

7. A clock control method, characterized in that: Applied to the clock control system according to any one of claims 1 to 6, the method comprises: The first clock module (1) generates and outputs a first clock signal based on an initial configuration signal, and the second clock module (2) generates and outputs a second clock signal based on the initial configuration signal; The phase detector (3) determines the phase difference between the first clock module (1) and the second clock module (2) based on the first clock signal and the second clock signal, and feeds back the phase difference to the controller (4); The controller (4) determines an adjustment signal based on the phase difference, and outputs the adjustment signal to the second clock module (2); The first clock module (1) or the second clock module (2) adjusts the corresponding clock signal based on the adjustment signal.

8. The method according to claim 7, characterized in that The first clock module (1) generates and outputs a first clock signal based on an initial configuration signal, and the second clock module (2) generates and outputs a second clock signal based on the initial configuration signal, comprising: If the initial configuration signal is a signal output by the controller (4), then in the first clock module (1), the first switch controls the first digital-to-analog converter to connect to the first crystal oscillator, so that the first digital-to-analog converter controls the first crystal oscillator to generate and output the first clock signal based on the initial configuration signal; In the second clock module (2), the second switch controls the second digital-to-analog converter to connect to the second crystal oscillator, so that the second digital-to-analog converter controls the second crystal oscillator to generate and output a second clock signal based on the initial configuration signal.

9. The method according to claim 7, characterized in that The first clock module (1) generates and outputs a first clock signal based on an initial configuration signal, and the second clock module (2) generates and outputs a second clock signal based on the initial configuration signal, comprising: If the initial configuration signal is an external input signal, in the first clock module (1), the first switch controls the first phase-locked loop to connect to the first crystal oscillator, so that the first phase-locked loop controls the first crystal oscillator to generate and output the first clock signal based on the initial configuration signal; In the second clock module (2), a second switch controls the second digital-to-analog converter to connect to the second crystal oscillator, so that the second digital-to-analog converter controls the second crystal oscillator to generate and output a second clock signal based on a reference signal output by the controller (4), wherein the reference signal is generated by the controller (4) based on the initial configuration signal input from the external input.

10. The method according to claim 7, characterized in that The controller (4) determines an adjustment signal based on the phase difference, comprising: The controller (4) searches for a corresponding relationship between the phase difference and the adjustment signal based on the phase difference, and determines the adjustment signal corresponding to the phase difference, wherein the corresponding relationship between the phase difference and the adjustment signal is calculated based on a gradient descent method.

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