MIMO wireless communication channel matrix compression method and device

Abstract

The invention discloses an MIMO (Multiple Input Multiple Output) wireless communication channel matrix compression method and device. The method comprises the following steps: dividing a channel matrix into a plurality of matrix sub-blocks with the same size; determining a sparse mode index value of each matrix sub-block according to the type of each matrix sub-block; storing each sparse mode index value into an index addressing array of a memory according to the numbering sequence of each matrix sub-block; for each sparse sub-block, generating a respective index column of each sparse sub-block, and storing each index column into an index addressing array according to the numbering sequence of each sparse sub-block; when matrix data are stored, all element data are stored in a block sparse channel array of a memory for dense sub-blocks, only all non-zero element data are stored in the block sparse channel array for sparse sub-blocks, and data are not stored for all-zero sub-blocks. According to the invention, the technical effect of effectively reducing the storage overhead of the channel matrix in MIMO wireless communication is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of sparse matrix data processing and storage, and particularly relates to a MIMO wireless communication channel matrix compression method and device. BACKGROUND

[0002] MIMO (Multiple Input Multiple Output) is a key technology in wireless communication. In a MIMO wireless communication system, a channel matrix is used to describe the wireless channel state between a transmitting end and a receiving end. Due to high antenna deployment density and complex channel environment, a MIMO channel matrix in practice often has high sparsity, that is, there are a large number of zero elements in the matrix.

[0003] The prior art usually adopts a general sparse matrix compression format (such as CSR, BCSR, etc.) when storing a MIMO wireless communication channel matrix of this kind of sparse matrix. However, these formats have the problem of large storage overhead when facing the characteristics of uneven sparsity distribution and various sparsity patterns of the channel matrix. How to reduce the storage overhead of the channel matrix in MIMO wireless communication is a technical problem that the prior art urgently needs to solve. SUMMARY

[0004] The present application proposes a MIMO wireless communication channel matrix compression method and device to solve at least one of the technical problems in the background.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a MIMO wireless communication channel matrix compression method is provided, which comprises:

[0006] dividing the MIMO wireless communication channel matrix into a plurality of matrix subblocks of consistent size;

[0007] determining the type of each matrix subblock according to the sparsity of each matrix subblock, wherein the matrix subblocks are divided into dense subblocks, sparse subblocks and all-zero subblocks according to the type, and determining the respective sparse pattern index value of each matrix subblock according to the type of each matrix subblock;

[0008] storing the sparse pattern index values in the index addressing array of the memory in the order of the numbers of the matrix subblocks;

[0009] for each sparse subblock, marking the position of a non-zero element in the matrix as 1 and the position of a zero element as 0 to generate the respective index column of each sparse subblock, and storing the index columns in the index addressing array in the order of the numbers of the sparse subblocks;

[0010] When storing matrix data, all the matrix sub-blocks are processed sequentially based on the numbering order of each matrix sub-block, wherein, for dense sub-blocks, all element data are stored in the block sparse channel array of the memory, for sparse sub-blocks, only all non-zero element data are stored in the block sparse channel array, and for all-zero sub-blocks, no data is stored.

[0011] Optionally, the MIMO wireless communication channel matrix compression method further includes:

[0012] When performing calculations, each sparse pattern index value in the index addressing array is read in sequence;

[0013] If the sparse pattern index value indicates a sparse sub-block, an index column corresponding to the sparse sub-block is read from the index addressing array, and the index column is broadcast to the input buffer and the bit / word row distributor. The input buffer selects input data at a corresponding position according to the index column, and the bit / word row distributor selects compressed matrix data at a corresponding position in the block sparse channel array according to the index column, so as to achieve alignment calculation between the input data and the compressed matrix data.

[0014] If the sparse mode index value indicates a dense sub-block, index control information identifying all data positions in the matrix sub-block as valid positions is broadcasted to the input buffer and the bit / word row distributor, the input buffer selects input data at corresponding positions according to the index control information, and the bit / word row distributor selects compressed matrix data at corresponding positions according to the index control information, so as to achieve alignment calculation between the input data and the compressed matrix data;

[0015] If the sparse pattern index value indicates an all-zero sub-block, the next sparse pattern index value is directly read.

[0016] Optionally, determining the type of each matrix sub-block according to the sparsity of each matrix sub-block includes:

[0017] When the sparsity of the matrix sub-block is equal to 1, the matrix sub-block is determined to be an all-zero sub-block;

[0018] When the sparsity of the matrix sub-block is greater than a preset sparsity threshold, determining that the matrix sub-block is a sparse sub-block;

[0019] When the sparsity of the matrix sub-block is less than or equal to the sparsity threshold, the matrix sub-block is determined to be a dense sub-block.

[0020] Optionally, the MIMO wireless communication channel matrix compression method further includes:

[0021] The sparsity threshold is determined based on the criterion that the storage overhead of the sparse sub-block is not greater than the storage overhead of the dense sub-block, wherein the storage overhead of the sparse sub-block includes: the storage overhead of the sparse pattern index value, the storage overhead of the index column, and the storage overhead of the non-zero element data, and the storage overhead of the non-zero element data is calculated based on the sparsity of the sparse sub-block; the storage overhead of the dense sub-block includes: the storage overhead of the sparse pattern index value and the storage overhead of all element data.

[0022] Optionally, during the process of selecting and aligning input data and compressed matrix data according to the index performed by the input buffer and the bit / word row distributor, a column-by-column processing method is adopted, and only one column of data in the matrix sub-block is processed in each cycle.

[0023] Optionally, the MIMO wireless communication channel matrix compression method further includes:

[0024] If the sparse pattern index value indicates an all-zero sub-block, the enable signal of the corresponding sense amplifier in the block sparse channel array is turned off to put the sense amplifier in an inactive state.

[0025] To achieve the above object, according to another aspect of the present invention, a MIMO wireless communication channel matrix compression device is provided, the device comprising:

[0026] A matrix sub-block partitioning module is used to divide the MIMO wireless communication channel matrix into multiple matrix sub-blocks of uniform size;

[0027] a sparse pattern index value generating module, configured to determine a type of each matrix sub-block according to the sparsity of each matrix sub-block, wherein the matrix sub-blocks are classified according to type as dense sub-blocks, sparse sub-blocks, and all-zero sub-blocks, and determine a sparse pattern index value of each matrix sub-block according to the type of each matrix sub-block;

[0028] A sparse pattern index value storage module, configured to store each of the sparse pattern index values ​​into an index addressing array of a memory according to the numbering order of each of the matrix sub-blocks;

[0029] an index column generation and storage module, configured to, for each of the sparse sub-blocks, mark the positions of non-zero elements in the matrix as 1 and the positions of zero elements as 0, generate an index column for each of the sparse sub-blocks, and store each of the index columns into the index addressing array in the order in which the sparse sub-blocks are numbered;

[0030] The compressed matrix data storage module is used to process all the matrix sub-blocks in sequence based on the numbering order of each matrix sub-block when storing matrix data, wherein, for dense sub-blocks, all element data are stored in the block sparse channel array of the memory, for sparse sub-blocks, only all non-zero element data are stored in the block sparse channel array, and no data is stored for all-zero sub-blocks.

[0031] Optionally, the MIMO wireless communication channel matrix compression device further includes:

[0032] An adaptive mapping matching module is configured to sequentially read each sparse pattern index value in the index addressing array during calculation; if the sparse pattern index value indicates a sparse sub-block, read the index column corresponding to the sparse sub-block from the index addressing array, broadcast the index column to the input buffer and the bit / word row distributor, the input buffer selects input data at a corresponding position based on the index column, and the bit / word row distributor selects compressed matrix data at a corresponding position in the block sparse channel array based on the index column, so as to achieve alignment calculation between the input data and the compressed matrix data; if the sparse pattern index value indicates a dense sub-block, broadcast index control information identifying all data positions in the matrix sub-block as valid positions to the input buffer and the bit / word row distributor, the input buffer selects input data at a corresponding position based on the index control information, and the bit / word row distributor selects compressed matrix data at a corresponding position based on the index control information, so as to achieve alignment calculation between the input data and the compressed matrix data; if the sparse pattern index value indicates an all-zero sub-block, directly read the next sparse pattern index value.

[0033] Optionally, the sparse pattern index value generation module includes:

[0034] The comparison and confirmation submodule is used to determine that the matrix subblock is an all-zero subblock when the sparsity of the matrix subblock is equal to 1, determine that the matrix subblock is a sparse subblock when the sparsity of the matrix subblock is greater than a preset sparsity threshold, and determine that the matrix subblock is a dense subblock when the sparsity of the matrix subblock is less than or equal to the sparsity threshold.

[0035] Optionally, the MIMO wireless communication channel matrix compression device further includes:

[0036] The sparsity threshold determination module is used to determine the sparsity threshold based on the criterion that the storage overhead of the sparse sub-block is not greater than the storage overhead of the dense sub-block, wherein the storage overhead of the sparse sub-block includes: the storage overhead of the sparse pattern index value, the storage overhead of the index column, and the storage overhead of the non-zero element data, and the storage overhead of the non-zero element data is calculated based on the sparsity of the sparse sub-block; the storage overhead of the dense sub-block includes: the storage overhead of the sparse pattern index value and the storage overhead of all element data.

[0037] Optionally, the adaptive mapping matching module is further configured to, if the sparse pattern index value indicates an all-zero sub-block, turn off an enable signal of a corresponding sense amplifier in the block sparse channel array to place the sense amplifier in an inactive state.

[0038] The beneficial effects of the present invention are:

[0039] The present invention divides the MIMO wireless communication channel matrix into blocks and then stores them in different ways according to the sparsity type of each block to minimize storage resources, thereby achieving the technical effect of effectively reducing the storage overhead of the channel matrix in MIMO wireless communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0041] Figure 1 This is a first flow chart of a MIMO wireless communication channel matrix compression method according to an embodiment of the present invention;

[0042] Figure 2 is a second flow chart of the MIMO wireless communication channel matrix compression method according to an embodiment of the present invention;

[0043] Figure 3 is a schematic diagram of dividing a sparse matrix into multiple matrix sub-blocks according to an embodiment of the present invention;

[0044] Figure 4 Schematic diagram of different types of matrix sub-block matrix data storage according to an embodiment of the present invention;

[0045] Figure 5 Schematic diagram of storage of indexes and data in a memory according to an embodiment of the present invention;

[0046] Figure 6 Schematic diagram of storage overhead of different types of matrix sub-blocks according to an embodiment of the present invention;

[0047] Figure 7 is a schematic diagram of an adaptive mapping and matching module according to an embodiment of the present invention;

[0048] Figure 8 Schematic diagram of data alignment processing of an input buffer and a bit / word row distributor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0050] It will be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0051] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or apparatuses.

[0052] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0053] Figure 1 FIG. 1 is a first flow chart of a MIMO wireless communication channel matrix compression method according to an embodiment of the present invention. Figure 1 As shown, in one embodiment of the present invention, the MIMO wireless communication channel matrix compression method of the present invention includes steps S101 to S105.

[0054] Step S101: Divide a MIMO wireless communication channel matrix into a plurality of matrix sub-blocks of the same size.

[0055] In the channel matrix of MIMO wireless communication, non-zero data is often unevenly distributed, with some areas being densely distributed, some areas being sparsely distributed, and some areas being all zero values. Therefore, the present invention proposes a new storage strategy for multiple matrix sub-blocks, such as Figure 3In the illustrated embodiment, the present invention partitions the original sparse matrix (i.e., the MIMO wireless communication channel matrix) into multiple 8×8 matrix sub-blocks. Each matrix sub-block maintains its own independent sparsity, ensuring comprehensive coverage of different sparsity levels. Compared to methods without sub-matrix partitioning, this solution not only reduces storage requirements but also simplifies overall storage operations.

[0056] In the present invention, the MIMO wireless communication channel matrix is ​​a two-dimensional real number matrix, and the dimension is usually M×N, where M and N can be typical large-scale communication matrix sizes such as 1024 and 2048. In order to facilitate unified processing and subsequent compressed storage, the present invention partitions the input high-dimensional MIMO channel matrix in the row and column directions into multiple sub-blocks. The number of rows and columns of each sub-block is a fixed value, such as 8×8 or 16×16. The partitioning method can be set according to the overall dimension of the matrix and the hardware structure configuration. Unifying the sub-block size is conducive to standardized recognition and encoding of sparse patterns, reducing control complexity, and facilitating the establishment of a consistent data addressing and scheduling mechanism in the hardware array.

[0057] like Figure 3 As shown, in one embodiment of the present invention, the present invention divides the input MIMO wireless communication channel matrix into multiple sub-blocks of fixed size. Each sub-block is a small 8×8 matrix. The present invention identifies the position of each sub-block by numbering (e.g., Block(i, j)) for subsequent sparsity determination and index construction. At the same time, in the data processing flow, column-wise order is preferably used to organize and access the matrix to adapt to index control broadcast and in-memory calculation paths.

[0058] Step S102: determining the type of each matrix sub-block according to the sparsity of each matrix sub-block, wherein the matrix sub-blocks are divided into dense sub-blocks, sparse sub-blocks and all-zero sub-blocks according to the type, and determining the sparse pattern index value of each matrix sub-block according to the type of each matrix sub-block.

[0059] In the present invention, each matrix sub-block is evaluated for sparsity and then classified according to its sparsity value. Sparsity is the ratio of the number of zero elements to the total number of elements in a matrix sub-block. If the sparsity is 100%, the sub-block is considered an all-zero sub-block. If the sparsity is greater than a set threshold, it is considered a sparse sub-block. If the sparsity is less than or equal to the set threshold, it is considered a dense sub-block.

[0060] like Figure 3 As shown, the present invention divides matrix sub-blocks into three types based on the number of zero data (Zero Data) and non-zero data (Non-ZeroData) in the matrix sub-blocks: dense (Dense), sparse (Sparse) and all-zero (All-Zero).

[0061] In the present invention, each type of sub-block corresponds to a unique sparse pattern index (SMI) value, which is encoded using 2 bits. In a specific embodiment of the present invention, code 00 represents an all-zero sub-block, code 01 represents a sparse sub-block, and code 11 represents a dense sub-block.

[0062] By classifying sub-blocks into different types, the present invention selects the optimal data compression and storage method based on the sparse structure characteristics of each sub-block type. Combined with the configuration of sparse pattern indexes, this allows for rapid identification of sub-block types and switching to the corresponding data read path during decoding or calculation, thereby reducing control logic complexity and improving processing efficiency.

[0063] Step S103 : storing the sparse pattern index values ​​into an index addressing array of a memory according to the numbering sequence of the matrix sub-blocks.

[0064] In the present invention, this step writes the sparse pattern index (SMI) values ​​of each sub-block into the memory's index addressing matrix (IAM) in numerical order, with each sub-block corresponding to an index position. Writing the sparse pattern index values ​​into the IAM enables the system to quickly determine the processing mode of each sub-block before calculation, controlling whether the data path reads the index column and accesses the data array, thereby improving the system's dynamic switching capabilities and overall response speed.

[0065] In one embodiment of the present invention, the memory is a magnetoresistive random access memory (MRAM).

[0066] In a specific embodiment of the present invention, the memory is specifically a spin-orbit torque magnetoresistive random access memory (SOT-MRAM). SOT-MRAM has the characteristics of non-volatility, high speed, and bit addressability, and is suitable as a storage medium for compressed control information.

[0067] like Figure 5 As shown, in Figure 5 In the SOT-MRAM array structure shown, the sparse mode index (SMI) is stored in a dedicated index address array (IAM) in the order of the matrix sub-block number. Each SMI value is sequentially arranged in column-priority order and stored in the index address array of the SOT-MRAM. The SMI storage structure maintains a one-to-one correspondence with the subsequent index columns and compressed data structures, facilitating rapid location and parsing.

[0068] Step S104: for each of the sparse sub-blocks, mark the non-zero element position in the matrix as 1 and the zero element position as 0, generate an index column for each of the sparse sub-blocks, and store each of the index columns in the index addressing array in the order of the numbering of the sparse sub-blocks.

[0069] In the present invention, for sparse sub-blocks, the index marks the non-zero element position as "1" and the zero position as "0", forming a bit index column. If the word block is 8×8, it will be a 64-bit index column. This index column is then stored in the index address array (IAM).

[0070] In the present invention, for each sparse sub-block, each position in the matrix is ​​traversed to generate an index column corresponding to the sub-block structure. The index column uses a binary mask to mark whether there is valid data at each position. The generated index column is written into the index addressing array according to the number, and together with the sparse pattern index, it constitutes the complete compression control information. By explicitly marking the non-zero data position, the present invention can avoid the subsequent writing of invalid data and reduce the storage load. The index column is subsequently used as a key control signal for sparse data decompression and multiplication alignment calculation, which can accurately control the access of the input path and data path, thereby improving the efficiency of the data path.

[0071] like Figure 5 As shown, in one embodiment of the present invention, the index columns are stored in the index address array (IAM) in the form of a bit mask constructed in column priority order, which is used to identify the location of non-zero elements in each sparse sub-block. Each index column is associated with the sparse pattern index value of the corresponding sub-block, and its length is consistent with the total number of sub-block elements (e.g., 64 bits for an 8×8 sub-block). The index column is subsequently broadcast to the input buffer and bit / word row allocator as control information during calculation, which is used to achieve aligned access of compressed data and input data, supporting accurate calculation of sparse matrices.

[0072] Step S105: When storing matrix data, all the matrix sub-blocks are processed sequentially based on the numbering order of each matrix sub-block, wherein for dense sub-blocks, all element data are stored in the block sparse channel array of the memory, for sparse sub-blocks, only all non-zero element data are stored in the block sparse channel array, and for all-zero sub-blocks, no data is stored.

[0073] In this invention, when storing specific matrix data, data is written to each subblock one by one in numerical order. For dense subblocks, all elements are written directly into the Block Sparse Channel array (BSC) without compression. For sparse subblocks, only non-zero elements are written according to their index columns, with the positions indicated by the index columns. For all-zero subblocks, the data writing step is skipped and no space is occupied in the BSC.

[0074] This write strategy ensures a high degree of alignment between the overall data storage structure and the index structure, significantly reducing the storage requirements for invalid data. This can significantly reduce MRAM space overhead, particularly in practical applications where the channel matrix is ​​highly sparse. Furthermore, sequential processing through numbering facilitates structured mapping of data within the memory, facilitating address alignment and streaming scheduling for subsequent decoding calculations.

[0075] Figure 4 Schematic diagram of matrix data storage of different types of matrix sub-blocks according to an embodiment of the present invention, such as Figure 4 As shown, Block #00 is a sparse sub-block with a sparse pattern index (SMI) of 01, indicating that the sub-block contains only a small number of non-zero elements. This sub-block is equipped with an index column (Index), which uses a 0 / 1 bit mask to mark which positions in the original data (Original Data) contain non-zero values. 1 indicates that the corresponding position is valid data, and 0 indicates that the zero value is not stored. During the actual data storage process, only the data items corresponding to the index value of 1 are extracted and stored sequentially in the block sparse channel array (BSC). This method effectively removes invalid zero elements and significantly reduces the storage overhead of the sparse sub-block.

[0076] Block #10 is a dense sub-block with a sparse pattern index (SMI) of 11, indicating that it contains a high number of nonzero elements. Due to the high data density and limited compression, this type of sub-block uses direct storage of raw data, with all data written to the BSC in sequence, unchanged. This type of sub-block does not require an index column, simplifying the read path and ensuring access efficiency while avoiding unnecessary indexing overhead.

[0077] Block #M0 is an all-zero sub-block, and its Sparse Pattern Index (SMI) is 00, indicating that all data in this sub-block is zero. In this case, the system does not need to store data values ​​or index information, retaining only the Sparse Pattern Index as an identifier, thereby minimizing storage space usage. During calculations, the SMI can be used to determine whether to skip read and calculation operations for this sub-block, effectively saving power and access time.

[0078] Figure 5 FIG. 1 is a schematic diagram of storage of indexes and data in a memory according to an embodiment of the present invention. Figure 5As shown in the figure, the IAM (index address array) is used to store compression control information related to each matrix sub-block, mainly including the sparse pattern index value (SMI) and the index column constructed for the sparse sub-block. The sparse pattern index value is used to identify the sub-block type (such as dense, sparse, or all zero), while the index column marks the position of non-zero elements in the sparse sub-block in the form of a bit mask. The IAM is physically deployed in the SOT-MRAM, supports bit-level addressing and high-frequency random access, and can realize fast parsing and path selection control of the compressed matrix structure, forming the core scheduling part of the sparse matrix compression storage structure.

[0079] The BSC (Block Sparse Channel Array) is used to store compressed matrix sub-block data. Specifically, for dense sub-blocks, the BSC stores all element data in its entirety; for sparse sub-blocks, the BSC stores only the non-zero element data in the order marked by the index column; and for all-zero sub-blocks, no data is stored in the BSC. As the primary data storage array, the BSC corresponds one-to-one with the index information recorded in the IAM and is deployed in the SOT-MRAM. Leveraging its high density, low power consumption, and bit addressing capabilities, it enables efficient access to compressed matrix data and in-memory computing support.

[0080] It can be seen from the above embodiments that the present invention effectively reduces the amount of redundant data in the storage process of the MIMO wireless communication channel matrix by classifying and compressing the sparse features at the sub-block level. Specifically, the present invention can adopt differentiated storage strategies for different sparsity types by uniformly dividing the matrix sub-blocks, judging the sparsity, setting the sparse pattern index, constructing the index column and classifying and storing the data, wherein the all-zero sub-blocks are completely skipped from being written, the sparse sub-blocks only store non-zero data, and the dense sub-blocks are directly written with the original values. The method of the present invention significantly reduces the storage overhead of the MIMO wireless communication channel matrix, improves the compression efficiency, and lays a structural foundation for subsequent rapid analysis and efficient calculation. It is particularly suitable for communication matrix scenarios with uneven sparse distribution.

[0081] By reducing the storage overhead of the channel matrix in MIMO wireless communications, the memory capacity requirements in base stations or terminal devices can be effectively reduced, reducing chip area and system power consumption. This also reduces data transfer and memory access latency, improving the real-time performance and energy efficiency of computational operations such as channel estimation and precoding. This optimization will help support larger-scale antenna array deployments in 5G and future 6G networks, and holds great promise for future applications.

[0082] In one embodiment of the present invention, determining the type of each matrix sub-block according to the sparsity of each matrix sub-block in step S102 specifically includes:

[0083] When the sparsity of the matrix sub-block is equal to 1, the matrix sub-block is determined to be an all-zero sub-block;

[0084] When the sparsity of the matrix sub-block is greater than a preset sparsity threshold, determining that the matrix sub-block is a sparse sub-block;

[0085] When the sparsity of the matrix sub-block is less than or equal to the sparsity threshold, the matrix sub-block is determined to be a dense sub-block.

[0086] In one embodiment of the present invention, the MIMO wireless communication channel matrix compression method of the present invention further includes:

[0087] The sparsity threshold is determined based on the criterion that the storage overhead of the sparse sub-block is not greater than the storage overhead of the dense sub-block, wherein the storage overhead of the sparse sub-block includes: the storage overhead of the sparse pattern index value, the storage overhead of the index column, and the storage overhead of the non-zero element data, and the storage overhead of the non-zero element data is calculated based on the sparsity of the sparse sub-block; the storage overhead of the dense sub-block includes: the storage overhead of the sparse pattern index value and the storage overhead of all element data.

[0088] In one embodiment of the present invention, the sparsity threshold may be determined by the following formula:

[0089]

[0090] Among them, the left side of the formula is the storage overhead of the sparse sub-block, the right side is the storage overhead of the dense sub-block, SMI is the storage overhead of the sparse pattern index value, Index is the storage overhead of the index column of the sparse sub-block, Bits is the number of bits occupied by each value in the block sparse channel array (for example, 16 bits), Block is the total number of elements in the sparse sub-block, for an N×N sparse sub-block, Block=N 2 , for example 64, is the sparsity threshold.

[0091] In one embodiment of the present invention, the matrix sub-block is an 8×8 matrix with a total of 64 elements. The block sparse channel array stores all data in column-order format. Each value in the block sparse channel array occupies 16 bits. The sparsity threshold calculated by the above formula is 6.4%. When the sparsity of a sparse sub-block exceeds 6.4%, it is classified as a sparse sub-block. Otherwise, if the sparsity does not exceed 6.4%, it is classified as a dense sub-block.

[0092] Figure 6 Schematic diagram of storage overhead of different types of matrix sub-blocks according to an embodiment of the present invention. Figure 6As shown in the figure, the storage overhead of a sparse sub-block (Sparse) consists of three main components: a sparse pattern index (SMI), an index column (Index), and non-zero data (Data). The SMI identifies the sub-block type and typically occupies a fixed bit width (e.g., 2 bits). The index column stores whether each element is non-zero in the form of a bit mask, occupying a number of bits equal to the number of elements in the sub-block (e.g., 64 bits for an 8×8 sub-block). The non-zero data portion only stores the actual data values ​​corresponding to the positions marked as 1 in the index column. Each value in the block sparse channel array occupies 16 bits.

[0093] Dense sub-blocks contain a large amount of non-zero data and are therefore not compressed. The storage overhead primarily consists of the sparse pattern index (SMI) and the complete data value. The SMI is also stored using a fixed bit width, while the data portion is written directly to the original values ​​of all elements in the sub-block. For example, an 8×8 dense sub-block requires storage of 64 values, each occupying 16 bits.

[0094] All-Zero sub-blocks contain no valid data and have minimal storage overhead. Only the Sparse Pattern Index (SMI) value needs to be stored to identify the sub-block type. Since all data is zero, there is no need to store index columns or data entities, nor is there a need to read or write the corresponding data path. The system can quickly skip the sub-block during operation by identifying the SMI value.

[0095] Since the present invention adopts a multi-sparse mode block-by-block storage strategy, directly multiplying the input with the block sparse channel array data may cause misalignment, resulting in calculation errors. To address this problem, the present invention proposes an adaptive mapping matching mechanism that aligns the input data with the BSC data to achieve accurate calculations. The adaptive mapping matching mechanism of the present invention can be specifically seen in Figure 2 The embodiment shown. Figure 2 As shown, in one embodiment of the present invention, the MIMO wireless communication channel matrix compression method of the present invention includes steps S201 to S204.

[0096] Step S201 , when performing calculation, sequentially read each sparse pattern index value in the index addressing array.

[0097] In the present invention, when performing calculations, the present invention sequentially reads the sparse pattern index value (SMI) corresponding to each matrix sub-block from the index address array (IAM) in column-priority order. Each SMI is a fixed-width code (e.g., 2 bits) used to indicate the type of the matrix sub-block. This step can be periodically triggered by a logic controller to decode the type of the matrix sub-blocks one by one. This processing of the present invention can achieve rapid identification of the storage mode of each matrix sub-block, enabling the system to determine in advance whether the current sub-block needs to be decompressed and whether it contains valid data without accessing the actual data, thereby improving the efficiency of access scheduling and the dynamic adaptability of the calculation path.

[0098] Step S202: If the sparse pattern index value indicates a sparse sub-block, the index column corresponding to the sparse sub-block is read from the index addressing array, and the index column is broadcast to the input buffer and the bit / word row distributor. The input buffer selects the input data at the corresponding position according to the index column, and the bit / word row distributor selects the compressed matrix data at the corresponding position in the block sparse channel array according to the index column, so as to realize the alignment calculation of the input data and the compressed matrix data.

[0099] In the present invention, when the SMI decoding result is "01", the system recognizes that the current processing object is a sparse sub-block. At this time, the corresponding index column is read from the IAM. The index column is a binary mask with a length equal to the number of sub-block elements (for example, 64 bits). The index column is broadcast to the input buffer and the bit / word row distributor, which respectively control the selection and alignment of the input data and the compressed matrix data. Optionally, data extraction is performed at a rhythm of one cycle per column to ensure that the valid elements in the calculation path can be correctly mapped.

[0100] This mechanism ensures that multiplication inputs are fully aligned with the data path while maintaining a sparse, compressed structure, avoiding misalignment issues caused by the sparse structure. Processing one column per cycle reduces read pressure, improves system stability, and keeps index broadcast overhead under control.

[0101] Step S203: If the sparse mode index value indicates a dense sub-block, index control information identifying all data positions in the matrix sub-block as valid positions is broadcast to the input buffer and the bit / word row distributor. The input buffer selects input data at corresponding positions according to the index control information, and the bit / word row distributor selects compressed matrix data at corresponding positions according to the index control information, so as to realize alignment calculation between the input data and the compressed matrix data.

[0102] In the present application, when the SMI decoding result is "11", the system determines that the current sub-block is a dense sub-block, that is, most of the data in the sub-block is non-zero value, and no compression is performed during storage. At this time, the system constructs a set of pre-set all "1" index control information, indicating that all data positions are valid. The index control signal is also broadcast to the input buffer and the bit / word line allocator, used to directly extract the input data and the corresponding matrix data at all positions of the dense sub-block. The present application avoids the overhead of constructing a real index column for the dense sub-block, while ensuring data integrity, taking into account access efficiency and logical consistency.

[0103] In an embodiment of the present application, the index control information indicating that all data positions in the matrix sub-block are valid positions is an index column with all elements being 1, for example, a 64-bit index column.

[0104] Step S204, if the sparse mode index value indicates a full zero sub-block, directly read the next sparse mode index value.

[0105] In the present application, when the SMI decoding result is "00", the system confirms that the current sub-block is a full zero sub-block, that is, there is no valid data. At this time, the index column reading and data access process is skipped, and the analysis process of the next sparse mode index value is directly entered. The processing method of the present application avoids unnecessary operations on invalid sub-blocks, which can greatly reduce memory access energy consumption and decoding overhead.

[0106] In a specific embodiment of the present application, the memory specifically adopts a spin orbit torque magnetoresistive random access memory (SOT-MRAM).

[0107] The present application uses a spin orbit torque magnetoresistive random access memory (SOT-MRAM) as the core storage medium, which overcomes the limitations of existing technologies such as CMOS-based crossbar and RRAM in terms of power consumption, stability, write speed and durability. Unlike the high static power consumption, large area occupation and susceptibility to leakage current problems existing in CMOS crossbar architecture, SOT-MRAM has the characteristics of non-volatility, low leakage, and fast writing, which can realize more efficient storage management and more reliable long-term operation. At the same time, compared with the scheme using RRAM with COO format, SOT-MRAM has better durability and stability in high-frequency write operation, and is not prone to problems such as write degradation and resistance fluctuation, ensuring the accuracy and consistency of the channel matrix in real-time updating process.

[0108] Furthermore, SOT-MRAM possesses bit addressability and high data reconstruction flexibility, enabling close integration with the sparse matrix compression storage format and alignment calculation mechanism of the present invention to achieve integrated storage, control, and computing. This allows the present invention to significantly reduce data handling and redundant computing overhead while maintaining a high compression ratio, fundamentally improving computational energy efficiency and meeting the practical needs of MIMO communication systems for high-speed, low-power, and highly reliable storage technology.

[0109] In one embodiment of the present invention, during the process of selecting and aligning input data and compressed matrix data according to the index performed by the input buffer and the bit / word row distributor, a column-by-column processing method is adopted, and only one column of data in the matrix sub-block is processed in each cycle.

[0110] In one embodiment of the present invention, to ensure precise alignment of input data with compressed matrix data within the in-memory computation path, the system employs a column-by-column processing strategy in the input buffer and bit / word row allocator: This strategy processes only one column of data within a matrix subblock per cycle. This strategy is particularly well-suited to the 8×8 matrix subblock structure employed in the present invention, where each subblock contains eight columns, requiring eight cycles to complete processing of the entire matrix subblock.

[0111] The design of the present invention originates from the column-order encoding feature of the index columns in the sparse sub-blocks. When a sub-block is determined to be a sparse sub-block, its corresponding index column is expanded into a mask vector in a column-first manner and broadcast to the input buffer and the bit / word row distributor. In each cycle, the system selects the input data with the position value of "1" in the corresponding column in the mask, and performs multiplication and addition calculations with the non-zero data compressed and stored in the block sparse channel array (BSC). The column-by-column processing method can avoid data misalignment or redundant scheduling problems caused by one-time full-block activation, reduce hardware complexity, and control the synchronization overhead of broadcast and sensing resources, thereby significantly improving the system's operational stability and energy efficiency while ensuring accuracy.

[0112] In one embodiment of the present invention, the MIMO wireless communication channel matrix compression method of the present invention further includes:

[0113] If the sparse pattern index value indicates an all-zero sub-block, the enable signal of the corresponding sense amplifier in the block sparse channel array is turned off to put the sense amplifier in an inactive state.

[0114] To further reduce power consumption, in one embodiment of the present invention, upon identifying an all-zero matrix sub-block (i.e., its sparsity pattern index is "00"), the system disables the enable signal for the corresponding sense amplifier (SA) in the block sparse channel array (BSC-CIM array), rendering the sense amplifier inactive. Specifically, upon reading the "00" index, the selector skips the computation scheduling process for that sub-block and simultaneously disables the corresponding SA, preventing ineffective data sensing and circuit activation.

[0115] This mechanism in the present invention establishes an index-controlled adaptive sense amplifier power-down strategy, utilizing dynamic enable control of the sensing unit to achieve power gating. This design can significantly reduce overall static and switching power consumption when a large number of all-zero blocks exist in a large sparse matrix. This is particularly suitable for applications in MIMO systems with highly sparse channel matrices and high computational intensity. In this way, the present invention not only achieves resource optimization in storage compression, but also improves energy efficiency in the computational phase.

[0116] Figure 8 FIG. 1 is a schematic diagram of data alignment processing of an input buffer and a bit / word row distributor according to an embodiment of the present invention. Figure 8 As shown, the computational architecture of the present invention includes an input buffer and a BSC-CIM array (block sparse channel computation array). This architecture leverages an index broadcast mechanism to physically synchronize the data path and input path through bit line drivers, word line drivers, and sense amplifiers (SAs), thereby completing in-memory computations on sparse compressed matrices.

[0117] During calculation, the sparse pattern index value (SMI) corresponding to each matrix sub-block is read from the index address array (IAM) in sequence, and different calculation paths are driven according to the SMI value:

[0118] If the SMI indicates a sparse sub-block (Sparse), the corresponding index column is read and broadcast to the InputBuffer and the bit / word row distributor. The input data is stored in the Input Buffer. After receiving the index column, only the data channel with a mask of "1" is activated to select the valid input data. At the same time, the bit / word row distributor in the BSC-CIM Array controls the selection of the corresponding compressed data according to the index column. Subsequently, the sense amplifier (SA) collects the compressed matrix data value corresponding to the input data on the activated column to complete the column-by-column multiplication and addition calculation. Since the sparse sub-block has a sparse structure, this process processes one column of data per cycle in a sub-block, and it takes a maximum of 8 cycles to complete the operation of the entire sub-block.

[0119] If the SMI indicates a dense sub-block (Dense), the system generates index control information that is logically equivalent to all 1s, indicating that all input data and matrix data are valid. This index information is also broadcast to the input buffer and the bit / word row allocator in the BSC-CIMArray. The input buffer is fully enabled, and the bit / word row allocator activates all sub-block rows in sequence to fully capture the entire block of data. This mode skips the index column read step, minimizing access latency and is suitable for areas with high data density.

[0120] If the SMI indicates an all-zero sub-block, the index column and data read operations are skipped, and all sense amplifiers are turned off in the current cycle, without activating any word lines or bit lines. This mechanism uses the SMI to control the sense amplifier enable signal, automatically powering down the sensing path, thereby avoiding unnecessary data transmission and computational power consumption in the inactive sub-block.

[0121] Figure 7 Schematic diagram of the adaptive mapping matching module according to an embodiment of the present invention. Figure 7 As shown, the present invention sequentially reads the sparse pattern index (SMI) from the index address array (IAM) via a selector to identify the compression type of the currently processed matrix sub-block. The SMI is a 2-bit code, with the most significant bit being the MSB and the least significant bit being the LSB. Both bits are used by decoding logic to drive sub-block classification decisions.

[0122] First, the SMI signal is fed into the control logic unit, which identifies the MSB and LSB combinations and classifies the sub-block into sparse, dense, or all-zero modes. When SMI = 00 (i.e., an all-zero sub-block), the FLAG00 unit is triggered, outputting a valid mask signal, indicating that the current sub-block contains no valid data. At this point, the module control path directly skips the index column and data access, and simultaneously disables the corresponding sense amplifier (SA) in the block sparse channel array (BSC) to avoid unnecessary power consumption.

[0123] If SMI≠00, the index column loading phase is entered. A MUX (multiplexer) is set in this module to select the index column that needs to be broadcast currently from three inputs according to the value of SMI. One of them comes from the actual sparse sub-block index column read from the IAM (applicable to SMI=01), another is a logically constructed all-"1" index column (applicable to SMI=11, corresponding to dense sub-blocks), and the third is an all-"0" index column (corresponding to all-zero sub-blocks, selected when controlled by FLAG00). After the MUX receives the SMI, the control logic determines the currently valid index type and outputs it.

[0124] The output index column is broadcast to the input buffer and bit / word row allocator. The input buffer uses this index column mask to filter the input vector data at the corresponding position, while the bit / word row allocator uses the same index to select the compressed matrix data in the block sparse channel array, achieving a one-to-one correspondence across the computational paths. This alignment operation is processed column by column, with one column of data processed per cycle. The computation of an 8×8 sub-block can be completed in eight consecutive cycles.

[0125] Through the above technical solutions, the adaptive sparse matrix compression circuit of the present invention not only achieves compression of multiple sparse patterns, significantly reducing storage overhead, but also reduces overall circuit power consumption by controlling the sense amplifier through indexing. Combined with the low power consumption, high speed, and non-volatility of MRAM, the present invention further expands the application potential of MRAM in MIMO wireless communications.

[0126] As can be seen from the above embodiments, the present invention innovatively adopts spin-orbit torque magnetic random access memory (SOT-MRAM) devices as core memory, and on this basis successfully builds an adaptive sparse matrix compression method that is highly compatible with the in-memory computing array. The present invention has excellent versatility and can implement accurate and efficient compression processing on sparse matrices of various sparsities. By flexibly using a variety of sparse modes, it perfectly matches the unique characteristics of the uneven distribution of sparse data in the channel matrix in MIMO wireless communications. In terms of storage and power consumption optimization, the present invention has achieved remarkable results. It can not only minimize storage overhead and greatly save storage resources, but also significantly reduce power consumption, effectively improve the energy efficiency ratio in the calculation process, and provide solid technical support for efficient and energy-saving computing systems. In addition, based on the above-mentioned advanced compression strategy, the present invention has carefully designed a set of adaptive mapping matching schemes, which have excellent performance and can complete various computing tasks quickly, efficiently and accurately, greatly improving computing efficiency, providing key assistance for performance improvement of MIMO wireless communication systems, and has broad application prospects and huge practical value.

[0127] Some terms that appear in the above embodiments of the present invention are explained below.

[0128] MRAM (Magnetoresistive Random Access Memory) is a non-volatile memory based on the magnetoresistive effect. It stores data by changing the magnetization direction of a magnetic material, offering high-speed read and write speeds, high durability, and data retention even after power failures. Compared to traditional storage technologies, MRAM offers advantages including speeds approaching DRAM, a lifespan far exceeding that of flash memory, and low power consumption, making it suitable for applications in embedded systems, automotive electronics, and artificial intelligence. As technology evolves, MRAM is expected to become a key storage solution in high-end computing and the Internet of Things.

[0129] SOT-MRAM: SOT-MRAM (Spin-Orbit Torque Magnetoresistive Random Access Memory) is a new type of non-volatile memory technology that uses the spin-orbit torque effect to drive magnetization reversal. It achieves higher write speeds and lower energy consumption by separating the read and write paths (current flows through the underlying heavy metal layer to generate a transverse spin current), while avoiding the write reliability issues of traditional STT-MRAM. Compared with traditional MRAM, SOT-MRAM has significantly improved write efficiency (more than 10 times faster), power consumption (reduced by 30%-50%), and durability (>1e16 times). SOT-MRAM is regarded as the next generation of high-performance MRAM, suitable for storage and computing integration and high-speed cache.

[0130] MIMO: Multiple Input Multiple Output (MIMO) is a key technology in wireless communications. By deploying multiple antennas at the transmitter and receiver, it leverages the spatial dimension to transmit data in parallel or enhance signal reliability, significantly improving system capacity and anti-interference capabilities. Its core principles include spatial multiplexing (simultaneous transmission of multiple signals) and spatial diversity (multipath fading resistance). Compared to traditional single-antenna (SISO) systems, MIMO can achieve several times the rate increase or expanded coverage within the same bandwidth. This technology is widely used in modern communication standards such as 5G and Wi-Fi 6, supporting high-density connection scenarios such as high-definition video and the Internet of Things.

[0131] In-memory computing (also known as integrated storage and computing, memory computing, etc., in English CIM / IMC): In-memory computing is a technology that breaks the bottleneck of the traditional von Neumann architecture. It embeds the computing unit into the storage unit and directly uses the physical properties of the storage device (such as resistance and current) to perform analog calculations, avoiding frequent data transfer between the processor and memory. Its core advantage is that it greatly reduces the energy consumption and latency caused by the "memory wall". It is particularly good at performing matrix multiplication and addition operations in the field of AI, and its energy efficiency can reach 10-100 times that of traditional GPU / CPU. It is currently mainly used in edge AI chips, neural network accelerators and other fields. Representative technologies include integrated storage and computing architectures based on RRAM and MRAM, which are regarded as the core direction of the next generation of low-power intelligent computing.

[0132] It should be noted that although a logical order is shown in the flowcharts, in some cases, the steps shown or described may be performed in an order different from that shown or described here.

[0133] Based on the same inventive concept, embodiments of the present invention also provide a MIMO wireless communication channel matrix compression device, as described in the following embodiments. Since the principles for solving problems in the MIMO wireless communication channel matrix compression device are similar to those in the MIMO wireless communication channel matrix compression method, the embodiments of the MIMO wireless communication channel matrix compression device can refer to the embodiments of the MIMO wireless communication channel matrix compression method, and any repetitions will not be repeated. As used below, the terms "unit" or "module" may refer to a combination of software and / or hardware that implements a predetermined function.

[0134] In one embodiment of the present invention, the MIMO wireless communication channel matrix compression apparatus of the present invention includes:

[0135] A matrix sub-block partitioning module is used to divide the MIMO wireless communication channel matrix into multiple matrix sub-blocks of uniform size;

[0136] a sparse pattern index value generating module, configured to determine a type of each matrix sub-block according to the sparsity of each matrix sub-block, wherein the matrix sub-blocks are classified according to type as dense sub-blocks, sparse sub-blocks, and all-zero sub-blocks, and determine a sparse pattern index value of each matrix sub-block according to the type of each matrix sub-block;

[0137] A sparse pattern index value storage module, configured to store each of the sparse pattern index values ​​into an index addressing array of a memory according to the numbering order of each of the matrix sub-blocks;

[0138] An index column generating and storing module is configured to mark the position of non-zero elements in the matrix as 1 and the position of zero elements as 0 to generate an index column of each sparse sub-block, and store the index columns in the index addressing array according to the numbering order of the sparse sub-blocks;

[0139] A compressed matrix data storing module is configured to sequentially process all the matrix sub-blocks according to the numbering order of the matrix sub-blocks when storing the matrix data, wherein all element data of a dense sub-block is stored in the block sparse channel array of the memory, only non-zero element data of a sparse sub-block is stored in the block sparse channel array of the memory, and no data is stored for a zero sub-block.

[0140] In an embodiment of the present application, the MIMO wireless communication channel matrix compression device further comprises:

[0141] An adaptive mapping matching module is configured to sequentially read the sparse pattern index values in the index addressing array when performing the calculation, read the index column corresponding to the sparse sub-block from the index addressing array if the sparse pattern index value indicates the sparse sub-block, broadcast the index column to the input buffer and the bit / word line allocator, the input buffer selects the input data at the corresponding position according to the index column, and the bit / word line allocator selects the compressed matrix data at the corresponding position in the block sparse channel array according to the index column to realize the aligned calculation of the input data and the compressed matrix data, broadcast the index control information indicating that all data positions in the matrix sub-block are valid positions to the input buffer and the bit / word line allocator if the sparse pattern index value indicates the dense sub-block, the input buffer selects the input data at the corresponding position according to the index control information, and the bit / word line allocator selects the compressed matrix data at the corresponding position according to the index control information to realize the aligned calculation of the input data and the compressed matrix data, and directly read the next sparse pattern index value if the sparse pattern index value indicates the zero sub-block.

[0142] In an embodiment of the present application, the adaptive mapping matching module can have the structure as shown in Figure 7 The working principle of the adaptive mapping matching module has been described above, and will not be repeated here.

[0143] In an embodiment of the present application, the sparse pattern index value generating module comprises:

[0144] A comparison and confirmation submodule is configured to determine that the matrix sub-block is a zero sub-block when the sparsity of the matrix sub-block is equal to 1, determine that the matrix sub-block is a sparse sub-block when the sparsity of the matrix sub-block is greater than a preset sparsity threshold, and determine that the matrix sub-block is a dense sub-block when the sparsity of the matrix sub-block is less than or equal to the sparsity threshold.

[0145] In one embodiment of the present invention, the MIMO wireless communication channel matrix compression apparatus of the present invention further includes:

[0146] The sparsity threshold determination module is used to determine the sparsity threshold based on the criterion that the storage overhead of the sparse sub-block is not greater than the storage overhead of the dense sub-block, wherein the storage overhead of the sparse sub-block includes: the storage overhead of the sparse pattern index value, the storage overhead of the index column, and the storage overhead of the non-zero element data, and the storage overhead of the non-zero element data is calculated based on the sparsity of the sparse sub-block; the storage overhead of the dense sub-block includes: the storage overhead of the sparse pattern index value and the storage overhead of all element data.

[0147] In one embodiment of the present invention, the input buffer and the bit / word row distributor select and align input data and compressed matrix data according to the index, using a column-by-column processing method, and only processes one column of data in the matrix sub-block in each cycle.

[0148] In one embodiment of the present invention, the adaptive mapping matching module is further configured to turn off an enable signal of a corresponding sense amplifier in the block sparse channel array if the sparse pattern index value indicates an all-zero sub-block, so that the sense amplifier is in an inactive state.

[0149] Obviously, those skilled in the art will appreciate that the modules or steps of the present invention described above can be implemented using a general-purpose computing device. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they can be implemented using program code executable by a computing device, which can then be stored in a storage device and executed by the computing device. Alternatively, they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0150] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A MIMO wireless communication channel matrix compression method, characterized in that: include: Dividing the MIMO wireless communication channel matrix into a plurality of matrix sub-blocks of uniform size; Determining a type of each matrix sub-block according to the sparsity of each matrix sub-block, wherein the matrix sub-blocks are classified according to type as: dense sub-blocks, sparse sub-blocks, and all-zero sub-blocks; and determining a sparsity pattern index value of each matrix sub-block according to the type of each matrix sub-block; Storing the sparse pattern index values ​​in an index addressing array of a memory according to the numbering order of the matrix sub-blocks; For each of the sparse sub-blocks, mark the non-zero element position in the matrix as 1 and the zero element position as 0, generate an index column for each of the sparse sub-blocks, and store each of the index columns into the index addressing array according to the numbering order of the sparse sub-blocks; When storing matrix data, all the matrix sub-blocks are processed sequentially based on the numbering order of each matrix sub-block, wherein, for dense sub-blocks, all element data are stored in the block sparse channel array of the memory, for sparse sub-blocks, only all non-zero element data are stored in the block sparse channel array, and for all-zero sub-blocks, no data is stored.

2. The MIMO wireless communication channel matrix compression method according to claim 1, characterized in that: Also includes: When performing calculations, each sparse pattern index value in the index addressing array is read in sequence; If the sparse pattern index value indicates a sparse sub-block, an index column corresponding to the sparse sub-block is read from the index addressing array, and the index column is broadcast to the input buffer and the bit / word row distributor. The input buffer selects input data at a corresponding position according to the index column, and the bit / word row distributor selects compressed matrix data at a corresponding position in the block sparse channel array according to the index column, so as to achieve alignment calculation between the input data and the compressed matrix data. If the sparse mode index value indicates a dense sub-block, index control information identifying all data positions in the matrix sub-block as valid positions is broadcasted to the input buffer and the bit / word row distributor, the input buffer selects input data at corresponding positions according to the index control information, and the bit / word row distributor selects compressed matrix data at corresponding positions according to the index control information, so as to achieve alignment calculation between the input data and the compressed matrix data; If the sparse pattern index value indicates an all-zero sub-block, the next sparse pattern index value is directly read.

3. The MIMO wireless communication channel matrix compression method according to claim 1, characterized in that: The determining the type of each matrix sub-block according to the sparsity of each matrix sub-block includes: When the sparsity of the matrix sub-block is equal to 1, the matrix sub-block is determined to be an all-zero sub-block; When the sparsity of the matrix sub-block is greater than a preset sparsity threshold, determining that the matrix sub-block is a sparse sub-block; When the sparsity of the matrix sub-block is less than or equal to the sparsity threshold, the matrix sub-block is determined to be a dense sub-block.

4. The MIMO wireless communication channel matrix compression method according to claim 3, characterized in that: Also includes: The sparsity threshold is determined based on the criterion that the storage overhead of the sparse sub-block is not greater than the storage overhead of the dense sub-block, wherein the storage overhead of the sparse sub-block includes: the storage overhead of the sparse pattern index value, the storage overhead of the index column, and the storage overhead of the non-zero element data, and the storage overhead of the non-zero element data is calculated based on the sparsity of the sparse sub-block; the storage overhead of the dense sub-block includes: the storage overhead of the sparse pattern index value and the storage overhead of all element data.

5. The MIMO wireless communication channel matrix compression method according to claim 2, characterized in that: In the process of selecting and aligning input data and compressed matrix data according to the index by the input buffer and the bit / word row distributor, a column-by-column processing method is adopted, and only one column of data in the matrix sub-block is processed in each cycle.

6. The MIMO wireless communication channel matrix compression method according to claim 2, characterized in that: Also includes: If the sparse pattern index value indicates an all-zero sub-block, the enable signal of the corresponding sense amplifier in the block sparse channel array is turned off to put the sense amplifier in an inactive state.

7. A MIMO wireless communication channel matrix compression device, characterized in that: include: A matrix sub-block partitioning module is used to divide the MIMO wireless communication channel matrix into multiple matrix sub-blocks of uniform size; a sparse pattern index value generating module, configured to determine a type of each matrix sub-block according to the sparsity of each matrix sub-block, wherein the matrix sub-blocks are classified according to type as dense sub-blocks, sparse sub-blocks, and all-zero sub-blocks, and determine a sparse pattern index value of each matrix sub-block according to the type of each matrix sub-block; A sparse pattern index value storage module, configured to store each of the sparse pattern index values ​​into an index addressing array of a memory according to the numbering order of each of the matrix sub-blocks; an index column generation and storage module, configured to, for each of the sparse sub-blocks, mark the positions of non-zero elements in the matrix as 1 and the positions of zero elements as 0, generate an index column for each of the sparse sub-blocks, and store each of the index columns into the index addressing array in the order in which the sparse sub-blocks are numbered; The compressed matrix data storage module is used to process all the matrix sub-blocks in sequence based on the numbering order of each matrix sub-block when storing matrix data, wherein, for dense sub-blocks, all element data are stored in the block sparse channel array of the memory, for sparse sub-blocks, only all non-zero element data are stored in the block sparse channel array, and no data is stored for all-zero sub-blocks.

8. The MIMO wireless communication channel matrix compression device according to claim 7, characterized in that: Also includes: An adaptive mapping matching module, configured to sequentially read each sparse pattern index value in the index addressing array when performing calculations; If the sparse pattern index value indicates a sparse sub-block, an index column corresponding to the sparse sub-block is read from the index addressing array, and the index column is broadcast to the input buffer and the bit / word row distributor. The input buffer selects input data at a corresponding position according to the index column, and the bit / word row distributor selects compressed matrix data at a corresponding position in the block sparse channel array according to the index column, so as to achieve alignment calculation between the input data and the compressed matrix data. If the sparse mode index value indicates a dense sub-block, index control information identifying all data positions in the matrix sub-block as valid positions is broadcasted to the input buffer and the bit / word row distributor, the input buffer selects input data at corresponding positions according to the index control information, and the bit / word row distributor selects compressed matrix data at corresponding positions according to the index control information, so as to achieve alignment calculation between the input data and the compressed matrix data; If the sparse pattern index value indicates an all-zero sub-block, the next sparse pattern index value is directly read.

9. The MIMO wireless communication channel matrix compression device according to claim 7, characterized in that: The sparse pattern index value generation module includes: a comparison and confirmation submodule, configured to determine that the matrix subblock is an all-zero subblock when the sparsity of the matrix subblock is equal to 1, determine that the matrix subblock is a sparse subblock when the sparsity of the matrix subblock is greater than a preset sparsity threshold, and determine that the matrix subblock is a dense subblock when the sparsity of the matrix subblock is less than or equal to the sparsity threshold; The MIMO wireless communication channel matrix compression device further includes: The sparsity threshold determination module is used to determine the sparsity threshold based on the criterion that the storage overhead of the sparse sub-block is not greater than the storage overhead of the dense sub-block, wherein the storage overhead of the sparse sub-block includes: the storage overhead of the sparse pattern index value, the storage overhead of the index column, and the storage overhead of the non-zero element data, and the storage overhead of the non-zero element data is calculated based on the sparsity of the sparse sub-block; the storage overhead of the dense sub-block includes: the storage overhead of the sparse pattern index value and the storage overhead of all element data.

10. The MIMO wireless communication channel matrix compression device according to claim 8, characterized in that: The adaptive mapping matching module is further configured to turn off an enable signal of a corresponding sense amplifier in the block sparse channel array if the sparse pattern index value indicates an all-zero sub-block, so as to place the sense amplifier in an inactive state.

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