Memory slot test method and server

Abstract

The embodiment of the invention provides a memory slot testing method and a server. In the embodiment of the invention, the CPLD is indicated to control the power supply chip to supply power to the target memory slot to be tested at present and prohibit power supply to the non-target memory slot in a manner of running the automatic script for testing and sending the IPMI command to the CPLD through the BMC of the server, so that different memory slot insertion methods are dynamically simulated for testing. By checking whether actual memory configuration obtained when the BIOS executes memory initialization in the restarting process of the server is matched with the current memory slot insertion method or not, testing of the current memory slot insertion method is achieved. According to the method, different memory slot insertion methods are automatically tested, so that the problems of high labor cost, low test efficiency and the like in the existing manual test can be avoided, the test efficiency is improved, and the problem that the memory slots are damaged due to frequent manual insertion and extraction of the memory bank can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing, in particular to a memory slot testing method and a server. BACKGROUND

[0002] In order to guarantee the hardware reliability of a server, a comprehensive hardware test needs to be performed on the server before it is shipped, and the memory slot test is one of the key test items. At present, in actual applications, the memory slot test is usually realized by manually plugging and unplugging the memory modules on the memory slots in different ways. However, this manual method has problems such as high labor cost and low test efficiency. SUMMARY

[0003] Therefore, the present application provides a memory slot testing method and a server to realize the memory slot test automatically and improve the test efficiency.

[0004] The present application provides a memory slot testing method, which is applied to a server, and the method comprises the following steps:

[0005] The memory slot testing method comprises the following steps: (1) running an automatic script to read the memory slot insertion method in a memory slot insertion method configuration file in sequence, and sending an Intelligent Platform Management Interface (IPMI) command to a Complex Programmable Logic Device (CPLD) in the server through a Baseboard Management Controller (BMC) in the server; the IPMI command indicates the memory slot insertion method; and (2) restarting the server after the BMC sends the IPMI command to the CPLD.

[0006] During the restarting process of the server, the CPLD controls a power chip in the server to supply power to a target memory slot in the memory slot insertion method and controls the power chip to prohibit power supply to the remaining non-target memory slots.

[0007] After the power supply to each target memory slot is completed, it is checked whether the actual memory configuration obtained when a Basic Input Output System (BIOS) performs memory initialization during the restarting process of the server matches the memory slot insertion method; the actual memory configuration is the usable memory determined by the BIOS based on memory initialization; and if the actual memory configuration matches the memory slot insertion method, it is determined that the memory slot insertion method meets the requirements.

[0008] The present application also provides a server, which comprises a CPU, a BMC, a CPLD, and a power chip.

[0009] The CPU is configured to read the memory slot insertion method in the memory slot insertion method configuration file in sequence by running the automation script, and send an IPMI command to the CPLD through the BMC; the IPMI command indicates the memory slot insertion method; the server is restarted after the BMC sends the IPMI command to the CPLD;

[0010] The CPU is further configured to control the power supply chip to supply power to the target memory slot in the memory slot insertion method and control the power supply chip to prohibit power supply to the remaining non-target memory slot during the server restart process by running the automation script; after completing the power supply to each target memory slot, check whether the actual memory configuration obtained when the Basic Input Output System (BIOS) performs memory initialization during the server restart process matches the memory slot insertion method; the actual memory configuration is the available memory determined by the BIOS based on memory initialization; if they match, it is determined that the memory slot insertion method meets the requirements.

[0011] From the above technical solutions, in the embodiments of the present application, by running the automation script for testing, the BMC of the server sends an IPMI command to the CPLD to indicate the CPLD to control the power supply chip to supply power to the target memory slot to be tested and to prohibit power supply to the non-target memory slot, so as to dynamically simulate different memory slot insertion methods for testing. Based on this, by checking whether the actual memory configuration obtained when the BIOS performs memory initialization during the server restart process matches the current memory slot insertion method, the test of the current memory slot insertion method is realized. This realizes the automated testing of different memory slot insertion methods, which not only avoids the problems such as high labor cost and low test efficiency of manual testing, improves the test efficiency, but also avoids the problem of damage to the memory slot caused by frequent manual insertion and removal of the memory stick. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and serve to explain the principles of the present application together with the specification.

[0013] Figure 1 A flowchart of a memory slot test method provided by an embodiment of the present application.

[0014] Figure 2 A flowchart of another memory slot test method provided by an embodiment of the present application.

[0015] Figure 3 A flowchart of another memory slot test method provided by an embodiment of the present application.

[0016] Figure 4 A flowchart of another memory slot test method provided by the embodiment of the present application.

[0017] Figure 5 A structural diagram of a server provided by the embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to make the technical solution provided by the embodiment of the present application better understood by those skilled in the art, and make the above-mentioned purposes, features and advantages of the embodiment of the present application more apparent and easy to understand, the technical solution in the embodiment of the present application is further described in detail below with reference to the drawings.

[0019] Referring to Figure 1 , Figure 1 A method flowchart provided by the embodiment of the present application. As an embodiment, the method is applied to a server. In the embodiment, the server at least includes a CPU, a BMC, a CPLD and a power chip; and the server is further configured with a plurality of memory slots.

[0020] As shown in Figure 1 , the flowchart can include the following steps:

[0021] Step 101: reading the memory slot insertion method in the memory slot insertion method configuration file in sequence by running an automation script, and sending an IPMI command to the CPLD in the server through the BMC in the server; the IPMI command indicates the current memory slot insertion method; and the server is restarted after the BMC sends the IPMI command to the CPLD.

[0022] In the embodiment, the memory slot test configuration file can include a plurality of different memory slot insertion methods, and each memory slot insertion method can include at least one memory slot identifier, that is, each memory slot insertion method indicates at least one memory slot. Alternatively, the embodiment does not specifically limit the configuration of the memory slot test configuration file, for example, the configuration of the memory slot test configuration file can be based on the memory slot insertion methods supported by the CPU of the server, specifically, for example, the memory slot test configuration file can include the memory slot insertion methods supported by the CPU of the server. Among the memory slot insertion methods supported by the CPU, the memory slots are the memory slots in the server.

[0023] In the embodiment, the above-mentioned automation script can be an execution script for memory slot test determined in advance based on actual test requirements. As an embodiment, the automation script can be run by the CPU of the server.

[0024] In this embodiment, as an embodiment, after sending an IPMI command indicating the current memory slot insertion method to the CPLD through the BMC of this server, an IPMI command instructing the server to restart can be sent to the BIOS of this server through the BMC, so that the BIOS of this server controls the restart of this server based on the IPMI command.

[0025] Step 102 : During the restart process of the server, the CPLD controls the power chip in the server to supply power to the target memory slots in the current memory slot insertion method, and controls the power chip to prohibit supplying power to the remaining non-target memory slots.

[0026] In this embodiment, as an example, when the CPLD receives an IPMI command from the BMC indicating the current memory slot configuration, it records the current memory slot configuration indicated by the IPMI command in a designated register of the CPLD, and the information in the designated register will not be lost due to a server restart. Based on this, during the restart process of the server, the CPLD can control the power supply chip in the server to supply power to the target memory slots in the current memory slot configuration based on the recorded memory slot configuration, and control the power supply chip to prohibit power supply to the remaining non-target memory slots.

[0027] As for how to use the CPLD to control the power chip in this server to supply power to the target memory slots in the current memory slot insertion method, and to control the power chip to prohibit power supply to the remaining non-target memory slots, the following examples will be used to describe it, which is not detailed here.

[0028] Step 103 , after power is supplied to each target memory slot, check whether the actual memory configuration obtained when the BIOS performs memory initialization during the restart of the server matches the current memory slot insertion method; if so, determine that the current memory slot insertion method meets the requirements.

[0029] In this embodiment, the actual memory configuration is the available memory determined by the server's BIOS based on memory initialization. As an embodiment, obtaining the actual memory configuration can be achieved by, for example, using a specified command in the server's operating system (OS) via the BIOS. Optionally, the specified command can be, for example, the dmidecode -t memory command, which is not specifically limited in this embodiment.

[0030] In this embodiment, after power is supplied to each target memory slot, it can be checked whether the actual memory configuration obtained when the BIOS performs memory initialization during the restart process of this server matches the current memory slot insertion method; if they match, it is determined that the current memory slot insertion method meets the requirements, that is, it means that the current memory slot insertion method is the memory slot insertion method adapted by the BIOS; correspondingly, if they do not match, it is determined that the current memory slot insertion method does not meet the requirements, that is, it means that the current memory slot insertion method is not the memory slot insertion method adapted by the BIOS.

[0031] Since the memory slot configuration adapted by the BIOS needs to be configured based on the memory slot configurations supported by the CPU, if the current memory slot configuration is not adapted by the BIOS, it indicates that there is a problem with the configuration of the memory slot configuration adapted by the BIOS. Based on this, as an embodiment, when it is determined that the current memory slot configuration does not meet the requirements, a corresponding log will be reported, which can be used by relevant technicians to conduct relevant analysis and problem location related to the memory slot configuration adapted by the BIOS based on the reported log.

[0032] As for how to determine whether power is supplied to each target memory slot in this step, and how to check whether the actual memory configuration obtained when the BIOS performs memory initialization during the server restart process matches the current memory slot insertion method, the following examples will be used to describe it, and no further details are given here.

[0033] So far, completed Figure 1 The process shown.

[0034] pass Figure 1 As can be seen from the process shown, in the embodiment of the present application, by running the automated script for testing, the server's BMC sends an IPMI command to the CPLD, instructing the CPLD to control the power chip to supply power to the target memory slot currently to be tested and to prohibit power supply to the non-target memory slots, so as to dynamically simulate different memory slot insertion methods for testing. Based on this, by checking whether the actual memory configuration obtained when the BIOS performs memory initialization during the server restart process matches the current memory slot insertion method, the current memory slot insertion method can be tested. This realizes automated testing of different memory slot insertion methods, which not only avoids the problems of existing manual testing such as high labor costs and low test efficiency, improves test efficiency, but also avoids the problem of memory slots being damaged due to frequent manual insertion and removal of memory sticks.

[0035] The following describes how to control the power chip in the server through the CPLD to supply power to the target memory slots in the current memory slot insertion method, and to control the power chip to prohibit power supply to the remaining non-target memory slots:

[0036] In this embodiment, as an example, refer to Figure 2 As shown in the above, the power chip in the server is controlled by the CPLD to supply power to the target memory slot in the current memory slot insertion method, and the power chip is controlled to prohibit power supply to the remaining non-target memory slot. In specific implementation, it may include the following steps:

[0037] In step 201, a first enable signal is sent to the power chip through the GPIO pin connected to the power chip on the CPLD, so that the power chip supplies power to the target memory slot in the current memory slot insertion method based on the first enable signal.

[0038] GPIO is the abbreviation of General Purpose Input Output.

[0039] The first enable signal may refer to an enable signal for indicating power supply to the target memory slot in the memory slot insertion method.

[0040] In step 202, a second enable signal is sent to the power chip through the GPIO pin connected to the power chip on the CPLD, so that the power chip prohibits power supply to the remaining non-target memory slot based on the second enable signal.

[0041] The second enable signal may refer to an enable signal for indicating power supply to the remaining non-target memory slot.

[0042] It should be noted that in this embodiment, steps 201 and 202 have no execution sequence, and the labels of steps 201 and 202 are only for convenience of description.

[0043] The determination of completing power supply to each target memory slot is described as follows:

[0044] In this embodiment, as an example, the determination of completing power supply to each target memory slot may be that when the CPLD receives the power supply success signal corresponding to each target memory slot feedback by the power chip, it is determined that the power supply to each target memory slot is completed.

[0045] In this embodiment, for each target memory slot, the power chip periodically reads the power supply voltage of the target memory slot within a specified time period after supplying power to the target memory slot. Based on this, if the power supply voltage of the target memory slot is monitored to be a specified voltage within the specified time period, the power supply success signal corresponding to the target memory slot will be generated and sent to the CPLD.

[0046] The following describes whether the actual memory configuration obtained when the BIOS performs memory initialization in the server restart process matches the current memory slot insertion method:

[0047] In the embodiment, the above checking is whether the actual memory configuration obtained when the BIOS performs the memory initialization in the server restart process matches the current memory slot insertion method. In a specific implementation, for example, the checking can be whether the memory slot where the memory is located in the actual memory configuration is consistent with the target memory slot in the memory slot insertion method. Based on this, if consistent, it is determined that the match, and if inconsistent, it is determined that the mismatch.

[0048] Here, the memory slot where the memory is located can be understood as the memory slot where the memory module such as the memory stick is inserted.

[0049] The memory initialization process of the BIOS is described below:

[0050] In the embodiment, as an example, in the memory initialization process of the BIOS, the BIOS will first identify the memory module (such as the memory stick) in the server to determine the available memory (that is, the memory provided by the identified memory module), and then the BIOS will allocate memory for the operating system and some specified hardware devices based on the determined available memory, and perform a flashing operation based on the memory to ensure that the above-mentioned identified memory module can work normally.

[0051] The memory slot test method shown in Figure 1 is further described below:

[0052] In the embodiment, as an example, referring to Figure 3 shown, after the CPLD controls the power supply chip in the server to supply power to the target memory slot in the memory slot insertion method and controls the power supply chip to prohibit power supply to the remaining non-target memory slots, the method further includes:

[0053] Step 301, when the CPLD detects a power supply anomaly, interrupt the test of the current memory slot insertion method, and when there is a memory slot insertion method in the memory slot insertion method configuration file that has not been read, restore the power supply state of all memory slots in the server to the power supply state of all memory slots when the BMC sends the IPMI command to the CPLD.

[0054] The IPMI command here refers to the IPMI command sent by the BMC to the CPLD to indicate the current memory slot insertion method.

[0055] In the embodiment, as an example, the above-mentioned power supply anomaly detected by the CPLD, in a specific implementation, for example, can be: when the CPLD receives at least one power supply failure signal corresponding to the target memory slot feedback by the power supply chip, it is determined that the power supply anomaly is monitored.

[0056] As described above, for each target memory slot, after the power chip supplies power to the target memory slot, it will regularly read the power supply voltage of the target memory slot within a specified time period. Based on this, if the power supply voltage of the target memory slot is not monitored to be the specified voltage within the specified time period, a power supply failure signal corresponding to the target memory slot will be generated and sent to the CPLD.

[0057] This embodiment monitors the power supply voltage of the target memory slot to realize power supply anomaly monitoring. When a power supply anomaly is detected, the power supply status of all memory slots in the server is restored to the power supply status of all memory slots when the BMC sends the IPMI command to the CPLD. The test environment is restored to the test environment when the BMC sends the IPMI command to the CPLD, so as to ensure that the test environment of each memory slot insertion method at the beginning of the test is consistent, thereby improving the reliability of the test.

[0058] Furthermore, in this embodiment, as an embodiment, if the actual memory configuration obtained when the BIOS performs memory initialization during the restart of this server matches the current memory slot insertion method, or if the actual memory configuration obtained when the BIOS performs memory initialization during the restart of this server does not match the current memory slot insertion method, then when there is a memory slot insertion method that has not been read in the memory slot insertion method configuration file, the power supply status of all memory slots in this server is restored to the power supply status of all memory slots in this server when the BMC sends the IPMI command to the CPLD, so as to ensure that the initial test environment of the next memory slot insertion method is consistent with the initial test environment of the current memory slot insertion method.

[0059] In this embodiment, as an example, restoring the power supply status of all memory slots in the server to the power supply status of all memory slots in the server when the BMC sends the IPMI command to the CPLD can be specifically implemented, for example, by sending an IPMI command to the CPLD to instruct the BMC to disable power supply to all memory slots in the server, so that upon receiving the IPMI command, the CPLD controls the power chip to disable power supply to all memory slots in the server. As for the specific method of controlling the power chip to disable power supply to all memory slots in the server, please refer to the above-mentioned relevant description and will not be repeated here.

[0060] In order to facilitate understanding of the specific implementation process of the above memory slot testing method, a specific embodiment is described below as an example.

[0061] As an example, see Figure 4 As shown, the specific implementation process of the memory slot testing method provided in this embodiment may include the following steps:

[0062] Step 401, run an automation script by the CPU of the server, read the memory slot insertion method in the memory slot insertion method configuration file in sequence, take each read memory slot insertion method as the current memory slot insertion method, and send an IPMI command indicating the current memory slot insertion method to the CPLD through the BMC of the server, the current memory slot insertion method indicating at least one target memory slot.

[0063] In the embodiment, the CPLD records each target memory slot indicated by the IPMI command in a specified register of the CPLD when receiving the IPMI command, so that each target memory slot can be powered based on each target memory slot in the specified register subsequently.

[0064] Step 402, restart the server through the BMC of the server, and control the power chip in the server to stop power supply for the non-target memory slot during the restart of the server, and control the power chip to supply power to the target memory slot in the current memory slot insertion method through the CPLD when receiving the power-off success signal corresponding to each non-target memory slot from the power chip.

[0065] The power-off success signal corresponding to any non-target memory slot is generated and sent to the CPLD by the power chip when the power chip monitors that the power voltage of the non-target memory slot is always less than or equal to the set voltage within a specified time. Optionally, the set voltage may be 0.2V, etc., which is not specifically limited in the embodiment.

[0066] Step 403, when receiving the power-on success signal corresponding to each target memory slot from the power chip through the CPLD, it is determined that the power supply for each target memory slot is completed, and step 404 is executed.

[0067] The power-on success signal may be a high-level power_ok signal.

[0068] Step 404, check whether the actual memory configuration obtained when the BIOS performs memory initialization during the restart of the server matches the memory slot insertion method; if yes, execute step 405, and if no, execute step 406.

[0069] Step 405, determine that the memory slot insertion method meets the requirements, and when there is an un-read memory slot insertion method in the memory slot insertion method configuration file, restore the power supply state of all memory slots in the server to the power supply state of all memory slots when the BMC sends the IPMI command to the CPLD, and continue to test the next memory slot insertion method.

[0070] Step 406: Determine that the memory slot configuration does not meet the requirements, report the corresponding log, and if there is a memory slot configuration that has not been read in the memory slot configuration file, restore the power supply status of all memory slots in the server to the power supply status of all memory slots when the BMC sends the IPMI command to the CPLD, and continue testing the next memory slot configuration.

[0071] In step 407, when a power failure signal corresponding to at least one target memory slot fed back by the power chip is received through the CPLD, it is determined that a power supply abnormality is detected. At this time, the test of the current memory slot insertion method is interrupted. When there is a memory slot insertion method that has not been read in the memory slot insertion method configuration file, the power supply status of all memory slots in the server is restored to the power supply status of all memory slots when the BMC sends the IPMI command to the CPLD, and the test of the next memory slot insertion method is continued.

[0072] The power failure signal here may be, for example, a low-level power_ok signal.

[0073] In this embodiment, as an embodiment, before continuing to test the next memory slot insertion method, the method further includes: clearing the target memory slot recorded in the designated register of the CPLD to avoid affecting the record of the target memory slot in the IPMIM instruction in subsequent tests.

[0074] This completes the description of the method provided in the embodiment of the present application. The following describes the server provided in the embodiment of the present application:

[0075] As an embodiment, this embodiment also provides a server. For example, see Figure 5 , Figure 5 This is a schematic diagram of the structure of a server provided in an embodiment of the present application. Figure 5 As shown, the server 500 is applied to a server, and the server 500 includes: a CPU 501, a BMC 502, a CPLD 503, and a power chip 504;

[0076] The CPU 501 is configured to sequentially read the memory slot insertion method in the memory slot insertion method configuration file by running an automated script, and send an IPMI command to the CPLD 503 via the BMC 502; the IPMI command indicates the memory slot insertion method; after the BMC 502 sends the IPMI command to the CPLD 503, the server 500 restarts;

[0077] The CPU 501 is further configured to control the power chip 504 to supply power to the target memory slot in the memory slot insertion mode and to disable the power supply to the remaining non-target memory slot in the server 500 restart process by running the automation script through the CPLD 503; and check whether the actual memory configuration obtained by the BIOS in the memory initialization in the server 500 restart process matches the memory slot insertion mode after completing the power supply to each target memory slot; the actual memory configuration is the usable memory determined by the BIOS based on the memory initialization; if the actual memory configuration matches the memory slot insertion mode, it is determined that the memory slot insertion mode meets the requirements.

[0078] As an embodiment, the control of the power chip 504 to supply power to the target memory slot in the memory slot insertion mode by the CPLD 503 comprises:

[0079] The CPLD 503 sends a first enable signal to the power chip 504 through the GPIO pin connected to the power chip 504, so that the power chip 504 supplies power to the target memory slot in the memory slot insertion mode based on the first enable signal.

[0080] The control of the power chip 504 to disable the power supply to the remaining non-target memory slot comprises:

[0081] The CPLD 503 sends a second enable signal to the power chip 504 through the GPIO pin connected to the power chip 504, so that the power chip 504 disables the power supply to the remaining non-target memory slot based on the second enable signal.

[0082] As an embodiment, the completion of the power supply to each target memory slot comprises:

[0083] The CPLD 503 receives the power supply success signal corresponding to each target memory slot fed back by the power chip 504, and determines that the power supply to each target memory slot is completed; wherein the power supply success signal corresponding to any target memory slot is sent by the power chip 504 to the CPLD 503 when the power chip 504 monitors the power supply voltage of the target memory slot to be a specified voltage within a specified time period.

[0084] As an embodiment, the CPU 501 is further configured to interrupt the test of the memory slot insertion mode when an abnormal power supply is monitored by the CPLD 503 by running the automation script, and restore the power supply state of all memory slots in the server 500 to the power supply state of all memory slots in the server 500 when the BMC 502 sends the IPMI command to the CPLD 503 when there is an un-read memory slot insertion mode in the memory slot insertion mode configuration file.

[0085] The monitoring of the power supply anomaly by the CPLD 503 comprises: determining that the power supply anomaly is monitored by the CPLD 503 when at least one target memory slot corresponding power supply failure signal fed back by the power supply chip 504 is received.

[0086] As an embodiment, the checking whether the actual memory configuration obtained when the BIOS performs memory initialization in the server 500 restart process matches the memory slot insertion method comprises:

[0087] Checking whether the memory slot in the actual memory configuration is consistent with the target memory slot in the memory slot insertion method.

[0088] As an embodiment, the CPU 501 is further configured to run an automated script, if the match, or if the mismatch, and if there is an un-read memory slot insertion method in the memory slot insertion method configuration file, restore the power supply state of all memory slots in the server 500 to the power supply state of all memory slots in the server 500 when the BMC 502 sends the IPMI command to the CPLD 503.

[0089] As an embodiment, the actual memory configuration is obtained by the following steps:

[0090] The actual memory configuration is obtained by using a specified command under the OS of the server 500.

[0091] So far, the structure of the server is described. Figure 5

[0092] The implementation process of the functions and roles of each device in the above server is specifically described in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0093] For the server embodiment, since it basically corresponds to the method embodiment, please refer to the part of the method embodiment for the related description. The server embodiment described above is only schematic. Those skilled in the art can understand and implement it without creating any creative labor.

[0094] The above is only a preferred embodiment of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.​

Claims

1. A memory slot testing method, characterized in that: The method is applied to a server and includes: The method comprises running an automated script to sequentially read the memory slot insertion method in the memory slot insertion method configuration file, and sending an intelligent platform management interface (IPMI) command to a complex programmable logic device (CPLD) in the server through a baseboard management controller (BMC) in the server; the IPMI command indicates the memory slot insertion method; and restarting the server after the BMC sends the IPMI command to the CPLD. During the restart process of the server, the CPLD controls a power chip in the server to supply power to a target memory slot in the memory slot insertion method, and controls the power chip to prohibit supplying power to the remaining non-target memory slots; After power is supplied to each target memory slot, check whether the actual memory configuration obtained when the basic input and output system BIOS performs memory initialization during the server restart process matches the memory slot insertion method; the actual memory configuration is the available memory determined by the BIOS based on the memory initialization; if they match, it is determined that the memory slot insertion method meets the requirements.

2. The method according to claim 1, characterized in that Controlling the power chip in the server by the CPLD to supply power to the target memory slot in the memory slot insertion method includes: sending a first enable signal to the power chip via a general purpose input / output (GPIO) pin on the CPLD connected to the power chip, so that the power chip supplies power to a target memory slot in the memory slot insertion method based on the first enable signal; Controlling the power chip to prohibit power supply to the remaining non-target memory slots includes: A second enable signal is sent to the power chip via a GPIO pin on the CPLD connected to the power chip, so that the power chip prohibits power supply to the remaining non-target memory slots based on the second enable signal.

3. The method according to claim 1, characterized in that The powering of each target memory slot includes: When the CPLD receives the power supply success signal corresponding to each target memory slot fed back by the power chip, it is determined that the power supply to each target memory slot is completed; wherein, the power supply success signal corresponding to any target memory slot is sent to the CPLD when the power chip monitors that the power supply voltage of the target memory slot is a specified voltage within a specified time period.

4. The method according to claim 1, wherein The method further comprises: When a power supply anomaly is detected by the CPLD, the test of the memory slot insertion method is interrupted, and when there is a memory slot insertion method that has not been read in the memory slot insertion method configuration file, the power supply state of all memory slots in the server is restored to the power supply state of all memory slots when the BMC sends the IPMI command to the CPLD; Among them, the power supply abnormality detected by the CPLD includes: when the CPLD receives a power supply failure signal corresponding to at least one target memory slot fed back by the power chip, it is determined that the power supply abnormality is detected; the power supply failure signal corresponding to any target memory slot is sent to the CPLD when the power chip does not detect that the power supply voltage of the target memory slot is the specified voltage within a specified time period.

5. The method according to claim 1, wherein The checking whether the actual memory configuration obtained when the basic input and output system BIOS performs memory initialization during the server restart process matches the memory slot insertion method includes: Check whether the memory slot where the memory is located in the actual memory configuration is consistent with the target memory slot in the memory slot insertion method.

6. The method according to claim 1, characterized in that The method further comprises: If they match, or if they do not match, when there is a memory slot insertion method that has not been read in the memory slot insertion method configuration file, the power supply status of all memory slots in the server is restored to the power supply status of all memory slots when the BMC sends the IPMI command to the CPLD.

7. The method according to claim 1, characterized in that The actual memory configuration is obtained by the following steps: The actual memory configuration is obtained using a specified command under the operating system (OS) of the server.

8. A server, characterized in that: The server includes: a central processing unit (CPU), a baseboard management controller (BMC), a complex programmable logic device (CPLD), and a power chip; The CPU is configured to sequentially read the memory slot insertion method in the memory slot insertion method configuration file by running an automated script, and send an Intelligent Platform Management Interface (IPMI) command to the CPLD via the BMC; the IPMI command indicates the memory slot insertion method; and the server restarts after the BMC sends the IPMI command to the CPLD. The CPU is further configured to, by running an automated script, control the power supply chip through the CPLD to supply power to the target memory slots in the memory slot insertion method during the restart process of the server, and to control the power supply chip to prohibit power supply to the remaining non-target memory slots; after completing power supply to each target memory slot, check whether the actual memory configuration obtained when the basic input and output system BIOS performs memory initialization during the restart process of the server matches the memory slot insertion method; the actual memory configuration is the available memory determined by the BIOS based on the memory initialization; if they match, it is determined that the memory slot insertion method meets the requirements.

9. The server according to claim 8, wherein: The controlling the power chip to supply power to the target memory slot in the memory slot insertion method by the CPLD includes: sending a first enable signal to the power chip via a general purpose input / output (GPIO) pin on the CPLD connected to the power chip, so that the power chip supplies power to a target memory slot in the memory slot insertion method based on the first enable signal; Controlling the power chip to prohibit power supply to the remaining non-target memory slots includes: A second enable signal is sent to the power chip via a GPIO pin on the CPLD connected to the power chip, so that the power chip prohibits power supply to the remaining non-target memory slots based on the second enable signal.

10. The server according to claim 8, wherein: The powering of each target memory slot includes: When the CPLD receives a power supply success signal corresponding to each target memory slot fed back by the power chip, it is determined that power supply to each target memory slot is completed; wherein the power supply success signal corresponding to any target memory slot is sent to the CPLD when the power chip detects that the power supply voltage of the target memory slot is a specified voltage within a specified time period; and / or, The CPU is further configured to, by running an automated script, interrupt the test of the memory slot insertion method when a power supply anomaly is detected by the CPLD, and, when an unread memory slot insertion method exists in the memory slot insertion method configuration file, restore the power supply state of all memory slots in the server to the power supply state of all memory slots when the BMC sends the IPMI command to the CPLD; The detecting of the power supply abnormality by the CPLD includes: determining that the power supply abnormality is detected when the CPLD receives a power supply failure signal corresponding to at least one target memory slot fed back by the power chip; the power supply failure signal corresponding to any target memory slot is sent to the CPLD when the power chip fails to detect that the power supply voltage of the target memory slot is a specified voltage within a specified time period; and / or, The checking whether the actual memory configuration obtained when the basic input and output system BIOS performs memory initialization during the server restart process matches the memory slot insertion method includes: Check whether the memory slot where the memory is located in the actual memory configuration is consistent with the target memory slot in the memory slot insertion method; and / or, The CPU is further configured to, by running an automated script, restore the power supply states of all memory slots in the server to the power supply states of all memory slots when the BMC sends the IPMI command to the CPLD if a match occurs, or if a match does not occur, when there is an unread memory slot insertion method in the memory slot insertion method configuration file; and / or, The actual memory configuration is obtained by the following steps: The actual memory configuration is obtained using a specified command under the operating system (OS) of the server.

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