Network-based forced assignment statement processing method, electronic equipment and medium

Abstract

The invention relates to the technical field of digital simulation, in particular to a net-based mandatory assignment statement processing method, electronic equipment and a medium, and the method comprises the following steps: in a compiling stage, firstly obtaining bits, acted by mandatory assignment statements, of a target net, and then obtaining bit information and a driving list of a top module corresponding to each bit; the method comprises the following steps of: in a simulation stage, recording each driver into a preset database file, transferring each driver to a bit of a corresponding top module according to a bit, and in a simulation stage, when a forced assignment statement occurs, applying a forced assignment state to the bit of the corresponding top module based on the preset database file, and updating a corresponding signal value into a corresponding signal value in the forced assignment statement. According to the method, the time and the memory overhead consumed by forcibly assigning the statement in the digital simulation process are reduced.

Description

Technical Field

[0001] The present invention relates to the field of digital simulation technology, and in particular to a method for processing forced assignment statements based on a wire network, electronic equipment, and a medium. Background Art

[0002] The forced assignment statement can force the modification of the signal value during the digital simulation process, and make it impossible for any value driven to affect the forced signal value. When the number of chip design levels is large and the data content of some levels is complex, the wire network may be connected to each module through a port. At this time, in order to maintain the forced signal value under each port of each module during the digital simulation process, it is necessary to find the ports of each module connected to the wire network. However, since there may be a driver for the current wire network in each module, the existing technology needs to assign the corresponding ports of all modules connected to the wire network to a forced modified state and a forced modified signal value information when implementing the forced assignment statement during the digital simulation process. In a complex design, it takes a lot of time and consumes a lot of memory. Therefore, how to reduce the time required for the forced assignment statement in the digital simulation process and reduce memory overhead has become a technical problem that needs to be solved urgently. Summary of the Invention

[0003] The purpose of the present invention is to provide a wire-net-based forced assignment statement processing method, electronic device and medium, which reduces the time and memory overhead required for forced assignment statements in a digital simulation process.

[0004] According to a first aspect of the present invention, a method for processing a forced assignment statement based on a wire net is provided, comprising: Step S1: In the compilation phase, obtain the bits {A1, A2, ..., A n ,...,A N}, A n The nth bit of the target net affected by the forced assignment statement, where n ranges from 1 to N, and N is the total number of bits affected by the forced assignment statement on the target net. The target net is a net on which the forced assignment statement is set and connected to an input port of the target module on which the forced assignment statement is set or an input port of a submodule instantiation of the target module; Step S2: Get each A n The corresponding top module bit information B n and A n Corresponding driver list {C1 n ,C2 n ,...,C i n ,...,C f(n) n} and record into a preset database file, C i n for A n The corresponding i-th drive, i is in the range of 1 to f(n), f(n) is A n The total number of corresponding drives; Step S3, in the chip design, each C i n Transfer to the corresponding B n , generate a compilation file, and then enter the simulation stage; Step S4, in the simulation stage, based on the compilation file, execute a simulation process, when the forced assignment statement occurs, based on the forced assignment statement identifier and each A n Query the preset database file to obtain each A n The corresponding B n ; Step S5, for each B n Apply a forced assignment state, update the corresponding signal value of B n The corresponding signal value of B n In the forced assignment statement.

[0005] According to the second aspect of the present application, an electronic device is provided, comprising: at least one processor; and a memory connected in communication with the at least one processor; wherein the memory stores instructions executed by the at least one processor, the instructions are configured to execute the method of the first aspect of the present application.

[0006] According to the third aspect of the present application, a computer readable storage medium is provided, which stores computer executable instructions, the computer instructions are used to execute the method of the first aspect of the present application.

[0007] Compared with the prior art, the present application has obvious advantages and beneficial effects. By the above technical scheme, the present application provides a forced assignment statement processing method based on a line net, an electronic device and a medium, which can achieve considerable technical progress and practicality, and has wide industrial utilization value. It has at least the following beneficial effects: During the compilation phase, the present invention first obtains the bit of the target network affected by the forced assignment statement, then obtains the bit information and driver list of the top module corresponding to each bit, and records them in a preset database file. Each driver is transferred bit by bit to the bit of the corresponding top module. During the simulation phase, when a forced assignment statement occurs, the bit of the corresponding top module is forced to be assigned a state based on the preset database file, and the corresponding signal value is updated to the corresponding signal value in the forced assignment statement. By adjusting the connection method between the driver and the signal and recording the optimization target of the forced assignment statement, the present invention realizes that a forced assignment statement only needs to be assigned once to be forced to modify the state and assign the forced modified signal value information, thereby achieving huge optimization. The time and memory overhead required for forced assignment statements in the digital simulation process are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 A flow chart of a method for processing forced assignment statements based on a wire net provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0010] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0011] The embodiment of the present invention provides a method for processing a forced assignment statement based on a wire net, such as Figure 1 Shown, including: Step S1: In the compilation phase, obtain the bits {A1, A2, ..., A n ,...,A N}, A n The nth bit of the target net affected by the forced assignment statement, where n ranges from 1 to N, and N is the total number of bits of the target net affected by the forced assignment statement. The target net is a net on which the forced assignment statement is set and which is connected to the input port (input) of the target module on which the forced assignment statement is set or the input port of the instantiation of a sub-module of the target module.

[0012] It should be noted that N≥1, that is, the bit of the target line net in the chip design that is forced to be assigned can be one or more bits. n ,...,A N It can be continuous bits, discontinuous bits, or partially continuous and partially discontinuous bits. As an example, the target net width is 64 bits, and the bits affected by the forced assignment statement are bits 0-31. It is understood that the object optimized by the present invention is the net that satisfies the forced assignment statement and is connected to the input port of the target module where the forced assignment statement is set or the input port of the instantiation of the submodule of the target module. The input port refers to the port where the signal value flows from the outside of the module to the module.

[0013] Step S2: Get each A n The corresponding top module bit information B n and A n Corresponding driver list {C1 n ,C2 n ,...,C i n ,...,C f(n) n}, and record it in the preset database file, C i n A n The corresponding i-th driver, i ranges from 1 to f(n), f(n) is A n The total number of corresponding drivers.

[0014] It should be noted that A n The corresponding driver is able to change A n The corresponding value of the driving signal. f(n)≥0, that is, A n The corresponding top module driver may not exist, may be one, or may be multiple.

[0015] Step S3, bit by bit each C in the chip design i n Transfer to the corresponding B n , generate compilation files, and then enter the simulation stage.

[0016] It should be noted that, through the processing of step S3, all drivers that may affect the signal value in the entire chip design are transferred to the top signal for the net affected by the forced assignment statement. It can be understood that steps S1-S3 are all executed during the compilation phase, while steps S4-S5 are executed during the simulation phase.

[0017] Step S4, in the simulation stage, a simulation process is performed based on the compiled file, when the forced assignment statement occurs, based on the forced assignment statement identification and each A n The preset database file is queried to obtain each A n Corresponding B n .

[0018] It should be noted that in the simulation stage, the simulation is normally operated, when the forced assignment statement occurs, the target net is acted on through the triggering event, and the steps S4-S5 are specifically implemented.

[0019] Step S5, for each B n The forced assignment state is applied to B n The corresponding signal value is updated to the corresponding signal value of B n In the forced assignment statement.

[0020] It should be noted that since all the drives are transferred to the corresponding top signals, when the signal values of these drives change and are conducted to the corresponding top signals, they are blocked by the forced assignment state, and all the input ports are in the direction of the sub-modules, so that the signal values conducted by all the sub-module related nets in the entire chip design are the signal values given by the forced assignment statement, thereby the effect of the forced assignment statement is realized.

[0021] The embodiment of the application adjusts the connection mode of the drive and the signal and the net object of the forced assignment statement, greatly improves the performance of the forced assignment statement under the premise of correct simulation function, and the improvement is more significant in complex design. Moreover, since the memory overhead is required for applying the forced state and retaining the signal value of the forced assignment, the memory usage can be greatly reduced in complex design.

[0022] As an embodiment, the step S1 comprises: Step S11, in the compilation stage, a module provided with a forced assignment statement in the chip design is determined as a target module.

[0023] The forced assignment statement is usually a statement containing "force".

[0024] Step S12, if the forced assignment statement acts on a net, and the net is connected to the input port of the target module or the input port of the sub-module instantiation of the target module, the net acted on by the forced assignment statement is determined as a target net.

[0025] It should be noted that the object optimized by the embodiment of the application must satisfy that the net acted on by the forced assignment statement is connected to the input port of the target module or the input port of the sub-module instantiation of the target module.

[0026] Step S12: Obtain the bits {A1, A2, ..., A n ,...,A N}.

[0027] It should be noted that the effective bits are clearly recorded in the forced assignment statement, so the bits of the target net affected by the forced assignment statement can be directly obtained based on the forced assignment statement corresponding to the target net.

[0028] As an embodiment, in step S2, each A is obtained n The corresponding top module bit information B n ,include: Step S21: Based on A n Traverse outwards the connected target module port or the input port of the target module's submodule instantiation to obtain each A n The corresponding top module bit information B n .

[0029] It should be noted that each A n Bit information B corresponding to only one top module n .

[0030] As an embodiment, in step S2, each A is obtained n Corresponding driver list {C1 n ,C2 n ,...,C i n ,...,C f(n) n},include: Step S22: Obtain each A in the chip design n All module ports and signals are connected.

[0031] It should be noted that by analyzing the code file corresponding to the chip design, each A n All module ports and signals are connected.

[0032] Step S33: traverse the chip design and obtain each A n List of drivers corresponding to all connected module ports and signals {C1 n ,C2 n ,...,C i n ,...,C f(n) n}.

[0033] It should be noted that by traversing the code file corresponding to the chip design, each A nThe drive list corresponding to all the connected module ports and signals, each A n The drive list corresponding to all the connected module ports and signals can have one or more drives, or can be empty.

[0034] As an embodiment, the step S3 comprises: Step S31, transferring each C i n bit by bit to the corresponding B n .

[0035] It should be noted that step S31 processes the drive transfer operation bit by bit, but in some scenarios, for multiple consecutive B n which belong to the same top module and have consecutive corresponding bits and the same corresponding drive list can be combined for overall operation, thereby reducing the number of transfers and further improving the processing efficiency of the forced assignment statement on the basis of ensuring the correctness of the processing result of the forced assignment statement.

[0036] As an embodiment, the step S3 comprises: Step C31, if there are multiple consecutive B n which belong to the same top module and have consecutive corresponding bits and the same corresponding drive list, then the multiple consecutive B n are merged into one bit interval.

[0037] Step C32, transferring all the drives corresponding to the bits in the bit interval to the corresponding bit interval.

[0038] Step C33, transferring each C n not belonging to the bit interval to the corresponding B i n bit by bit. n .

[0039] It should be noted that through steps C31-C32, for multiple consecutive B n which belong to the same top module and have consecutive corresponding bits and the same corresponding drive list can be combined for overall operation, thereby reducing the number of transfers and further improving the processing efficiency of the forced assignment statement on the basis of ensuring the correctness of the processing result of the forced assignment statement.

[0040] It should be noted that the forced assignment statement can act on the entire simulation stage, or can only act on part of the time in the simulation stage. If it is necessary to implement only acting on part of the time in the simulation stage, it is necessary to set the time period corresponding to the forced assignment statement in the chip design. When in such a scenario, as an embodiment, between the step S3 and the step S4 comprises: Step S10, if the chip design is provided with the action time period corresponding to the forced assignment statement, the steps S4-S5 are executed within the action time period, and the simulation process is executed according to the original chip design in the invalid state of the forced assignment statement outside the action time period.

[0041] It should be noted that, if the chip design is provided with the action time period corresponding to the forced assignment statement, the corresponding forced assignment statement is implemented based on the transferred drive and the preset database file within the action time period. Outside the action time period, the simulation process needs to be executed according to the original chip design in the invalid state of the forced assignment statement. The action time period corresponding to the forced assignment statement can be flexibly set according to specific application requirements.

[0042] In the embodiment of the application, the bits acted on by the forced assignment statement of the target line net are acquired first in the compilation phase, the bit information and the drive list of the corresponding top module of each bit are acquired, and recorded into the preset database file. Each drive is transferred to the corresponding bit of the top module bit by bit. In the simulation phase, when the forced assignment statement occurs, the corresponding top module bit is forced to be assigned based on the preset database file, and the corresponding signal value is updated to the corresponding signal value in the forced assignment statement. The application adjusts the connection mode of the drive and the signal, and records the optimization action target of the forced assignment statement, so that the forced assignment statement only needs to be assigned once to be forced to modify the state and the signal value information of the forced modification, and great optimization is achieved. The time and memory overheads consumed by the forced assignment statement in the digital simulation process are reduced.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing specific embodiments only and is not intended to be limiting. As used in this description, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] It should be noted that some of the example embodiments are described as processes that are depicted as flow diagrams. Although the flow diagrams describe the processes as a sequential process, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be re-arranged. A process can be terminated when its operations are completed, but could also occur over longer periods of time. Processes might also have additional steps not included in the figure. A process can correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

[0045] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0046] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0047] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for processing forced assignment statements based on a wire net, characterized in that: include: Step S1: In the compilation phase, obtain the bits {A1, A2, ..., A n ,...,A N }, A n The nth bit of the target net affected by the forced assignment statement, where n ranges from 1 to N, and N is the total number of bits affected by the forced assignment statement on the target net. The target net is a net on which the forced assignment statement is set and connected to an input port of the target module on which the forced assignment statement is set or an input port of a submodule instantiation of the target module; Step S2: Get each A n The corresponding top module bit information B n and A n Corresponding driver list {C1 n ,C2 n ,...,C i n ,...,C f(n) n }, and record it in the preset database file, C i n A n The corresponding i-th driver, i ranges from 1 to f(n), f(n) is A n The total number of corresponding drivers; Step S3, bit by bit each C in the chip design i n Transfer to the corresponding B n , generate compilation files, and then enter the simulation stage; Step S4: In the simulation phase, the simulation process is executed based on the compiled file. When the forced assignment statement occurs, the forced assignment statement identifier and each A n Query the preset database file to obtain each A n Corresponding B n ; Step S5: for each B n Apply forced assignment state, B n The corresponding signal value is updated to B in the forced assignment statement n The corresponding signal value.

2. The method according to claim 1, characterized in that The step S1 comprises: Step S11: During the compilation phase, a module in the chip design that has a mandatory assignment statement is determined as a target module; Step S12: If the forced assignment statement acts on a net, and the net on which the forced assignment statement acts is connected to an input port of a target module or an input port of an instantiation of a submodule of the target module, the net on which the forced assignment statement acts is determined as a target net. Step S12: Obtain the bits {A1, A2, ..., A n ,...,A N }.

3. The method according to claim 1, characterized in that In step S2, each A is obtained n The corresponding top module bit information B n ,include: Step S21: Based on A n Traverse outwards the connected target module port or the input port of the target module's submodule instantiation to obtain each A n The corresponding top module bit information B n .

4. The method according to claim 1 or 2, characterized in that In step S2, each A is obtained n Corresponding driver list {C1 n ,C2 n ,...,C i n ,...,C f(n) n },include: Step S22: Obtain each A in the chip design n All module ports and signals connected; Step S33: traverse the chip design and obtain each A n List of drivers corresponding to all connected module ports and signals {C1 n ,C2 n ,...,C i n ,...,C f(n) n }.

5. The method according to claim 1, wherein The step S3 comprises: Step S31: Each C in the chip design i n Transfer to the corresponding B bit by bit n .

6. The method according to claim 1, characterized in that The step S3 comprises: Step C31: If there are multiple consecutive B n Belong to the same top module and the corresponding bits are continuous and the corresponding drive lists are the same, then the multiple consecutive B n Merge into one bit interval; Step C32: transfer the driving components corresponding to all bits in the bit interval to the corresponding bit interval; Step C33: B that does not belong to the bit interval n Each corresponding C i n Transfer to the corresponding B bit by bit n .

7. The method according to claim 1, characterized in that The steps between step S3 and step S4 include: Step S10: If the chip design is provided with an effective time period corresponding to a forced assignment statement, then steps S4 to S5 are executed within the effective time period; outside the effective time period, the simulation process is executed according to the original chip design in an invalid state of the forced assignment statement.

8. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 7.

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