Chip circuit detailed layout optimization method based on dynamic programming

Abstract

The invention discloses a chip circuit detailed layout optimization method based on dynamic programming, and the method comprises the steps: carrying out the static time sequence analysis of an initial transistor position, recognizing a negative slack region on a critical path, and carrying out the heuristic optimization with the region as a target in a detailed layout process of time sequence driving of chip circuit wiring; defining a self-adaptive search window: dynamically adjusting the movable range of the unit according to the influence of the unit on a path time sequence, so that optimization is focused on a key region, and meaningless disturbance to a non-key region is avoided; and fine-grained unit movement based on dynamic programming: enumerating all legal unit arrangements in a local window, and accurately solving an optimal layout scheme in combination with time sequence cost and legality constraints. According to the method, sufficient generalization ability under different target densities and layout resources can be ensured, and interaction among different units generated in a global layout stage in a local range is considered.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit layout, and particularly relates to a chip circuit detailed layout optimization method based on dynamic programming. BACKGROUND

[0002] In digital chip design, timing convergence is a crucial link, which directly determines whether the chip can realize the expected function after tape-out.

[0003] In order to improve the success rate of timing convergence, a timing-driven design method is introduced into the layout stage, and the core idea is to take the timing information as the guiding factor of layout optimization, thereby providing more optimization space for subsequent processes. However, the existing timing-driven layout method is mostly limited to independent adjustment of a single type of unit, and this way has obvious limitations. First, when the design scale is large, the solution space of the layout will expand sharply, and the complex constraint conditions make the fine optimization of the unit position only rely on the exhaustive search with extremely high calculation cost, which undoubtedly slows down the design progress and increases the development cost. Secondly, the traditional optimization method (such as Lagrange relaxation method) tends to pursue a local optimal solution at each step, and this "short-sighted" strategy is often difficult to approach a global optimal solution in a complex circuit design, resulting in an unsatisfactory final result. In addition, the existing method usually ignores the orientation information of the initial layout when optimizing the timing, and this information loss may lead the optimization process to fall into inefficient cyclic iteration, which not only wastes computing resources but also prolongs the design cycle.

[0004] Although the size of the search window is a key parameter that controls both the running time and the quality of the solution, its design usually requires a lot of trial and error and is deeply affected by subjective factors. Therefore, it is difficult to ensure sufficient generalization ability under different target densities and layout resources.

[0005] The existing timing-driven detailed layout method only considers the relationship between the current target unit and the units connected to it in the abstract timing graph, without considering the interaction between different units in the local range generated by the global layout stage. SUMMARY

[0006] To solve the above problems, the application provides a chip circuit detailed layout optimization method based on dynamic programming, which can ensure sufficient generalization ability under different target densities and layout resources, and consider the interaction between different units in the local range generated by the global layout stage.

[0007] To achieve the above purpose, the technical scheme adopted by the application is: a chip circuit detailed layout optimization method based on dynamic programming, in the timing-driven detailed layout process of chip circuit wiring, comprising the steps of:

[0008] The initial transistor position is statically timed, a negative slack area on the critical path is identified, and heuristic optimization is carried out on the area as the target;

[0009] Adaptive search window definition: dynamically adjust the movable range of the cell according to its influence on the path timing, focus optimization on the critical area, and avoid unnecessary disturbance to the non-critical area;

[0010] Fine-grained cell movement based on dynamic programming: enumerate all legal cell arrangements in the local window, combine timing cost and legality constraints, and accurately solve the optimal layout scheme.

[0011] Further, the input is the initial cell coordinates after global layout and its network connection information, and the negative slack path and critical cell under the current layout are identified through static timing analysis.

[0012] Further, in the adaptive search window definition process, when optimizing a certain area or certain cells in the circuit locally, a spatial range is limited; within this range, the algorithm allows a selected group of cells to move, exchange or rearrange between legal positions to optimize timing, wire length and congestion indicators.

[0013] Further, the judgment condition in the adaptive search window definition process is:

[0014]

[0015] For the cells moved by the previous stage, n cells are selected in turn according to the importance of the pins to form a rectangle completely surrounding these cells.

[0016] Further, in the adaptive search window definition process,

[0017] Use tail insertion to read the coordinate data generated by the previous black box process into the initial double-linked list in order; starting from the head of the initial double-linked list, when adding a cell to the current rectangle, it is necessary to calculate whether the distance from the cell to the center of the rectangle exceeds the Manhattan distance limit, where the distance constraint formula is as follows:

[0018]

[0019] lim x And lim y Are the displacement limits of the current transistor in the x and y coordinate directions of the entire layout. Max.Disp is a hyperparameter to constrain detailed layout to avoid excessive disturbance to global layout;

[0020] If the limit is exceeded, the cells are temporarily stored in a secondary list; once n cells are queued and a rectangle is constructed, the cells in the secondary list are reinserted in order at the head of the original doubly linked list; this process is repeated until no more rectangles can be constructed in the original doubly linked list.

[0021] Further, a dynamic programming cell movement method based on trigger position reconstruction is established, comprising:

[0022] By moving the trigger within a reasonable range, the dynamic adjustment of the propagation delay between adjacent paths is realized, thereby repairing the setup and hold violations and optimizing the overall slack distribution without introducing illegal layout.

[0023] Further, the relocation problem of the trigger in the local area is modeled as a minimum cost arrangement problem with blocking constraints, and a dynamic programming strategy is introduced for solving.

[0024] Further, the dynamic programming strategy comprises:

[0025] Adjacent paths with violations are extracted through static timing analysis, and the last stage logic cell c1 of path A and the first stage logic cell c2 of path B are taken as reference points. The slack value is calculated to obtain two feasible placement regions centered on c1 and c2; wherein the Manhattan distance d is determined by the initial distance between the current position of the trigger and the reference point minus the timing cost difference calculated based on the Elmore delay model formula; if there is an overlap between the two rectangular regions, the intersection is the target region where the trigger can be legally moved; optimization is performed in this region, while reducing the propagation delay of path A and increasing the delay of path B, to achieve balanced adjustment between setup and hold violations.

[0026] Further, to find the optimal trigger placement position in the feasible placement region, the feasible placement region is discretized into an r×c two-dimensional grid, and all blocking regions are marked as unusable regions; then a three-dimensional dynamic programming table dp[n+1][r+1][c+1] is constructed, where dp[i][j][k] represents the minimum cost of placing the ith trigger at position (j, k); the cost function considers factors including path slack, wiring cost, and congestion factors; during state transition, all illegal positions are skipped, and the optimal predecessor position is recorded; finally, the complete trigger placement path is restored through backtracking.

[0027] Further, in each local trigger adjustment, the clock network and path delay of the entire circuit are not immediately updated, but only assume that the current combinational logic structure is fixed, and the delay change is locally effective; subsequently, the LCB redistribution strategy is used for global timing correction.

[0028] The beneficial effects of the technical solution are as follows:

[0029] The application designs a self-adaptive window size determination mechanism, solves the problem of difficult determination of window size in the existing search window algorithm, and realizes the trade-off between running speed and quality. The size of the search window is determined efficiently and adaptively, which solves the problem of window design depending on a large number of trial and error and subjective factors. Under different target densities and layout resources, sufficient generalization ability is achieved.

[0030] By solving the problem of determining the size of the search window, the problem of determining the size of the search space is solved. For a cell motion with a defined search space, an intuitive method is to decompose it into subproblems and solve them sequentially. Obviously, the solutions of these subproblems are interdependent and can be used as part of solving larger problems. In order to utilize the interdependence between cells, a cell movement based on dynamic programming is used, which regards all rows and sites within the layout area occupied by each rectangle as an input grid. The cells within the rectangle moved in the current black box process are considered as movable cells. The macros and cells that are not moved in the grid are regarded as blocks, indicating areas that cannot be placed. The final output is a set of position solutions after local dynamic programming enhancement.

[0031] The application determines the optimal placement position of the cell efficiently through dynamic programming-based layout optimization. By constructing a three-dimensional DP state space, the layout cost, timing constraints and grid feasibility are considered comprehensively, avoiding the dependence of traditional methods on local search or brute force search. Through the global optimization characteristics of dynamic programming, we can ensure the convergence of the optimal solution under complex layout environment, and efficiently determine the optimal placement path through the backtracking mechanism, thereby improving the layout quality and reducing the calculation cost. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A dynamic programming-based chip detailed layout optimization method flowchart of the application;

[0033] Figure 2 A circuit arrangement diagram in an extreme case in an embodiment of the application;

[0034] Figure 3 A traditional search window definition diagram in an embodiment of the application, (a) is the moving range of dynamic programming when a search window is constructed with two consecutive transistors, and (b) is the moving range of dynamic programming when a search window is constructed with 10 consecutive transistors;

[0035] Figure 41 and 2 are diagrams showing the sizes of the optional areas in the embodiment of the present invention, (c) is the search window constructed with two consecutive transistors, and (d) is the dynamically planned moving range when the search window is constructed with 10 consecutive transistors.

[0036] Figure 5 This is an example diagram of trigger movement in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described below with reference to the accompanying drawings.

[0038] In this embodiment, see Figure 1 As shown, the present invention proposes a chip circuit detailed layout optimization method based on dynamic programming, which includes the following steps in the timing-driven detailed layout process of chip circuit wiring:

[0039] Perform static timing analysis of the initial transistor positions to identify the negative slack region on the critical path and perform heuristic optimization targeting this region.

[0040] However, traditional black-box optimization algorithms such as simulated annealing (SA) and particle swarm optimization (PSO) are prone to falling into local optima or generating a large number of invalid perturbations due to their strong randomness and slow convergence, seriously affecting optimization quality and efficiency. To overcome this shortcoming, we introduce two key enhancement strategies: adaptive search window determination and unit movement based on dynamic programming.

[0041] Adaptive search window definition: Dynamically adjust the movable range of a unit based on its impact on path timing, so that the optimization focuses on key areas and avoids unnecessary disturbances in non-critical areas.

[0042] Fine-grained cell movement based on dynamic programming: Enumerate all legal cell arrangements in a local window, combine timing costs and legality constraints, and accurately solve the optimal layout solution, significantly improving the quality and stability of the solution.

[0043] Through these two enhancements, the process not only effectively avoids the inherent disadvantages of the black-box algorithm, but also significantly improves the convergence speed and final timing performance of layout optimization.

[0044] The optimization scheme in the above embodiment uses the initial cell coordinates and network connectivity information after global layout as input. Static timing analysis is then used to identify negative slack paths and key cells in the current layout. These key cells form the core area of ​​optimization and serve as candidate perturbations in the heuristic optimization phase.

[0045] As an optimization of the above embodiment, in the process of defining the adaptive search window, a spatial range is defined when optimizing a certain region or certain cells in the circuit; within this range, the algorithm allows a selected group of cells to move, exchange or rearrange between legal positions to optimize timing, wire length and congestion indicators.

[0046] Traditional search window algorithms perform brute-force search for optimal positions within a local range, but due to the large size and complex structure of the circuit, it is difficult for a fixed-size window to adapt to different scenarios, especially in the significant trade-off between area and computational complexity. In addition, as a key hyperparameter, the window size often requires a large number of trial parameters and is extremely dependent on human experience.

[0047] Based on an important observation in static timing analysis: in the static timing analysis of super-large scale integrated circuits, since timing propagates from the main input level to the main output level. Therefore: the slack of the main input is always greater than or equal to the slack of the main output. In addition, for the timing critical path, the most critical cells tend to physically cluster (non-strictly). As shown in Figure 2 , when the cells on the critical path (from PI to PO) are all in the same row, the extreme case occurs. Obviously, cells with similar time criticality are usually closer to each other. For this reason, we introduce the concept of importance:

[0048] The decision condition in the process of defining the adaptive search window is:

[0049]

[0050] For the cells moved by the previous stage, n cells are selected in turn according to the pin importance to construct a rectangle that completely encloses these cells, as shown in Figure 3 :

[0051] Figure 3 : In a design of a million-gate circuit, the initial layout obtained by the first iteration of the heuristic algorithm, where the red nodes represent each transistor cell. The rectangle obtained by substituting n cells into the clustering algorithm (the size of the solution space in subsequent movement) represents the green rectangle, which represents the area that is less than or equal to 2×li m x ×2×lim y (variable meaning as shown in equation 4), and the purple rectangle represents the area greater than this equation.

[0052] It is worth noting that there is a positive correlation between the size of n and the area of the constructed rectangle (not strictly). The above so-called non-strictly refers to the fact that constructing a rectangle with two cells in each cluster (n = 2) still has the case of excessive rectangle area (similar time criticality, but large distance), asFigure 3 (a) the middle purple rectangle. This is unacceptable for the search window algorithm. The above problem is solved by the following method.

[0053] The coordinate data generated by the previous black box process is read into the initial double-linked list in order using tail insertion; starting from the head of the initial double-linked list, each time a cell is added to the current rectangle, it is necessary to calculate whether the distance from the cell to the center of the rectangle exceeds the Manhattan distance limit, where the distance constraint formula is as follows:

[0054]

[0055] lim x and lim y are the displacement limits of the current transistor in the x and y directions of the entire layout, respectively. Max.Disp is a hyperparameter that constrains the detailed layout to avoid excessive disturbance to the global layout;

[0056] If the limit is exceeded, the cell is temporarily stored in the auxiliary list; once n cells are queued and a rectangle is constructed, the cells in the secondary list are reinserted into the head of the initial double-linked list in order (cells in the temporary list that are inserted closer to the original list head) ; this process is repeated until no more rectangles can be constructed in the original double-linked list (no pair of nodes within the Manhattan distance limit). The intuitive result is shown in Figure 4 compared with Figure 3 It can be seen that even when the moving range is constructed with 10 transistors in a group, the embodiment of the present application can still maintain good balance of the moving range.

[0057] Through the above adaptive search window construction strategy, we effectively overcome the three major problems faced by traditional fixed window methods in large-scale circuit layout: first, the window size does not match the circuit structure, resulting in some key areas not being covered or causing redundant search; second, the parameters are highly dependent on manual debugging, making it difficult to adapt to different design scenarios; third, when the physical distribution of key units is discrete, the fixed window may cause the solution space to expand, seriously affecting the optimization efficiency. We dynamically construct a set of local rectangular regions with compactness, strong timing correlation, and controllable area based on timing importance and physical adjacency. These regions not only effectively focus on key path units, significantly reducing invalid disturbance, but also provide a clear structure and clear boundary input for subsequent dynamic programming-based unit movement, thereby significantly improving optimization quality, running efficiency, and overall scalability of the algorithm. The final output is a series of range coordinates of search sub-regions that meet the adaptive constraints, which can be directly used for high-quality layout optimization in the next stage.

[0058] As an optimization scheme of the above embodiment, after the search window range is defined, in order to improve the effect of timing optimization, a dynamic programming cell movement method based on trigger position reconstruction is established, including:

[0059] As shown in Figure 5 The core idea of the method is: by moving the trigger within a reasonable range, the dynamic adjustment of the propagation delay between adjacent paths is realized, so that the setup and hold violations are repaired and the overall slack distribution is optimized without introducing illegal layout.

[0060] In order to efficiently perform the movement operation of the trigger, the relocation problem of the trigger in the local area is modeled as a minimum cost arrangement problem with blocking constraints, and a dynamic programming strategy is introduced for solving.

[0061] The dynamic programming strategy includes:

[0062] Adjacent paths with violations are extracted through static timing analysis, and the last stage logic cell c1 of path A and the first stage logic cell c2 of path B are taken as reference points. The slack value is calculated to obtain two feasible placement areas centered on c1 and c2; wherein the Manhattan distance d is determined by the initial distance between the current position of the trigger and the reference point minus the timing cost difference calculated based on the Elmore delay model formula; if there is an overlap between the two rectangular areas, the intersection is the target area where the trigger can be legally moved; optimization is performed in this area, while reducing the propagation delay of path A and increasing the delay of path B, achieving balanced adjustment between setup and hold violations.

[0063] In order to find the optimal trigger placement position in the feasible placement area, the feasible placement area is discretized into an rxc two-dimensional grid, and all blocking areas (such as macro cells, non-placed cells, etc.) are marked as unusable areas. Then a three-dimensional dynamic programming table dp[n+1][r+1][c+1] is constructed, where dp[i][j][k] represents the minimum cost of placing the ith trigger at (j, k) position. The cost function considers factors including path slack, wiring cost, congestion factor. In the state transition process, all illegal positions are skipped, and the optimal predecessor position is recorded. Finally, the complete trigger placement path is restored through backtracking. This method effectively converts the trigger reconstruction problem into a dynamic optimization problem with clear structure and efficient solution, significantly improving the quality and convergence speed of the solution.

[0064] In the actual process, in order to avoid the waste of resources caused by excessive iteration, the idea of delayed update in deep learning is used. In each local trigger adjustment, the clock network and path delay of the entire circuit are not updated immediately, but only the current combination logic structure is assumed to be fixed, and the delay change is locally effective. Subsequently, the LCB redistribution strategy is used for global timing correction. This processing method avoids repeated calculation, improves system efficiency, and ensures the timing convergence and global consistency of the final layout.

[0065] The above shows and describes the basic principles and main features of the present application and the advantages of the present application. Those skilled in the art should understand that the present application is not limited to the above embodiments, and the above embodiments and descriptions in the specification are only to illustrate the principles of the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the claimed present application. The scope of protection of the present application is defined by the appended claims and their equivalents.

Claims

1. A chip circuit detailed layout optimization method based on dynamic programming, characterized in that: The detailed layout process of timing-driven chip circuit wiring includes the following steps: Perform static timing analysis of the initial transistor positions to identify the negative slack region on the critical path and perform heuristic optimization targeting this region. Adaptive search window definition: Dynamically adjust the movable range of a unit based on its impact on path timing, focusing the optimization on key areas and avoiding unnecessary disturbances in non-critical areas; Fine-grained cell movement based on dynamic programming: Enumerate all legal cell arrangements in a local window, combine timing cost and legality constraints, and accurately solve the optimal layout solution.

2. The chip circuit detailed layout optimization method based on dynamic programming according to claim 1, characterized in that: The input is the initial cell coordinates and network connection information after global layout, and static timing analysis is used to identify the negative slack paths and key cells under the current layout.

3. The chip circuit detailed layout optimization method based on dynamic programming according to claim 1, characterized in that: In the adaptive search window definition process, a spatial range is defined when locally optimizing a region or certain cells in a circuit; within this range, the algorithm allows a selected set of cells to be moved, swapped, or rearranged between legal positions to optimize timing, line length, and congestion indicators.

4. The chip circuit detailed layout optimization method based on dynamic programming according to claim 3, characterized in that: The decision conditions in the adaptive search window definition process are: For the cells moved through the previous stage, n cells are selected in sequence according to the pin importance to construct a rectangle that completely surrounds these cells.

5. The chip circuit detailed layout optimization method based on dynamic programming according to claim 4, characterized in that: In the adaptive search window definition process, Use tail insertion to read the coordinate data generated by the previous black box process into the initial doubly linked list in sequence; starting from the head of the initial doubly linked list, each time a cell is added to the current rectangle, it is necessary to calculate whether the distance from the cell to the center of the rectangle exceeds the Manhattan distance limit. The distance constraint formula is as follows: lim x with lim y They are the displacement limits of the current transistor in the horizontal and vertical directions of the entire layout respectively. Max.Disp is a hyperparameter that constrains the detailed layout to avoid excessive perturbation of the global layout; If the limit is exceeded, the cells are temporarily stored in a secondary list; once n cells are queued and a rectangle is constructed, the cells in the secondary list are reinserted in order at the head of the initial doubly linked list; This process is repeated until no more rectangles can be constructed in the original doubly linked list.

6. The chip circuit detailed layout optimization method based on dynamic programming according to claim 1, characterized in that: Establish a dynamic programming unit movement method based on trigger position reconstruction, including: By moving the trigger within a reasonable range, the propagation delay between adjacent paths is dynamically adjusted, thereby fixing setup and hold violations and optimizing the overall slack distribution without introducing illegal layouts.

7. The chip circuit detailed layout optimization method based on dynamic programming according to claim 6, characterized in that: The flip-flop relocation problem in a local area is modeled as a minimum cost permutation problem with blocking constraints, and a dynamic programming strategy is introduced to solve it.

8. The chip circuit detailed layout optimization method based on dynamic programming according to claim 7, characterized in that: Dynamic programming strategies include: Static timing analysis extracts adjacent paths with violations. Using the last-level logic cell c1 of path A and the first-level logic cell c2 of path B as reference points, combined with the slack value, two feasible placement areas centered on c1 and c2 are calculated. The Manhattan distance d is determined by subtracting the timing cost difference calculated based on the Elmore delay model formula from the initial distance between the trigger's current position and the reference point. If the two rectangular areas overlap, the intersection is the target area where the trigger can legally move. Optimization is performed within this area, simultaneously reducing the propagation delay of path A and increasing the delay of path B to achieve a balance between setup and hold violations.

9. The chip circuit detailed layout optimization method based on dynamic programming according to claim 8, characterized in that: To find the optimal trigger placement location in the feasible placement area, the feasible placement area is discretized into an r×c two-dimensional grid, and all blocked areas are marked as unavailable areas; A three-dimensional dynamic programming table dp[n+1][r+1][c+1] is then constructed, where dp[i][j][k] represents the minimum cost of placing the i-th trigger at position (j, k). The cost function comprehensively considers factors such as path slack, wiring cost, and congestion. During the state transition process, all illegal positions are skipped and the optimal predecessor position is recorded. Finally, the complete trigger placement path is restored through backtracking.

10. The chip circuit detailed layout optimization method based on dynamic programming according to claim 9, characterized in that: In each local trigger adjustment, the clock network and path delay of the entire circuit are not immediately fully updated. Instead, it is assumed that the current combinational logic structure is fixed and the delay change is only effective locally. Subsequently, the proposed LCB reallocation strategy is used to perform global timing correction.

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