A method and apparatus for classifying static timing analysis reports

Abstract

The present application relates to the technical field of microcircuit analysis, and discloses a classification method and equipment for static timing analysis report. The present application comprises the following steps: determining the type of the static timing analysis report of the target timing path; if the static timing analysis report is the setup time type, dividing the data path of the target timing path into intra-module paths and cross-module paths; dividing the violations existing in the intra-module paths to the corresponding modules to obtain a first violation division result; determining a plurality of target modules corresponding to the cross-module paths with violations; calculating the violation value contribution degree of each target module; dividing the violations existing in the cross-module paths to the corresponding target modules according to the violation value contribution degree of each target module to obtain a second violation division result; and determining the violations of the target timing path belonging to each module according to the first violation division result and the second violation division result. The present application can efficiently process the static timing analysis report, and improve the efficiency and accuracy.

Description

Technical Field

[0001] This invention relates to the field of microcircuit analysis technology, specifically to a classification method and device for static timing analysis reports. Background Technology

[0002] In full-scale static timing analysis, in order to effectively transmit the analysis results to different module designers so that they can perform subsequent processing according to their respective design responsibilities, there are currently two main processing methods.

[0003] The first approach is to have each module's designer directly analyze the original static timing analysis report and extract the relevant parts for their own module. While this method is straightforward, the sheer volume of information in a single report becomes enormous with the dramatic increase in the number of transistors on a chip. This significantly increases the time and machine resources required to open the report, making it increasingly difficult for designers to extract the information they are interested in.

[0004] The second approach involves adding path combinations when running a static time-series analysis task, or reopening the stored database and adjusting reporting options to make the static time-series analysis tool generate more clearly categorized reports. While this method improves report readability to some extent, it still has some issues. For example, using the path combination method requires pre-setting many combinations for the static time-series analysis task, increasing its complexity, and for certain types of reports, categorization by adding path combinations is not possible. Furthermore, reopening the stored database to customize reporting options is a secondary operation, increasing project iteration time. Summary of the Invention

[0005] In view of this, the present invention provides a classification method and device for static time series analysis reports, which can efficiently process static time series analysis reports and improve efficiency and accuracy.

[0006] In a first aspect, the present invention provides a classification method for static timing analysis reports, comprising: determining the type of static timing analysis report of a target timing path; if the static timing analysis report is of the setup time type, dividing the data path of the target timing path into intra-module paths and cross-module paths; assigning violations existing in intra-module paths to the corresponding modules to obtain a first violation classification result; determining multiple target modules corresponding to the cross-module paths containing violations; calculating the violation value contribution of each target module based on the logic level, delay, ratio of delay to logic level, and whether there are outliers; assigning violations existing in cross-module paths to the corresponding target modules based on the violation value contribution of each target module to obtain a second violation classification result; and determining the violations of the target timing path belonging to each module based on the first and second violation classification results.

[0007] The classification method for static time series analysis reports provided in this embodiment performs an initial classification based on the type of the static time series analysis report, dividing the data path of the target time series path into intra-module paths and cross-module paths. This allows violations in the target time series path to be accurately located to specific modules. By calculating the contribution of violation values ​​of each target module, violations in cross-module paths are further classified based on this contribution, further improving the accuracy of classification. By calculating the contribution of violation values, it can be determined which modules contribute more to the violations. For violations in cross-module paths, calculating the contribution of each target module helps to accurately determine the module to which the violations in the cross-module path belong. For cross-module paths with violations, analyzing the contribution of each target module, rather than judging the module to which the violation belongs based on the path's logical hierarchy, can avoid overly arbitrary classification, thereby preventing situations where the module showing the violation in the report does not match the module that actually needs to be repaired.

[0008] In one optional implementation, the violation value contribution of each target module is calculated based on the logic level, delay, the ratio of delay to logic level, and whether there are outliers. This includes: calculating a base score for the violation value contribution of each target module based on the logic level, delay, and the ratio of delay to logic level; if the target module does not have outliers, the base score is determined as the violation value contribution of the target module; if the target module has outliers, an additional score for the violation value contribution is calculated based on the standard unit delay of the outlier and the delay of all standard units on the data path of the target timing path, and the sum of the base score and the additional score is determined as the violation value contribution of the target module.

[0009] The classification method for static timing analysis reports provided in this embodiment calculates a base score based on the number of logic levels, latency, and the ratio of latency to logic levels for each target module. The base score reflects the basic performance of the target module in terms of logic complexity and latency. By determining whether there are outliers in the target module, it can accurately identify cases where the latency of a certain level or several levels of standard units in the violation path is abnormally large. If there are outliers in the target module, additional points are calculated based on the latency of the standard units of the outliers and the latency of all standard units on the data path of the target timing path. The additional points can correct the base score, and finally calculate the final score, which comprehensively reflects the actual situation of the target module, making the final score more objective and fair. Giving additional points to modules with outliers can highlight the importance of outliers. In general, logic levels with abnormal latency need to be repaired first in actual engineering. This avoids the outliers in modules with many logic levels being hidden in the calculation of the base score, and improves the accuracy of violation attribution in the target timing path.

[0010] In one optional implementation, a basic score for the violation value contribution of each target module is calculated based on the logic level, delay, and the ratio of delay to logic level of each target module. This includes: determining a weight vector corresponding to the level of the data path of the target timing path, wherein the weight vector contains weight values ​​corresponding to the logic level, delay, and the ratio of delay to logic level, and different weight vectors correspond to different levels; and calculating a normalized weighted average of the logic level of the standard unit on the data path of the target timing path relative to the logic level, delay, and ratio of delay to logic level of each target module based on the weight vector, to obtain the basic score for the violation value contribution of each target module.

[0011] The classification method for static time series analysis reports provided in this embodiment determines a weight vector for each level interval based on the number of levels in the data path of the target time series path. Introducing the weight vector can comprehensively and accurately evaluate the contribution of the target module to the violation value. The weight vector is determined according to the number of levels in the data path, which can flexibly adapt to the different impacts of various factors on the contribution of violation value under different levels, improving the flexibility and applicability of the evaluation. Using the determined weight vector, the logic level, delay, and the ratio of delay to logic level of each target module are normalized. The weighted average is calculated based on the normalized values ​​and the corresponding weights to obtain the basic score of the contribution of each target module to the violation value. By calculating the normalized weighted average, the difference in the dimensions between different factors is eliminated, making the evaluation results more accurate and reliable.

[0012] In one optional implementation, the method includes: if the number of standard unit levels in the data path of the target timing path is less than a preset value, then it is determined that there are no outliers in the data path of the target timing path; if the number of standard unit levels in the data path of the target timing path is greater than or equal to the preset value, the average value and standard deviation of the delay of all standard units in the data path of the target timing path are calculated; based on the delay, average value and standard deviation of each standard unit, it is determined whether the delay of each standard unit meets the set conditions; if the delay of the standard unit meets the set conditions, the standard unit is determined to be an outlier; and the module containing the outlier is determined to be the module with outliers.

[0013] The classification method for static time series analysis reports provided in this embodiment can exclude data paths with fewer standard unit levels by judging whether the number of standard unit levels is less than a preset value, thereby avoiding calculation errors caused by small sample size. By calculating the average delay and standard deviation, and combining them with set conditions, it can determine whether the delay of each standard unit is abnormal, and more accurately locate the abnormal points in the data path.

[0014] In one optional implementation, if the static timing analysis report is of the hold-time type, it includes: determining the logical level at which the end point of the data path of the target timing path is located; and determining the violations of the target timing path belonging to each module based on the logical level at which the end point of the data path of the target timing path is located.

[0015] The classification method for static timing analysis reports provided in this embodiment is based on the logical level of the end point of the data path of the target timing path. It is based on the fact that the repair of time type violations is usually carried out in the module corresponding to the logical level of the end point. This classification method reduces the complexity of attribution judgment while ensuring classification accuracy.

[0016] In one optional implementation, if the static timing analysis report is a design rule or other type, it includes: determining the specific violation entries of the design rule and other types of violations; and determining the violations belonging to each module based on the logical level of the specific violation entries of the design rule and other types of violations.

[0017] The classification method for static timing analysis reports provided in this embodiment is based on the fact that design rules and other types of violations are ultimately manifested as single-point violations such as a certain level of standard unit, a certain interconnect, or a certain pin. By locating single-point violations, the module to which the violation belongs can be quickly found, thereby enabling module designers to more quickly and clearly obtain the entries related to design rules and other types of violations in their respective modules.

[0018] In one optional implementation, the method includes: determining the violations belonging to each module based on the static time series analysis reports in the full-scale static time series analysis; combining the modules to which the violations are classified, assigning the report content of each violation path or specific violation item in each static time series analysis report in the full-scale static time series analysis to the corresponding module, and generating a module analysis report for each module; and integrating the module analysis reports for all analysis scenarios of each module to generate a global summary report.

[0019] The classification method for static time series analysis reports provided in this embodiment divides the static time series analysis report into module analysis reports for each module, and further generates a global summary report, making the report content clearer and more organized, improving the readability of the report, and the separate module analysis reports help to quickly locate the problem.

[0020] In one optional implementation, based on the module to which the violation is classified, the report content of each violation path or specific violation item in each static timing analysis report in the fully unfolded static timing analysis is divided into corresponding modules, generating module analysis reports for each module. This includes: if the static timing analysis report is a timing inspection report, determining the primary category type of the static timing analysis report based on the inspection type of the scenario in the static timing analysis report; and determining the secondary category type of the static timing analysis report based on the physical type of the start and end points of the data path of the target timing path. The secondary categories include input port to register, register to... Registers, register-to-output ports, and input-to-output ports; based on the module to which the violation of the target timing path belongs, the static timing analysis report of the target timing path is divided into the corresponding third-level subclass of the module, establishing the correspondence between the static timing analysis report and the module, with each module corresponding to a third-level subclass; if the second-level subclass of the static timing analysis report of the target timing path is register-to-register, then based on whether the reference names of the modules to which the start and end points of the data path of the target timing path belong are the same, the further fourth-level subclass of the static timing analysis report of the target timing path in the corresponding third-level subclass module is determined.

[0021] The classification method for static timing analysis reports provided in this embodiment determines its primary category type based on the inspection type of the static timing analysis report scenario. Specifically, it is either a MAX or MIN type, corresponding to setup time inspection and hold time inspection, respectively, reflecting the guiding principle of timing inspection reports. Based on the physical type of the start and end points of the target timing path's data path, the report is further subdivided into secondary categories. These secondary categories represent different types of data flow paths. In hierarchical module design, further classification of different types of timing paths of interest to module designers helps them decouple the distribution and performance of different types of timing paths. Based on the module to which the violation of the target timing path belongs, the static timing data of the target timing path is further classified. The analysis reports are categorized into three levels of subcategories corresponding to their respective modules, establishing a correspondence between reports and modules. This ensures that each module can obtain a detailed timing analysis report related to it. For the second-level subcategories, register-to-register data paths, further classification is performed after the third-level classification because register-to-register data paths are the part that designers of each module are most concerned about in hierarchical module design, and their performance best reflects the quality of each module's design. Based on whether the reference names of the modules to which the start and end points of the target timing path belong are the same, the static timing analysis report of the target timing path is further determined into a fourth-level subcategory within the corresponding third-level subcategory module. This subdivision helps to obtain more detailed reports on register-to-register data paths within each module and across different modules more quickly and comprehensively.

[0022] In one optional implementation, based on the module to which the violation belongs after classification, the report content of each violation path or specific violation item in each static timing analysis report in the fully unfolded static timing analysis is divided into the corresponding module, generating a module analysis report for each module. This includes: if the static timing analysis report is a design rule check or other type of check report, creating a setting name directory and using the setting name directory as the first-level category of the static timing analysis report; according to the module corresponding to the logical level of the specific violation item in the static timing analysis report, dividing the static timing analysis report into the second-level sub-categories of the module, establishing the correspondence between the static timing analysis report and the module, with each module corresponding to a second-level sub-category; and determining the third-level sub-category of the static timing analysis report in the corresponding module based on the violation type contained in the static timing analysis report.

[0023] The classification method for static timing analysis reports provided in this embodiment creates a directory with a set name as the first-level category for static timing analysis reports. Reports of different design rule checks and other types of checks are uniformly classified under the corresponding directory for easy management and retrieval. By classifying the reports into second-level subcategories of modules according to the logical level of the specific violation entries in the static timing analysis reports, a correspondence between reports and modules is established, so that each module can obtain detailed inspection reports related to it. This also helps to quickly locate the module where the problem is located and improves the efficiency of problem solving. Based on the violation types contained in the static timing analysis reports, the third-level subcategories of the reports in the corresponding modules are further determined. By subdividing the reports into three levels of subcategories, problems can be identified and analyzed more accurately.

[0024] In a second aspect, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the upgrade method of the first aspect or any corresponding embodiment described above. Attached Figure Description

[0025] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0026] Figure 1 This is a flowchart illustrating a classification method for static time-series analysis reports according to an embodiment of the present invention;

[0027] Figure 2This is a flowchart illustrating another classification method for static time series analysis reports according to an embodiment of the present invention;

[0028] Figure 3 This is a flowchart illustrating another classification method for static time series analysis reports according to an embodiment of the present invention;

[0029] Figure 4 This is a flowchart illustrating another classification method for static time series analysis reports according to an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of the timing check report directory structure according to an embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram of the module summary report of the timing check report in an embodiment of the present invention;

[0032] Figure 7 This is a flowchart illustrating an additional classification method for static time series analysis reports according to an embodiment of the present invention;

[0033] Figure 8 This is a schematic diagram of the directory structure of the design rule check and other types of check reports in the embodiments of the present invention;

[0034] Figure 9 This is a schematic diagram of the module summary report of the design rule check and other types of check reports in the embodiments of the present invention;

[0035] Figure 10 This is a schematic diagram of the content of the global summary report in an embodiment of the present invention;

[0036] Figure 11 This is a schematic diagram illustrating the content of the global summary report for overall planning in an embodiment of the present invention;

[0037] Figure 12 This is a schematic diagram of the content of the global summary report of the top-level module in an embodiment of the present invention;

[0038] Figure 13 This is a schematic diagram of the content of a global summary report of one of the modules in an embodiment of the present invention;

[0039] Figure 14 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] Currently, in full-scale static timing analysis, to achieve task division by distributing report results to different module designers, two main approaches exist: The first involves each module designer analyzing the original static timing analysis report and extracting their own relevant information. The second involves adding path combinations during the static timing analysis task or reopening the stored database and adjusting report options to make the static timing analysis tool generate more clearly categorized reports. The first approach suffers from several drawbacks. The increased number of transistors in the chip results in a massive amount of information in the generated reports, significantly increasing the time and resources required to open and process them. Designers struggle to quickly locate the necessary information, and the separate processing of the same report by different module designers leads to duplication of work, low efficiency, and project management chaos due to inconsistent terminology. The second approach, using path combination methods, requires pre-setting many combinations for the static timing analysis task, increasing its complexity. Furthermore, for certain types of reports, categorization through path combination is not feasible.

[0042] According to an embodiment of the present invention, a classification method for static timing analysis reports is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0043] This embodiment provides a classification method for static time series analysis reports. Figure 1 This is a flowchart illustrating a classification method for static time-series analysis reports according to an embodiment of the present invention, as shown below. Figure 1 As shown, the process includes the following steps:

[0044] Step S101: Determine the type of static timing analysis report for the target timing path.

[0045] In one alternative embodiment, the static timing analysis report of the target timing path may include setup time type, hold time type, design rule type, and other types.

[0046] Step S102: If the static timing analysis report is of the establishment time type, the target timing path is divided into intra-module paths and cross-module paths.

[0047] In one optional embodiment, the setup time type includes setup time violation, recovery time violation, maximum delay violation, and data check violation.

[0048] In one optional embodiment, based on the differences in the logical levels of the starting point, passing point, and ending point of the target timing path's data path and the modules they belong to, paths can be divided into intra-module and cross-module paths. The starting point of the target timing path's data path is the emit-edge trigger on the target timing path's data path; the passing point is each standard cell traversed on the target timing path's data path; and the ending point is the receive-edge trigger on the target timing path's data path. The logical levels are determined according to the complexity of the design and functional requirements. For example, the logical level of the emit-edge trigger might be "top-level name / instantiation name of module a a1 / a". 11 / a 111 ".

[0049] In an optional embodiment, if the start point, transit point, and end point of the data path of the target timing path are all located within the same module, then this path is an intra-module path. For example, in "top-level name / instance name of module a a1 / a 11 / a 111 Under this naming convention, if the starting point, transit point, and ending point of the target timing path's data path are all under the level of "top-level name / instance name of module a a1", and all logic under this level is within a submodule with the reference name a, then this path is an intramodule path of module a. If the starting point, transit point, and ending point of the target timing path's data path cross different modules, then this path is a cross-module path. For example, in "top-level name / instance name of module a a1 / a..." 11 / a 111 Under this naming rule, if the starting point and subsequent passage points of the data path of the target timing path are at the level of "top-level name / instance name a1 of module a", and the remaining passage points and ending point are at the level of "top-level name / instance name b1 of module b", then this path is a cross-module path, and its data path crosses two modules with reference names a and b respectively. By dividing the target timing path into intra-module paths and cross-module paths, violations of the target timing path can be accurately attributed to specific modules.

[0050] In one optional embodiment, the data paths of the target timing path are initially classified according to the type of static timing analysis report, and divided into intra-module paths and cross-module paths, so that violations of the target timing path can be accurately located on specific modules.

[0051] Step S103: Assign violations existing in the path within the module to the corresponding module to obtain the first violation assignment result.

[0052] In an alternative embodiment, for paths within a module, violations generated by that path belong to that module.

[0053] Step S104: Identify the multiple target modules corresponding to the cross-module path with the violation.

[0054] In one optional embodiment, for cross-module paths with violations, the violations are attributed to the module that contributed the most to the violations. Cross-module paths involve interactions and connections between modules. When a violation is detected, it is necessary to ensure that all modules involved in the violation are accurately located. By determining the multiple target modules corresponding to the cross-module paths with violations, it can be ensured that no module related to the violation is missed, thereby improving the accuracy of problem location.

[0055] Step S105: Calculate the violation value contribution of each target module based on the logic level, delay, ratio of delay to logic level, and whether there are outliers.

[0056] In an optional embodiment, since the determination of the contribution of a module to a violation is quite complex, it is exemplarily necessary to analyze multiple aspects such as clock tree skew, number of standard cell levels in the data path, placement of standard cells, threshold voltage of standard cells, selection of standard cells, interconnect winding quality, whether interconnects are detours, interconnect crosstalk, and early design planning. Since the above-mentioned factors can ultimately cause changes in apparent factors such as logic levels and delays, this invention selects three dimensions—logic levels, delay, and the ratio of delay to logic levels—to calculate the contribution of each target module to the violation value.

[0057] Step S106: Based on the contribution of each target module's violation value, the violations existing in the cross-module path are assigned to the corresponding target modules to obtain the second violation assignment result.

[0058] In one optional embodiment, violations existing in cross-module paths are further divided based on the calculated contribution of each target module's violation value, which improves the accuracy of classification. By calculating the contribution of violation values, it is possible to identify which modules contribute more to the violations, which helps to accurately classify the modules to which violations existing in cross-module paths belong.

[0059] Step S107: Based on the first violation classification result and the second violation classification result, determine the violations belonging to the target timing paths of each module.

[0060] This embodiment provides a classification method for static time series analysis reports. It performs a preliminary classification based on the type of the static time series analysis report, dividing the data path of the target time series path into intra-module paths and cross-module paths. This allows violations in the target time series path to be accurately located to specific modules. By calculating the contribution of each target module's violation value, violations in cross-module paths are further classified based on this contribution, further improving the accuracy of the classification. Calculating the contribution of violation values ​​clarifies which modules contribute more to the violations. For violations in cross-module paths, calculating the contribution of each target module helps to accurately determine the module to which the violations belong. For cross-module paths with violations, analyzing the contribution of each target module, rather than judging the module to which the violations belong based on the path's logical hierarchy, avoids overly arbitrary classification, thus preventing situations where the module showing the violation in the report does not match the module that actually needs to be repaired.

[0061] This embodiment provides a classification method for static time series analysis reports. Figure 2 This is a flowchart illustrating another classification method for static time series analysis reports according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0062] Step S201: Determine the type of static timing analysis report for the target timing path. See details below. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0063] Step S202: If the static timing analysis report is of the setup time type, divide the data path of the target timing path into intra-module paths and cross-module paths. For details, please refer to [link to relevant documentation]. Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0064] Step S203: Violations existing in the paths within a module are assigned to the corresponding modules, resulting in the first violation assignment result. For details, please refer to [link to relevant documentation]. Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0065] Step S204: Identify the multiple target modules corresponding to the cross-module path with the violation. For details, please refer to [link to relevant documentation]. Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0066] Step S205: Calculate the basic score of the violation value contribution of each target module based on the logic level, delay, and the ratio of delay to logic level of each target module.

[0067] In an optional embodiment, the logic level, delay, and the ratio of delay to logic level of each target module refer to the logic level of the standard unit on the data path of the target timing path, the sum of the levels and delays of the standard units of each target module, and the ratio of the sum of delays to the level. Each module refers to a design module with a specific reference name that is artificially divided for parallel design. Based on the logic level, delay, and the ratio of delay to logic level of each target module, a basic score is calculated. The basic score can reflect the basic performance of the target module in terms of logic complexity and delay performance.

[0068] Specifically, step S205 includes:

[0069] Step S2051: Based on the number of levels of the data path in the target timing path, determine the weight vector corresponding to the level. The weight vector contains the weight values ​​corresponding to the logical level, delay, and the ratio of delay to logical level. Different levels correspond to different weight vectors.

[0070] In one optional embodiment, determining different weight vectors corresponding to different levels includes: constructing their own evaluation sequences for different logic level intervals, calculating the weight value of each variable in the intervals of different logic levels, calculating the consistency ratio, judging whether the weight values ​​are reasonable, and determining the final weight vectors for logic level, delay, and the ratio of delay to logic level.

[0071] In one optional embodiment, since the calculation of the base score of the target module requires combining the ratio of the delay to the number of logic levels of the target module, when the number of logic levels of the target module is small, the delay of each logic level will have a significant impact on the ratio of delay to the number of logic levels. However, when the number of logic levels of the target module is large, even if a certain logic level in the target module has a large delay, the final calculated ratio of delay to the number of logic levels will not change significantly. In this case, if the ratio of delay to the number of logic levels is still given a large weight, the final calculated base score will not reflect the abnormal delay of that logic level. For example, if the total number of stages is 30, with 10 stages in module a and an average latency of 10 ps, ​​and another 20 stages in module b and an average latency of 9 ps, increasing the weight of the ratio of latency to the number of logic stages would attribute the timing path violation to module a. However, in reality, some stages in module b have higher latency. For instance, three stages might have latencies of 20 ps, ​​19 ps, and 21 ps, respectively. These three stages have significantly higher latency than the average. However, because module b has more stages and the other stages have lower latency, this calculation hides the impact of these three logic stages on overall performance. Therefore, different weight vectors should be set for different stages.

[0072] In an optional embodiment, an evaluation sequence for each target module is constructed. The variables are the logic level, delay, and the ratio of delay to logic level for each target module. All variables are compared pairwise, and the comparison scale uses 1 to 9 and their reciprocals, where 1 indicates equal importance, 3 indicates the former is slightly more important than the latter, 5 indicates the former is significantly more important than the latter, 7 indicates the former is strongly more important than the latter, and 9 indicates the former is extremely more important than the latter. 2, 4, 6, and 8 are the intermediate values ​​of the above adjacent judgments. The assignment of weight vectors corresponding to different logic levels in this invention is only an example. Exemplarily, in this invention, the evaluation sequence is constructed by combining the interval distribution of the total logic levels on the data path as follows:

[0073] Total number of levels ≤ 10 series Delay Delay / Number of Stages series 1 1 / 2 1 / 4 Delay 2 1 1 / 3 Delay / Number of Stages 4 3 1

[0074] 10 < total series ≤ 20 series Delay Delay / Number of Stages series 1 1 1 / 4 Delay 1 1 1 / 2 Delay / Number of Stages 4 2 1

[0075] Total number of levels ≥ 20 series Delay Delay / Number of Stages series 1 1 1 / 3 Delay 1 1 1 / 2 Delay / Number of Stages 3 2 1

[0076] In one optional embodiment, calculating the weight value of each variable includes calculating the geometric mean of the elements in each row of the evaluation sequence and normalizing the result to obtain the weight value. For example, the weight value of each variable in an evaluation sequence with a total number of levels ≤ 10 is calculated.

[0077] Calculate the geometric mean of the elements in each row:

[0078] For series:

[0079] Regarding delay:

[0080] For delays / stages:

[0081] The weight values ​​are obtained by normalization:

[0082] Series weights:

[0083]

[0084] Delay / series weights:

[0085] In one optional embodiment, calculating the consistency ratio and determining whether the weight values ​​are reasonable includes using the "sum method" to calculate the maximum eigenvalue of the matrix. For example, calculating the consistency ratio of the evaluation series with a total level ≤ 10 and determining whether the weight values ​​of the evaluation series with a total level ≤ 10 are reasonable.

[0086] The evaluation matrix is ​​normalized column-wise, that is, each element of a column is divided by the sum of the elements in that column, resulting in:

[0087]

[0088] Summing the normalized evaluation matrix row by row yields:

[0089]

[0090] Normalize the rows and vectors of the evaluation matrix to obtain the eigenvectors:

[0091]

[0092] Calculate the judgment evaluation matrix multiplied by the eigenvector to obtain:

[0093]

[0094] Calculate the largest eigenvalue:

[0095]

[0096] In one optional embodiment, calculating the largest eigenvalue includes calculating a consistency index, finding the average random consistency index RI of the corresponding third-order matrix, calculating the consistency ratio, and determining whether the matrix has satisfactory consistency.

[0097] The consistency index CI is calculated to obtain:

[0098] In a third-order matrix, n=3

[0099] Find the average random consistency index (RI) of the corresponding third-order matrix:

[0100] RI≈0.58

[0101] Calculate the consistency ratio (CR) to obtain:

[0102]

[0103] The judgment matrix has satisfactory consistency.

[0104] Since the consistency ratio CR < 0.1, the calculated weights of 0.137, 0.239, and 0.724 are reasonable.

[0105] Determine the final series, delay, and weight vector of the delay-to-logic-series ratio.

[0106] After calculation, the final weight vector is:

[0107]

[0108] In one optional embodiment, a weight vector is determined for each level interval based on the level of the data path of the target time-series path. Introducing the weight vector can comprehensively and accurately evaluate the contribution of the target module to the violation value. The weight vector is determined according to the level of the data path, which can flexibly adapt to the different impacts of various factors on the contribution of the violation value under different levels, thereby improving the flexibility and applicability of the evaluation.

[0109] Step S2052: Based on the weight vector, perform normalized weighted average calculation on the logic level of the standard unit on the data path of the target timing path relative to the logic level, delay, and ratio of delay to logic level of each target module to obtain the basic score of the violation value contribution of each target module.

[0110] In one optional embodiment, for example, the data path of the target timing path passes through m modules, namely module 1, module 2, ..., module m. Through calculation, the data path of the target timing path has a total of k levels. The selected weight vector is (a1, a2, a3). According to the module distribution, the maximum logical level of a single module is k. max The maximum delay for a single module is d. max The ratio of the maximum delay of a single module to the number of logic levels is (d / k). max .

[0111] The series number of a certain module i is k i The delay is d i Then, the module calculates its base score S using a normalized weighted average algorithm. i S i The base score is out of 100.

[0112]

[0113] In one optional embodiment, a defined weight vector is used to normalize the logic level, delay, and the ratio of delay to logic level of each target module. A weighted average is then calculated based on the normalized values ​​and the corresponding weights to obtain the basic score of the violation value contribution of each target module. By using the normalized weighted average calculation, the difference in dimensions between different factors is eliminated, making the evaluation results more accurate and reliable.

[0114] Step S206: Determine whether the standard unit level of the data path of the target timing path is less than a preset value.

[0115] If the number of standard unit levels in the data path of the target time sequence path is less than the preset value, it is determined that there are no abnormal points in the data path of the target time sequence path.

[0116] If the standard cell level of the data path in the target timing path is greater than or equal to the preset value...

[0117] Calculate the average and standard deviation of the delay of all standard cells in the data path of the target timing path.

[0118] In an optional embodiment, for example, the preset value can be set to 5 levels. When the number of standard unit levels in the data path of the target time series path is less than 5, only a few standard unit delay data are available for analysis. In this case, if the average and standard deviation of the delay of all standard units in the data path of the target time series path are calculated, the calculated results are easily affected by extreme values. However, when the number of standard unit levels in the data path of the target time series path is greater than 5, it means that there is more standard unit delay data available for analysis. The larger the sample size, the closer the estimated average and standard deviation are to the true value, and the higher the significance of the statistical results. Thus, the calculated statistics are more reliable.

[0119] In one optional embodiment, by determining whether the standard unit level is less than a preset value, data paths with fewer standard unit levels can be excluded, thereby avoiding calculation errors caused by a small sample size.

[0120] Step S207: Based on the delay, average value and standard deviation of each standard unit, determine whether the delay of each standard unit meets the set conditions.

[0121] If the delay of the standard unit meets the set conditions, the standard unit is determined to be an anomaly.

[0122] If the delay of the standard unit does not meet the set conditions, it is determined that there are no abnormal points in the data path of the target timing path.

[0123] In an optional embodiment, the set condition is x > 1.5μ and x > μ + 3δ, where x is the delay of each standard unit, μ is the average of all standard units, and δ is the standard deviation of all standard units. The set condition is based on the properties of the normal distribution to determine whether there are outliers in the data path of the target time series path. In statistics, approximately 99.7% of the data will fall within three standard deviations on both sides of the average. When x > μ + 3δ, it means that the delay x of the standard unit exceeds the third standard deviation to the right of the average μ. 1.5μ can identify delays that significantly deviate from the normal range. Therefore, if the delay of a certain level of standard unit in the data path of the target time series path is x, and x > 1.5μ and x > μ + 3δ, it is determined that there are outliers in the data path of this target time series path. By calculating the average delay and standard deviation, and combining the set condition to determine whether the delay of each standard unit is abnormal, it is possible to more accurately locate outliers in the data path.

[0124] Step S208: The module containing the anomaly is identified as the module with the anomaly.

[0125] Step S209: If there are no outliers in the target module, the base score is determined as the contribution of the violation value of the target module.

[0126] In one optional embodiment, by determining whether there are abnormal points in the target module, it is possible to accurately identify cases where the delay of a certain level or several levels of standard units in the violation path is abnormally large.

[0127] Step S210: If there are anomalies in the target module, calculate the extra score for the contribution of the violation value based on the standard unit delay of the target module, and determine the sum of the basic score and the extra score as the contribution of the violation value of the target module.

[0128] In an optional embodiment, assuming the module with the anomaly is module i, then this module will receive an additional bonus S. add :

[0129]

[0130] Among them, S add For the module's extra points, x represents the delay of a standard unit at a certain level in the data path of the target timing path, and μ represents the delay of the module. i This is the average delay of all standard cells in the data path of the target timing path.

[0131] Calculated score S of module i i for:

[0132]

[0133] In one optional embodiment, by calculating the average delay and standard deviation, and combining them with set conditions, it is possible to determine whether the delay of each standard unit is abnormal, thereby more accurately locating the abnormal points in the data path.

[0134] In an optional embodiment, if the target module has anomalies, additional points are calculated based on the standard unit delay of the anomaly and the delays of all standard units on the data path of the target timing path. These additional points can correct the base score, ultimately calculating the final score and comprehensively reflecting the actual situation of the target module, making the final score more objective and fair. Giving additional points to modules with anomalies highlights their importance; typically, logic levels with abnormal delays are those that need to be prioritized for repair in actual engineering. This prevents anomalies in modules with many logic levels from being hidden in the base score calculation, improving the accuracy of violation attribution in the target timing path.

[0135] Step S211: Based on the contribution of each target module's violation value, the violations existing in the cross-module path are assigned to the corresponding target modules to obtain the second violation assignment result.

[0136] In an optional embodiment, for example, if the contribution of target module 1 to the target violation existing in the cross-module path is 90 and the contribution of target module 2 to the target violation existing in the cross-module path is 10, and 90 > 10, then the violation existing in the cross-module path is assigned to target module 1.

[0137] Step S212: Based on the first violation classification result and the second violation classification result, determine the violations belonging to the target timing paths of each module.

[0138] This embodiment provides a classification method for static time series analysis reports. Figure 3 This is another flowchart illustrating a classification method for static time-series analysis reports according to an embodiment of the present invention, such as... Figure 3 As shown, the process includes the following steps:

[0139] Step S301: Determine the type of static timing analysis report for the target timing path. For details, please refer to [link to relevant documentation]. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0140] Step S302: If the static timing analysis report is of the setup time type, divide the data path of the target timing path into intra-module paths and cross-module paths. For details, please refer to [link to relevant documentation]. Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0141] Step S303: Violations existing in the paths within a module are assigned to the corresponding modules, resulting in the first violation assignment result. For details, please refer to [link to relevant documentation]. Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0142] Step S304: Identify the multiple target modules corresponding to the cross-module path with the violation. For details, please refer to [link to relevant documentation]. Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0143] Step S305: Calculate the violation value contribution of each target module based on its logic level, delay, the ratio of delay to logic level, and whether it has anomalies. For details, please refer to [link to relevant documentation]. Figure 2 Steps S205 to S207 of the illustrated embodiment will not be described again here.

[0144] Step S306: Based on the contribution of each target module's violation value, violations existing in cross-module paths are assigned to the corresponding target modules to obtain the second violation assignment result. For details, please refer to [link to relevant documentation]. Figure 1 Step S106 of the illustrated embodiment will not be described again here.

[0145] Step S307: Based on the first violation classification result and the second violation classification result, determine the violations belonging to the target timing paths of each module.

[0146] If the static time series analysis report is of the hold-time type, then proceed with steps S308-S309.

[0147] In one alternative embodiment, the hold time type includes hold time violation, remove time violation, and minimum delay violation.

[0148] Step S308: Determine the logical level at which the end point of the data path of the target timing path is located.

[0149] In one optional embodiment, the most common engineering approach to fix hold-time type violations is to add a delay before the end point. Therefore, in this invention, the module to which the hold-time violation belongs is the module corresponding to the logical level where the end point is located.

[0150] Step S309: Determine the violations of the target timing path belonging to each module based on the logical level of the end point of the data path of the target timing path.

[0151] In one optional embodiment, based on the logical level of the end point of the data path of the target time-series path, the repair of violations based on the time type is usually performed in the module corresponding to the logical level of the end point. This classification method reduces the complexity of attribution judgment while ensuring classification accuracy.

[0152] If the static timing analysis report is a design rule or other type, then proceed with steps S310-S311.

[0153] In one alternative embodiment, the design rule type and other types include violations of checks for maximum clock signal transition time, maximum data signal transition time, maximum clock load capacitance, maximum data load capacitance, crosstalk, minimum period, dual switching, and minimum waveform width.

[0154] Step S310: Determine the specific violation entries for design rules and other types of violations.

[0155] Step S311: Based on the logical hierarchy of the specific violation entries in the design rules and other types of violations, determine the specific entries of the violations belonging to each module.

[0156] In an optional embodiment, the specific violation entries of design rule type violations include clock signal conversion maximum time violation, data signal conversion maximum time violation, clock maximum load capacitance violation, data maximum load capacitance violation, crosstalk violation, minimum period violation, double switching violation, and minimum waveform width violation. The specific violation entries of design rules and other types of violations are specifically manifested as violations generated by a certain level standard unit, a certain interconnect, or a certain pin of a certain module. For example, the clock maximum load capacitance violation may be manifested as an excessive load capacitance of a certain pin of standard unit a1 of module a. Therefore, the module to which the clock maximum load capacitance violation of the pin of standard unit a1 belongs is module a. Since design rules and other types of violations are ultimately manifested as specific single-point violations, the module to which this type of violation entry belongs is the module corresponding to the logic level where the violation entry is located. Through single-point violation location, the module to which the violation belongs can be quickly found, thereby enabling module designers to more quickly and clearly obtain the relevant design rule and other types of violation entries in their respective modules.

[0157] Step S312: Based on the static timing analysis reports in the full-scale static timing analysis, determine the violations belonging to the target timing path or specific entry of each module.

[0158] In one optional embodiment, the chip typically employs multiple operating modes, exemplarily including functional mode, test mode, high-voltage mode, and low-voltage mode. Simultaneously, the chip is also subject to various fluctuations, exemplarily including chip manufacturing process fluctuations, voltage fluctuations, temperature fluctuations, and changes in chip parasitic parameters caused by manufacturing process fluctuations. To address these complex scenarios, the industry typically employs combinations of different operating modes, extreme processes, voltages, temperatures, and extreme parasitic parameter conditions, combined with different inspection types, to create different analysis scenarios. This reflects the specific timing analysis scenario the report focuses on. A static timing analysis report is generated for each specific timing analysis scenario; therefore, a fully flattened static timing analysis includes multiple types of static timing analysis reports across various analysis scenarios.

[0159] Step S313: Based on the module to which the violation belongs after classification, divide the report content of each violation path or specific violation item in each static time series analysis report in the fully unfolded static time series analysis into the corresponding module, and generate the module analysis report for each module.

[0160] Step S314: Integrate the module analysis reports from all analysis scenarios of each module to generate a global summary report.

[0161] In one optional embodiment, by dividing the static time series analysis report into module analysis reports for each module, and further generating a global summary report, the report content becomes clearer and more organized, improving the readability of the report. The separate module analysis reports help to quickly locate the problem.

[0162] This embodiment provides a classification method for static time series analysis reports. Figure 4 This is a flowchart illustrating another classification method for static time series analysis reports according to an embodiment of the present invention, such as... Figure 4 As shown, the process includes the following steps:

[0163] Step S401: Determine the type of static timing analysis report for the target timing path. See details below. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0164] Step S402: If the static timing analysis report is of the setup time type, divide the data path of the target timing path into intra-module paths and cross-module paths. For details, please refer to [link to relevant documentation]. Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0165] Step S403: Violations existing in the paths within a module are assigned to the corresponding modules, resulting in the first violation assignment result. For details, please refer to [link to relevant documentation]. Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0166] Step S404: Identify the multiple target modules corresponding to the cross-module path with the violation. For details, please refer to [link to relevant documentation]. Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0167] Step S405: Calculate the violation value contribution of each target module based on its logic level, delay, the ratio of delay to logic level, and whether it has anomalies. For details, please refer to [link to relevant documentation]. Figure 2 Steps S205 to S207 of the illustrated embodiment will not be described again here.

[0168] Step S406: Based on the contribution of each target module's violation value, violations existing in cross-module paths are assigned to the corresponding target modules to obtain the second violation assignment result. For details, please refer to [link to relevant documentation]. Figure 1 Step S106 of the illustrated embodiment will not be described again here.

[0169] Step S407: Based on the first violation classification result and the second violation classification result, determine the violations belonging to the target timing paths of each module.

[0170] Step S408: Based on the static timing analysis reports in the full-scale static timing analysis, determine the violations belonging to the target timing paths of each module.

[0171] Step S409: Based on the module to which the violation belongs after classification, divide each static time series analysis report in the full-scale static time series analysis into the corresponding module and generate the module analysis report for each module.

[0172] Specifically, step S409 includes:

[0173] Step S4091: If the static timing analysis report is a timing inspection report, determine the primary category type of the static timing analysis report based on the inspection type of the scenario in the static timing analysis report.

[0174] In one optional embodiment, the timing check report in the static timing analysis report is a check report for setup time violations, hold time violations, recovery time violations, removal time violations, maximum delay violations, minimum delay violations, and data check violations. The static timing analysis report has two check types: setup time type and check time type.

[0175] In one optional embodiment, the primary category type is determined based on the inspection type of the scenario in the static time series analysis report. Specifically, it is either a MAX or MIN type, which corresponds to two types: setup time inspection and hold time inspection, respectively, reflecting the guiding classification of the time series inspection report.

[0176] Step S4092: Based on the physical type of the starting and ending points of the data path of the target timing path, determine the secondary subclass type of the static timing analysis report. The secondary subclass includes input port to register, register to register, register to output port, and input port to output port.

[0177] In one optional embodiment, the report is further subdivided into two subcategories based on the physical type of the start and end points of the data path of the target time-series path. Each subcategory represents a different type of data flow path.

[0178] In an optional embodiment, if the physical type of the starting point of the data path of the target timing path in the first-level major category is an input port and the physical type of the ending point is a register, then the static timing analysis report of the target timing path is divided into input port to register. If the physical type of the starting point of the data path of the target timing path in the first-level major category is a register and the physical type of the ending point is also a register, then the static timing analysis report of the target timing path is divided into register to register. If the physical type of the starting point of the data path of the target timing path in the first-level major category is a register and the physical type of the ending point is an output port, then the static timing analysis report of the target timing path is divided into register to output port. If the physical type of the starting point of the data path of the target timing path in the first-level major category is an input port and the physical type of the ending point is an output port, then the static timing analysis report of the target timing path is divided into input port to output port. The input port is used to receive input signals from outside the module. The register is a standard unit triggered by a clock that has data latching and transmission functions. The output port is used by the module to output signals to the outside.

[0179] In one optional embodiment, the report is further subdivided into two subcategories based on the physical type of the start and end points of the data path of the target time-series path. The two subcategories represent different types of data flow paths. In the hierarchical module design, further classification of different types of time-series paths of concern to module designers helps module designers to perform decoupling analysis on the distribution performance of different types of time-series paths.

[0180] Step S4093: Based on the module to which the violation of the target timing path belongs, divide the static timing analysis report of the target timing path into the corresponding third-level subclass of the module, establish the correspondence between the static timing analysis report and the module, and each module corresponds to a third-level subclass.

[0181] In one optional embodiment, based on the module to which the violation of the target timing path belongs, the static timing analysis report of the target timing path is divided into the three-level subcategories corresponding to the module, thus establishing a correspondence between the report and the module, so that each module can obtain a detailed timing analysis report related to it.

[0182] Step S4094: If the second-level subclass of the static timing analysis report of the target timing path is register to register, then determine the fourth-level subclass of the static timing analysis report of the target timing path in the module corresponding to the third-level subclass based on whether the reference names of the modules to which the start and end points of the data path of the target timing path belong are the same.

[0183] If the reference names of the modules to which the start and end points of the data path of the target timing path belong are the same, then the static timing report will be divided into a fourth-level subclass with the name "internal".

[0184] If the reference names of the modules to which the start and end points of the data path of the target timing path belong are different, then the static timing report will be classified into a fourth-level subclass named "Interface".

[0185] In one optional embodiment, if the reference names of the starting and ending points of the data path of the target timing path from register to register are the same (i.e., they belong to the same module), then the static timing report of the target timing path is classified into the fourth-level subclass named "Internal". This type of path usually indicates that the signal is transmitted between registers within the same module and does not involve the interface between modules. In some cases, the reference names of the modules to which the starting and ending points of the target timing path belong are the same, but the reference names of the modules to which some passing points belong are different. To simplify the classification, this situation is also classified into the fourth-level subclass named "Internal". If the reference names of the modules to which the starting and ending points of the data path of the target timing path belong are different (i.e., they belong to different modules), then the static timing report is classified into the fourth-level subclass named "Interface". This type of path indicates that the signal has a transmission interface between different modules.

[0186] In one optional embodiment, register-to-register data paths, which are secondary subcategories, are further classified after the tertiary classification because register-to-register data paths are the part that designers of each module are most concerned about in hierarchical module design, and their performance best reflects the quality of each module design.

[0187] In an optional embodiment, for a target timing path that is a register-to-register subclass at the second level, the fourth level subclass of the static timing analysis report in the corresponding module is further determined based on whether the reference names of the modules to which the start and end points of the target timing path belong are the same. This subdivision helps to obtain more detailed reports of register-to-register within each module and across different modules more quickly and comprehensively, as well as to more accurately identify and analyze the inter-module connections of the target timing path.

[0188] In an optional embodiment, directories with corresponding names are set for the above four-level categories. The collection of static timing analysis reports that satisfy the target timing paths of each terminal sub-category is written into different reports. The report names are composed of IN, OUT, and the reference names of the modules corresponding to the logical levels of the start and end points, separated by four underscores, according to the type of the start and end points. At the same time, a module summary report is generated, which is located in the same position as the third-level directory.

[0189] In an alternative embodiment, such as Figure 5 As shown, Figure 5This is a schematic diagram of the timing inspection report directory structure according to an embodiment of the present invention. MAX / or MIN / respectively represent the inspection type for setup time or hold time in a certain scenario; IN2REG / represents the second-level subclass name from input port to register, REG2REG / represents the second-level subclass name from register to register, REG2OUT represents the second-level subclass name from register to output port, and IN2OUT / represents the second-level subclass name from input port to output port; TOP_ONLY / represents the top-level module, BLOCK_1 / to BLOCK_N / represent modules 1 to N, where BLOCK_1 represents module 1 and BLOCK_N represents module N, and N is a variable representing any number of modules; IN____OUT.rpt represents the report text printed and output by printing the set of static timing reports for all target timing paths from input ports to output ports belonging to a certain module, and IN____BLOCK_k.rpt represents all input ports belonging to a certain module. The `BLOCK_m____OUT.rpt` represents the set of static timing reports printed and output for the target timing paths from the starting point of the module named `BLOCK_m` at the logical level to the output port. `BLOCK_m____BLOCK_n.rpt` represents the set of static timing analysis reports printed and output for the target timing paths from the starting point of the module named `BLOCK_m` at the logical level to the output port at the logical level. `IN2OUT.sum` represents the summary report for all modules belonging to the `IN2OUT` subclass, `IN2REG.sum` represents the summary report for all modules belonging to the `IN2REG` subclass, and `REG2OUT.sum` represents the summary report for all modules belonging to the `IN2REG` subclass. 'm' represents the summary report of all modules belonging to the REG2OUT subclass, and REG2REG.sum represents the summary report of all modules belonging to the REG2REG subclass. Level 1, 2, 3, and 4 represent different directory structure levels. For example, MAX / IN2OUT / TOP_ONLY / IN____OUT.rpt represents the static time series report collection printed and output in a certain analysis scenario, belonging to the establishment time type check, with the data path starting at the input port and ending at the output port, and the violation belonging to the top-level module. MIN / REG2REG / TOP_ONLY / INTERNAL / TOP_ONLY____TOP_ONLY.`rpt` represents a collection of static timing analysis reports printed and output for all target timing paths in a specific analysis scenario, belonging to a hold-time type check, with both the data path starting and ending in a register, belonging to the top-level module, and sharing the same reference name (both modules being the top-level module).

[0190] In an alternative embodiment, such as Figure 6 As shown, Figure 6 yes Figure 5 The schematic diagram of the module summary report of the timing check report mentioned in the embodiment of the present invention is shown. In this diagram, WNS represents the worst-case negative margin, TNS represents the total negative margin, FEP represents the total number of violation termination points, and the step values ​​of the WNS distribution are only for illustration and need to be dynamically adjusted according to the timing status. The Overall row is always located at the first line of the content section and serves as a summary of the following rows. The value of the WNS column in the Overall row is the minimum value of the values ​​below that column, and the values ​​of the other value columns in the Overall row are the sum of the values ​​below that column.

[0191] Step S410: Integrate the module analysis reports from all analysis scenarios of each module to generate a global summary report.

[0192] This embodiment provides a classification method for static time series analysis reports. Figure 7 This is a flowchart illustrating an additional classification method for static time-series analysis reports according to an embodiment of the present invention, such as... Figure 7 As shown, the process includes the following steps:

[0193] Step S701: Determine the type of static timing analysis report for the target timing path. See details below. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0194] Step S702: If the static timing analysis report is of the setup time type, divide the data path of the target timing path into intra-module paths and cross-module paths. For details, please refer to [link to relevant documentation]. Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0195] Step S703: Violations existing in the paths within a module are assigned to the corresponding modules, resulting in the first violation assignment result. For details, please refer to [link to relevant documentation]. Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0196] Step S704: Identify the multiple target modules corresponding to the cross-module path with the violation. For details, please refer to [link to relevant documentation]. Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0197] Step S705: Calculate the violation value contribution of each target module based on its logic level, delay, the ratio of delay to logic level, and whether it has anomalies. For details, please refer to [link to relevant documentation]. Figure 2 Steps S205 to S207 of the illustrated embodiment will not be described again here.

[0198] Step S707: Based on the contribution of violation values ​​of each target module, violations existing in cross-module paths are assigned to the corresponding target modules to obtain the second violation assignment result. For details, please refer to [link to relevant documentation]. Figure 1 Step S107 of the illustrated embodiment will not be described again here.

[0199] Step S707: Based on the first violation classification result and the second violation classification result, determine the violations belonging to the target timing paths of each module.

[0200] Step S708: Based on the static timing analysis reports in the full-scale static timing analysis, determine the violations belonging to the target timing paths of each module.

[0201] Step S709: Based on the module to which the violation belongs after classification, divide each static time series analysis report in the full-scale static time series analysis into the corresponding module and generate the module analysis report for each module.

[0202] Specifically, step S709 includes:

[0203] Step S7091: If the static timing analysis report is a design rule check or other type of check report, create a setting name directory and use the setting name directory as the first-level category of the static timing analysis report.

[0204] In one optional embodiment, for example, a first-level directory named drv is created as the classification basis for the first-level category, and a directory with a set name is created as the first-level category for static time series analysis reports. Different design rule checks and other types of check reports are uniformly classified into the corresponding directories for easy management and retrieval.

[0205] Step S7092: Based on the module corresponding to the logical level of the specific violation item in the static timing analysis report, divide the static timing analysis report into the second-level subclass of the module, establish the correspondence between the static timing analysis report and the module, and each module corresponds to a second-level subclass.

[0206] In one optional embodiment, for example, a second-level subdirectory named TOP_ONLY and each block reference name is created, where TOP_ONLY represents the top-level module and block represents the module. If the module corresponding to the logical level of a specific violation entry in the static timing analysis report is the top-level module, then the report of that specific violation entry in the static timing analysis report is assigned to the second-level subdirectory named TOP_ONLY. If the module corresponding to the logical level of a specific violation entry in the static timing analysis report is not the top-level module, for example, if the module corresponding to the logical level of a specific violation entry in the static timing analysis report is module 1, then the report of that specific violation entry in the static timing analysis report is assigned to the second-level subdirectory named BLOCK_1.

[0207] In one optional embodiment, the report is divided into secondary subcategories of modules according to the logical level of the specific violation item in the static time series analysis report. This establishes a correspondence between the report and the module, enabling each module to obtain a detailed inspection report related to it. This also helps to quickly locate the module where the problem is located and improves the efficiency of problem solving.

[0208] Step S7093: Based on the violation types contained in the static timing analysis report, determine the third-level subclass of the static timing analysis report in the corresponding module.

[0209] In one optional embodiment, for example, static timing reports are categorized into three subcategories named clk_tran, data_tran, clk_cap, data_cap, noise, min_period, double_switch, and min_pulse_width based on the type of violation. clk_tran represents the maximum transition time violation of the clock signal, data_tran represents the maximum transition time violation of the data signal, clk_cap represents the maximum load capacitance violation of the clock signal, data_cap represents the maximum load capacitance violation of the data signal, noise represents crosstalk violation, min_period represents the minimum period violation, double_switch represents the double switching violation, and min_pulse_width represents the minimum waveform width violation.

[0210] In one optional embodiment, reports for all entries categorized into third-level subcategories are printed and output to files corresponding to the third-level subcategory names. For design rule checks and other types of check reports, a module summary report is generated. This report is located alongside the second-level directory, such as... Figure 8 As shown, Figure 8 This is a schematic diagram of the directory structure of the design rule check and other types of check reports in the embodiments of the present invention, as shown below. Figure 9 As shown, Figure 9 This is a schematic diagram of the module summary report of the design rule check and other types of check reports in the embodiments of the present invention.

[0211] In one optional embodiment, based on the violation types contained in the static time series analysis report, the report is further classified into three subcategories in the corresponding module. By subdividing the report into three subcategories, problems can be identified and analyzed more accurately.

[0212] Step S710: Integrate the module analysis reports from all analysis scenarios of each module to generate a global summary report.

[0213] In one optional embodiment, module analysis reports from all analysis scenarios of each module are integrated to generate a global summary report, where scenario represents the analysis scenario, such as... Figure 10 As shown, Figure 10 This is a schematic diagram of the content of the global summary report in an embodiment of the present invention. The global summary report contains information on all modules. To allow designers of each module to focus on the parts they are more concerned with, the present invention can also split the report, such as... Figure 11 As shown, Figure 11 This is a schematic diagram illustrating the content of the global summary report for overall planning in an embodiment of the present invention, as shown below. Figure 12 As shown, Figure 12 This is a schematic diagram of the content of the global summary report of the top-level module in an embodiment of the present invention, as shown below. Figure 13 As shown, Figure 13 This is a schematic diagram of the content of a global summary report of one of the modules in an embodiment of the present invention.

[0214] Figure 14 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 14 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 14 Take a processor 10 as an example.

[0215] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0216] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0217] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0218] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0219] The computer device also includes an input device 30 and an output device 40. The processor 10, memory 20, input device 30, and output device 40 can be connected via a bus or other means. Figure 5 Taking the example of a connection between China and Israel via a bus.

[0220] Input device 30 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the computer device, such as a touchscreen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 40 may include display devices, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibration motors). The aforementioned display devices include, but are not limited to, liquid crystal displays, light-emitting diodes, displays, and plasma displays. In some alternative embodiments, the display device may be a touchscreen.

[0221] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0222] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method of classifying reports for static timing analysis, the method comprising: The method comprises: determining the type of a static timing analysis report of a target timing path; if the static timing analysis report is of a setup time type, dividing a data path of the target timing path into an intra-module path and a cross-module path; dividing violations existing in the intra-module path to corresponding modules to obtain a first violation division result; determining a plurality of target modules corresponding to the cross-module path in which violations exist; calculating a violation value contribution degree of each of the target modules according to the number of logic stages, the delay, the ratio of the delay to the number of logic stages, and whether the target module has an abnormal point; dividing violations existing in the cross-module path to corresponding target modules according to the violation value contribution degrees of the target modules to obtain a second violation division result; determining violations of the target timing path attributed to each module according to the first violation division result and the second violation division result.

2. The method of claim 1, wherein, The calculation of the violation value contribution degree of each of the target modules according to the number of logic stages, the delay, the ratio of the delay to the number of logic stages, and whether the target module has an abnormal point comprises: calculating a base score of the violation value contribution degree of each of the target modules according to the number of logic stages, the delay, and the ratio of the delay to the number of logic stages; if the target module does not have an abnormal point, determining the base score as the violation value contribution degree of the target module; if the target module has an abnormal point, calculating an additional score of the violation value contribution degree according to the standard cell delay of the abnormal point and the standard cell delay on the data path of the target timing path, and determining the sum of the base score and the additional score as the violation value contribution degree of the target module.

3. The method of claim 2, wherein, The calculation of the base score of the violation value contribution degree of each of the target modules according to the number of logic stages, the delay, and the ratio of the delay to the number of logic stages comprises: determining a weight vector corresponding to the number of stages of the data path of the target timing path, the weight vector containing weight values corresponding to the number of logic stages, the delay, and the ratio of the delay to the number of logic stages respectively, different weight vectors corresponding to different numbers of stages; performing a normalized weighted average calculation on the number of logic stages, the delay, and the ratio of the delay to the number of logic stages of a standard cell at a logic level of the data path of the target timing path in each of the target modules according to the weight vector to obtain the base score of the violation value contribution degree of each of the target modules.

4. The method of claim 2, wherein, comprising: if the number of standard cell stages of the data path of the target timing path is less than a preset value, determining that there is no abnormal point in the data path of the target timing path; if the number of standard cell stages of the data path of the target timing path is greater than or equal to a preset value, calculating the average value and the standard deviation of the delays of all standard cells in the data path of the target timing path; determining whether the delay of each standard cell satisfies a set condition according to the delay of each standard cell, the average value, and the standard deviation; if the delay of a standard cell satisfies the set condition, determining that the standard cell is an abnormal point; determining a module containing the abnormal point as a module in which an abnormal point exists.

5. The method of claim 1, wherein, If the static timing analysis report is a hold time type, the method comprises: determining the logic level where the end point of the data path of the target timing path is located; determining the violation of the target timing path attributed to each module according to the logic level where the end point of the data path of the target timing path is located.

6. The method of claim 1, wherein, If the static timing analysis report is a design rule and other type, the method comprises: determining the specific violation item of the design rule and other type violation; determining the violation of the specific item attributed to each module according to the logic level where the specific violation item of the design rule and other type violation is located.

7. The method of claim 1, wherein, The method further comprises: determining the violation of the timing path or the specific item attributed to each module according to each static timing analysis report in the full flattening static timing analysis; dividing the report content of each violation path or specific violation item in each static timing analysis report in the full flattening static timing analysis into the corresponding module according to the module to which the violation is attributed after classification, generating a module analysis report of each module; integrating the module analysis reports of all analysis scenarios of the modules to produce a global summary report.

8. The method of claim 7, wherein, The method further comprises: If the static timing analysis report is a timing check report, determining the primary large category type of the static timing analysis report according to the check type of the scenario of the static timing analysis report; determining the secondary small category type of the static timing analysis report according to the physical type of the start point and the end point of the data path of the target timing path, the secondary small category comprising input port to register, register to register, register to output port and input port to output port; dividing the static timing analysis report of the target timing path into the corresponding tertiary small category of the module to which the target timing path belongs according to the module to which the violation of the target timing path belongs, establishing the corresponding relationship between the static timing analysis report and the module, each module corresponding to one tertiary small category; If the secondary small category of the static timing analysis report of the target timing path is register to register, determining the further quaternary small category of the static timing analysis report of the target timing path in the corresponding tertiary small category module according to whether the reference names of the modules to which the start point and the end point of the data path of the target timing path belong are the same.

9. The method of claim 8, wherein, The method further comprises: If the static timing analysis report is a design rule check and other type check report, creating a setting name directory, taking the setting name directory as the primary large category of the static timing analysis report; According to a logic level corresponding to a module where a specific violation item in the static timing analysis report is located, the static timing analysis report is classified into a secondary subclass of the module, a corresponding relationship between the static timing analysis report and the module is established, and each module corresponds to a secondary subclass; According to a violation type contained in the static timing analysis report, a tertiary subclass of the static timing analysis report in the corresponding module is determined.

10. A computer device, comprising: Comprise: A memory and a processor, which are communicatively connected with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the method in any one of claims 1 to 9.

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