Bus-controllable video parallel processing method, device and server
Through the bus-controllable video parallel processing method, the memory and processor burden problems of traditional video processing technology in ultra-high-resolution video are solved, and efficient video processing effects are achieved.
Patent Information
- Application Number
- CN202510935000.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-08
- Publication Date
- 2025-10-17
AI Technical Summary
When processing ultra-high-resolution videos, traditional video processing technology suffers from insufficient computing power, high latency, high power consumption, high memory consumption, and heavy processor burden, resulting in decreased frame rate and loss of image quality.
A bus-controlled video parallel processing method is adopted. After collecting video data, the target segmentation line parameters are determined based on the storage data bit width and resolution information of the storage device, and image segmentation and mirror edge filling processing are performed. The video data is stored in the left and right memories, and 3D image processing is performed. Finally, it is spliced into a video stream for display.
While ensuring video quality, it significantly reduces the memory overhead and processor burden of video processing, and improves video processing efficiency.
Smart Images
Figure CN120807796A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of image processing, and in particular to a bus-controllable video parallel processing method and device and server. BACKGROUND
[0002] With the popularization of 4k / 8k ultra-high resolution video, the traditional video processing technology has problems such as insufficient computing power, high delay, and high power consumption when processing ultra-high resolution video. At present, the related technology proposes that directly processing high-resolution video will cause the GPU / CPU load to be too high, and the edge computing device can be used to process the ultra-high resolution video in real time, but real-time processing is prone to frame rate reduction or loss of image quality, and the edge computing device has high memory consumption of the row buffer and heavy burden of the processor when processing the ultra-high resolution video in real time, and it is also difficult to guarantee the frame rate and image quality of the video. SUMMARY
[0003] Therefore, the purpose of the present application is to provide a bus-controllable video parallel processing method, device and server, which can significantly reduce the memory consumption and processor burden when processing video while guaranteeing the video quality.
[0004] In a first aspect, an embodiment of the present application provides a bus-controllable video parallel processing method, which comprises: collecting video data to be processed, and determining target split line parameters based on the storage data bit width of a storage device and the resolution information of the video data to be processed, wherein the target split line parameters include: an overlapping center line, a right starting split line, a left starting split line, an effective data end line and a data supplement split line; performing image segmentation processing and mirror edge supplement processing on each frame of input image in the video data to be processed according to the target split line parameters, determining the target left split image and the target right split image after segmentation, and storing the target left split image and the target right split image into left memory and right memory respectively; performing 3D image processing on the stored target left split image and target right split image, and extracting and splicing the target left split image and the target right split image into a video stream for display when the 3D image processing is completed.
[0005] In an embodiment, the step of determining the target split line parameters based on the storage data bit width of the storage device and the resolution information of the video data to be processed comprises: performing storage analysis processing on the storage data bit width and the resolution information of the video data to be processed by a preset de-fogging algorithm to determine the minimum score of storage; determining the overlapping center line, the right starting split line, the left starting split line and the effective data end line according to the minimum score of storage and a preset split line ratio, and determining the data supplement split line according to the difference of the images split by the right starting split line and the left starting split line.
[0006] In one embodiment, according to the target segmentation line parameters, image segmentation processing and mirror edge filling processing are performed on each frame input image in the processed video data to determine the target left segmentation image and the target right segmentation image after segmentation, including: determining the image on the left side of the left starting segmentation line in the input image as the target left segmentation image, and determining the image on the right side of the right starting segmentation line as the first right segmentation image; according to the target left segmentation image and the complementary data segmentation line, mirror edge filling processing is performed on the first right segmentation image to determine the target right segmentation image.
[0007] In one embodiment, the first right segmented image is mirror-padded based on the target left segmented image and the complementary data segmentation line to determine the target right segmented image, including: determining the image width between the valid data end line and the complementary data segmentation line as the complementary image width; intercepting a left symmetric image of the complementary image width at the left boundary of the target left segmented image, and determining a right symmetric image that is a mirror image complementary to the left symmetric image; combining the right symmetric image and the first right segmented image to determine the target right segmented image, so that the image sizes of the target left segmented image and the target right segmented image are the same.
[0008] In one embodiment, after the step of determining the target left segmented image and the target right segmented image after segmentation, it includes: performing Bayer domain processing and luminance and chrominance domain processing on the target left segmented image and the target right segmented image in sequence to quickly reduce noise and filter the segmented low-resolution data, and convert the image into a video format.
[0009] In one embodiment, the step of storing the target left segmented image and the target right segmented image in the left memory and the right memory, respectively, includes: performing image cropping processing on the target left segmented image and the target right segmented image, determining the image portion to the left of the overlapping center line in the target left segmented image as the current left memory image, and storing it in the left memory; determining the image portion before the overlapping center line and the valid data end line in the target right segmented image as the current right memory image, and storing it in the right memory.
[0010] In one embodiment, the step of performing 3D image processing on the stored target left segmentation image and the target right segmentation image includes: combining the image between the overlapping center line and the left starting segmentation line in the current right memory image with the current left memory image to determine it as the previous frame left memory image; combining the image between the overlapping center line and the right starting segmentation line in the current left memory image with the current right memory image and the right symmetrical image to determine it as the previous frame right memory image; and combining the current left memory image, the current right memory image, the previous frame left memory image, and the previous frame right memory image to perform 3D image processing to eliminate the difference in the transition area between the left and right images after 3D processing.
[0011] In a second aspect, the embodiment of the present application further provides a bus-controllable video parallel processing device, which comprises: a parameter setting module, configured to collect video data to be processed, and determine target split line parameters based on a storage data bit width of a storage device and resolution information of the video data to be processed, wherein the target split line parameters comprise: an overlapping center line, a right start split line, a left start split line, an effective data end line and a supplementary data split line; an image splitting module, configured to perform image splitting processing and mirror edge supplementing processing on each frame of input image in the video data to be processed according to the target split line parameters, determine a target left split image and a target right split image after splitting, and store the target left split image and the target right split image into a left memory and a right memory respectively; and an image processing module, configured to perform 3D image processing on the target left split image and the target right split image after storage, and extract and splice the target left split image and the target right split image into a video stream for display when the 3D image processing is completed.
[0012] In a third aspect, the embodiment of the present application further provides an electronic device, comprising a processor and a memory, wherein the memory stores computer executable instructions capable of being executed by the processor, and the processor executes the computer executable instructions to implement the method of any one of the first aspect.
[0013] In a fourth aspect, the embodiment of the present application further provides a computer readable storage medium, wherein the computer readable storage medium stores computer executable instructions, and the computer executable instructions, when invoked and executed by a processor, cause the processor to implement the method of any one of the first aspect.
[0014] The embodiment of the present application brings the following beneficial effects:
[0015] The bus-controllable video parallel processing method, device and server provided by the embodiment of the present application, after collecting video data to be processed, determine target split line parameters based on a storage data bit width of a storage device and resolution information of the video data to be processed, then perform image splitting processing and mirror edge supplementing processing on each frame of input image in the video data to be processed according to the target split line parameters, determine a target left split image and a target right split image after splitting, and store the target left split image and the target right split image into a left memory and a right memory respectively, finally perform 3D image processing on the target left split image and the target right split image after storage, and extract and splice the target left split image and the target right split image into a video stream for display when the 3D image processing is completed, which can significantly reduce memory consumption and processor burden during video processing while ensuring video quality.
[0016] Other features and advantages of the present application will be set forth in the descriptions that follow, and in part will be apparent from the description, or can be learned by practice of the application. The purposes and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
[0017] To make the above objectives, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are specifically described below, and the accompanying drawings are referred to for illustration. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.
[0019] Figure 1 A structural schematic diagram of a bus-controllable video parallel processing system provided by an embodiment of the present application is shown in the following figure.
[0020] Figure 2 A flowchart of a bus-controllable video parallel processing method provided by an embodiment of the present application is shown in the following figure.
[0021] Figure 3 A flowchart of a data processing method provided by an embodiment of the present application is shown in the following figure.
[0022] Figure 4 A schematic diagram of an input video data cutting method provided by an embodiment of the present application is shown in the following figure.
[0023] Figure 5 A schematic diagram of a mirror image edge filling method provided by an embodiment of the present application is shown in the following figure.
[0024] Figure 6 A schematic diagram of another mirror image edge filling method provided by an embodiment of the present application is shown in the following figure.
[0025] Figure 7 A schematic diagram of a front and back field signal cutting method provided by an embodiment of the present application is shown in the following figure.
[0026] Figure 8 A schematic diagram of 3D processing data storage provided by an embodiment of the present application is shown in the following figure.
[0027] Figure 9 A structural schematic diagram of 3D processing data retrieval provided by an embodiment of the present application is shown in the following figure.
[0028] Figure 10 A schematic diagram of data retrieval display provided by an embodiment of the present application is shown in the following figure.
[0029] Figure 11 A schematic structural diagram of a bus-controllable video parallel processing device provided by an embodiment of the present invention;
[0030] Figure 12 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.
[0032] At present, with the popularization of 4k / 8k ultra-high-resolution videos, traditional video processing technologies will encounter problems such as insufficient computing power, high latency, and high power consumption when processing ultra-high-resolution videos. Relevant technologies have proposed that directly processing high-resolution videos will lead to excessive GPU / CPU load. Ultra-high-resolution videos can be processed in real time through edge computing devices, but real-time processing is prone to frame rate drop or image quality loss. In addition, when edge computing devices process ultra-high-resolution videos in real time, the memory consumption of the row cache is high, the burden on the processor is heavy, and it is difficult to ensure the frame rate and image quality of the video. Based on this, the bus-controllable video parallel processing method, device and server provided by the present invention can significantly reduce the memory overhead and processor burden during video processing while ensuring video quality.
[0033] To facilitate understanding of this embodiment, a bus-controlled video parallel processing method disclosed in an embodiment of the present invention is first described in detail. The method is applied to a bus-controlled video parallel processing system. To facilitate understanding of the bus-controlled video parallel processing system, an embodiment of the present invention provides a structural diagram of a bus-controlled video parallel processing system, as shown in FIG. Figure 1 As shown, the video collection module collects the real-time video input from the outside and stores it into the memory, and then uses the APB bus configuration parameters to control the video processing, thereby taking out the segmented low-resolution video data in real time.
[0034] based on Figure 1 The bus-controlled video parallel processing system is shown in FIG. , and the bus-controlled video parallel processing method is described in detail in the embodiment of the present invention. Figure 2 The flowchart of a bus-controllable video parallel processing method shown in FIG. 1 mainly includes the following steps S202 to S206:
[0035] In step S202, the video data to be processed is collected, and based on the storage data bit width of the storage device and the resolution information of the video data to be processed, the target split line parameters are determined, wherein the target split line parameters include: the overlapping center line, the right starting split line, the left starting split line, the effective data end line, and the supplementary data split line. The video data to be processed is Bayer data, which uses a red, green, and blue (RGB) filter array to sample each pixel. Since each pixel point can only sense one color, the initial information obtained by the CCD is Bayer data with only one channel per pixel. Color images are obtained through interpolation, so the Bayer data needs to be converted to YC data format for video display. YC data refers to luminance data Y and chrominance data C.
[0036] In an embodiment, the storage data bit width and the resolution information of the video data to be processed can be analyzed and processed by a preset dehazing algorithm to determine the minimum score stored, and then the overlapping center line, the right starting split line, the left starting split line, and the effective data end line are determined according to the stored minimum score and the preset split line ratio. The supplementary data split line is determined according to the difference between the images split by the right starting split line and the left starting split line. In actual application, the parameter configuration is based on the memory data bit width. The bayer data here uses 10-bit data, and the memory data bit width is 64 bits, so 6 bayer data can be stored at a time. The bit width of the yc data is 8 bits, so 8 data can be stored in memory at a time. The ltm and dehazing in isp video processing follow the data block size of 52 alignment, so 4224 / 52 is 84. In addition, the best split ratio corresponding to each resolution is stored in the database. The effect of the processed image is best under the best split ratio. For example, the split line ratio is 10:13:16 under the resolution of 4224*3144. Therefore, three split lines of 1680, 2688, and 2184 are obtained. Then, the size of the left and right data is ensured to be the same, so 144*3144 data will be supplemented on the right side. If the supplemented data is directly copied to the edge, a large fault will occur near the original data 4224. Therefore, mirror edge supplementation is adopted, and the data on the left side of the original data is copied as a reference for filtering.
[0037] Step S204, based on the target segmentation line parameters, image segmentation processing and mirror edge filling processing are performed on each frame input image in the to-be-processed video data, and a target left segmented image and a target right segmented image after segmentation are determined. The target left segmented image and the target right segmented image are stored in the left memory and the right memory, respectively. In one embodiment, the line field and data can be received by a video collection device, and the collected Bayer data can be stored in the memory to generate a new line field. The Bayer data is retrieved from the memory, and various noise reduction and filtering processes are performed on the retrieved Bayer data before being stored in the memory for YC3D processing.
[0038] Step S206, performing 3D image processing on the stored target left segmented image and the target right segmented image, and when the 3D image processing is completed, extracting the target left segmented image and the target right segmented image and splicing them into a video stream for display. In one embodiment, the data after the YC3D processing (i.e., the 3D image processing) is stored in the memory and needs to be re-stitched into the original image for VO display.
[0039] The bus-controllable video parallel processing method provided by the embodiment of the present invention can significantly reduce the memory overhead and processor burden during video processing while ensuring video quality.
[0040] See also Figure 3 The embodiment of the present invention further provides an implementation method for video processing, for details, see (1) to (5) below:
[0041] (1) See Figure 4 The schematic diagram of a method for cutting input video data is shown. Taking a 4224*3144 input video, a memory data bit width of 64 bits, a Bayer domain data of 10 bits, and a YC domain data of 8 bits as an example, the image on the left side of the left starting dividing line in the input image is determined as the target left dividing image, and the image on the right side of the right starting dividing line is determined as the first right dividing image. Then, according to the target left dividing image and the complementary data dividing line, the first right dividing image is mirror-padding processed to determine the target right dividing image. In one embodiment, the right starting line is configured as 1680, the left starting dividing line is configured as 2688, the overlapping center line is configured as 2184, the complementary data dividing line is 4368, the complementary data is 144*3144, and the mirror-padding principle is adopted to ensure that the boundary data defects of the right image are smaller.
[0042] In one embodiment, the mirror edge filling principle can be found in Figure 5 A schematic diagram of a mirror edge filling method shown in Figure 6Another mirror edge filling method is shown in the schematic diagram. The overlap center line-right starting split line = left starting split line-overlap center line, so as to ensure that the video transition regions on the left and right sides are the same, and the sizes of the split left and right images are the same. Specifically, the image width between the effective data end line and the fill data split line can be determined as the fill image width, the left symmetrical image of the fill image width is cut at the left boundary of the target left split image, and the right symmetrical image that is mirror complementary to the left symmetrical image is determined, the target right split image is determined by combining the right symmetrical image and the first right split image, so that the image sizes of the target left split image and the target right split image are the same. The field signal changes before and after splitting can be referred to Figure 7 A schematic diagram of cutting the field signal before and after splitting is shown.
[0043] (2) The target left split image and the target right split image are sequentially processed in the Bayer domain and the luminance chroma domain to quickly denoise and filter the small resolution data after splitting, and convert the image into a video format. In actual application, the split small resolution real-time video data can be processed through the bayer domain module and the YC domain module, respectively. In these two functional blocks, the filter and denoising module originally needs a 4224-depth row buffer for data storage. After processing the two small resolution videos, only a 2688-depth row buffer is needed, thereby reducing the circuit area.
[0044] (3) Referring to Figure 8 A schematic diagram of 3D processing data storage is shown. Image cropping processing is performed on the target left split image and the target right split image. The image part on the left side of the overlap center line in the target left split image is determined as the current left memory image and stored in the left memory, i.e., the video data in the 2184*3144 region of the left image is stored in the memory, and the data on the right side of 504*3144 is discarded by using the cropping module. The image part before the overlap center line and the effective data end line in the target right split image is determined as the current right memory image and stored in the right memory, i.e., the video data in the 2040*3144 region of the right image is stored in the memory, and the data on the left side of 504*3144 and the right side of 144*3144 is discarded by using the cropping module.
[0045] (4) Referring to Figure 9The structure diagram of taking data of one 3D processing is shown, the image between the overlapping center line and the left starting split line in the current right memory image is combined with the current left memory image to determine the last frame left memory image, that is, the left image takes out 2184*3144 data from the left memory and 504*3144 data from the right memory, the image between the overlapping center line and the right starting split line in the current left memory image is combined with the current right memory image and the right symmetric image to determine the last frame right memory image, that is, the right image takes out 2040*3144 data from the right memory and 504*3144 data from the left memory, and the mirror edge 144*3144 data is performed on the rightmost side, the current left memory image, the current right memory image, the last frame left memory image and the last frame right memory image are combined for 3D image processing to eliminate the transition area difference between the left and right images after 3D processing, wherein the 504*3144 data is the overlapping transition data, and each of the left and right images takes a part of data of the other as transition processing to reduce the difference between the two.
[0046] (5) refer to Figure 10 The schematic diagram of taking data display is shown, the video data obtained by using the current real-time streaming video data and the last frame data taken out from the memory for calculation is displayed again according to Figure 8 The flow shown is stored in the memory, and finally the vo display takes out the whole block of video data from the memory as a 4224*3144 video stream for display.
[0047] In summary, the application can use the apb bus to configure different split line parameters for inputting videos with different resolutions, thereby adapting to more application scenarios, originally, the 1300w resolution (4224*3144) video needs 4 4224 row buffers to store data when applying 5*5 filtering during row buffer data storage in video processing, but only 4 2688 row buffers are needed to store data after splitting by the video parallel processing of the application, in addition, 4224 data need to be processed per row and 3144 rows need to be processed when storing in the memory, which will cause other modules to wait when using the memory, but after splitting into 2668*3144, the time length of one command processing by the cpu is reduced, thereby reducing the cpu burden and ensuring the frame rate and image quality of the video.
[0048] For the bus controllable video parallel processing method provided by the foregoing embodiment, an embodiment of the application provides a bus controllable video parallel processing device, refer to Figure 11A structure diagram of a bus-controllable video parallel processing device is shown, which comprises the following parts:
[0049] A parameter setting module 1102 collects video data to be processed, and determines target split line parameters based on storage data bit width of a storage device and resolution information of the video data to be processed, wherein the target split line parameters comprise an overlapping center line, a right start split line, a left start split line, an effective data end line and a supplementary data split line.
[0050] An image splitting module 1104 performs image splitting processing and mirror edge supplementing processing on each frame of input image in the video data to be processed according to the target split line parameters, determines target left split images and target right split images after splitting, and stores the target left split images and the target right split images into left memory and right memory respectively.
[0051] An image processing module 1106 performs 3D image processing on the stored target left split images and target right split images, and extracts and splices the target left split images and the target right split images into a video stream for display when the 3D image processing is completed.
[0052] The bus-controllable video parallel processing device provided by the embodiments of the present application can significantly reduce memory consumption and processor burden during video processing while ensuring video quality.
[0053] In one implementation, when determining the target split line parameters based on the storage data bit width of the storage device and the resolution information of the video data to be processed, the parameter setting module 1102 is further configured to: perform storage analysis processing on the storage data bit width and the resolution information of the video data to be processed by a preset defogging algorithm, determine a minimum score of storage; determine the overlapping center line, the right start split line, the left start split line and the effective data end line according to the minimum score of storage and a preset split line ratio, and determine the supplementary data split line according to the difference of images split by the right start split line and the left start split line.
[0054] In one implementation, when performing the image splitting processing and the mirror edge supplementing processing on each frame of input image in the video data to be processed according to the target split line parameters, and determining the target left split images and the target right split images after splitting, the image splitting module 1104 is further configured to: determine the image on the left side of the left start split line in the input image as the target left split image, and determine the image on the right side of the right start split line as a first right split image; perform mirror edge supplementing processing on the first right split image according to the target left split image and the supplementary data split line, and determine the target right split image.
[0055] In one embodiment, when the step of performing mirror edge filling processing on the first right split image according to the target left split image and the supplementary data split line to determine the target right split image is performed, the image splitting module 1104 is further configured to: determine the image width between the effective data end line and the supplementary data split line as a supplementary image width; cut a left symmetrical image of the supplementary image width from the left boundary of the target left split image, and determine a right symmetrical image that is mirror complementary to the left symmetrical image; and combine the right symmetrical image and the first right split image to determine the target right split image, so that the image sizes of the target left split image and the target right split image are the same.
[0056] In one embodiment, after the step of determining the split target left split image and the split target right split image is performed, the image splitting module 1104 is further configured to: sequentially perform Bayer domain processing and luminance chroma domain processing on the target left split image and the target right split image, to quickly reduce noise and filter the split small resolution data, and convert the image into a video format.
[0057] In one embodiment, when the step of storing the target left split image and the target right split image into the left memory and the right memory respectively is performed, the image processing module 1106 is further configured to: perform image cropping processing on the target left split image and the target right split image, determine a left image part of the target left split image that overlaps the center line as a current left memory image, and store the current left memory image into the left memory; and determine an image part of the target right split image that is before the center line and the effective data end line as a current right memory image, and store the current right memory image into the right memory.
[0058] In one embodiment, when the step of performing 3D image processing on the stored target left split image and the target right split image is performed, the image processing module 1106 is further configured to: combine an image between the center line and the left start split line in the current right memory image with the current left memory image to determine a previous frame left memory image; combine an image between the center line and the right start split line in the current left memory image with the current right memory image and the right symmetrical image to determine a previous frame right memory image; and combine the current left memory image, the current right memory image, the previous frame left memory image, and the previous frame right memory image to perform 3D image processing, so as to eliminate the transition area difference between the left and right images after 3D processing.
[0059] The device provided in the embodiments of the present application has the same implementation principle and technical effects as the foregoing method embodiments, and for brevity of description, the part not mentioned in the device embodiment can be referred to the corresponding content in the foregoing method embodiments.
[0060] The electronic device provided by the embodiment of the present application, specifically, comprises a processor and a storage device; the storage device stores a computer program, and the computer program performs the method according to any one of the above embodiments when being run by the processor.
[0061] Figure 12 The structural schematic diagram of the electronic device provided by the embodiment of the present application, the electronic device 100 comprises a processor 120, a memory 121, a bus 122 and a communication interface 123, the processor 120, the communication interface 123 and the memory 121 are connected through the bus 122; the processor 120 is used for executing the executable module stored in the memory 121, for example, a computer program.
[0062] The memory 121 can contain a high-speed random access memory (RAM, Random Access Memory) and can also include a non-volatile memory, for example, at least one disk memory. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 123 (which can be wired or wireless), and the Internet, a wide area network, a local area network, a metropolitan area network, etc. can be used.
[0063] The bus 122 can be an ISA bus, a PCI bus or an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, Figure 12 Only one bidirectional arrow is used in the figure, but it does not mean that there is only one bus or only one type of bus.
[0064] The memory 121 is used for storing a program, and the processor 120 executes the program after receiving an execution instruction. The method performed by the device defined by the flow process disclosed in any one of the above embodiments can be applied to the processor 120 or realized by the processor 120.
[0065] The processor 120 can be an integrated circuit chip with a processing capability of signals. In the implementation process, each step of the above method can be completed by the integrated logic circuit of hardware in the processor 120 or the instruction in the form of software. The processor 120 described above can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. Each method, step and logic block disclosed in the embodiment of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiment of the present application can be directly embodied as a hardware decoding processor for execution, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the memory 121, and the processor 120 reads the information in the memory 121 and combines the hardware to complete the steps of the above method.
[0066] The computer program product of the readable storage medium provided by the embodiment of the present application includes a computer readable storage medium storing program codes, and the instructions included in the program codes can be used to execute the method described in the foregoing method embodiment. The specific implementation can be referred to the foregoing method embodiment, and will not be described here.
[0067] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the present application that essentially contribute to the prior art or the parts of the technical solutions can be embodied in the form of software products. The computer software product is stored in a storage medium and includes instructions for making a computer device (which can be a personal computer, an electronic device, or a network device, etc.) execute all or part of the steps of the method described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.
[0068] Finally, it should be noted that: the above-described embodiments are only specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, but not to limit them. The protection scope of the present application is not limited to this. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily think of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed by the present application, or make equivalent replacements to some of the technical features. The modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A bus-controllable video parallel processing method, characterized in that: The method comprises: Collecting video data to be processed, and determining target segmentation line parameters based on the storage data bit width of the storage device and the resolution information of the video data to be processed, wherein the target segmentation line parameters include: an overlapping center line, a right starting segmentation line, a left starting segmentation line, a valid data end line, and a supplementary data segmentation line; Performing image segmentation processing and mirror edge filling processing on each frame input image in the to-be-processed video data according to the target segmentation line parameters, determining a target left segmented image and a target right segmented image after segmentation, and storing the target left segmented image and the target right segmented image in a left memory and a right memory, respectively; 3D image processing is performed on the stored target left segmented image and the target right segmented image, and when the 3D image processing is completed, the target left segmented image and the target right segmented image are extracted and spliced into a video stream for display.
2. The bus-controllable video parallel processing method according to claim 1, characterized in that: The step of determining target segmentation line parameters based on the storage data bit width of the storage device and the resolution information of the video data to be processed includes: Performing storage analysis on the stored data bit width and the resolution information of the video data to be processed by a preset defogging algorithm to determine a minimum storage score; According to the stored minimum score and the preset segmentation line ratio, the overlapping center line, the right starting segmentation line, the left starting segmentation line and the valid data end line are determined, and the complementary data segmentation line is determined according to the difference between the images segmented by the right starting segmentation line and the left starting segmentation line.
3. The bus-controllable video parallel processing method according to claim 1, characterized in that: The step of performing image segmentation processing and mirror edge filling processing on each frame input image in the to-be-processed video data according to the target segmentation line parameters to determine the target left segmented image and the target right segmented image after segmentation includes: Determine, in the input image, an image on the left side of the left starting segmentation line as the target left segmentation image, and determine an image on the right side of the right starting segmentation line as the first right segmentation image; According to the target left segmented image and the complementary data segmentation line, the first right segmented image is subjected to mirror-image edge-filling processing to determine the target right segmented image.
4. The bus-controllable video parallel processing method according to claim 3, characterized in that: The step of performing mirror edge padding processing on the first right segmented image according to the target left segmented image and the data patching line to determine the target right segmented image includes: Determine the image width between the valid data end line and the supplementary data dividing line as the supplementary image width; intercepting a left symmetric image of the complementary image width at the left boundary of the target left segmented image, and determining a right symmetric image that is a mirror image complementary to the left symmetric image; The right symmetrical image and the first right segmented image are combined to determine the target right segmented image, so that the target left segmented image and the target right segmented image have the same image size.
5. The bus-controllable video parallel processing method according to claim 1, characterized in that: After the step of determining the segmented target left segmented image and the target right segmented image, the method includes: The target left segmented image and the target right segmented image are sequentially processed in the Bayer domain and the luminance and chrominance domain to quickly reduce noise and filter the segmented small-resolution data, and the images are converted into a video format.
6. The bus-controllable video parallel processing method according to claim 1, characterized in that: The step of storing the target left segmented image and the target right segmented image in a left memory and a right memory respectively comprises: Performing image cropping processing on the target left segmented image and the target right segmented image, determining the image portion on the left side of the overlapping center line in the target left segmented image as the current left memory image, and storing the image in the left memory; The image portion before the overlapping center line and the valid data end line in the target right segmented image is determined as the current right memory image and stored in the right memory.
7. The bus-controllable video parallel processing method according to claim 1, characterized in that: The step of performing 3D image processing on the stored target left segmented image and the target right segmented image comprises: Combining the image between the overlapping center line and the left starting dividing line in the current right memory image with the current left memory image to determine the image as the previous frame of the left memory image; Combining the image between the overlapping midline and the right starting segmentation line in the current left memory image with the current right memory image and the right symmetrical image to determine the image as the previous frame right memory image; The current left memory image, the current right memory image, the previous left memory image and the previous right memory image are combined to perform 3D image processing to eliminate the difference in transition areas between the left and right images after 3D processing.
8. A bus-controllable video parallel processing device, characterized in that: The device comprises: A parameter setting module collects the video data to be processed and determines the target segmentation line parameters based on the storage data bit width of the storage device and the resolution information of the video data to be processed, wherein the target segmentation line parameters include: overlapping center line, right starting segmentation line, left starting segmentation line, valid data end line and supplementary data segmentation line; an image segmentation module, performing image segmentation processing and mirror edge filling processing on each frame input image in the to-be-processed video data according to the target segmentation line parameters, determining a target left segmented image and a target right segmented image after segmentation, and storing the target left segmented image and the target right segmented image in a left memory and a right memory, respectively; The image processing module performs 3D image processing on the stored target left segmented image and the target right segmented image, and extracts and splices the target left segmented image and the target right segmented image into a video stream for display when the 3D image processing is completed.
9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the method according to any one of claims 1 to 7.