Method and apparatus for multi-chip link management in a multi-chip verification environment

Abstract

The application provides a multi-chip link management method and device in a multi-chip verification environment. A programmable topology management module is used to maintain a global link mapping relationship database, and then a link mapping pair representing a link is added to the global link mapping relationship database. When data transmission between chips is required, the receiving end chip identifier of the target link is determined through the global link mapping relationship database, and then the verification data of the data transmission request is routed to the receiving end chip through the target link. Since the link mapping pair is configured through the global link mapping relationship database, the connection relationship of the chips is decoupled from the hardware, thereby achieving dynamic management of the topology connection and the connection of the link, reducing the step of manual configuration, reducing the risk of human error, thereby reducing the verification cost and improving the verification efficiency.

Description

Technical Field

[0001] This application relates to the field of chip verification, and more specifically, to a method and apparatus for multi-chip link management in a multi-chip verification environment. Background Technology

[0002] As chip applications become increasingly widespread, chip interconnect architectures are becoming more and more complex. For example, high-performance chips such as network chips, graphics processing units, and memory chips often require testing in multi-chip interconnect environments during their verification process.

[0003] In existing technologies, in order to build a multi-chip interconnect topology, testers often need to manually complete the topology linking of the multi-chips, and then set the corresponding underlying code on the basis of the topology.

[0004] However, existing technologies require modifications to the underlying code whenever the topology needs to be adjusted. Furthermore, the complexity of the topology and the high cost of maintaining the state of each chip further increase implementation costs and reduce verification efficiency. Summary of the Invention

[0005] The purpose of this application is to provide a method and apparatus for multi-chip link management in a multi-chip verification environment, which reduces the complexity of topology configuration and improves verification efficiency.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0007] In a first aspect, embodiments of this application provide a multi-chip link management method, including:

[0008] Create a programmable topology management module, which includes a global link mapping relationship library for storing links;

[0009] In response to the user's topology configuration command, obtain the link mapping pair in the topology configuration command; the link mapping pair represents the two endpoint chip identifiers in the link to be added;

[0010] Add the link mapping pair to the global link mapping relationship library;

[0011] In response to a data transmission request between chips, the target link and the transmitter chip identifier of the target link are obtained according to the data transmission request; the transmitter chip identifier is one of the two endpoint chip identifiers of the target link, representing the transmitter chip of the target link;

[0012] The receiver chip identifier of the target link is queried in the global link mapping database; the receiver chip identifier represents the receiver chip of the target link.

[0013] The verification data of the data transmission request is routed to the receiving chip through the target link.

[0014] Secondly, embodiments of this application provide a multi-chip link management device, including: a creation module, an acquisition module, a query module, and a transmission module;

[0015] The creation module is used to create a programmable topology management module, which includes a global link mapping relationship library for storing links;

[0016] The acquisition module is used to respond to the user's topology configuration command, obtain the link mapping pair in the topology configuration command; the link mapping pair represents the two endpoint chip identifiers in the link to be added; add the link mapping pair to the global link mapping relationship library; respond to the data transmission request between chips, and obtain the target link and the sending chip identifier of the target link according to the data transmission request; the sending chip identifier is one of the two endpoint chip identifiers of the target link, representing the sending chip of the target link;

[0017] The query module is used to query the receiver chip identifier of the target link in the global link mapping relationship database; the receiver chip identifier represents the receiver chip of the target link.

[0018] The transmission module is used to route the verification data of the data transmission request to the receiving chip through the target link.

[0019] Thirdly, embodiments of this application provide an electronic device, which includes a memory for storing one or more programs and a processor. When the one or more programs are executed by the processor, the chips in a chip array are verified through a communication interface, thereby implementing the methods described in the first aspect and various possible implementations above.

[0020] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the methods described in the first aspect and various possible implementations.

[0021] Compared to existing technologies, the multi-chip link management method and apparatus in a multi-chip verification environment provided in this application maintains a global link mapping relationship library through a programmable topology management module. Link mapping pairs representing links are then added to this library. When inter-chip data transmission is required, the receiver chip identifier of the target link is determined through the global link mapping relationship library, thus routing the verification data requesting data to the receiver chip via the target link. Because the link mapping pairs are configured through the global link mapping relationship library, the chip connection relationships are decoupled from the hardware, thereby achieving dynamic management of topology connections and link connections. This reduces manual configuration steps, lowers the risk of human error, reduces verification costs, and improves verification efficiency.

[0022] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a common chip topology.

[0025] Figure 2 A flowchart illustrating a multi-chip link management method in a multi-chip verification environment provided by an embodiment of the present invention;

[0026] Figure 3 A flowchart illustrating another multi-chip link management method in a multi-chip verification environment provided by an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of a chip type enumeration provided in an embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of a chip information structure provided in an embodiment of the present invention;

[0029] Figure 6 A schematic diagram of a link endpoint structure provided in an embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of a link mapping structure provided in an embodiment of the present invention;

[0031] Figure 8A schematic diagram of a global link mapping relationship library provided in an embodiment of the present invention;

[0032] Figure 9 A flowchart illustrating another multi-chip link management method in a multi-chip verification environment provided by an embodiment of the present invention;

[0033] Figure 10 This is a schematic diagram of a link mapping queue provided in an embodiment of the present invention;

[0034] Figure 11 This is a schematic diagram illustrating data transmission based on a chip link, provided as an embodiment of the present invention.

[0035] Figure 12 This is a schematic diagram of a multi-chip link management architecture provided in an embodiment of the present invention;

[0036] Figure 13 This is a schematic diagram of a multi-chip link management device provided in an embodiment of the present invention;

[0037] Figure 14 This is a schematic diagram of another multi-chip link management device provided in an embodiment of the present invention;

[0038] Figure 15 This is a schematic structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0041] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0042] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0043] In the description of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0044] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0045] Figure 1 For a schematic diagram of common chip topologies, please refer to [link / reference]. Figure 1 , Figure 1 (a) shows a single-level interconnect topology, in which chips _1 to _4 are connected to chip _5 respectively, forming a single-level interconnect topology. Figure 1 In (b), chips 1 to 4 are connected to chip 5, chips 7 to 10 are connected to chip 6, and then chip 5 is connected to chip 6, thus forming a two-level interconnection topology. Figure 1 In (c), chips _1 to _4 are connected to chip _5, and chips _1 to _4 are connected to chip _6, chips _10 to _13 are connected to chip _8, and chips _10 to _13 are connected to chip _9. Furthermore, chips _5, _6, _8, and _9 are connected to chip _7, thus forming a three-level interconnected topology. Figure 1 In (c), chips _1 to _8 are connected to other chips respectively, thus forming a fully interconnected topology.

[0046] The above Figure 1This demonstrates the diversity of chip topologies. Clearly, for different topologies, the conventional approach of using fixed connections necessitates modifications to the underlying code when the topology changes, increasing verification complexity and reducing verification efficiency.

[0047] Furthermore, due to the complexity of the links in the chip's topology, it is difficult to maintain the link status in the existing methods. Once the chip or link malfunctions, the interconnection status cannot be flexibly adjusted, thus affecting the controllability of the verification.

[0048] Furthermore, when implementing different topologies, conventional solutions often employ manual connections, which can easily lead to connection errors. Additionally, due to the need for random connections during verification, existing topology connection methods cannot quickly respond to more granular control functions such as online / offline switching and operation undoing.

[0049] To address the aforementioned issues, this application provides a more flexible dynamic management mechanism for multiple chips, the core of which is:

[0050] 1. Construct a programmable topology management module with built-in functions to implement various functions during multi-chip verification, such as link establishment, deletion, addition, chip status control, and display. Further functions may be added later through programming to achieve even more features.

[0051] 2. Maintain hierarchical topology information through a global link mapping database, such as chip type, chip identifier, link number, and link status. Then, use this topology information to dynamically add or remove links.

[0052] To better illustrate the improvement mechanism of this application, a possible implementation of a multi-chip link management method in a multi-chip verification environment is provided below. Specifically, Figure 2 This is a flowchart illustrating a multi-chip link management method in a multi-chip verification environment according to an embodiment of the present invention. (See attached diagram.) Figure 2 The method includes:

[0053] Step 100: Create a programmable topology management module.

[0054] The programmable topology management module includes a global link mapping relationship library for storing links.

[0055] Step 101: Respond to the user's topology configuration command and obtain the link mapping pairs in the topology configuration command.

[0056] Among them, the link mapping pairs represent the two endpoint chip identifiers in the link to be added.

[0057] Optionally, the link mapping records the endpoint chip identifiers at both ends of a link simultaneously—one source endpoint and one destination endpoint. This allows for easy configuration of the connection by requiring only information from one end to obtain the endpoint chip identifier of the domain segment, simplifying the configuration process and facilitating the tracing and debugging of each link during verification.

[0058] Step 102: Add the link mapping pairs to the global link mapping relationship library.

[0059] Step 103: Respond to the data transmission request between chips and obtain the target link and the sending chip identifier of the target link according to the data transmission request.

[0060] The transmitter chip identifier is one of the two endpoint chip identifiers of the target link; the transmitter chip identifier represents the transmitter chip of the target link.

[0061] Step 104: Query the receiver chip identifier of the target link in the global link mapping database.

[0062] Among them, the receiver chip identifier represents the receiver chip of the target link.

[0063] Step 105: Route the verification data of the data transmission request to the receiving chip through the target link.

[0064] The multi-chip link management method in a multi-chip verification environment provided in this invention maintains a global link mapping relationship library through a programmable topology management module. Link mapping pairs representing links are then added to this library. When inter-chip data transmission is required, the receiver chip identifier of the target link is determined through the global link mapping relationship library, thus routing the verification data requesting data to the receiver chip via the target link. Because the link mapping pairs are configured through the global link mapping relationship library, the chip connection relationships are decoupled from the hardware, thereby achieving dynamic management of topology connections and link connections. This reduces manual configuration steps, lowers the risk of human error, reduces verification costs, and improves verification efficiency.

[0065] Obviously, because this solution can flexibly configure and manage each chip topology in the chip topology to be verified at the link level, it can handle changes in chip topology across various topology methods (such as...). Figure 1 (As shown in the various topologies), the various embodiments of the present invention can be better adapted dynamically.

[0066] Alternatively, the following provides a possible implementation for creating a programmable topology management module, specifically, in Figure 2 On this basis, Figure 3A flowchart illustrating another multi-chip link management method in a multi-chip verification environment provided by an embodiment of the present invention is shown below. Figure 3 Step 100 includes:

[0067] Step 100-1: Obtain at least one link mapping structure to generate a global link mapping relationship library.

[0068] Step 100-2: Create a programmable topology management module based on the global link mapping relationship library.

[0069] Alternatively, the link mapping structure can be obtained by constructing hierarchical topology information. An example of a design rule for topology information is provided below.

[0070] First, we can enumerate the chip type (chip_type_e). Specifically, Figure 4 This is a schematic diagram of a chip type enumeration provided in an embodiment of the present invention. See also: Figure 4 The “chip_type_e” defines several required chip types: chip_A, chip_B, chip_C, chip_D, etc.

[0071] Optionally, a chip information structure (chip_info_t) can be constructed to define the chip information structure: containing chip type and chip identifier, used to identify basic information about a chip. Specifically, Figure 5 This is a schematic diagram of a chip information structure provided in an embodiment of the present invention. See also: Figure 5 Here, "chip_type_e" represents the enumerated chip type; "chip_id" is used as a unique identifier (chip identifier) ​​for the same chip type in the verification environment. See Table 1 for details:

[0072]

[0073] Optionally, a link endpoint structure (endpoint_t) can be constructed to describe the chip information (including chip type, chip number, and the link number corresponding to that chip) of any endpoint chip of a link. Specifically, Figure 6 This is a schematic diagram of a link endpoint structure provided in an embodiment of the present invention. See also: Figure 6 Here, "chip_info_t" is used to represent the chip information structure; "link" is used to represent the corresponding link number.

[0074] Optionally, a link mapping structure (link_mapping_t) can be constructed to describe the bidirectional connection information between the endpoint chips of a link. Specifically, Figure 7This is a schematic diagram of a link mapping structure provided in an embodiment of the present invention. See also: Figure 7 The link mapping structure includes the chip information structure (ep_a) of endpoint chip A, the chip information structure (ep_b) of endpoint chip B, and the link status bits (link_vld). See Table 2 for details:

[0075]

[0076] The status bit indicates the validity of the link, enabling validity control and link disconnection functions. A vld control signal is introduced for each link, allowing dynamic enabling or disabling of the connection during verification. For temporary disconnections, the programmable topology management module provides a link disconnection operation, which promptly sets the corresponding link's link_vld to invalid and synchronously updates the peer's status, ensuring the system remains in a valid topology state after disconnection.

[0077] Optionally, Figure 8 This is a schematic diagram of a global link mapping relationship library provided in an embodiment of the present invention. See also... Figure 8 This global link mapping relationship library can construct hierarchical topology information through the aforementioned link mapping structure (link_mapping_t), link endpoint structure (endpoint_t), chip information structure (chip_info_t), chip type (chip_type_e), etc., so as to enable subsequent dynamic topology management.

[0078] It should be noted that the global link mapping database can store the link mapping pairs of all links in the topology corresponding to each verification in the form of a queue, and the information of each link mapping pair can be... Figure 8 The information structure shown is maintained.

[0079] Optionally, as mentioned above, a link is configured by responding to the link mapping pairs in the topology configuration command. There are several ways to configure this, such as obtaining the user's topology configuration command by directly calling the mapping add function; or having the user input the topology configuration command through a graphical interface. The following provides possible implementations for obtaining link mapping pairs; specifically... Figure 2 On this basis, Figure 9 A flowchart illustrating another multi-chip link management method in a multi-chip verification environment provided by an embodiment of the present invention is shown below. Figure 9 Step 101 includes:

[0080] Step 101-1a: Respond to the user's call to the endpoint creation function of the programmable topology management module and generate the first topology configuration instruction.

[0081] Step 101-1b: Obtain the link mapping pair according to the first topology configuration instruction.

[0082] Step 101-2a: Respond to the user's input of a second topology configuration command through the graphical interface. The second topology configuration command represents the topology drawing between multiple chips and generates topology configuration code corresponding to the topology drawing.

[0083] Step 101-2b: Obtain the link mapping pairs according to the topology configuration code.

[0084] Optionally, this programmable topology management module can be implemented through a configuration class, and the corresponding global link mapping relationship library can be a link mapping pair queue (mappings_list), as shown in the following example:

[0085] `link_mapping_t` (link mapping structure) `mappings_list[$]`; / / A queue of all link mapping pairs, containing information about the chips at both ends of all connected links.

[0086] Therefore, whether using a mapping addition function or a graphical interface for input, the obtained link mapping pairs can be added to the link mapping pair queue (mappings_list). Optionally, Figure 10 This is a schematic diagram of a link mapping pair queue provided in an embodiment of the present invention. See [link to diagram]. Figure 10 This link mapping pair queue contains link mapping pair 1, which corresponds to a link mapping structure 1, containing link 0: from chip_A to chip_B. Link mapping pair 2 corresponds to a link mapping structure 2, which contains link 1: from chip_A to chip_B.

[0087] When topology configuration instructions are obtained through the above method, and new link mapping pairs are subsequently obtained, such as Figure 9 As shown, link mapping pair 3 is added to the link mapping pair queue.

[0088] Optionally, the programmable topology management module can have a variety of built-in functions. The following table 3 provides an example description of the various functions and their functions.

[0089]

[0090] The functions are described below:

[0091] 1) Mapping addition function (add_mapping):

[0092] function void add_mapping(endpoint_t ep_a, endpoint_t ep_b)

[0093] Function: Add a link mapping pair, forming a bidirectional connection between endpoints ep_a and ep_b, and store the result in mapping_list.

[0094] Parameter: ep_a: Source endpoint structure, containing chip type, chip identifier and link number.

[0095] ep_b: Target endpoint structure.

[0096] 2) Endpoint creation function (add_mapping_by_params):

[0097] function void add_mapping_by_params(chip_type_e type_a, int chip_id_a, int link_a,chip_type_e type_b, int chip_id_b, int link_b)

[0098] Function: Creates endpoints_t at both ends based on chip type, chip, and link number parameters, and calls add_mapping.

[0099] Parameters: type_a, chip_id_a, link_a: chip type, chip identifier, and link number of endpoint A.

[0100] type_b, chip_id_b, link_b: The corresponding parameters for endpoint B.

[0101] 3) Link mapping lookup function (get_mapping):

[0102] function mapping_pair_t get_mapping(chip_type_e chip_type, int chip_id, int link)

[0103] Function: Searches for a link mapping pair in mapping_list that contains a specified endpoint and returns the entire mapping_pair_t.

[0104] Parameters: chip_type, chip_id, link: endpoint information used for matching.

[0105] Returns: A matching mapping_pair_t; if not found, a dummy with all fields having invalid values ​​is returned.

[0106] 4) Peer query function (get_peer):

[0107] function endpoint_t get_peer(chip_type_e chip_type, int chip_id, intlink)

[0108] Function: Query the peer information of a given endpoint, and return only the other endpoint_t.

[0109] Parameters: Same as get_mapping.

[0110] Returns: the corresponding endpoint_t, or dummy if not found.

[0111] 5) Endpoint chip comparison function (compare_endpoints):

[0112] function int compare_endpoints(endpoint_t a, endpoint_t b)

[0113] Function: Compares two endpoint objects and returns -1, 0, or 1 in the order of "chip type → chip identifier → link number".

[0114] Parameters: a, b: the two endpoints to be compared.

[0115] Returns: -1 indicates a is less than b, 0 indicates they are equal, and 1 indicates a is greater than b.

[0116] Usage: Called when performing internal sorting or user-defined sorting.

[0117] 6) Link mapping comparison function (endpoint chip):

[0118] function int compare_mapping(mapping_pair_t a, mapping_pair_t b)

[0119] Function: First compare a.ep_a with b.ep_a, and if they are equal, then compare ep_b.

[0120] Parameters: a, b: Two link mapping pairs to be compared.

[0121] Returns: Same as compare_endpoints.

[0122] Usage: Used for comparing link mapping pairs before display_sorted() sorting.

[0123] 7) Display function (display_sorted):

[0124] function void display_sorted()

[0125] Function: Sort the current mapping_list and print all link mapping pairs in tabular form.

[0126] Implementation: Use bubble sort combined with compare_mapping to output a formatted text header and mapping information for each line.

[0127] 8) Add an acknowledgment function (is_connected) to the endpoint chip:

[0128] function bit is_connected(chip_type_e chip_type, int chip_id, intlink)

[0129] Function: Determines whether the specified endpoint exists in any added link mapping pair.

[0130] Return value: 1 indicates connected, 0 indicates not connected.

[0131] 9) function void display_unconnected_links()

[0132] Function: Iterate through all chip types and chip identifiers, and print a list of link numbers for which no mapping has been established.

[0133] 10) Link mapping deletion function (remove_connection):

[0134] function void remove_connection(chip_type_e chip_type, int chip_id, int link)

[0135] Function: Deletes the link mapping pair containing the specified endpoint from mapping_list and prints the deletion result.

[0136] 11) Chip update function (set_chip_online_status):

[0137] function void set_chip_online_status(chip_type_e type, int chip_id,bit status);

[0138] Function: Set the chip's online status: online / offline, input parameter status: 1 for online, 0 for offline.

[0139] 12) Link update function (set_link_vld_status):

[0140] function void set_link_vld_status (chip_type_e type, int chip_id, bitstatus);

[0141] Function: Sets the link to active / inactive. Input parameter status: 1 for active, 0 for inactive.

[0142] 13) Chip batch connection configuration function (add_links_between_range):

[0143] function void add_links_between_range(

[0144] chip_type_e chip_type_a, int id_a,

[0145] int start_link_a, int end_link_a,

[0146] chip_type_e chip_type_b, int id_b,

[0147] int start_link_b, int end_link_b,

[0148] int num_connections,LinkMode mode );

[0150] This chip's batch connection configuration function supports defining the range of interfaces and links, such as bit width or index intervals. Through unified range configuration, multiple related links can be generated and controlled in batches, simplifying the connection configuration process for large-scale similar interfaces. Simultaneously, the parameterized template design allows different chip types to quickly reuse the same configuration logic, enhancing flexibility.

[0151] Optionally, referring to Table 3 above, this embodiment can achieve dynamic management of the link by calling various functions as shown in Table 3 at appropriate times, as in one or a combination of the following possible implementation methods:

[0152] Based on the user's addition command, the new link mapping pair is added to the global link mapping relationship library by calling the addition function [add_mapping].

[0153] Based on the user's deletion command, the deletion function [remove_connection] is called to remove the link mapping pair to be deleted from the global link mapping relationship database.

[0154] The status bit of each link mapping pair in the global link mapping relationship database is updated using the link update function

set_link_vld_status

[0155] The online status of each endpoint chip in the global link mapping database is updated using the chip update function

set_chip_online_status

[0156] In response to a query command, the peer query function is invoked to retrieve peer information of the target endpoint in the link mapping pair corresponding to the query command from the global link mapping relationship database.

[0157] In response to the display command, at least one link mapping pair in the global link mapping relationship library is displayed by calling the display function.

[0158] Based on the functions described above, the following is a possible implementation method for configuring the chip link:

[0159] 1. Create a programmable topology management module

[0160] In one possible implementation, the programmable topology management module can be a configuration class instance (chip_connect_cfg), as shown in the following example:

[0161] chip_connect_cfg cfg = new();

[0162] 2. Users establish link mapping pairs

[0163] See the previous text Figure 9 It can be seen that there are two mechanisms for establishing link mapping pairs:

[0164] 2.1 Chip link connections can be established by directly calling the endpoint creation function (add_mapping_by_params), passing in the chip type, chip identifier, and link number of both endpoints. This allows for the rapid generation of all connections in the required topology. For example:

[0165] cfg.add_mapping_by_params(CHIP_A, 0, 0,

[0166] CHIP_B, 0, 36);

[0167] cfg.add_mapping_by_params(CHIP_A, 1, 0,

[0168] CHIP_B, 1, 37);

[0169] The two calls to the add_mapping_by_params function above respectively implemented the connection between CHIP_A#0 link 0 and CHIP_B#0 link 36 and the connection between CHIP_A#1 link 0 and CHIP_B#1 link 37.

[0170] 2.2 Chip link connections are indirectly achieved through topology diagram connections implemented via a graphical interface.

[0171] Referring to the previous text, the second topology configuration instruction in step 101-2a represents the topology drawing between multiple chips, which then derives SV code (i.e., topology configuration code) to indirectly generate chip link mapping pairs. The exported SV code also calls the add_mapping_by_params function to achieve the connection.

[0172] 3. Implement data connections between design codes of different chips.

[0173] Optionally, Figure 11 This is a schematic diagram of data transmission based on a chip link, provided as an embodiment of the present invention. (See attached diagram.) Figure 11 Data output from chip_A can be transmitted to the data routing interface component (connect_uvc) of the verification environment. This component then uses the peer query function (get_peer) of the programmable topology management module 21 to query the peer chip information based on the information of chip_A (including chip type, chip identifier, and link number), thereby accurately transmitting the data to the corresponding link of chip_B. Conversely, data sent by chip_B can also establish a connection in a similar manner. For example:

[0174] endpoint_t peer = cfg.get_peer(CHIP_A, 0, 0);

[0175] / / peer.info.chip_type, peer.info.chip_id, peer.link are the peer chip information.

[0176] To achieve the steps and corresponding technical effects of the examples described above, this application also provides possible implementations of a multi-chip link management architecture. Specifically, Figure 12 This is a schematic diagram of a multi-chip link management architecture provided in an embodiment of the present invention. See also... Figure 12 The architecture includes: a user interaction layer 20, a programmable topology management module 21, a storage layer 22, and an execution layer 23 for the verification environment.

[0177] The user interaction layer 20 includes a graphical interface 201 and an API configuration interface 202.

[0178] This graphical interface 201 is used to visualize the generation of topology-related information, such as allowing users to input second topology configuration commands through the graphical interface, or to display topology configuration code (SV / Python).

[0179] The graphical interface 201 can send topology configuration commands to the programmable topology management module 21, or receive topology verification results (e.g., collision detection) sent by the programmable topology management module 21.

[0180] This graphical interface 201 serves as an auxiliary configuration entry point, visually displaying the connection relationships between various chip interfaces and supporting batch connection or disconnection operations. Through this user-friendly graphical interface, users can intuitively set various parameters of the verification environment without manually writing code, thereby improving configuration efficiency and visualization.

[0181] This API configuration interface 202 can be used to provide the above-mentioned... Figure 3 It provides multiple function call entry points and supports scripted batch operation functionality.

[0182] The API configuration interface 202 can directly drive the programmable topology management module 21 to perform the related operations described above, such as responding to user calls to the endpoint creation function of the programmable topology management module and generating the first topology configuration instruction.

[0183] The programmable topology management module 21 can be used to parse commands issued by the graphical interface 201 and the API configuration interface 202, such as generating and deleting link mapping pairs. Furthermore, this programmable topology management module 21 can maintain relevant information about chips and links through the global link mapping relationship library 210. It implements bidirectional mapping between the source and target ends of each link and provides a query interface for obtaining the peer link, thereby ensuring the traceability of data flow and link consistency.

[0184] Furthermore, the programmable topology management module 21 can perform status monitoring, specifically through the maintenance, synchronization, and updating of status bits. During the verification process, the physical chip interface 231 will send status feedback to the global link mapping database 210 to confirm the "online status of the chip," "link valid / invalid," etc.

[0185] Optionally, when adding a new link, the programmable topology management module 21 will check for possible conflicts, such as duplicate connections to the same endpoint chip or simultaneous enabling of mutually exclusive links. If a conflict is detected, the system will prompt and prevent illegal configuration, thereby avoiding problems such as dual-drive and floating during simulation and ensuring the robustness of the verification environment.

[0186] Optionally, the architecture of the programmable topology management module 21 supports multi-chip (DUT) parallel verification scenarios. By predefining interface signatures and extended configurations for various chip types, it can automatically adapt to the connection requirements of different chips, achieving cross-chip interconnection management. This flexible extension mechanism facilitates testing multiple chips within the same framework, improving the reusability of the verification environment.

[0187] The global link mapping library 210 is used to dynamically store all link mapping structures. Optionally, the aforementioned display function (display_sorted) can also be used to provide a snapshot of the link topology.

[0188] Storage layer 22 is used to actually store the various link mapping pairs of the global link mapping relationship library 210.

[0189] Optionally, the execution layer 23 of the verification environment includes: a data routing interface group 230 and a physical chip interface 231.

[0190] The data routing interface group 230 is used to call the peer query function (get_peer) to query the global link mapping relationship library 210 to obtain the query results. This allows them to obtain status information maintained by the global link mapping relationship library 210, such as the chip's online status and link validity / invalidity.

[0191] In addition, the data routing interface group 230 can also adapt to different chip interface protocols.

[0192] The data routing interface group 230 is also used for sending and receiving data between chips.

[0193] To achieve the steps and corresponding technical effects of the above examples, this application also provides a possible implementation of a multi-chip link management device, specifically, Figure 13 This is a schematic diagram of a multi-chip link management device provided in an embodiment of the present invention. See also: Figure 13The multi-chip link management device 30 includes: a creation module 301, an acquisition module 302, a query module 303, and a transmission module 304.

[0194] Create module 301, which is used to create a programmable topology management module. The programmable topology management module contains a global link mapping relationship library for storing links.

[0195] The acquisition module 302 is used to respond to the user's topology configuration command, obtain the link mapping pair in the topology configuration command; the link mapping pair represents the two endpoint chip identifiers in the link to be added; add the link mapping pair to the global link mapping relationship library; respond to the data transmission request between chips, and obtain the target link and the sending chip identifier of the target link according to the data transmission request; the sending chip identifier is one of the two endpoint chip identifiers of the target link, and the sending chip identifier represents the sending chip of the target link.

[0196] The query module 303 is used to query the receiver chip identifier of the target link in the global link mapping relationship database; the receiver chip identifier represents the receiver chip of the target link.

[0197] The transmission module 304 is used to route the verification data of the data transmission request to the receiving chip through the target link.

[0198] Optionally, module 301 is created to obtain at least one link mapping structure to generate a global link mapping relationship library; and a programmable topology management module is created based on the global link mapping relationship library.

[0199] Optionally, the acquisition module 302 is specifically used to respond to the user's call to the endpoint creation function of the programmable topology management module, generate a first topology configuration instruction, and obtain a link mapping pair according to the first topology configuration instruction; and / or, respond to the user's input of a second topology configuration instruction through a graphical interface, the second topology configuration instruction representing the topology drawing between multiple chips, and generate a topology configuration code corresponding to the topology drawing; and obtain a link mapping pair according to the topology configuration code.

[0200] Optionally, the global link mapping database also maintains a status bit for each link mapping pair, which indicates whether the corresponding link mapping pair is valid or invalid. The global link mapping database also maintains the online status of each endpoint chip. Figure 13 On this basis, Figure 14 This is a schematic diagram of another multi-chip link management device provided in an embodiment of the present invention. See also: Figure 14 The device also includes a function call module 305.

[0201] The function call module 305 is used to add new link mapping pairs to the global link mapping relationship library by calling the add function according to the user's add instruction; or delete the link mapping pairs to be deleted from the global link mapping relationship library by calling the delete function according to the user's delete instruction; or update the status bit of each link mapping pair in the global link mapping relationship library by calling the link update function; or update the online status of each endpoint chip in the global link mapping relationship library by calling the chip update function.

[0202] Optionally, the function call module 305 is also used to respond to a query command by calling a function to query the peer information of the target endpoint in the link mapping pair corresponding to the query command in the global link mapping relationship library; and / or, in response to a display command, to display at least one link mapping pair in the global link mapping relationship library by calling a display function.

[0203] Please see Figure 15 , Figure 15 This is a schematic structural block diagram of an electronic device provided in an embodiment of this application. The electronic device 40 includes a memory 401, a processor 402, a communication interface 403, and a chip array 404. The memory 401, processor 402, and communication interface 403 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The memory 401 can be used to store software programs and modules, such as the program instructions / modules corresponding to the multi-chip link management device 30 provided in this application embodiment. The processor 402 executes various functional applications and data processing by executing the software programs and modules stored in the memory 401. The communication interface 403 can be used for signaling or data communication with other node devices.

[0204] The memory 401 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0205] Processor 402 can be an integrated circuit chip with signal processing capabilities. Processor 402 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0206] The communication interface 403 is used to connect the processor 402 and the chip array 404.

[0207] Chip array 404 may contain one or more chips to be verified, such as GPU chips, NPU chips, and memory chips.

[0208] Understandable. Figure 15 The structure shown is for illustrative purposes only; the electronic device may also include components that are more advanced than those shown. Figure 15 The components shown may include more or fewer components, such as a programmable switching matrix (dynamic reconfiguration of physical links), a power management module (e.g., controlling chip status using set_chip_online_status), a status monitoring interface (status bit synchronization), etc., or have similar features. Figure 15 The different configurations shown. Figure 15 The components shown can be implemented using hardware, software, or a combination thereof.

[0209] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0210] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0211] If a function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0212] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0213] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for multi-chip link management in a multi-chip verification environment, the method comprising: The method comprises the following steps: creating a programmable topology management module, wherein the programmable topology management module comprises a global link mapping relationship database for storing links; in response to a user calling an endpoint creation function of the programmable topology management module, generating a first topology configuration instruction, and obtaining a link mapping pair according to the first topology configuration instruction; and / or, in response to a second topology configuration instruction input by a user through a graphical interface, the second topology configuration instruction representing a topology drawing between multiple chips, and generating a topology configuration code corresponding to the topology drawing; obtaining a link mapping pair according to the topology configuration code; the link mapping pair representing two endpoint chip identifiers in a link to be added; adding the link mapping pair to the global link mapping relationship database; in response to a data transmission request between chips, obtaining a target link and a sending end chip identifier of the target link according to the data transmission request; the sending end chip identifier being one of two endpoint chip identifiers of the target link, representing a sending end chip of the target link; querying a receiving end chip identifier of the target link in the global link mapping relationship database; the receiving end chip identifier representing a receiving end chip of the target link; routing verification data of the data transmission request to the receiving end chip through the target link.

2. The method of claim 1, wherein, The step of creating the programmable topology management module comprises: obtaining at least one link mapping structure to generate the global link mapping relationship database; creating the programmable topology management module according to the global link mapping relationship database.

3. The method of claim 1, wherein, The global link mapping relationship database also maintains a state bit of each link mapping pair, and the state bit is used to indicate that the corresponding link mapping pair is valid or invalid; the global link mapping relationship database also maintains an online state of each endpoint chip; the method further comprises: according to a user's increase instruction, adding a new link mapping pair in the global link mapping relationship database by calling an adding function; or, according to a user's deletion instruction, deleting a link mapping pair to be deleted in the global link mapping relationship database by calling a deleting function; or, updating the state bit of each link mapping pair in the global link mapping relationship database through a link updating function; or, updating the online state of each endpoint chip in the global link mapping relationship database through a chip updating function.

4. The method of claim 1, wherein, The method further comprises: in response to a query instruction, querying opposite end information of a target endpoint in a link mapping pair corresponding to the query instruction in the global link mapping relationship database by calling a function; and / or, in response to a display instruction, displaying at least one link mapping pair in the global link mapping relationship database by calling a display function.

5. In a multi-chip verification environment, a multi-chip link management apparatus, comprising: The method comprises the following steps: creating a module, an obtaining module, a querying module and a transmission module; the creating module is configured to create a programmable topology management module, wherein the programmable topology management module comprises a global link mapping relationship database for storing links; The acquisition module is configured to generate a first topology configuration instruction in response to a user calling an endpoint creation function of the programmable topology management module, and obtain a link mapping pair according to the first topology configuration instruction; and / or generate a topology configuration code corresponding to a topology drawing between a plurality of chips in response to a user inputting a second topology configuration instruction through a graphical interface, the second topology configuration instruction representing the topology drawing. The topology configuration code is used to obtain a link mapping pair, and the link mapping pair represents two endpoint chip identifiers in a link to be added. The link mapping pair is added to the global link mapping relationship database. In response to a data transmission request between chips, a target link and a sending endpoint chip identifier of the target link are obtained according to the data transmission request. The sending endpoint chip identifier is one of two endpoint chip identifiers of the target link and represents a sending endpoint chip of the target link. The query module is configured to query a receiving endpoint chip identifier of the target link in the global link mapping relationship database. The receiving endpoint chip identifier represents a receiving endpoint chip of the target link. The transmission module is configured to route verification data of the data transmission request to the receiving endpoint chip through the target link.

6. The apparatus of claim 5, wherein, The creation module is specifically configured to obtain at least one link mapping structure to generate the global link mapping relationship database, and create the programmable topology management module according to the global link mapping relationship database.

7. The apparatus of claim 5, wherein, The global link mapping relationship database further maintains a state bit of each link mapping pair, and the state bit is used to indicate that the corresponding link mapping pair is valid or invalid. The global link mapping relationship database further maintains an online state of each endpoint chip, and further includes a function calling module. The function calling module is configured to add a new link mapping pair in the global link mapping relationship database by calling an adding function according to an adding instruction of a user, or delete a link mapping pair to be deleted in the global link mapping relationship database by calling a deleting function according to a deleting instruction of the user, or update the state bit of each link mapping pair in the global link mapping relationship database by calling a link updating function, or update the online state of each endpoint chip in the global link mapping relationship database by calling a chip updating function.

8. An electronic device, comprising: The memory is configured to store one or more programs. The processor is configured to verify chips in a chip array through the communication interface when the one or more programs are executed by the processor, so as to implement the method in any one of claims 1-4. The memory is configured to store one or more programs. The processor is configured to verify chips in a chip array through the communication interface when the one or more programs are executed by the processor, so as to implement the method in any one of claims 1-4.

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