PC value log generation method

Abstract

The embodiment of the invention provides a PC value log generation method, and relates to the technical field of storage. The method comprises the following steps: acquiring a program counter value output by a central processing unit core; compressing the program counter values to generate program counter value log data packets with specified formats corresponding to the program counter values; combining the generated one or more program counter value log data packets to obtain a combined data packet; and transmitting the combined data packet to a memory. The program counter value sequence collected by the program counter value method is compressed to generate the program counter value log data packet with the specified format, and the total size of the program counter value log data packet is smaller than the size of the program counter value sequence, so that the bandwidth for transmitting the program counter value is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, and in particular to a PC value log generation method. BACKGROUND

[0002] The control component of an electronic device includes one or more CPUs (Central Processing Units), and each CPU includes one or more CPU cores. The CPU cores are real physical processing units, and each CPU core can work independently and in parallel. For example, the CPU cores execute a firmware program during work, and output a PC value of each instruction of the firmware program. The PC value is the value of the program counter of the CPU core, and represents the address of the instruction submitted by the CPU core. The instruction submitted by the CPU core is the instruction that is completed by the CPU core and makes the execution result take effect in the CPU core. The sequence of PC values represents the order of execution of each instruction of the CPU core, so that the process of the CPU core executing the firmware program can be restored by analyzing the PC values, and the firmware program and the correctness of the control component can be identified. For this purpose, as shown in the prior art, the control component provides a program counter value log unit (referred to as a PC value log unit), which collects the PC values output by each CPU core during the work of the control component, generates a PC value log in chronological order, and writes the PC value log into a memory such as a DRAM (Dynamic Random Access Memory) so that a host computer can obtain the PC value log. The PC value log can be used to analyze the work process of the control component, debug the firmware, repair defects of the control component, and simulate the behavior of the control component. Figure 1

[0003] However, the CPU core works at a high frequency, for example, 1 GHz. Each CPU core can submit multiple instructions per clock cycle, so that a high bandwidth is required to output the PC value log during the work of the CPU core. Taking the case that the control component includes two CPU cores, the working frequency is 1 GHz, and the length of each PC value is 48 bits as an example, the two CPU cores generate 10^9*2*6 bytes of PC values per second, and at least 12 GB of bandwidth is required to record the PC values. When the number of CPU cores increases, the bandwidth required to record the PC values further increases. The bandwidth of the control component is a limited resource, which is mainly used to realize the functions of the control component itself. Therefore, it is necessary to reduce the bandwidth required to record the PC value log and reduce the competition for the bandwidth resource of the control component. SUMMARY

[0004] To solve the above technical problems or at least partially solve the above technical problems, the embodiments of the present application provide a PC value log generation method and a program counter value log unit.​

[0005] The PC value log generation method provided by the embodiments of the present application comprises: collecting a program counter value output by a central processor core; compressing the program counter value to generate a program counter value log data packet with a specified format corresponding to each program counter value; and combining one or more generated program counter value log data packets to obtain a combined data packet.

[0006] Optionally, the program counter value log data packet with the specified format comprises a packet format symbol bit and a data bit; the packet format symbol bit represents the type of the program counter value log data packet; and the data bit records a value related to the program counter value.

[0007] Optionally, the generation of the program counter value log data packet with the specified format corresponding to the program counter value comprises: taking the value of all bit positions of the program counter value or the value of specified bit positions in the program counter value as the value recorded by the data bit.

[0008] Optionally, the generation of the program counter value log data packet with the specified format corresponding to the program counter value comprises: taking the difference between two adjacent program counter values or the value of specified bit positions in the difference as the value recorded by the data bit of the program counter value log data packet corresponding to the latter program counter value of the two adjacent program counter values.

[0009] Optionally, the generation of the program counter value log data packet with the specified format corresponding to the program counter value comprises: taking the value of all bit positions of the first program counter value collected by each power-on start as the value recorded by the data bit of the program counter value log data packet corresponding to the first program counter value.

[0010] Optionally, the generation of the program counter value log data packet with the specified format corresponding to the program counter value comprises: determining the type of the program counter value log data packet corresponding to the latter program counter value of two adjacent program counter values according to the comparison result of the two adjacent program counter values.

[0011] Optionally, the generation of the program counter value log data packet with the specified format corresponding to each program counter value comprises: determining the range of bit positions that have changed in two adjacent program counter values, and determining the type of the program counter value log data packet corresponding to the latter program counter value of the two adjacent program counter values according to the range of bit positions that have changed.

[0012] Optionally, the generating the program counter value log data packet with the specified format corresponding to the program counter value comprises: in response to the two adjacent program counter values being the same, generating the program counter value log data packet corresponding to one of the two adjacent program counter values.

[0013] Optionally, the program counter value log data packet comprises one or more of the following types: a first data packet, a second data packet, and a third data packet; wherein the first data packet has a size of 16 bits, the second data packet has a size of 32 bits, and the third data packet has a size of 64 bits.

[0014] Optionally, the generating the program counter value log data packet with the specified format corresponding to each of the program counter values comprises: generating the third data packet for the first program counter value collected at each power-on start.

[0015] Optionally, the generating the program counter value log data packet with the specified format corresponding to each of the program counter values comprises: if the changed bit position between the two adjacent program counter values is within the bit position range recordable by the data bit of the first data packet, generating the first data packet for the later program counter value of the two adjacent program counter values; or, if the changed bit position between the two adjacent program counter values is beyond the bit position range recordable by the data bit of the first data packet and within the bit position range recordable by the data bit of the second data packet, generating the second data packet for the later program counter value of the two adjacent program counter values; or, if the changed bit position between the two adjacent program counter values is beyond the bit position range recordable by the data bit of the second data packet, generating the third data packet for the later program counter value of the two adjacent program counter values.

[0016] Optionally, the size of the combined data packet is consistent with the bit width of the bus for transmitting the combined data packet.

[0017] Optionally, the combining the one or more generated program counter value log data packets to obtain a combined data packet comprises: if the total size of the N continuously generated program counter value log data packets is consistent with the size of the combined data packet, combining the N continuously generated program counter value log data packets to obtain the combined data packet, N being a positive integer not less than 1; or, if the total size of the N continuously generated program counter value log data packets is smaller than the size of the combined data packet and the total size of the N+1 continuously generated program counter value log data packets is greater than the size of the combined data packet, combining the N continuously generated program counter value log data packets and filling invalid data in the combined data packet after the N program counter value log data packets are combined.

[0018] Optionally, the size of the combined data packet is 64 bits; if one third data packet, two second data packets and four first data packets are successively generated, the third data packet is taken as a combined data packet, the two second data packets are combined as a combined data packet, and the four first data packets are combined as a combined data packet; or, if one second data packet, one first data packet and one third data packet are successively generated, the second data packet, the first data packet and 16 bits of invalid data are combined as a combined data packet, and the third data packet is taken as a combined data packet; or, if two first data packets and one third data packet are successively generated, the two first data packets and 32 bits of invalid data are combined as a combined data packet, and the third data packet is taken as a combined data packet.

[0019] Optionally, the program counter value output by the central processor core is collected according to a selected specified collection mode.

[0020] Optionally, the specified collection mode includes a continuous mode, an interval trigger mode and / or a threshold trigger mode; wherein,

[0021] The continuous mode is to continuously collect the program counter value output by the central processor core at each clock cycle;

[0022] The interval trigger mode is to collect the program counter value output by the central processor core that belongs to a preset program counter value interval; and / or

[0023] The threshold trigger mode is to continuously or periodically collect the program counter value output by the central processor core in response to detecting that the program counter value output by the central processor core is greater than a preset threshold.

[0024] Optionally, the method further includes: adding the combined data packet to a queue, and transmitting the combined data packet in the queue to a memory; detecting whether the queue is overflowed, and stopping collecting the program counter value output by the central processor core in response to detecting that the queue is overflowed.

[0025] Optionally, the method further includes: in response to detecting that a generation condition of a related data packet is met, generating the related data packet with a specified format, and adding the related data packet to the queue and transmitting the related data packet in the queue to a memory.

[0026] Optionally, the related data packet includes one or more of the following: a synchronization data packet, a timestamp data packet, an overflow data packet and a timeout data packet;

[0027] The generating the relevant data packet in the specified format in response to detecting that the generation condition of the relevant data packet is met comprises: generating a synchronization data packet in response to detecting that the program counter value output by the central processing unit core is started to be collected; generating a timestamp data packet in response to a specified time interval or a specified number of program counter values being collected; generating an overflow data packet in response to detecting that the queue is overflowed; and / or generating a timeout data packet in response to no program counter value log data packet being generated for a specified length of time.

[0028] Optionally, the synchronization data packet comprises a packet format symbol bit, an ID bit, a channel bit, and a data bit; the timestamp data packet comprises a packet format symbol bit, an ID bit, and a data bit; the overflow data packet comprises a packet format symbol bit, an ID bit, a specified value bit, and a data bit; and the timeout data packet comprises one of the timestamp data packet and one of the first data packet.

[0029] The data bits of the synchronization data packet, the timestamp data packet, and the overflow data packet respectively record time information of generating the synchronization data packet, the timestamp data packet, and the overflow data packet, and the specified value bit is used to record a preset specified value.

[0030] Optionally, the method further comprises: merging one or more of the combined data packets and one or more of the relevant data packets to obtain a merged data packet; adding the merged data packet to the queue, the merged data packet being consistent with the bit width of a bus for transmitting the merged data packet; and transmitting the merged data packet in the queue to a memory.

[0031] Optionally, the merging one or more of the combined data packets and one or more of the relevant data packets to obtain a merged data packet comprises: if the total size of M continuously generated combined data packets and / or relevant data packets is consistent with the size of the merged data packet, merging the M continuously generated combined data packets and / or relevant data packets to obtain the merged data packet, wherein M is a positive integer not less than 1; if the total size of the M continuously generated combined data packets and / or relevant data packets is less than the size of the merged data packet and the total size of M+1 continuously generated combined data packets and / or relevant data packets is greater than the size of the merged data packet, merging the M combined data packets and / or relevant data packets and filling invalid data in the data packet obtained by merging the M combined data packets and / or relevant data packets to obtain the merged data packet.

[0032] Optionally, the collecting the program counter value output by the central processing unit core comprises: collecting each program counter value output by the central processing unit core.

[0033] In a second aspect, an embodiment of the present invention further provides a program counter value log unit, which is coupled to a central processing unit to execute the PC value log generation method provided in any embodiment of the present application.

[0034] The PC value log generation method provided in the embodiment of the present application compresses the program counter value output by the central processing unit core, generates a program counter value log data packet with a specified format corresponding to each program counter value, and then combines various program counter value log data packets with a specified format to achieve compression of the program counter value in certain scenarios, reduce the size of the program counter value sequence, and thereby reduce the bandwidth for transmitting the program counter value log data packet. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0036] Figure 1 Shows a schematic structural diagram of a control component in the prior art;

[0037] Figure 2 A schematic diagram of the structure of a PC value log unit according to an embodiment of the present application is shown;

[0038] Figure 3A A schematic diagram showing the data format of an S packet according to an embodiment of the present application is shown;

[0039] Figure 3B A schematic diagram showing the data format of an L packet according to an embodiment of the present application is shown;

[0040] Figure 3C A schematic diagram showing the data format of the A packet according to an embodiment of the present application;

[0041] Figure 4 A schematic diagram of a process of processing a PC value by a PC value log unit according to an embodiment of the present application is shown;

[0042] Figure 5 A schematic structural diagram of a control component according to an embodiment of the present application is shown;

[0043] Figure 6 A schematic structural diagram of a control component according to another embodiment of the present application is shown;

[0044] Figure 7 A schematic diagram showing the structure of a PC value log unit according to another embodiment of the present application is shown;

[0045] Figure 8 Fig. 1 shows a flowchart of the PC value log unit processing PC values according to an embodiment of the present application;

[0046] Figure 9 Fig. 2 shows a structure diagram of the PC value log unit according to an embodiment of the present application;

[0047] Figure 10 Fig. 3 shows a structure diagram of the PC value log unit according to another embodiment of the present application;

[0048] Figure 11A Fig. 4 shows a diagram of the synchronization data packet according to an embodiment of the present application;

[0049] Figure 11B Fig. 5 shows a diagram of the timestamp data packet according to an embodiment of the present application;

[0050] Figure 11C Fig. 6 shows a diagram of the overflow data packet according to an embodiment of the present application;

[0051] Figures 12-16 Fig. 7 shows a flowchart of the PC value log unit processing PC values according to an embodiment of the present application;

[0052] Figure 17 Fig. 8 shows a flowchart of the PC value log unit processing PC values according to an embodiment of the present application;

[0053] Figure 18 Fig. 9 shows a structure diagram of the control component according to an embodiment of the present application;

[0054] Figure 19 Fig. 10 shows a flowchart of the control component processing PC values according to an embodiment of the present application. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0056] Figure 2 Fig. 1 shows a structure diagram of the PC value log unit according to an embodiment of the present application. As shown in Fig. 1, the PC value log unit 200 includes a collection subunit 201, a compression subunit 202 and a combination subunit 203. Figure 2

[0057] The collection subunit 201 is coupled with the CPU core to collect the PC values output by the CPU core.

[0058] ​The CPU core outputs the PC value of the instruction submitted in the current clock cycle in each clock cycle. Depending on the micro-architecture adopted by the CPU core, the maximum number of instructions submitted by the CPU core in each clock cycle can be different, for example, the maximum number of instructions submitted by the CPU core can be 1, 2, 3 or 4. Correspondingly, the number of PC values output by the CPU core in each clock cycle can also be different, and the number of PC values collected by the collection subunit 201 in each clock cycle is also different.

[0059] In an optional embodiment, the PC log channels are used to distinguish the PC values of different instructions submitted by the CPU core in the same clock cycle. For example, the CPU core processes a maximum of two instructions in each clock cycle, and correspondingly outputs a maximum of two PC values, and the PC log channels corresponding to the two PC values are CH0 and CH1 respectively. The number of PC value log channels represents the maximum number of instructions submitted by the CPU core in each clock cycle, but in a certain clock cycle, the actual number of instructions submitted by the CPU core can be less than the number of PC log channels. For example, the number of PC log channels of the CPU core is 4, which means that the CPU core submits a maximum of four instructions in each clock cycle, and the CPU core outputs a maximum of four PC values, and the CPU core outputs a maximum of four PC values in a certain clock cycle. 0, 1, 2, 3 or 4, and the collection subunit 201 collects a maximum of 4 PC values, and the collection subunit 201 collects a maximum of 4 PC values in a certain clock cycle. 0, 1, 2, 3 or 4.

[0060] The compression subunit 202 is coupled to the collection subunit 201, and compresses the PC value sequence formed by one or more PC values collected by the collection subunit 201, and generates the corresponding program counter value log data packet (hereinafter referred to as PC value log data packet) having a specified format for each PC value. Optionally, the specified format of the PC value log data packet generated by the compression subunit 202 is defined by a tool processing the PC value log, so that the tool processing the PC value log can obtain the correct PC value sequence from the data packet having the specified format.

[0061] In an optional embodiment, the specified format of the PC value log data packet generated by the compression subunit 202 includes a packet format symbol bit, an ID bit, a channel bit and a data bit. The packet format symbol bit represents the type of the program counter value log data packet; the ID bit represents the ID of the central processing unit core outputting the program counter value, the channel bit represents the program counter value log channel of the central processing unit core outputting the program counter value, and the data bit records the numerical value related to the program counter value. Optionally, the data bit is used to record the numerical value of all bits of the program counter value or the numerical value of the specified bit. Still optionally, the data bit is used to record the difference between the adjacent two program counter values or the numerical value of the specified bit in the difference, and the data bit is the data bit of the program counter value log data packet of the latter one of the adjacent two program counter values.

[0062] As an optional example, the PC value log data packet with a specified format generated by the compression subunit 202 includes data packets in multiple formats. For example, the PC value log data packet includes an S data packet (hereinafter collectively referred to as an S packet), an L data packet (hereinafter collectively referred to as an L packet), and an A data packet (hereinafter collectively referred to as an A packet).

[0063] Figure 3A A schematic diagram showing the data format of an S packet according to an embodiment of the present application is shown.

[0064] like Figure 3A As shown, the S packet size is 16 bits ( Figure 3A The S packet shown includes bits 0 to 15. Bits 0 through 2 are packet format bits, used to identify the type of data packet. If a data packet is 16 bits and bits 0 through 2 are 010, then the data packet is an S packet. Bits 3 through 5 are ID bits, representing the ID (Core ID) of the CPU core that submitted the PC value corresponding to the data packet. Bit 6 is the channel bit, representing the PC log channel that submitted the PC value corresponding to the data packet. Bits 7 through 15 are data bits, used to record data about the PC value itself, such as the values ​​of all bits of the PC value or the values ​​of specific bits within the PC value. For example, the values ​​recorded by bits 7 through 15 are denoted as Addr[a:b], where a represents the ath bit of the PC value and b represents the bth bit of the PC value. For example, bits 7 through 15 in the S packet record the values ​​of bits 1 through 9 in the PC value sequence. Optionally, the values ​​of the first to ninth bits in the PC value sequence can be recorded as Addr[9:1]( Figure 3A In the example, Addr[1] and Addr[9:2] are combined to get Addr[9:1]).

[0065] In an optional embodiment, the 7th to 15th bits in the S packet are used to record data calculated by the PC value, such as recording the difference between two adjacent PC values ​​or the numerical value of a specified bit in the difference. The S packet generated in this case represents a PC value log data packet corresponding to the latter PC value of the two adjacent PC values. As an optional example, the 7th to 15th bits in the S packet are used to record the numerical values ​​of the 1st to 9th bits in the difference between PC2 (the latter PC value) and PC1 (the previous PC value).

[0066] Figure 3B A schematic diagram showing the data format of an L packet according to an embodiment of the present application is shown.

[0067] like Figure 3B As shown, the size of the L packet is 32 bits (as Figure 3BThe L packet includes 0-31 bits as shown. The 0th bit-2nd bit in the L packet is a packet format symbol bit, which is used to represent the type of the data packet. For example, if a data packet is 32 bits, and the 0th bit-2nd bit is 001, the data packet is an L packet. The 3rd bit-5th bit is an ID bit, which represents the ID of the CPU core that submits the PC value corresponding to the data packet. The 6th bit is a channel bit, which represents the PC log channel of the PC value corresponding to the data packet. The 7th bit-31st bit is a data bit, which is used to record data of the PC value itself, for example, the value of all bits of the PC value or the value of a specified bit in the PC value. For example, the 7th bit-31st bit in the L packet records the value of the 1st bit-25th bit of the PC value. Alternatively, the value of the 1st bit-25th bit in the PC value sequence can be recorded as Addr[25:1].

[0068] For another example, the 7th bit-31st bit in the L packet is used to record data calculated from the PC value, for example, the difference between two adjacent PC values or the value of a specified bit in the difference. In this case, the generated L packet represents the PC value log data packet corresponding to the latter one of the two adjacent PC values. As an optional example, the 7th bit-31st bit in the L packet is used to record the value of the 1st bit-25th bit in the difference between PC2 (the latter PC value) and PC1 (the former PC value).

[0069] Figure 3C A diagram showing the data format of the A packet of the embodiment of the application is shown.

[0070] As shown in Figure 3C The size of the A packet is 64 bits as shown in Figure 3B The A packet includes 0-63 bits as shown. The 0th bit-2nd bit in the A packet is a packet format symbol bit, which is used to represent the type of the data packet. For example, if a data packet is 64 bits, and the 0th bit-2nd bit is 100, the data packet is an A packet. The 3rd bit-5th bit is an ID bit, which represents the ID of the CPU core that submits the PC value corresponding to the data packet. The 6th bit is a channel bit, which represents the PC log channel of the PC value corresponding to the data packet. The 7th bit-53rd bit is a data bit, which is used to record data of the PC value itself, for example, the value of all bits of the PC value or the value of a specified bit in the PC value. For example, the 7th bit-53rd bit in the A packet records the value of the 1st bit-47th bit of the PC value. Alternatively, the value of the 1st bit-47th bit of the PC value can be recorded as Addr[47:1].

[0071] For example, the 7th bit to the 53rd bit of the A packet is used to record data calculated by the PC value, such as recording the difference between two adjacent PC values or the value of a specified bit in the difference. In this case, the A packet generated represents the PC value log data packet corresponding to the latter PC value of the two adjacent PC values. As an optional example, the 7th bit to the 53rd bit of the A packet is used to record the value of the 1st bit to the 47th bit in the difference between PC2 (the latter PC value) and PC1 (the former PC value). The 54th bit to the 53rd bit of the A packet is not used and can be a default value such as 0.

[0072] It should be understood that, in the process of generating the PC value log data packet corresponding to each PC value by the compression subunit 202 according to each PC value collected by the collection subunit 201, the PC value log data packet generated for the first PC value collected by the collection subunit 201 each time the collection subunit 201 is powered on should record the value of all bits of the PC value. For example, the A packet can record the value of all bits of a PC value, and the compression subunit 202 processes the PC value sequence. The PC value log data packet generated for the first PC value should be an A packet (the A packet records the value of all bits of the first PC value), and the PC value log data packet corresponding to other PC values can be one of an S packet, an L packet, and an A packet.

[0073] As an optional example, the PC value output by the CPU core is 48 bits, and the PC value sequence generated by the CPU core in a certain period of time is [10000, 10002, 10004, 10006, 10008, 10010]. The PC value log data packet corresponding to each PC value is generated by processing each PC value in the PC value sequence. The first PC value log data packet needs to carry the complete PC value, so the first PC value 10000 in the PC value sequence [10000, 10002, 10004, 10006, 10008, 10010] generates an A packet. The difference between the subsequent PC value and the previous PC value is 2, and the bit position that changes between the two adjacent PC values is within the bit position range that can be recorded by the data bit of an S packet. The S packet can carry the difference, so the PC value log data packet corresponding to the subsequent PC value is an S packet. Therefore, the PC value log data packets generated corresponding to the PC value sequence [10000, 10002, 10004, 10006, 10008, 10010] are as follows:

[0074] PC value log data packet 1: A packet (carrying PC value = 10000, the PC value is 48 bits)

[0075] PC value log data packet 2: S packet (carrying PC difference = 2)

[0076] PC value log data packet 3: S packet (carrying PC difference = 2)

[0077] PC value log data packet 4: S packet (carrying PC difference = 2)

[0078] PC value log data packet 5: S packet (carrying PC difference = 2)

[0079] PC value log data packet 6: S packet (carrying PC difference = 2)

[0080] The size of the PC value sequence [10000, 10002, 10004, 10006, 10008, 10010] is 36 bytes, the total size of the generated PC value log data packet sequence (PC value log data packet 1-PC value log data packet 6) is 18 bytes, and the size of the PC value log data packet sequence generated by the PC value log unit is smaller than the size of the PC value sequence. Therefore, the PC value log unit realizes compression of the PC value sequence by combined use of A packets, S packets and L packets in the process of processing PC values in the PC value sequence.

[0081] In order to recover the correct PC value sequence from the PC value log data packets 1-6, for the received A packet, the PC value carried by the A packet is taken as the current PC value, and for the received S packet, the PC difference carried by the S packet is added to the previous current PC value to obtain a new current PC value.

[0082] For example, the PC value sequence generated by the CPU core in a certain period of time is [10000, 10002, 11004, 11006, 11008, 12010]. Compression of the PC value sequence is realized by combined use of A packets, S packets and L packets to generate PC value log data packets. The data bits in the A packets, S packets and L packets record the difference between adjacent two PC values. The first PC value log data packet needs to carry a complete PC value, so the first PC value 10000 generates an A packet. The difference between the third PC value 11004 and the second PC value 10002 is 1002, which exceeds the bit range that can be recorded by the data bits of the S packet, but does not exceed the bit range that can be recorded by the data bits of the L packet. The 16-bit S packet cannot carry the difference, but the 32-bit L packet can carry the difference, so the format of the PC value log data packet corresponding to the third PC value is L packet, and the formats of the PC value log data packets corresponding to the second PC value, the fourth PC value, the fifth PC value and the sixth PC value are S packets.

[0083] The PC value sequence [10000, 10002, 11004, 11006, 11008, 12010] corresponds to a plurality of PC value log data packets generated in turn as follows:

[0084] PC value log data packet 1: A packet (carrying PC value = 10000, PC value size is 48 bits)

[0085] PC value log data packet 2: S packet (carrying PC difference = 2)

[0086] PC value log data packet 3: L packet (carrying PC difference = 1002)

[0087] PC value log data packet 4: S packet (carrying PC difference = 2)

[0088] PC value log data packet 5: S packet (carrying PC difference = 2)

[0089] PC value log data packet 6: S packet (carrying PC difference = 2)

[0090] The size of the PC value sequence [10000, 10002, 11004, 11006, 11008, 12010] is 36 bytes, and the total size of the generated PC value log data packet sequence (PC value log data packet 1-PC value log data packet 6) is 20 bytes.

[0091] In the embodiments of the present application, the PC value log packets with the specified format are generated by using the A packet, the S packet and the L packet in combination to compress the PC value sequence, and the tool for processing the PC log can recover the correct PC value sequence from the PC value log data packets.

[0092] In the optional embodiments, before the compression subunit 202 generates the PC value log data packets with the specified format by compressing the PC value sequence, the compression subunit 202 further includes a de-duplication process on the PC value sequence. For example, in the case that there are N identical PC values in the PC value sequence (N is a positive integer greater than 1), the compression subunit 202 deletes the (N-1) identical PC values in the PC value sequence, and only one PC value is reserved in the PC value sequence. The compression subunit 202 generates the PC value log data packet with the specified format corresponding to each PC value in the de-duplicated PC value sequence.

[0093] In the optional embodiments, the compression subunit 202 further compresses the PC value sequence by using a compression algorithm (such as the Huffman compression algorithm), and generates the PC value log data packet with the specified format corresponding to each PC value.

[0094] Continuing to refer to Figure 2After the PC value log unit 200 collects the PC value (such as the PC value corresponding to the PC value log data packet) output by the CPU core, the PC value log unit 200 needs to store the collected PC value in the memory (such as the DRAM). The PC value log unit 200 and the memory transmit data through the bus. In different application scenarios, the bus width between the PC value log unit 200 and the memory can be different, for example, the bus width is 128 bits or 64 bits. The PC value log unit 200 generates the PC value log data packet with a size that is not necessarily consistent with the bus width. For example, the PC value log unit 200 generates the PC value log data packet with a specified format, and the size of the PC value log data packet is, for example, 32 bits, 16 bits, or 64 bits. However, when transmitting data through the bus, the size of the data packet needs to be consistent with the bus width. Therefore, the PC value log unit 200 is further provided with the combination sub-unit 203.

[0095] The combination sub-unit 203 is coupled with the compression sub-unit 202, combines the plurality of PC value log data packets generated by the compression sub-unit 202, and obtains a combination data packet with a specified size. The size of the combination data packet is consistent with the bus width coupled with the PC value log unit.

[0096] For example, the size of the PC value log data packet is not consistent with the bus width coupled with the PC value log unit. The combination sub-unit 203 combines the plurality of PC value log data packets into a combination data packet with a size consistent with the bus width, so as to write the PC value log data packet into the memory such as the DRAM through the bus. As an optional example, the size of the PC value log data packet is 16 bits, and the bus width is 256 bits. The combination sub-unit 203 needs to combine 16 PC value log data packets into one combination data packet.

[0097] The PC value log unit provided by the embodiment of the application generates the PC value log data packet corresponding to each PC value by compressing the PC value sequence collected by the collection sub-unit through the compression sub-unit. In some scenarios, the combination of the plurality of PC value log data packets (such as the S packet, the L packet, and the A packet) can realize the compression of the PC value, reduce the size of the PC value sequence, and further reduce the bandwidth of the PC value log data packet. In addition, the combination sub-unit combines the PC value log data packet into a combination data packet with a bus width, so as to store the combination data packet in the memory through the bus.

[0098] As an example, the collection sub-unit 201, the compression sub-unit 202, and the combination sub-unit 203 in the PC value log unit 200 provided by the embodiment of the application are hardware circuit units composed of hardware circuits. As long as the hardware circuit units can realize the corresponding functions, the composition of the hardware circuit units such as the collection sub-unit 201, the compression sub-unit 202, and the combination sub-unit 203 is not limited.

[0099] Figure 4 The flowchart of the PC value log unit processing PC value of an embodiment of the present application is shown. As shown, the process of the PC value log unit processing PC value includes: Figure 4

[0100] Step S401: The collection subunit collects the PC value output by the CPU core.

[0101] Step S402: The compression subunit compresses the PC value sequence formed by one or more PC values collected by the collection subunit, and generates the PC value log data packet corresponding to each PC value.

[0102] Step S403: The combination subunit combines one or more PC value log data packets to obtain a combination data packet. The combination data packet has a specified size, and the size is consistent with the bus bit width, for example, 64 bits, 128 bits or 256 bits.

[0103] Step S404: The combination subunit stores the combination data packet into the memory such as DRAM through the bus.

[0104] For step S403, if the bus bit width is 64 bits, the PC value log data packets received by the combination subunit are A packet (such as A1 packet), L packet, S packet (such as S1 packet), A packet (such as A2 packet), S packet (such as S2 packet), S packet (such as S3 packet), and S packet (such as S4 packet). Then, the combination subunit separately takes A1 packet as combination data packet 1; combines L packet and S1 packet as combination data packet 2, and L packet and S packet have 48 bits in common, so the combination data packet 2 also includes 16 bits of invalid data; separately takes A2 packet as combination data packet 3; combines S2 packet, S3 packet and S4 packet as combination data packet 4, and since S2 packet, S3 packet and S4 packet have 48 bits in common, the combination data packet 4 also includes 16 bits of invalid data. As an example, the invalid data in the combination data packet is located in the low bit of the combination data packet, for example, the 16 bits of invalid data in combination data packet 4 are located in 0-15 bits of combination data packet 4.

[0105] In an optional embodiment, multiple CPU cores are adopted in the control component of the electronic device, and a corresponding PC value log unit is set for each CPU core to collect and compress the PC value sequence output by the CPU core, and to generate a combination data packet. Wherein, the CPU cores in the control component are independent of each other, and one CPU core works while the other CPU cores may work or not work. The PC value log units are also independent of each other, and independently collect the PC value output by the corresponding CPU core and generate a combination data packet.

[0106] In the case where the control component includes multiple CPU cores, the combination data packet generated by one of the PC value log units is selected by a multiplexer or an arbitrator to be transmitted to the DRAM.​

[0107] As an optional example, as shown in Figure 5 , the control component of the electronic device includes 4 CPU cores, CPU core 0, CPU core 1, CPU core 2, and CPU core 3. A corresponding PC value log unit (which can be a PC value log unit as shown in Figure 2 , Figure 7 , Figure 9 or Figure 10 ) is set for each CPU core, and there are 4 PC value log units in total: PC value log unit 0, PC value log unit 1, PC value log unit 2, and PC value log unit 3. CPU core 0, CPU core 1, CPU core 2, and CPU core 3 work independently of each other, and PC value log unit 0, PC value log unit 1, PC value log unit 2, and PC value log unit 3 also independently collect the PC values output by the CPU cores coupled thereto. PC value log unit 0 collects and compresses the PC values output by CPU core 0 and generates a combined data packet. PC value log unit 1 collects and compresses the PC values output by CPU core 1 and generates a combined data packet. PC value log unit 2 collects and compresses the PC values output by CPU core 2 and generates a combined data packet. PC value log unit 3 collects and compresses the PC values output by CPU core 3 and generates a combined data packet.

[0108] As shown in Figure 5 , the control component further includes a multiplexer coupled to PC value log unit 0, PC value log unit 1, PC value log unit 2, and PC value log unit 3, which selects the combined data packet generated by one of PC value log unit 0, PC value log unit 1, PC value log unit 2, and PC value log unit 3 to store in a memory such as a DRAM. For example, the multiplexer stores the combined data packet generated by PC value log unit 0 in the memory at T1 period, stores the combined data packet generated by PC value log unit 1 in the memory at T2 period, stores the combined data packet generated by PC value log unit 2 in the memory at T3 period, and stores the combined data packet generated by PC value log unit 3 in the memory at T4 period.

[0109] In an optional embodiment, the control component of the electronic device comprises a plurality of CPU clusters, each of which comprises one or more CPU cores. The CPU clusters are independent of each other, and the operation of the CPU cores in one CPU cluster does not affect the operation of the CPU cores in another CPU cluster. The CPU cores in each CPU cluster are independent of each other. A corresponding PC value log unit is provided for each CPU core in each CPU cluster to collect, compress and generate a combined data packet of the PC values output by the corresponding CPU core. The PC value log units are independent of each other, and each PC value log unit independently collects the PC values of the corresponding CPU core and generates a combined data packet. Each CPU cluster corresponds to a multiplexer, and the multiplexer corresponding to each CPU cluster is used to transmit the combined data packet generated by one of the PC value log units corresponding to the CPU cluster to the DRAM. The multiplexers corresponding to each CPU cluster are independent of each other.

[0110] As an optional example, as shown in Figure 6 , the control component of the electronic device comprises two CPU clusters: CPU cluster 0 and CPU cluster 1. CPU cluster 0 comprises four CPU cores: CPU core 0, CPU core 1, CPU core 2 and CPU core 3. CPU cluster 1 comprises two CPU cores: CPU core 4 and CPU core 5. CPU cluster 0 and CPU cluster 1 are independent of each other. The CPU cores included in CPU cluster 0, CPU core 0, CPU core 1, CPU core 2 and CPU core 3, are independent of each other. The CPU cores included in CPU cluster 1, CPU core 4 and CPU core 5, are independent of each other.

[0111] As shown in Figure 6 , the control component further comprises six PC value log units (which can be the PC value log units shown in Figure 2 , Figure 7 , Figure 9 or Figure 10 ), namely PC value log unit 0, PC value log unit 1, PC value log unit 2, PC value log unit 3, PC value log unit 4 and PC value log unit 5. The six PC value log units are coupled to CPU core 0, CPU core 1, CPU core 2, CPU core 3, CPU core 4 and CPU core 5, respectively. PC value log unit 0 processes the PC values output by CPU core 0, PC value log unit 1 processes the PC values output by CPU core 1, PC value log unit 2 processes the PC values output by CPU core 2, PC value log unit 3 processes the PC values output by CPU core 3, PC value log unit 4 processes the PC values output by CPU core 4, and PC value log unit 5 processes the PC values output by CPU core 5.

[0112] As shown in Figure 6As shown, the control component further comprises multiplexer 1 and multiplexer 2. Multiplexer 1 corresponds to CPU cluster 0, and multiplexer 2 corresponds to CPU cluster 1. Multiplexer 0 and multiplexer 1 are independent of each other, and the operation of multiplexer 1 is not affected by multiplexer 0. Multiplexer 1 stores the combined data packet generated from one of PC value log unit 0, PC value log unit 1, PC value log unit 2, and PC value log unit 3 into DRAM. Multiplexer 2 stores the combined data packet generated from one of PC value log unit 4 and PC value log unit 5 into DRAM.

[0113] Figure 7 A structural schematic diagram of a PC value log unit of yet another embodiment of the present application is shown. As shown, the PC value log unit 700 comprises collection subunit 701, multiplexer 702, compression subunit 703, and combination subunit 704. The input end of the multiplexer is coupled to the output end of the collection subunit 701, and the output end of the multiplexer is coupled to the input end of the compression subunit 703. The output end of the compression subunit 703 is coupled to the input end of the combination subunit 704. Figure 7 The collection subunit 701 collects the PC value output by the CPU core. The collection subunit 701 comprises mode selection module 7011, continuous mode collection module 7012, interval trigger mode collection module 7013, and threshold trigger mode collection module 7014.

[0114] The mode selection module 7011 transmits the PC value from the CPU core to one of the continuous mode collection module 7012, the interval trigger mode collection module 7013, and the threshold trigger mode collection module 7014 according to whether the enable signal is valid. One of the continuous mode collection module 7012, the interval trigger mode collection module 7013, and the threshold trigger mode collection module 7014 collects the PC value output by the CPU core according to its corresponding collection mode. For example, the continuous mode collection module corresponds to a valid enable signal, and the mode selection module 7011 transmits the PC value output by the CPU core to the continuous mode collection module 7012, which collects the PC value by its corresponding collection mode. For another example, the interval trigger mode collection module 7013 corresponds to a valid enable signal, and the mode selection module 7011 transmits the PC value output by the CPU core to the interval trigger mode collection module 7013, which collects the PC value by its corresponding collection mode.

[0115]

[0116] ​As an example, the continuous mode collection module 7012 collects PC values output by the CPU core continuously, e.g., at every clock cycle. The interval triggered mode collection module 7013 collects PC values within a preconfigured PC value interval, e.g., the preconfigured PC value interval is [0, 10], and the interval triggered mode collection module 7013 collects PC values when the PC value output by the CPU core is between 0 and 10. The threshold triggered mode collection module 7014 collects PC values continuously and delivers the collected PC values to the multiplexer 702 when the PC value output by the CPU core is greater than a preconfigured threshold. Optionally, the threshold triggered mode collection module 7014 collects PC values continuously in response to detecting that the PC value output by the CPU core is greater than the preconfigured threshold. For example, if the threshold triggered mode collection module 7014 detects that the PC value output by the CPU core is greater than the preconfigured threshold, then the threshold triggered mode collection module 7014 collects PC values at every clock cycle. Still optionally, the threshold triggered mode collection module 7014 collects PC values periodically in response to detecting that the PC value output by the CPU core is greater than the preconfigured threshold. For example, if the threshold triggered mode collection module 7014 detects that the PC value output by the CPU core is greater than the preconfigured threshold, then the threshold triggered mode collection module 7014 collects PC values periodically according to a configured PC value collection interval, e.g., collecting PC values once every N clock cycles.

[0117] One of the continuous mode collection module 7012, the interval triggered mode collection module 7013, and the threshold triggered mode collection module 7014 delivers the collected PC values to the multiplexer 702. For example, the multiplexer 702 includes three input terminals coupled to the output terminals of the continuous mode collection module 7012, the interval triggered mode collection module 7013, and the threshold triggered mode collection module 7014, respectively, and an output terminal coupled to the input terminal of the compression subunit 703, and the multiplexer 702 delivers the PC value collected by one of the continuous mode collection module 7012, the interval triggered mode collection module 7013, and the threshold triggered mode collection module 7014 to the compression subunit 703.

[0118] The compression subunit 703 generates a PC value log data packet having a specified format according to each received PC value. As an example, the compression subunit 703 determines the format of the PC value log data packet corresponding to the current PC value according to the comparison result of the current received PC value and the last PC value, and generates the PC value log data packet corresponding to the current PC value according to the format of the PC value log data packet. As shown in FIG. 7B, the compression subunit 703 includes a current PC value register 7031, a last PC value register 7032, a data packet selection module 7033, and a data packet generation module 7034. Figure 7

[0119] ​The current PC value register 7031 records the current PC value received from the multiplexer 702. The last PC value register 7032 records the last PC value received from the multiplexer 702.

[0120] The data packet selection module 7033 compares the current PC value recorded by the current PC value register (denoted as PC value 2) with the last PC value recorded by the last PC value register (denoted as PC value 1), and selects the format of the PC value log data packet corresponding to the PC value 2 according to the comparison result. For example, the data packet selection module 7033 compares the PC value 2 with the PC value 1 bit by bit, determines the format of the PC value log data packet corresponding to the PC value 2 according to the comparison result of the PC value 2 and the PC value 1, and generates the PC value log data packet corresponding to the PC value 2 according to the determined format of the PC value log data packet, for example, the PC value log data packet corresponding to the PC value 2 is one of the S packet, the L packet and the A packet.

[0121] The data packet generation module 7034 generates the PC value log data packet corresponding to the current PC value according to the determined format of the PC value log data packet. The specific process of determining the format of the PC value log data packet corresponding to the PC value and generating the PC value log data packet corresponding to the current PC value by the data packet mode selection module 7033 is described below Figure 8 The above is not repeated here.

[0122] The combination subunit 704 combines one or more PC value log data packets output by the data packet generation module 7034 to generate a combined data packet, and stores the combined data packet into a memory such as a DRAM through a bus. The size of the combined data packet is consistent with the bus bit width used for transmitting the combined data packet.

[0123] The PC value log unit of the embodiment of the present application provides multiple PC value collection modes, and can provide diversified PC value collection modes for different scenarios to meet different requirements.

[0124] As an example, the collection subunit 701, the multiplexer 702, the compression subunit 703 and the combination subunit 704 in the PC value log unit 700 are hardware circuit units composed of hardware circuits. As long as the hardware circuit units of the collection subunit 701, the multiplexer 702, the compression subunit 703 and the combination subunit 704 can realize their corresponding functions, any hardware circuit units are acceptable, which are not limited here.

[0125] Figure 8 A flowchart of the PC value log unit of the embodiment of the present application processing the PC value is shown. As Figure 8 shown, the flowchart includes:

[0126] Step S801: The mode selection module 7011 delivers the PC value from the CPU core to one of the continuous mode collection module 7012, the interval trigger mode collection module 7013, the threshold trigger mode collection module 7014 according to whether the enable signal is valid (e.g., process (1) as shown in FIG. 7). Figure 7

[0127] Step S802: One of the continuous mode collection module 7012, the interval trigger mode collection module 7013, the threshold trigger mode collection module 7014 collects the PC value output by the CPU core and delivers the collected PC value to the multiplexer 702.

[0128] The mode selection module 7011 delivers the PC value from the CPU core to the continuous mode collection module 7012 in response to the enable signal corresponding to the continuous mode collection module being valid (e.g., process (2a) as shown in FIG. 7). Figure 7

[0129] The mode selection module 7011 delivers the PC value from the CPU core to the interval trigger mode collection module 7013 in response to the enable signal corresponding to the interval trigger mode collection module being valid (e.g., process (2b) as shown in FIG. 7). Figure 7

[0130] The mode selection module 7011 delivers the PC value from the CPU core to the threshold trigger mode collection module 7014 in response to the enable signal corresponding to the threshold trigger mode collection module being valid (e.g., process (2c) as shown in FIG. 7). Figure 7

[0131] The continuous mode collection module 7012 continuously collects the PC value output by the CPU core and delivers the collected PC value to the multiplexer 702 (e.g., process (3a) as shown in FIG. 7). Figure 7

[0132] The interval trigger mode collection module 7013 collects the PC value and delivers the collected PC value to the multiplexer 702 in the case where the PC value output by the CPU core belongs to a preconfigured PC value interval (e.g., process (3b) as shown in FIG. 7). Figure 7

[0133] The threshold trigger mode collection module 7013 continuously collects the PC value and delivers the collected PC value to the multiplexer 702 in the case where the PC value output by the CPU core is greater than a preset threshold (e.g., process (3c) as shown in FIG. 7). Figure 7

[0134] Step S803: The multiplexer 702 delivers the currently received PC value to the compression subunit 703.

[0135] The compression subunit 703 stores the current PC value delivered by the multiplexer to a current PC value register (e.g.,​​​​​​​Figure 7 The process (4a) ) shown.

[0136] Step S804: The compression subunit 703 determines the PC value log data packet format corresponding to the current PC value, and generates the PC value log data packet corresponding to the current PC value based on the PC value log data packet format.

[0137] The compression subunit 703 stores the previous PC value stored in the current PC value register into the previous PC value register before storing the current PC value into the current PC value register (as shown in Figure 7 The process (4b) ) shown.

[0138] The data packet selection module 7033 compares the current PC value stored in the current PC value register with the previous PC value stored in the previous PC value register, and selects the format of the PC value log data packet corresponding to the current PC value according to the comparison result (as shown in Figure 7 The process (5a) ) shown. If the current PC value is the same as the previous PC value, the previous PC value is discarded (as shown in Figure 7 The process (5b) ) shown.

[0139] For example, if the current PC value is not the same as the previous PC value, the current received PC value is compared with the previous PC value, the range of the bit positions where the change exists in the two adjacent PC values is determined, and the format of the PC value log data packet corresponding to the current PC value is determined according to the range. For example, the PC value is 48 bits, if the range of the changed bit positions of the two adjacent PC values is N+8 and below (N represents the starting bit position of the effective bits recorded by the PC value log data packet), the format of the PC value log data packet is selected as S packet; if the range of the changed bit positions of the two adjacent PC values is 25 and below, the format of the PC value log data packet is selected as L packet; if the range of the changed bit positions of the two adjacent PC values is 47 and below, the format of the PC value log data packet is selected as A packet. As an example, the first PC value received by the compression subunit 703, the format of the PC value log data packet corresponding to the PC value is A packet.

[0140] For another example, the current received PC value and the previous PC value are both divided into 3 parts (47-26 bits, 25-N+9 bits, N+8-N bits, wherein N represents the starting bit position of the effective bits recorded by the PC value log data packet). Whether the 26-47 bits are the same is compared. If the 26-47 bits are the same, A packet is not selected, and the 25-N+9 bits are continued to be compared. If the 26-47 bits are not the same, the format of the PC value log data packet is selected as A packet. If the 25-N+9 bits are the same, the N+8-N bits are continued to be compared. If the 25-N+9 bits are not the same, the format of the PC value log data packet is selected as L packet. If the N+8-N bits are not the same, the format of the PC value log data packet is selected as S packet.

[0141] The data packet generation module generates a corresponding PC value log data packet according to the PC value log data packet format selected for the current PC value (as shown in process (6) of Figure 7 The PC value log data packet is passed to the combination subunit (as shown in process (7) of Figure 7

[0142] Step S805: The combination subunit combines the PC value log data packets corresponding to multiple PC values, generates a combination data packet, and stores the combination data packet to the DRAM through the bus (as shown in process (8) of Figure 7

[0143] In an optional embodiment, there is also a queue (such as a first-in first-out queue FIFO) between the PC value log unit and the memory (such as the DRAM), and the combination data packet stored to the memory passes through the queue for buffering. For example, the PC value log unit first buffers the generated combination data packet in the queue, and then stores the combination data packet buffered in the queue to the memory such as the DRAM. However, the input frequency and the output frequency of the queue are not necessarily the same. Since the queue has a limited depth (the number of combination data packets that the queue can store is limited), when the input frequency of the queue is greater than the output frequency, the queue will overflow because the speed of the combination data packets input to the queue is greater than the speed of the combination data packets read from the queue. When the queue overflows, all the overflowed data packets are not reliable. To improve the reliability of the data packets, in an optional embodiment of the present application, the PC value log unit can include an overflow detection subunit to detect whether the queue overflows. When it is detected that the queue overflows, the collection of the PC values is stopped.

[0144] Figure 9 A structure diagram of the PC value log unit according to an embodiment of the present application is shown. As shown in Figure 9 Based on the PC value log unit shown in Figure 7 The PC value log unit 700 further includes an overflow detection subunit 705. The overflow detection subunit 705 is coupled to the mode selection module 7011. In response to detecting that the queue overflows, the overflow detection subunit 705 generates a control signal and sends the control signal to the mode selection module 7011 to control the mode selection module 7011 to invalidate the enable signal, so that the collection subunit stops collecting the PC values.

[0145] Figure 10 A structure diagram of the PC value log unit according to another embodiment of the present application is shown. As shown in Figure 10 Based on the PC value log unit shown in Figure 9 The PC value log unit further includes a data packet generation subunit 706.

[0146] ​​The data packet generating subunit 706 generates a relevant data packet of a specified format in response to detecting that a relevant data packet generation condition is satisfied. Optionally, the relevant data packet generated by the data packet generating subunit 706 can include at least one of the following types: a synchronization data packet, a timestamp data packet, a timeout data packet, and an overflow data packet.

[0147] Optionally, the data packet generating subunit 706 generates a synchronization data packet in response to detecting that the PC value log unit is powered on. The synchronization data packet records time information of generating the synchronization data packet, to represent time information of the PC value log unit starting to work after being powered on.

[0148] Optionally, the data packet generating subunit 706 generates a timestamp data packet in response to a specified time interval or a specified number of PC values being collected. The timestamp data packet records time information of generating the timestamp data packet.

[0149] Optionally, the data packet generating subunit 706 generates an overflow data packet in response to the overflow detecting subunit 1004 detecting that the buffer queue is overflowing. The overflow data packet records time information of generating the overflow data packet, to represent that the queue is overflowing.

[0150] Optionally, the data packet generating subunit 706 generates a timeout data packet in response to the compression subunit not generating a PC log data packet for a specified time length, to represent that a timeout condition occurs. As an example, the timeout data packet includes a timestamp data packet and an A packet; wherein the timestamp data packet included in the timeout data packet records time of generating the timestamp data packet, to represent time of the timeout condition occurring.

[0151] As an example, the data packet generating subunit 706 is coupled with the queue, and stores the generated relevant data packets into the queue, and then stores the relevant data packets in the queue into the memory.

[0152] In an optional embodiment, the above-mentioned synchronization data packet, timestamp data packet, and overflow data packet are all 64-bit data packets.

[0153] Figure 11A A schematic diagram of a synchronization data packet is shown. As shown in Figure 11A The 0th-2nd bits of the synchronization data packet are packet format symbol bits. If the 0th-2nd bits are 111, it indicates that the data packet is a synchronization data packet. The 3rd-5th bits of the synchronization data packet are ID bits, representing an ID of a CPU core corresponding to the PC value log unit. The 6th bit is a channel bit, representing a PC log channel corresponding to the PC value collected by the PC value log unit. The 7th-63rd bits are data bits, recording time information of generating the synchronization data packet.

[0154] Figure 11B A schematic diagram of a timestamp data packet is shown. As shown inFigure 11B As shown in FIG. 6, the 0th-2nd bits of the timestamp data packet 0 are packet format symbol bits. If the 0th-2nd bits are 201, it indicates that the data packet is a timestamp data packet. The 3rd-5th bits of the timestamp data packet are ID bits, representing the ID of the CPU core corresponding to the PC value log unit. The 6th bit-63rd bit are data bits, recording the time information of generating the timestamp data packet.

[0155] Figure 11C An illustration of the overflow data packet is shown. As shown in FIG. 7, the 0th-2nd bits of the overflow data packet 0 are packet format symbol bits. If the 0th-2nd bits are 011, it indicates that the data packet is an overflow data packet. The 3rd-5th bits of the overflow data packet are Core bits, representing the CPU core corresponding to the overflow data packet. The 6th bit is a fixed value 0, and the 7th bit-63rd bit are data bits, recording the time information of generating the overflow data packet. Figure 11C

[0156] An illustration of the processing flow of the PC value log unit is shown in FIG. 8. As shown in FIG. 8, the data processing flow of the PC value log unit includes: Figures 12-16 Figure 10 As shown in FIG. 9, the data processing flow of the PC value log unit includes: Figure 12

[0157] Step S1201: Collecting PC values according to the selected specified collection mode.

[0158] Step S1202: Compressing each collected PC value, and generating a PC value log data packet with a specified format corresponding to each PC value.

[0159] Step S1203: Combining the generated PC value log data packets to obtain a combined data packet with a specified size.

[0160] Step S1204: Adding the generated combined data packet to the queue.

[0161] Step S1205: Moving the combined data packet in the queue to the memory such as DRAM.

[0162] As shown in FIG. 10, the data processing flow of the PC value log unit further includes: Figure 13

[0163] Step S1301: Generating an overflow data packet in response to detecting that the queue is overflowing.

[0164] Step S1302: Stopping collecting PC values.

[0165] Step S1303: Adding the generated overflow data packet to the queue.

[0166] ​​​Optionally, the order of step S1302 and step S1303 can be exchanged, for example, the generated overflow data packet is added to the queue first and then the collection of PC value is stopped. Still optionally, the PC value log unit does not perform step S1302, only performs step S1301 and step S1303.

[0167] As shown in Figure 14 , the data processing flow of the PC value log unit further includes:

[0168] Step S1401: in response to that no PC value is collected or no PC value log data packet is generated within a specified length of time, a timestamp data packet and an A packet are generated, and the generated timestamp data packet and A packet are used as a timeout data packet.

[0169] Step S1402: the generated timeout data packet is added to the queue.

[0170] As shown in Figure 15 , the data processing flow of the PC value log unit further includes:

[0171] Step S1501: in response to a specified time interval, a timestamp data packet is generated; or in response to that a specified number of PC value log data packets are generated, a timestamp data packet is generated.

[0172] Step S1502: the generated timestamp data packet is added to the queue.

[0173] As shown in Figure 16 , the data processing flow of the PC value log unit further includes:

[0174] Step S1601: in response to that the PC value log unit starts collecting PC values, a synchronization data packet is generated.

[0175] Step S1602: the generated synchronization data packet is added to the queue.

[0176] As can be seen from Figures 12-16 , the PC value log unit generates the synchronization data packet, the timestamp data packet, the timeout data packet and the overflow data packet independently and without affecting each other. The PC value log unit detects that the generation condition of a certain related data packet is met, and then generates the related data packet.

[0177] Figure 17 A flowchart of the PC value log unit processing PC values according to an embodiment of the present application is shown. As shown in Figure 17 , the flowchart includes:

[0178] Step S1701: start collecting the PC values output by the CPU core.

[0179] Step S1702: determine whether the collection interval is set or the collection threshold is set.

[0180] Step S1703 - 1 : Continuously collect PC values ​​without setting a collection interval and a collection threshold.

[0181] Step S1702 - 2 : When a collection interval is set and the enable signal of the interval-triggered collection mode is valid, PC values ​​are collected according to the interval-triggered collection mode.

[0182] Step S1703-3: If an acquisition threshold is set, determine whether the enable signal of the threshold-triggered acquisition mode is valid; if the enable signal of the threshold-triggered acquisition mode is determined to be valid, acquire the PC value according to the threshold-triggered acquisition mode. Alternatively, if an acquisition interval is set, determine whether the enable signal of the interval-triggered acquisition mode is valid; if the enable signal of the interval-triggered acquisition mode is determined to be valid, acquire the PC value according to the interval-triggered acquisition mode.

[0183] Step S1704: Compare the current PC value with the previous PC value and determine the comparison result.

[0184] Step S1705: Determine the format of the PC value log data packet corresponding to the current PC value based on the comparison result.

[0185] Step S1706: Generate a PC value log data packet corresponding to the current PC value according to the format of the PC value log data packet corresponding to the current PC value.

[0186] Step S1707 - 1 : Combine one or more PC value log data packets to generate a combined data packet.

[0187] Step S1707 - 2 : In response to starting to collect PC values, generate a synchronization data packet.

[0188] Step S1707 - 3 : In response to a specified time interval or a specified number of PC values ​​being collected, a timestamp data packet is generated.

[0189] Step S1707-4: In response to not collecting a PC value or generating a PC value log data packet within a specified length of time, a timestamp data packet and an A packet are generated, and the generated timestamp data packet and A packet are used as timeout data packets.

[0190] Step S1707 - 5 : In response to detecting a queue overflow, an overflow data packet is generated, and collection of PC values ​​is stopped.

[0191] Step S1708: Store the combined data packet, synchronization data packet, timestamp data packet, timeout data packet and overflow data packet into a queue.

[0192] Step S1709: Determine whether the queue overflows.

[0193] Step S1710: If the queue does not overflow, move the combined data packet, synchronization data packet, timestamp data packet, timeout data packet and overflow data packet in the queue to the DRAM.

[0194] In this embodiment, steps S1707-1, S1707-2, S1707-3, S1707-4, and S1707-5 are not executed sequentially, and there is no order in the timing of generating each data packet. These steps are independent of each other.

[0195] Figure 18 FIG. 1 shows a schematic diagram of the structure of the control component of an embodiment of the present application. Figure 18 As shown, the control component includes CPU Cluster 0 and CPU Cluster 1. CPU Cluster 0 includes two CPU cores, CPU Core 0 and CPU Core 1. CPU Cluster 1 includes two CPU cores, CPU Core 2 and CPU Core 3. CPU Cluster 0 and CPU Cluster 1 are independent of each other, CPU Core 0 and CPU Core 1 are independent of each other, and CPU Core 2 and CPU Core 3 are independent of each other.

[0196] like Figure 18 As shown, the control component further includes PC value logging unit 0, PC value logging unit 1, PC value logging unit 2, and PC value logging unit 3. PC value logging unit 0, PC value logging unit 1, PC value logging unit 2, and PC value logging unit 3 are independent of each other. PC value logging unit 0 is coupled to CPU core 0 and processes the PC value output by CPU core 0. PC value logging unit 1 is coupled to CPU core 1 and processes the PC value output by CPU core 1. PC value logging unit 2 is coupled to CPU core 2 and processes the PC value output by CPU core 2. PC value logging unit 3 is coupled to CPU core 3 and processes the PC value output by CPU core 3.

[0197] like Figure 18As shown, the control component further comprises a data packet merging unit 0, a data packet merging unit 1, a data packet merging unit 2 and a data packet merging unit 3. The data packet merging unit 0 is coupled with the PC value log unit 0 and merges one or more data packets outputted by the PC value log unit 0. The data packet merging unit 1 is coupled with the PC value log unit 1 and merges one or more data packets outputted by the PC value log unit 1. The data packet merging unit 2 is coupled with the PC value log unit 2 and merges one or more data packets outputted by the PC value log unit 2. The data packet merging unit 3 is coupled with the PC value log unit 3 and merges one or more data packets outputted by the PC value log unit 3. The data packets outputted by the PC value log units comprise, for example, a combination data packet, an overflow data packet, a synchronization data packet, a time stamp data packet, a timeout data packet, and each data packet merging unit merges the data packets outputted by the corresponding PC value log unit to generate a merged data packet. For example, the data packet merging unit 0 obtains a combination data packet, a synchronization data packet, a time stamp data packet and an overflow data packet from the PC value log unit 0, and the data packet merging unit 0 merges one or more of the combination data packet, the synchronization data packet, the time stamp data packet and the overflow data packet to generate a merged data packet. For example, the size of the merged data packet is 256 bits, and the sizes of the combination data packet, the synchronization data packet, the time stamp data packet and the overflow data packet are 64 bits respectively, and thus the data packet merging unit 0 merges four 64-bit data packets into one merged data packet, such as merging three combination data packets and one synchronization data packet into one merged data packet.

[0198] As Figure 18As shown, the control component further includes multiplexer 0, multiplexer 1, queue 0, queue 1 and arbiter. Multiplexer 0 is coupled with packet merging unit 0 and packet merging unit 1, and stores the merged packet output from one of packet merging unit 0 and packet merging unit 1 into queue 0. Multiplexer 1 is coupled with packet merging unit 2 and packet merging unit 3, and stores the merged packet output from one of packet merging unit 2 and packet merging unit 3 into queue 1. The arbiter is coupled with queue 0 and queue 1, and selects the merged packet from queue 0 or queue 1 to store into DRAM through the arbiter. The CPU core 0, CPU core 1, CPU core 2 and CPU core 3 in the control component share the bandwidth of the bus, and the bus bandwidth is allocated to each CPU core through multiplexer 0, multiplexer 1 and the arbiter. For example, in Tl period, multiplexer 0 selects to store the merged packet generated by packet merging unit 0 into queue 0. In T2 period, multiplexer 0 selects to store the merged packet generated by packet merging unit 1 into queue 0. In T3 period, multiplexer 1 selects to store the merged packet generated by packet merging unit 2 into queue 1. In T4 period, multiplexer 1 selects to store the merged packet generated by packet merging unit 3 into queue 1. Meanwhile, in Tl period and T2 period, the arbiter stores the packet in queue 0 into DRAM. In T3 period and T4 period, the arbiter stores the packet in queue 1 into DRAM.

[0199] In an optional embodiment, if only one or part of the CPU cores are working in a certain period of time, the multiplexer allocates the bus bandwidth to the working CPU cores. For example, in a certain period of time, only CPU core 0 and CPU core 1 are working in the control component, and the bus bandwidth is allocated to CPU core 0 and CPU core 1 through multiplexer 0. For example, in Tl period, multiplexer 0 selects to store the merged packet generated by packet merging unit 0 into queue 0. In T2 period, multiplexer 0 selects to store the merged packet generated by packet merging unit 1 into queue 0. In T3 period, multiplexer 0 selects to store the merged packet generated by packet merging unit 0 into queue 0. In T4 period, multiplexer 0 selects to store the merged packet generated by packet merging unit 1 into queue 0. Meanwhile, in Tl period-T4 period, the arbiter stores the packet in queue 0 into DRAM.

[0200] Figure 19 A flowchart of the control component processing PC values in the embodiment of the present application is shown. As shown, the flowchart includes: Figure 19

[0201] Step S1901: Each PC value log unit collects the PC value output by the CPU core coupled thereto, and generates a combination data packet and a related data packet.

[0202] ​Step S1902: Each PC value log unit passes the generated combined data packet and the associated data packet to the data packet merging unit coupled thereto.

[0203] Step S1903: Each data packet merging unit merges the combined data packet and the associated data packet received thereby to obtain a merged data packet.

[0204] Step S1904: The multiplexer selects the merged data packet generated by one of the data packet merging units coupled thereto from the plurality of data packet merging units coupled thereto and stores the merged data packet into the corresponding queue.

[0205] Step S1905: The arbiter selects the merged data packet stored in one of the queues coupled thereto from the plurality of queues coupled thereto and stores the merged data packet into the DRAM.

[0206] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the preferred embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to cover all such variations and modifications as fall within the scope of the application. It should be apparent that the application is not limited to the specific embodiments described herein, but can be practiced with modification and alteration within the scope and spirit of the present application. Accordingly, the specification is to be regarded in an illustrative, rather than a restrictive sense, as the application is intended to encompass all changes and modifications that fall within the scope of the claims and their equivalents.

Claims

1. A PC duty log generation method characterized by, The method comprises: collecting program counter values output by a central processor core; compressing the program counter values to generate program counter value log data packets of a specified format corresponding to each of the program counter values; combining one or more of the generated program counter value log data packets to obtain a combined data packet.

2. The method of claim 1, wherein, The generating of the program counter value log data packet of the specified format corresponding to each of the program counter values comprises: determining a range of bit positions that have changed in two adjacent program counter values, and determining a type of the program counter value log data packet corresponding to a later program counter value in the two adjacent program counter values according to the range of bit positions that have changed.

3. The method according to claim 1 or 2, characterized in that, The program counter value log data packet comprises one or more of the following types: a first data packet, a second data packet, and a third data packet; wherein the first data packet has a size of 16 bits, the second data packet has a size of 32 bits, and the third data packet has a size of 64 bits.

4. The method of claim 3, wherein, The generating of the program counter value log data packet of the specified format corresponding to each of the program counter values comprises: generating the third data packet for a first program counter value collected at each power-on.

5. The method according to claim 3 or 4, characterized in that, The generating of the program counter value log data packet of the specified format corresponding to each of the program counter values comprises: if the range of bit positions that have changed in the two adjacent program counter values is within the range of bit positions that can be recorded by the data bits of the first data packet, generating the first data packet for the later program counter value in the two adjacent program counter values; or, if the range of bit positions that have changed in the two adjacent program counter values exceeds the range of bit positions that can be recorded by the data bits of the first data packet and is within the range of bit positions that can be recorded by the data bits of the second data packet, generating the second data packet for the later program counter value in the two adjacent program counter values; or, if the range of bit positions that have changed in the two adjacent program counter values exceeds the range of bit positions that can be recorded by the data bits of the second data packet, generating the third data packet for the later program counter value in the two adjacent program counter values.

6. The method according to any one of claims 1 to 5, characterized in that, The collecting of the program counter values output by the central processor core comprises: collecting the program counter values output by the central processor core according to a selected specified collection mode.

7. The method of claim 6, wherein, The specified collection mode comprises a continuous mode, an interval trigger mode, and / or a threshold trigger mode; wherein, the continuous mode is to continuously collect the program counter values output by the central processor core at each clock cycle; the interval trigger mode is to collect the program counter values output by the central processor core that belong to a preset program counter value interval; and / or the threshold trigger mode is to continuously or periodically collect the program counter values output by the central processor core in response to detecting that the program counter values output by the central processor core are greater than a preset threshold.

8. The method according to any one of claims 1 to 7, characterized in that, The method further comprises: in response to detecting that a generation condition of a related data packet is met, generating the related data packet of the specified format, adding the related data packet to the queue, and transmitting the related data packets in the queue to a memory.

9. The method of claim 8, wherein, The correlation data packet comprises one or more of: a synchronization data packet, a timestamp data packet, an overflow data packet, and a timeout data packet; The generating the correlation data packet having a specified format in response to detecting that a generation condition of the correlation data packet is satisfied comprises: generating a synchronization data packet in response to detecting that the collection of the program counter value output by the central processing unit core is started; generating a timestamp data packet in response to a specified time interval or a specified number of program counter values being collected; generating an overflow data packet in response to detecting that the queue is overflowed; and / or generating a timeout data packet in response to no program counter value log data packet being generated for a specified length of time.

10. A program counter value logging unit, characterized by The program counter value log unit is coupled with a central processing unit core and performs the method of any one of claims 1-9.

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