Operation method of memory, dynamic random access memory and memory system

Abstract

The invention provides an operation method of a memory, a dynamic random access memory and a memory system, and relates to the technical field of semiconductor chips. The method comprises the steps of determining a target storage array in response to a storage array activation signal, and performing a refresh operation on the target storage array in response to a refresh signal. The invention aims to improve the problem of high power consumption in a memory refreshing process.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a method for operating a memory, a dynamic random access memory, and a memory system. Background Technology

[0002] Dynamic Random Access Memory (DRAM) consists of capacitors and transistors. Capacitors are used to store data, while transistors are used to read and write data. However, capacitors are subject to charge decay, which can affect the integrity and security of the data stored in the memory. Summary of the Invention

[0003] The embodiments disclosed herein provide a method for operating a memory, a dynamic random access memory (DRAM), and a memory system. The embodiments of this disclosure adopt the following technical solutions:

[0004] Firstly, a method for operating a memory is provided, applied to a dynamic random access memory, the method comprising:

[0005] In response to a storage array activation signal, a target storage array is determined, and in response to a refresh signal, a refresh operation is performed on the target storage array, wherein the target storage array is a storage array that is in an active state.

[0006] In some embodiments, an indication message is stored in the memory, and the indication message stores an activation status identifier. Determining the target storage array includes: obtaining the activation status identifier from the indication message and determining the target storage array based on the activation status identifier.

[0007] In some embodiments, the method further includes: determining a non-target storage array based on an activation status identifier, the activation status identifier being used to identify a storage array in an active state, and performing a disable operation on the non-target storage array in response to a refresh signal.

[0008] In some embodiments, the method further includes: updating the activation status identifier of the corresponding storage array in the indication message in response to the activation signal.

[0009] In some embodiments, the method further includes performing a refresh operation on the target storage array in response to a periodically transmitted refresh signal.

[0010] In some embodiments, before responding to a refresh signal, the method further includes: entering a self-refresh mode in response to a first enable signal, wherein the first enable signal is a low-level signal.

[0011] In some embodiments, the method further includes: exiting the self-refresh mode in response to a second enable signal, wherein the second enable signal is a high-level signal.

[0012] In a second aspect, a dynamic random access memory is provided, comprising: a memory array and peripheral circuitry coupled to the memory array, the peripheral circuitry being configured to: determine a target memory array in response to a memory array activation signal, and perform a refresh operation on the target memory array in response to a refresh signal, wherein the target memory array is a memory array in an active state.

[0013] In some embodiments, the memory includes a register circuit that stores an indication message containing an activation status identifier. The peripheral circuit is further configured to: obtain the activation status identifier from the indication message and determine the target memory array based on the activation status identifier.

[0014] In some embodiments, the peripheral circuitry is further configured to: determine a non-target memory array based on an activation state identifier, the activation state identifier being used to identify a memory array in an active state, and perform a disable operation on the non-target memory array in response to a refresh signal.

[0015] In some embodiments, the peripheral circuitry is further configured to update the activation status identifier of the corresponding storage array in the indication message in response to the activation signal.

[0016] In some embodiments, the peripheral circuitry is further configured to perform a refresh operation on the target memory array in response to a periodically transmitted refresh signal.

[0017] In some embodiments, the peripheral circuitry is further configured to enter a self-refresh mode in response to a first enable signal, wherein the first enable signal is a low-level signal.

[0018] In some embodiments, the peripheral circuitry is further configured to exit the self-refresh mode in response to a second enable signal, wherein the second enable signal is a high-level signal.

[0019] Thirdly, this disclosure provides a storage system including a memory controller and a dynamic random access memory (DRAM) as described in the second aspect above, wherein the memory controller is configured to control the DRAM.

[0020] Fourthly, this disclosure provides a computer-readable storage medium storing computer-executable instructions; when executed, the computer-executable instructions are able to implement the method of any one of the first aspects.

[0021] Fifthly, this disclosure provides an electronic device including a processor and a readable storage medium coupled to the processor, the readable storage medium storing executable instructions that, when executed by the processor, can implement the method of any one of the first aspects. Attached Figure Description

[0022] Figure 1 A block diagram of a storage device provided in an embodiment of this disclosure;

[0023] Figure 2 A block diagram of another storage device provided in an embodiment of this disclosure;

[0024] Figure 3 A schematic diagram of the structure of a dynamic random access memory provided in an embodiment of this disclosure;

[0025] Figure 4 A flowchart illustrating the operation method of the memory provided in this embodiment of the disclosure;

[0026] Figure 5 A circuit diagram of a dynamic random access memory provided in an embodiment of this disclosure;

[0027] Figure 6 A schematic diagram illustrating the effect of the memory operation method provided in the embodiments of this disclosure. Detailed Implementation

[0028] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the figures. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0029] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplarily," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

[0030] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0031] In describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact; in this case, "coupled" can also be described as "connected." Furthermore, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0032] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0033] "A and / or B" includes three combinations: A only, B only, and a combination of A and B. The use of "applies to" or "configured to" in this document implies open and inclusive language, which does not preclude applicability to or configuration to perform additional tasks or steps on devices. Additionally, the use of "based on" implies openness and inclusivity, as processes, steps, calculations, or other actions "based on" one or more conditions or values ​​may in practice be based on additional conditions or values ​​beyond those conditions.

[0034] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0035] DRAM is a common type of random access memory with wide applications in the storage field. In practical applications, DRAM can have various application architectures. In some embodiments, DRAM is part of the controller within an SSD storage system. For examples, see [link to relevant documentation]. Figure 1 DRAM can be directly coupled to the memory controller. Figure 1 A schematic diagram illustrating an example architecture of a storage device with DRAM is shown. Figure 1As shown, this architecture includes a host 10 and a storage system 20. The storage system 20 includes a memory controller 201, DRAM 202, and at least one non-volatile memory (NAND) 203. The memory controller 201 is communicatively connected to the host 10 and is used to receive data read commands or data write commands from the host 10, and to perform data read operations or data write operations on the NAND according to the received data read commands or data write commands. DRAM 202 and at least one NAND 203 are communicatively connected to the memory controller 201. A logic-to-physical address mapping table (L2P mapping table) is stored in DRAM 202. NAND 203 is used to store data. During data read operations, after receiving a first data read command from the host 10 through an interface module, the memory controller 201 sends a physical address search request to DRAM 202, the physical address search request including the host logical address hit by the first data read. DRAM 202 uses the host logical address to search for the physical address of NAND 203 in the stored L2P mapping table and sends the found physical address to memory controller 201. Memory controller 201 sends a second data read command containing the physical address to NAND 203. NAND 203 uses the physical address in the second data read command to sense data, and when NAND 203 is ready to receive data, memory controller 202 reads the data and provides it to host 10 through the interface module.

[0036] In other examples, DRAM is a separate structure outside the SSD storage system, connected directly to the host as a standalone storage system. See examples below. Figure 2 In this architecture, the DRAM can be directly coupled to the host, including a host 10, DRAM 20, and a storage system 30. The storage system 30 includes a memory controller 301 and at least one non-volatile memory (NAND) 302. The memory controller 301 is communicatively connected to the host 10 and is used to receive data read commands or data write commands from the host 10, and to perform data read operations or data write operations on the NAND according to the received data read commands or data write commands. The memory controller 301 performs the corresponding operation based on the type of request.

[0037] DRAM comprises multiple memory banks, each containing multiple subarrays, and each subarray contains memory cells arranged in an array. Each memory cell is connected to several word lines (WL) and bit lines (BL), and adjacent subarrays are connected by multiple sense amplifiers (SA). Each sense amplifier has a positive input (BL) and an inverting input. Each of the two adjacent memory cell subarrays is connected to a column of memory cells.

[0038] Each DRAM memory cell can consist of a MOS transistor and a capacitor, using external electronic charge to store bits. Over time, current leaks from the capacitor, and when the charge level falls below a threshold, the DRAM will be unable to correctly read the stored data. Therefore, to maintain data integrity, the capacitor needs to be recharged.

[0039] Figure 3 A schematic diagram of the memory array 400 and peripheral circuitry 300 of the DRAM memory 202 is shown. Figure 3 In this circuit, peripheral circuitry 300 includes a command decoder circuit 310, control logic circuitry 320, row decoder 330, voltage generator 340, column decoder 360, page buffer 350, data bus 370, register circuitry 380, and refresh timer 390. It should be understood that in some examples, it may also include... Figure 4 Additional circuitry not shown.

[0040] Command decoder circuit 310 can be coupled to control logic circuit 320 and act as a control buffer to buffer control commands received from memory controller 201 and relay them to control logic circuit 320, and to buffer status information received from control logic circuit 320 and relay it to the host. Command decoder circuit 310 can also be coupled to page buffer 350 via data bus 370 and act as both command decoder circuit 310 and data buffer to buffer data and relay it to or from memory array 400.

[0041] The control logic circuit 320 can be coupled to the voltage generator 340, page buffer 350, column decoder 360, row decoder 330, and command decoder circuit 310, and is configured to control the operation of each peripheral circuit. The control logic circuit 320 can generate operation signals in response to commands or control signals from the memory controller 201 to control the operation of the row decoder 330, column decoder 360, page buffer 350, and voltage generator 340; wherein the command can be a programming command, a read command, etc.

[0042] The row decoder 330, in response to control by the control logic circuitry 320, supplies word line voltages generated by the voltage generator 340 to the selected and unselected word lines of the memory array 400. As described in detail below, the row decoder 330 is configured to perform programming operations on memory cells coupled to one or more selected word lines in the memory cell array 300.

[0043] Voltage generator 340 can use external or internal power supply voltages to generate various voltages for performing operations such as erasing, programming, reading, and verification on memory array 400.

[0044] The column decoder 360 can respond to the control logic circuit 320 and select the memory array 400 by applying a bit line voltage generated from the voltage generator 340.

[0045] Page buffer 350 can read data from and program (write) data to memory array 400 according to control signals from control logic circuit 320. In one example, page buffer 350 can store programming data to be programmed into memory array 400 (write data). In another example, page buffer 350 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer 350 can also detect a low-power signal from the bit line representing the data bit stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation.

[0046] The register circuit 380 can be coupled to the control logic circuit 320 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0047] The refresh timer 390 can be used to generate periodic refresh signals.

[0048] Those skilled in the art will understand that the operations performed by the line decoder 330, page buffer 350, control logic circuit 320, and voltage generator 340 described in this disclosure can be performed by processing circuitry. This processing circuitry may include, but is not limited to, hardware of logic circuitry or a hardware / software combination of a processor executing software.

[0049] The process of recharging the capacitor is equivalent to refreshing the DRAM. There are two ways to refresh the DRAM memory. (Continue reading...) Figure 2 The first refresh mode is Auto Refresh (AR) mode. In AR mode, the memory controller 201 periodically sends refresh commands to the DRAM memory 202, and the command decoder in the DRAM memory 202...

[0050] Circuit 310 is responsible for identifying and parsing the auto-refresh signal sent from memory controller 201. After parsing, DRAM memory 202 performs a refresh operation on its internal memory array 400. When DRAM memory 202 is active, auto-refresh mode can be used to retain the data stored in the DRAM memory cells.

[0051] The second refresh mode is Self Refresh (SR) mode. Compared to automatic refresh mode, self refresh mode is used for data storage in low-power sleep mode. In self refresh mode, DRAM memory 202 relies on refresh commands sent by its internal refresh timer 390 to trigger the refresh operation. Therefore, in self refresh mode, it is not necessary for memory controller 201 to send refresh commands to DRAM memory 202 to trigger the refresh operation. When DRAM memory 202 is in an idle or low-power state, self refresh mode is used to retain the data stored in the DRAM memory cells.

[0052] The refresh operation can be understood as accessing DRAM memory cells row by row or column by column, reading their stored contents, and then rewriting them to refresh the data stored in the DRAM memory cells, thereby preventing data from becoming invalid due to prolonged inaccessibility. Since the DRAM is unavailable during the refresh process, to reduce the impact of refresh operations on memory performance degradation and simultaneously reduce memory power consumption, a Partial Array Self-Refresh (PASR) refresh mode can be used. PASR allows a portion of the DRAM memory cells to remain available during refresh, thus reducing performance loss during the refresh period. During refresh, only a portion of the memory array performs the refresh operation, while other memory arrays continue to provide services, thus reducing the impact of refresh operations on memory access performance. For example, self-refresh can be performed on 1 / 2 or 1 / 4 of the memory array.

[0053] Currently, some array self-refresh modes randomly select storage arrays for refresh during self-refresh, without considering the state of the storage arrays. The state of a storage array can include an active state and an inactive state.

[0054] An active state can refer to a storage array being active, in use, or ready to be accessed. When the storage array is active, it may be reading, writing, or performing other data operations in response to requests from the memory controller. An active state can also refer to a storage array being idle, inactive, or unused. In an inactive state, the storage array may be in standby mode, with no tasks being performed, or in a low-power state. Performing a refresh operation on an inactive storage array will increase unnecessary power consumption.

[0055] Below, we will combine the appendix Figure 4 The present disclosure describes the operation method of the memory provided. The operation method of the memory provided is applied to the peripheral circuit of DRAM. Specifically, when the aforementioned peripheral circuit is working, it executes the following... Figure 4 The operation method shown includes steps S10 to S20.

[0056] In S10, in response to the storage array activation signal, the target storage array is determined.

[0057] First, the DRAM needs to be in self-refresh mode to trigger the method provided in this disclosure. Whether the DRAM enters self-refresh mode is controlled by the clock enable signal sent by the memory controller. When the clock enable signal sent by the memory controller is a low-level signal, the DRAM enters self-refresh mode. Furthermore, in self-refresh mode, all external signals sent by the memory controller other than the clock enable signal are invalid.

[0058] Before performing a refresh operation, it's necessary to filter out target and non-target memory arrays. During the refresh operation, only the target memory array needs to be refreshed, significantly reducing the power consumption required for the refresh operation. The specific process of filtering out the target memory array is achieved by parsing the activation instructions issued by the memory controller. When the memory controller needs to read or write to a specific memory array, it sends corresponding address and control signals to the DRAM to selectively activate the required memory array. After receiving these signals, the DRAM determines the location of the memory array to be accessed based on the address signal and decides whether to activate the memory array based on the control signal.

[0059] When the memory controller sends an activation signal to the DRAM, the DRAM puts the corresponding memory array into an active state. This means that the memory array is ready to receive read or write commands from the memory controller and to transfer stored data to the memory controller or receive new data from the memory controller. By sending an activation signal to the memory array, the memory controller can selectively access a specific memory array and put it into an active state when needed for data read or write operations.

[0060] The DRAM stores an indication message containing an activation status identifier. By recording the activation status identifier of the memory array carried in the activation signal, the memory array can be divided into an active target memory array and an inactive non-target memory array. (See also...) Figure 5 The recording of the activation state of the memory array can be achieved through register circuitry, and this disclosure does not limit the specific structure of the register circuitry. For example, when the memory controller sends an activation signal to the DRAM carrying the identification information of memory array A, the register circuitry corresponding to memory array A can record and update the activation state identifier of memory array A from "inactive" to "activated". By obtaining the activation state identifier stored in the register circuitry, it is possible to determine whether the memory array is in an active or inactive state.

[0061] When the clock enable signal from the memory controller is set to high, the DRAM will exit self-refresh mode and resume normal read / write operations. In self-refresh mode, the DRAM performs internal refresh operations to maintain data stability. This mechanism ensures that the DRAM can autonomously perform refresh operations without affecting normal system operation, thereby maintaining data integrity and stability.

[0062] Controlling the self-refresh operation via a clock enable signal allows for precise control over the timing and frequency of refreshes to meet the system's real-time memory access needs. By triggering the self-refresh operation only when needed, energy consumption can be reduced. Entering self-refresh mode when DRAM is not in use reduces power consumption, thus saving energy.

[0063] In S20, in response to the refresh signal, a refresh operation is performed on the target storage array.

[0064] After the refresh signal is triggered, a refresh operation will be performed on the target memory array, and a disable operation will be performed on the non-target memory array. For example, the specific process of refreshing an arbitrary target memory array is described below. Before reading, each bit line is first pre-charged, that is, the bit line voltage is pulled up to a preset voltage, which can be half of the supply voltage. This creates a voltage difference between the bit line and the storage capacitor voltage of the DRAM memory cell. After the pre-charging is completed, the connection between the bit line and the pre-charging power supply can be disconnected. At this time, the bit line is in a floating state, and the voltage still remains at half of the supply voltage. Then the reading process begins. First, the row address is input on the address bus. Immediately afterward, the row address strobe is enabled. Once enabled, the DRAM caches the row address and sends it to the decoding module. The decoding module decodes the row address into a one-hot code. Each bit of the one-hot code is connected to the corresponding word line. The one-hot code pulls up the voltage of one word line, turning on the cell row corresponding to that word line. This means the transistor in that cell row is turned on, and the storage capacitors and bit lines of each DRAM cell in that cell row are connected. If the DRAM cell stores bit information 1, meaning the voltage of the storage capacitor is equal to the supply voltage, the storage capacitor voltage is higher than the bit line voltage, causing the capacitor to discharge and the bit line voltage to rise slightly. If the DRAM cell stores bit information 0, meaning the storage capacitor voltage is equal to ground (0 voltage), the bit line voltage is higher than the storage capacitor voltage, causing the bit line to charge the storage capacitor and the bit line voltage to drop slightly.

[0065] The amplifier captures minute voltage fluctuations on the bit lines and generates and temporarily stores the storage capacitor voltage of the DRAM memory cell locally through differential sensing. For example, if the storage capacitor of the DRAM memory cell equals the supply voltage, the bit line voltage rises slightly. The amplifier compares this bit line voltage with the voltage of another reference line, amplifies the voltage difference between the two through feedback from analog circuitry, and finally generates an output voltage equal to the supply voltage locally, which is then latched by a latch. Similarly, if the storage capacitor voltage of the DRAM memory cell is equal to 0, the amplifier will eventually generate an output voltage equal to 0, and latch the 0 voltage using a latch. After the amplifier latches the row data, it sends the row data to a multiplexer. The multiplexer sends a specific bit in the cell row to the output line according to the column address. After the output, the amplifier's data needs to be written back to the cell row, that is, the bit line is pulled high to the supply voltage or 0 voltage according to the amplifier's latch value. The bit line charges and discharges the storage capacitor of the DRAM memory cell. After the charging and discharging is completed, the word line can be turned off. After writing back the data and turning off the word line, the bit line is connected to the pre-charge power supply to pre-charge the bit line to half of the supply voltage, preparing for the next read and write operation.

[0066] While performing a refresh operation on the target storage array, it is also necessary to disable non-target storage arrays. Disabling non-target storage arrays can be achieved using segment masking. For example, each storage array corresponds to a bitmask. When disabling non-target storage arrays, they are masked according to their bitmasks, thus avoiding refreshing unnecessary storage arrays. This significantly reduces the energy consumption required for self-refresh operations while maintaining data integrity.

[0067] The identification information of the storage array is dynamically updated upon activation. In one feasible approach, the method further includes updating the activation status identifier of the corresponding storage array in the indication message. When the activation signal is triggered, not only is the identification information of the storage array updated, but its activation status identifier is also updated to the corresponding status. By associating the activation status identifier of the storage array with its identification information, the status of each array in the storage system can be managed more effectively. When a storage array is activated, its corresponding activation status identifier is updated, allowing for faster identification of which storage arrays are active and which are inactive, thus facilitating real-time monitoring and management.

[0068] The refresh timer in the peripheral circuit generates a refresh signal at preset time intervals, which periodically triggers various components of the system. This periodic refresh signal is crucial for the system's stability and performance. It not only ensures timely data updates but also helps prevent errors caused by timing misalignments. The refresh timer's function is to schedule various system tasks by precisely controlling the time intervals, thereby improving the system's response speed and stability.

[0069] See Figure 6 This disclosure provides an overall description of the memory operation method. In existing self-refresh modes, a portion of the memory array is randomly selected for refresh. As shown in Strategy A, bank0, bank1, and bank2 might be selected for refresh, even though they are all inactive, resulting in unnecessary energy consumption. In the solution provided in this disclosure, the active memory array is selected as the target memory array for refresh. As shown in Strategy B, bank13, bank14, and bank15 are selected for refresh, even though they are all active. By refreshing only the active memory array, unnecessary energy consumption is reduced.

[0070] The memory operation method disclosed herein uses the activation state of the storage array as a filtering condition to precisely select the target storage arrays that need to be refreshed. Therefore, only these active target storage arrays are selected for the refresh operation, while those inactive storage arrays are not refreshed. Compared to the traditional method of refreshing all storage arrays, this significantly reduces energy consumption. It can minimize energy consumption while ensuring data stability. Especially in large-scale storage systems, this optimization can significantly reduce the overall energy consumption of the system and improve energy utilization efficiency.

[0071] Embodiments of this disclosure also provide a dynamic random access memory, including: a memory array and peripheral circuitry coupled to the memory array, the peripheral circuitry being configured to: determine a target memory array in response to a memory array activation signal, and perform a refresh operation on the target memory array in response to a refresh signal, wherein the target memory array is a memory array in an active state.

[0072] In one possible embodiment of this disclosure, the memory includes a register circuit that stores an indication message containing an activation status identifier. The peripheral circuit is further configured to: obtain the activation status identifier from the indication message and determine the target memory array based on the activation status identifier.

[0073] In one possible implementation of this disclosure, the peripheral circuitry is further configured to: determine a non-target memory array based on an activation state identifier, the activation state identifier being used to identify a memory array in an active state, and, in response to a refresh signal, perform a disable operation on the non-target memory array.

[0074] In one possible implementation of this disclosure, the peripheral circuitry is further configured to update the activation status identifier of the corresponding memory array in the indication message in response to the activation signal.

[0075] In one possible implementation of this disclosure, the peripheral circuitry is further configured to perform a refresh operation on the target memory array in response to a periodically transmitted refresh signal.

[0076] In one possible implementation of this disclosure, the peripheral circuitry is further configured to enter a self-refresh mode in response to a first enable signal, wherein the first enable signal is a low-level signal.

[0077] In one possible implementation of this disclosure, the peripheral circuitry is further configured to exit the self-refresh mode in response to a second enable signal, wherein the second enable signal is a high-level signal.

[0078] The memory controller provided in this disclosure may include a cache and one or more processors. The cache stores computer-executable instructions, and the one or more processors execute the computer-executable instructions to implement the memory operation method of this disclosure.

[0079] This disclosure also provides a storage system including a memory controller and the aforementioned dynamic random access memory, wherein the memory controller is configured to control the dynamic random access memory.

[0080] This disclosure also provides an electronic device, which includes a host computer and the aforementioned storage system. The host computer is connected to the storage system and is used to store data in the storage system or read data from the storage system. For example, the electronic device can be one of the aforementioned examples. Figure 1 The electronic device shown.

[0081] This embodiment provides a computer-readable storage medium having a computer program stored thereon, the computer program being used to implement the memory operation method as disclosed herein.

[0082] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, please refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0083] In the several embodiments provided in this disclosure, it should be understood that the provided programming methods and memory can be implemented in other ways. For example, the division of a certain module is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0084] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0085] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for operating a memory, applied to a dynamic random access memory, characterized in that, The method includes: In response to the storage array activation signal, the target storage array is determined; In response to a refresh signal, a refresh operation is performed on the target storage array, wherein the target storage array is a storage array that is in an active state.

2. The method according to claim 1, characterized in that, The memory stores an indication message, and the indication message stores an activation status identifier. Determining the target storage array includes: The activation status identifier is obtained from the indication message, and the target storage array is determined based on the activation status identifier.

3. The method according to claim 2, characterized in that, The method further includes: The non-target storage array is determined based on the activation status identifier, which is used to identify the storage array that is in an active state; In response to the refresh signal, a disable operation is performed on the non-target storage array.

4. The method according to claim 3, characterized in that, The method further includes: In response to the activation signal, the activation status identifier of the corresponding storage array in the indication message is updated.

5. The method according to claim 1, characterized in that, The method further includes: A refresh operation is performed on the target storage array in response to the periodically sent refresh signal.

6. The method according to claim 1, characterized in that, Prior to responding to the refresh signal, the method further includes: In response to a first enable signal, the system enters a self-refresh mode, wherein the first enable signal is a low-level signal.

7. The method according to claim 1 or 6, characterized in that, The method further includes: In response to the second enable signal, exit the self-refresh mode, wherein the second enable signal is a high-level signal.

8. A dynamic random access memory, characterized in that, include: A storage array and peripheral circuitry coupled to the storage array, the peripheral circuitry being configured as follows: In response to the storage array activation signal, the target storage array is determined; In response to a refresh signal, a refresh operation is performed on the target storage array, wherein the target storage array is a storage array that is in an active state.

9. The memory according to claim 8, characterized in that, The memory includes a register circuit that stores an indication message, the indication message storing an activation status identifier, and the peripheral circuit is further configured to: The activation status identifier is obtained from the indication message, and the target storage array is determined based on the activation status identifier.

10. The memory according to claim 8, characterized in that, The peripheral circuit is also configured to: The non-target storage array is determined based on the activation status identifier, which is used to identify the storage array that is in an active state; In response to the refresh signal, a disable operation is performed on the non-target storage array.

11. The memory according to claim 10, characterized in that, The peripheral circuit is also configured to: In response to the activation signal, the activation status identifier of the corresponding storage array in the indication message is updated.

12. The memory according to claim 8, characterized in that, The peripheral circuit is also configured to: A refresh operation is performed on the target storage array in response to the periodically sent refresh signal.

13. The memory according to claim 9, characterized in that, The peripheral circuit is also configured to: In response to a first enable signal, the system enters a self-refresh mode, wherein the first enable signal is a low-level signal.

14. The memory according to claim 8 or 13, characterized in that, The peripheral circuit is also configured to: In response to the second enable signal, exit the self-refresh mode, wherein the second enable signal is a high-level signal.

15. A storage system, characterized in that, The storage system includes a memory controller and a memory, the memory controller being coupled to the memory, and the memory being a dynamic random access memory as described in any one of claims 8-14.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions; when the computer-executable instructions are executed, they can implement the method provided by any one of claims 1-7.

17. A computer device, characterized in that: The method includes a processor and a readable storage medium coupled to the processor, the readable storage medium storing executable instructions that, when executed by the processor, enable the implementation of the method according to any one of claims 1-7.

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