Packaging method of VCSEL chip device

Abstract

The invention provides a packaging method of a VCSEL chip device, and relates to the technical field of semiconductor laser packaging. The method comprises the following steps of: copying a micro lens array at one time on the back surface of a VCSEL (Vertical Cavity Surface Emitting Laser) wafer on which a front electrode is completed by utilizing wafer-level UV (Ultraviolet) nano-imprinting, so that the optical center of a micro lens is self-aligned with the center of an active area of a light-emitting unit, and meanwhile, realizing light beam shaping and wafer-level mechanical protection; cutting the wafer into single chips, directly bonding front electrodes of the chips to a metal bonding pad of a driving IC (integrated circuit) in a flip-chip bonding manner, enabling the back surfaces of the chips to become final light-emitting surfaces, and synchronously establishing electric connection and a low-thermal-resistance heat dissipation channel; and finally, low-modulus bottom filling glue is injected between the chip and the driving IC, and high-transmission transparent epoxy resin is coated on the periphery of the chip and above the micro lenses on the back surface to form a chip-scale packaging body without a shell. Through the steps, alignment and forming of the micro lens are completed in the wafer stage, and the packaging thickness and the optical loss are remarkably reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor laser packaging technology, specifically a packaging method for a VCSEL chip device. Background Technology

[0002] VCSEL (Vertical-Cavity Surface-Emitting Laser) chips require high beam quality, compact packaging, and good heat dissipation in applications such as 3D sensing, LiDAR, and optical communication. Traditional packaging methods involve emitting light from the front of the chip, achieving electrical connections via wire bonding, and then mounting an independent microlens or glass cover on the front for beam shaping. In this structure, the light path must pass through the air-glass interface of the package cover, introducing Fresnel reflection losses and potentially causing beam shift due to misalignment between the lens and the emitting unit. Simultaneously, the front electrodes and bonding wires occupy the outer perimeter of the emitting surface, limiting the lens diameter and fill factor, further reducing optical power density. Furthermore, heat generated in the active region of the chip must be conducted through multiple stages—the substrate, wires, and package substrate—resulting in high thermal resistance, leading to increased junction temperature, wavelength drift, and power attenuation during long-term operation.

[0003] The existing technology CN115685418B-VCSEL proposes a chip module, its microlens, and fabrication method. However, the optical components used to shape the beam emitted by the bare VCSEL chip have a large space requirement. This method achieves optimal shaping of the VCSEL beam quality parameters at the chip level, maintaining the size advantage of the VCSEL chip while changing the beam quality parameters, and enabling the array integration of VCSEL chips.

[0004] However, while existing chip modules, their microlenses, and fabrication methods have reduced size compared to the earlier "casing + independent lens" approach, they still have the following shortcomings: Lateral alignment of the microlens and the light-emitting unit depends on subsequent processes (substrate curing, photolithography, or mechanical alignment), and the measured offset is generally >3µm, which is difficult to meet the requirements of small divergence angle or high-density array applications; there is at least one optical adhesive or air layer at the lens-chip interface, and the interface reflection and absorption cause 3-8% light loss; the module thickness is coupled with the working distance, making it impossible to achieve "ultra-thin" and "high collimation" at the same time; the heat dissipation channel is not integrated with the optical shaping structure in the same layer, and the space for reducing thermal resistance is limited. Summary of the Invention

[0005] (a) Technical problems to be solved To address the systemic defects of existing technologies, such as large optical alignment errors, high interface losses, high thermal resistance, and large size, this invention proposes a three-step method: "wafer-level back-side microlens + flip-chip bonding + transparent epoxy integration". The core idea is to complete the precise forming and positioning of optical components at the wafer stage, then use flip-chip bonding to three-dimensionally co-construct the optical components, electrical interconnects, and heat dissipation channels, and finally encapsulate them with transparent epoxy in one step to achieve shell-less chip-level packaging.

[0006] (II) Technical Solution To achieve the above objectives, the present invention provides the following technical solution: a packaging method for a VCSEL chip device, comprising the following steps: Step 1: Form a self-aligned microlens array on the back side of the VCSEL wafer using wafer-level UV nanoimprinting; Step 2: Divide the wafer and flip-chip bond the individual chips to the driver IC; Step 3: Inject bottom filler and coat with transparent epoxy resin to form a chip-level package.

[0007] Preferably, step one includes: spin-coating B-staged epoxy resin onto the back of a VCSEL wafer with a completed front electrode, and replicating the array in one step under UV light using a nanoimprint template with a microlens structure, so that the optical center of each microlens deviates from the center of the active area of ​​the light-emitting unit by ≤3µm; after curing, a microlens structure with a thickness of 30-80µm, a refractive index of 1.50-1.55, and a fill factor of ≥90% is formed, while simultaneously achieving beam collimation and wafer-level mechanical protection.

[0008] Preferably, step two includes: cutting the wafer with microlenses into single chips, pre-applying gold-tin eutectic solder to the front electrode of the chip; bonding the front of the chip to the pad of the driver IC by flip-chip bonding, controlling the reflow peak temperature to 280℃±5℃, forming solder joints with a height of 5-15µm, and simultaneously establishing electrical connections and heat conduction paths, so that the microlenses on the back of the chip serve as the light-emitting surface.

[0009] Preferably, step three includes: injecting a bottom filler with an elastic modulus ≤2GPa and a CTE ≤25ppm / ℃ into the gap between the chip and the driver IC, and curing it below 150℃ to absorb thermal stress; then coating the chip and the microlens surface with a transparent epoxy resin with a transmittance of ≥90% at 850nm, forming a 20-50µm thick protective layer above the lens apex, with a surface roughness Ra ≤10nm after curing, and the final package projection area is no more than 1.2 times that of the chip.

[0010] Preferably, a thermal via or an aluminum nitride high thermal conductivity layer is integrated below the pad of the driver IC, and the thermal resistance of the solder joint is ≤0.5K / W.

[0011] Preferably, the UV nanoimprinting uses 365nm wavelength ultraviolet light, with an exposure dose of 200-400mJ / cm² and an imprinting pressure of 0.5-2MPa.

[0012] Preferably, the transparent epoxy resin coating is performed using a vacuum-assisted molding process, and the resin viscosity is controlled to be ≤500 cP to avoid microlens deformation.

[0013] Preferably, the bottom filler contains silica stress-absorbing particles with a diameter of 1-5µm, and the amount added is 5-10wt%.

[0014] (III) Beneficial Effects This invention provides a packaging method for VCSEL chip devices, which has the following advantages: By replicating a microlens array on the back of a wafer using wafer-level UV nanoimprinting, the optical center of each microlens is automatically aligned with the center of the active region of its corresponding light-emitting unit. Lateral deviation is stably controlled within 3μm, far less than the 5μm or more offset commonly found in traditional secondary alignment processes. This self-alignment capability eliminates accumulated errors from subsequent bonding or photolithography, ensuring that high-density VCSEL arrays maintain consistent far-field directivity and beam quality. This provides a mass-producible precision foundation for small divergence angle, highly integrated 3D sensing, and LiDAR systems.

[0015] The lens and the light-emitting area employ an integrated transparent epoxy structure with no air gap. The refractive index of 1.50–1.55 is well-matched to the chip material, achieving a transmittance of over 90% in the 850nm wavelength band. A surface roughness Ra≤10nm further suppresses scattering. Compared to the multiple interfaces of air-lens-adhesive layers in traditional solutions, this design reduces interface reflection loss from 3–8% to less than 2%, directly increasing the module's output power by over 5%, while simultaneously reducing system-level power consumption and thermal load.

[0016] The flip-chip solder gold-tin eutectic bumps form a vertical heat dissipation path with the thermal vias / high thermal conductivity layer beneath the driver IC pads. A single bump has a thermal resistance ≤0.5K / W, allowing heat to travel directly from the active area to the substrate via the solder joint, eliminating the need for lateral diffusion across the substrate thickness. A low-modulus underfill adhesive and a transparent epoxy overlay synergistically absorb thermal stress. After 500 thermal cycles at -40–125℃, the solder joints exhibit zero cracks and transmittance attenuation of less than 1.5%, significantly suppressing wavelength drift and power decay caused by junction temperature rise, meeting automotive-grade long-term reliability requirements. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the system of the present invention. Detailed Implementation

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0019] Example 1: like Figure 1 As shown, this embodiment of the invention provides a packaging method for a VCSEL chip device. Step one: On the back side of the VCSEL wafer with the front electrode already completed, a microlens array is replicated in one step using wafer-level UV nanoimprinting. The optical center of each microlens is self-aligned with the center of the active area of ​​the corresponding light-emitting unit, thereby simultaneously achieving beam shaping on a single wafer and providing a mechanical protective layer for the chip surface. The B-staged epoxy resin used in UV nanoimprinting has a refractive index of 1.50-1.55 after curing. The thickness of the formed microlens structure is 30-80µm. The positional deviation between the optical center of the microlens and the center of the active area of ​​the corresponding light-emitting unit is ≤3µm. The fill factor of the microlens array is ≥90%.

[0020] Step 2: The wafer obtained in Step 1 is diced into individual VCSEL chips with back microlenses. Then, the front electrode of the chip is directly bonded to the metal pad of the driver IC by flip-chip bonding, so that the back of the chip becomes the final light-emitting surface. In this way, electrical connection is formed and heat conduction path is established in the same bonding step. Gold-tin eutectic solder is used for flip-chip bonding. The height of the solder joint formed after reflow is 5–15µm, and the reflow peak temperature is 280℃±5℃.

[0021] Step 3: Inject low-modulus underfill adhesive between the chip and the driver IC, and coat the chip periphery and the microlens on the back with high-transmittance chip-level transparent epoxy resin to form a shell-less chip-level package. The curing temperature of the underfill adhesive is below 150℃, the coefficient of thermal expansion is ≤25ppm / ℃, and the elastic modulus is ≤2GPa. The transmittance of the transparent epoxy resin at 850nm wavelength is ≥90%, and the surface roughness Ra of the light-emitting surface after curing is ≤10nm. A 20–50µm thick flat or micro-arc protective layer of transparent epoxy resin is formed above the apex of the microlens. A thermal via or a high thermal conductivity material layer is integrated under the metal pads of the driver IC.

[0022] Among them, the microlens array has both optical collimation and stress buffering functions, the flip-chip structure provides both electrical interconnection and heat dissipation channels, the transparent epoxy resin achieves chip sealing and maintains light emission efficiency, and the projected area of ​​the package is no more than 1.2 times the projected area of ​​the chip.

[0023] Example 2: This invention provides a packaging method for a VCSEL chip device, including a wafer-level microlens replication process, a flip-chip bonding process, an underfill and epoxy coating process, and a process window verification.

[0024] The process steps of the wafer-level microlens replication process are as follows: the back side of the 6-inch GaAs VCSEL wafer with the front electrode completed is cleaned with oxygen plasma for 30 seconds to remove organic residues; B-staged epoxy resin (viscosity 350 cP at 25℃) is dynamically spin-coated at 1500 rpm, and the wet film thickness is controlled at 45±5µm before imprinting; imprinting is performed using a quartz master mold under a soft film pressure of 0.10MPa, 365nm UV exposure at 300mJ / cm², and the measured refractive index after curing is 1.52; after demolding, it is baked at 150℃ for 30 minutes, and the final microlens has a sagitta of 20µm and a radius of curvature of 100µm.

[0025] The effect was verified by randomly selecting 9 points for measurement. The average offset between the center of the microlens and the center of the active area of ​​the light-emitting unit was 2.1µm (Max 2.8µm), and the fill factor was ≥92%. The surface roughness of the lens was Ra=7nm, which met the beam collimation requirements.

[0026] The flip-chip bonding process involves the following steps: gold-tin eutectic bumps with a thickness of 10µm are electroplated on the Au electrode on the front side of the chip, and after reflow, 8µm high solder joints are formed; a 50µm diameter copper-filled thermal via is pre-fabricated below the driver IC pad; the bonding head temperature is 275℃, the pressure is 0.5N / bump, and the dwell time is 3s to achieve eutectic fusion; after bonding, X-ray inspection shows a void ratio of 2.3%.

[0027] The performance was verified using the four-wire method, and the single convex point resistance was measured to be 0.8mΩ, the thermal resistance was 0.42K / W, and the shear strength was 65gf / convex point, which meets the automotive-grade requirements.

[0028] The process steps for underfill and epoxy coating are as follows: inject underfill adhesive (elastic modulus 1.2 GPa, CTE 22 ppm / ℃) into the chip-IC gap and cure at 110℃ for 45 min; use vacuum molding (vacuum degree less than 5 mbar, mold temperature 90℃) to coat transparent epoxy resin with a viscosity of 300 cP and a gel time of 8 min; after molding, cure again at 150℃ for 60 min, with a protective layer thickness of 30 ± 3 µm and a radius of curvature of 8 mm.

[0029] Performance verification: After 500 thermal cycles from -40 to 125℃, no cracks were found in the solder joints; after aging at 85℃ / 85%RH for 1000h, the transmittance decreased by 1.4%, and the yellowing index ΔYI=0.6; the projected area of ​​the package is 1.15 times that of the chip.

[0030] Process window validation includes the following experiments: 1. Parameter gradient experiment: Keeping other conditions constant, only the elastic modulus of the bottom filler was changed to three groups: 0.5, 1.0, and 2.0 GPa. The results showed that when the modulus was ≥1 GPa, the shear force was >55 gf and there were no filling voids; when the modulus was less than 1 GPa, delamination occurred after thermal cycling.

[0031] 2. Scalability verification: Examples 1-3 were repeated for three array sizes of 8×8, 12×12, and 16×16, and consistent results were obtained, proving that this process is universal for chip size.

[0032] Example 3: Based on Example 2, the B-staged epoxy was replaced with a high-refractive-index UV-silicon hybrid resin (n=1.60±0.02, Tg=150℃). This resin has a transmittance of >92% at 365nm and a water absorption rate of <0.15%, and can suppress lens deformation under 85℃ / 85%RH conditions. The spin-coating thickness was maintained at 30-80µm, and the imprinting pressure was reduced to 0.06MPa to completely fill the mold, reducing wafer warpage by 15%; the measured microlens height error was less than 1.2µm, the far-field divergence angle decreased from 6.2° to 5.4°, and the spot energy concentration was improved by 8%.

[0033] Example 4: Building upon Example 2, a copper pillar + SnAgTi nano-silver paste was used instead of a gold-tin eutectic. The copper pillar had a diameter of 25µm and a height of 18µm, with 5µm of SnAgTi nano-silver paste printed on the top. The reflow peak temperature was 230℃±5℃, and the liquidus time was <15s, significantly reducing the thermal budget. After reflow, a Cu3Sn+Ag3Sn composite IMC was formed with a void ratio of <1%. The thermal resistance was further reduced to 0.28K / W (AlN substrate), and the shear strength was increased to 80gf / bump, meeting the AEC-Q100 Grade 0 requirements.

[0034] Example 5: Based on Example 2, 3 wt% self-healing microcapsules (core material is dicyclopentadiene-DCPD, shell material is polyurea) with a particle size of 2–5 µm were added to the bottom filler adhesive. When microcracks appear at the solder joint or epoxy / chip interface, crack propagation triggers microcapsule rupture, and DCPD polymerizes in situ under the action of a catalyst, achieving self-healing of the cracks.

[0035] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A packaging method for a VCSEL chip device, characterized in that, The following steps are involved: Step 1: On the back side of the VCSEL wafer with the front electrode already completed, a microlens array is replicated in one step using wafer-level UV nanoimprinting. This allows the optical center of each microlens to be self-aligned with the center of the active region of the corresponding light-emitting unit, thereby simultaneously achieving beam shaping on a single wafer and providing a mechanical protective layer for the chip surface. Step 2: The wafer obtained in Step 1 is diced into individual VCSEL chips with back microlenses. Then, the front electrode of the chip is directly bonded to the metal pad of the driver IC by flip-chip bonding, so that the back of the chip becomes the final light-emitting surface, thereby forming an electrical connection and establishing a heat conduction path in the same bonding step. Step 3: Inject low-modulus underfill adhesive between the chip and the driver IC, and coat the chip with high-transmittance chip-level transparent epoxy resin around the chip and above the microlens on the back to form a shell-less chip-level package. The microlens array has both optical collimation and stress buffering functions, the flip-chip bonding structure provides both electrical interconnection and heat dissipation channels, the transparent epoxy resin achieves chip sealing and maintains light emission efficiency, and the projected area of ​​the package is no more than 1.2 times the projected area of ​​the chip.

2. The packaging method for a VCSEL chip device according to claim 1, characterized in that: The UV nanoimprinting uses B-staged epoxy resin with a refractive index of 1.50-1.55 after curing, and the resulting microlens structure has a thickness of 30-80µm.

3. The packaging method for a VCSEL chip device according to claim 1, characterized in that: The positional deviation between the optical center of the microlens and the center of the active region of the corresponding light-emitting unit is ≤3µm, and the fill factor of the microlens array is ≥90%.

4. The packaging method for a VCSEL chip device according to claim 1, characterized in that: The flip-chip soldering uses gold-tin eutectic solder, and the solder joint height formed after reflow is 5–15µm, with a reflow peak temperature of 280℃±5℃.

5. The packaging method for a VCSEL chip device according to claim 1, characterized in that: The curing temperature of the bottom filler is below 150°C, the coefficient of thermal expansion is ≤25ppm / °C, and the elastic modulus is ≤2GPa.

6. The packaging method for a VCSEL chip device according to claim 1, characterized in that: The transparent epoxy resin has a transmittance of ≥90% at a wavelength of 850nm, and the surface roughness Ra of the light-emitting surface after curing is ≤10nm.

7. The packaging method for a VCSEL chip device according to claim 1, characterized in that: The transparent epoxy resin forms a 20–50 µm thick flat or slightly curved protective layer above the apex of the microlens.

8. The packaging method for a VCSEL chip device according to claim 1, characterized in that: The driver IC has thermal vias or a layer of highly thermally conductive material integrated beneath its metal pads.

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