MOS device and manufacturing method thereof

Abstract

The invention provides an MOS device and a manufacturing method thereof, and the method comprises the steps: forming a basic oxide layer on the surface of a semiconductor substrate through a rapid thermal oxidation method, introducing nitrogen into the basic oxide layer until the average nitrogen concentration reaches a preset value, and enabling the part with the maximum nitrogen ion concentration to be far away from the interface distribution of the basic oxide layer / semiconductor substrate, and then carrying out annealing treatment after nitriding and manufacturing the PMOS transistor, wherein a gate dielectric layer of the PMOS transistor adopts the basic oxide layer after nitrogen introduction. According to the invention, the basic oxide layer is formed by adopting a rapid thermal oxidation method, so that the introduction of hydrogen can be reduced, the maximum concentration of nitrogen ions is distributed far away from the interface, so that the influence on Si-H bonds can be reduced, the interface defects are reduced, and the NBTI service life is prolonged. According to the invention, the stress proximity technology can be further introduced to improve the performance of the NMOS, the buffer layer is utilized to block the damage of plasma to the gate dielectric layer in the forming process of the silicon nitride tensile stress layer, the quality of the gate dielectric layer is improved, and the reliability of the device is further improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a MOS device and its fabrication method. Background Technology

[0002] Negative bias temperature instability (NBTI) is a loss mechanism in P-MOS devices that occurs when the device is in a high-temperature and inversion state. NBTI is caused by positive charge defects in the interface states and bulk. NBTI significantly reduces the voltage drop across P-MOS devices. th , I dsat , I dlin g m The drift of characteristic parameters is currently the most serious reliability problem of P-MOS devices.

[0003] like Figure 1 The diagram illustrates the physical mechanism of NBTI generation in PMOS transistors, where S represents the source, G represents the gate, and D represents the drain. Specifically, the physical mechanism of NBTI generation has two aspects (Mechanism I and Mechanism II). One aspect is interface trapped charge (DT). it On the other hand, there is the oxide trapped charge (N). ot The formation of Si / SiO2 interface states in the gate oxide layer is the main factor leading to the NBTI effect. During device operation, when a negative gate bias is applied to the PMOS, a high electric field is generated on the gate. Holes are attracted to the Si / SiO2 interface, weakening and breaking the Si-H bonds at the interface, forming positively charged interface states and traps. The reaction is Si3≡SiH+h. + →Si3≡Si·+H + In addition, the H generated by the breaking of Si-H bonds + It enters the oxide layer and combines with holes to generate oxide layer charge.

[0004] During device fabrication, hydrogen is present in many processes such as implantation film deposition, etching, ion implantation, and cleaning. Driven by thermal budget, this hydrogen diffuses to the Si / SiO2 interface and combines with Si dangling bonds to form Si-H bonds, thereby exacerbating the NBTI effect.

[0005] Therefore, how to improve the NBTI effect to enhance the reliability of MOS devices has become an important technical problem that needs to be solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a MOS device and its fabrication method, which solves the problem of reduced reliability of MOS devices due to temperature instability caused by negative bias in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides a method for fabricating a MOS device, comprising the following steps:

[0009] A semiconductor substrate is provided, and a basic oxide layer is formed on the surface of the semiconductor substrate using a rapid thermal oxidation method;

[0010] Nitrogen is introduced into the base oxide layer until the average nitrogen concentration in the base oxide layer reaches a preset value, and the point of maximum nitrogen ion concentration is far from the interface distribution of the base oxide layer / the semiconductor substrate.

[0011] Perform nitriding followed by annealing;

[0012] A PMOS transistor is fabricated, the PMOS transistor including a gate structure on the semiconductor substrate, sidewalls on both sides of the gate structure and source / drain regions in the semiconductor substrate, the gate structure including a gate dielectric layer and a gate conductive layer on the gate dielectric layer, the gate dielectric layer being the base oxide layer after the introduction of nitrogen.

[0013] Optionally, the temperature range of the rapid thermal oxidation method is 950℃~1200℃, and the time range is 30 seconds~40 seconds.

[0014] Optionally, the method of introducing nitrogen into the base oxide layer includes performing decoupled plasma nitriding in a machine chamber, wherein, by adjusting the working cycle of the machine chamber, the average nitrogen concentration in the base oxide layer reaches the preset value, and the point of maximum nitrogen ion concentration is far from the interface distribution of the base oxide layer / the semiconductor substrate.

[0015] Optionally, adjusting the working cycle of the machine chamber includes adjusting the power supply duty cycle for performing nitrogen molecule dissociation, wherein the power supply duty cycle ranges from 5% to 15%.

[0016] Optionally, the method further includes the step of fabricating an NMOS transistor, wherein the NMOS transistor is separated from the PMOS transistor by an isolation structure located in the semiconductor substrate, and the NMOS transistor includes a gate structure located on the semiconductor substrate, sidewalls located on both sides of the gate structure, and source / drain regions located in the semiconductor substrate.

[0017] Optionally, the following steps are also included:

[0018] A silicon nitride tensile stress layer is formed on the semiconductor substrate, and the silicon nitride tensile stress layer covers the PMOS transistor and the NMOS transistor;

[0019] Annealing is performed to release the stress in the silicon nitride tensile layer;

[0020] Remove the silicon nitride tensile stress layer.

[0021] Optionally, the method for forming the silicon nitride tensile stress layer includes plasma-enhanced chemical vapor deposition.

[0022] Optionally, before forming the silicon nitride tensile stress layer, a silicon nitride buffer layer covering the PMOS transistor and the NMOS transistor is first formed on the semiconductor substrate using low-pressure chemical vapor deposition. Plasma is not used in the formation of the silicon nitride buffer layer.

[0023] Optionally, before forming the silicon nitride buffer layer, an etch stop layer covering the PMOS transistor and the NMOS transistor is first formed on the semiconductor substrate.

[0024] Optionally, the thickness ratio of the silicon nitride buffer layer to the silicon nitride tensile stress layer is in the range of 1:3 to 1.5:3.

[0025] Optionally, the annealing process for releasing the stress in the silicon nitride tensile layer includes spike annealing and laser annealing.

[0026] The present invention also provides a MOS device, comprising:

[0027] Semiconductor substrate;

[0028] A PMOS transistor includes a gate structure on a semiconductor substrate, sidewalls on both sides of the gate structure, and source / drain regions in the semiconductor substrate. The gate structure includes a gate dielectric layer and a gate conductive layer on the gate dielectric layer. The gate dielectric layer is a base oxide layer with nitrogen introduced. The base oxide layer is formed on the surface of the semiconductor substrate by a rapid thermal oxidation method. The average nitrogen concentration in the base oxide layer reaches a preset value, and the point where the nitrogen ion concentration is maximum is far away from the interface distribution of the base oxide layer and the semiconductor substrate.

[0029] Optionally, the MOS device further includes an NMOS transistor, which is separated from the PMOS transistor by an isolation structure located in the semiconductor substrate. The NMOS transistor includes a gate structure located on the semiconductor substrate, sidewalls located on both sides of the gate structure, and source / drain regions located in the semiconductor substrate.

[0030] As described above, the fabrication method of the MOS device of the present invention employs a rapid thermal oxidation method to form a base oxide layer on the surface of a semiconductor substrate, and introduces nitrogen into the base oxide layer until the average nitrogen concentration in the base oxide layer reaches a preset value. The location of the maximum nitrogen ion concentration is located away from the interface distribution of the base oxide layer / semiconductor substrate. Then, a nitriding and annealing process is performed to fabricate a PMOS transistor. The gate dielectric layer of the PMOS transistor uses the aforementioned nitrogen-introduced base oxide layer. In this invention, the rapid thermal oxidation method for forming the base oxide layer on the surface of the semiconductor substrate reduces the introduction of hydrogen. When introducing nitrogen into the base oxide layer, ensuring that the location of the maximum nitrogen ion concentration is located away from the interface distribution of the base oxide layer / semiconductor substrate reduces the impact on Si-H bonds, reduces interface defects, and thereby improves NBTI lifetime. In an optional embodiment of the present invention, stress proximity technology can be further introduced to improve NMOS performance. Specifically, before forming the silicon nitride tensile stress layer, an LPCVD method can be used to form a silicon nitride buffer layer to protect the gate dielectric layer. When the silicon nitride tensile stress layer is subsequently formed using PECVD, this buffer layer can prevent damage to the gate dielectric layer from plasma during PECVD film formation, improving the quality of the gate dielectric layer and further enhancing device reliability. Furthermore, the silicon nitride buffer layer formed by LPCVD does not introduce additional stress because the LPCVD process forms films on both the front and back sides of the wafer; therefore, the stress on both sides is canceled out, without affecting the normal process. The silicon nitride buffer layer is ultimately removed along with the silicon nitride tensile stress layer formed by PECVD. Attached Figure Description

[0031] Figure 1 This is shown as the physical mechanism generated by NBTI.

[0032] Figure 2 The diagram shown is a process flow diagram of the fabrication method of the MOS device of the present invention.

[0033] Figure 3 The diagram shown illustrates the structure of a PMOS transistor fabricated using the method for fabricating a MOS device according to the present invention.

[0034] Figure 4 The diagram shown illustrates the structure obtained after forming an etch stop layer in the fabrication method of the MOS device of the present invention.

[0035] Figure 5The diagram shown illustrates the structure obtained after forming a silicon nitride buffer layer in the fabrication method of the MOS device of the present invention.

[0036] Figure 6 The diagram shows the structure obtained after forming a silicon nitride tensile stress layer according to the fabrication method of the MOS device of the present invention.

[0037] Figure 7 The diagram shown is a schematic of the structure obtained after removing the silicon nitride tensile stress layer and the silicon nitride buffer layer in the fabrication method of the MOS device of the present invention.

[0038] Component designation explanation

[0039] Steps S1 to S4

[0040] 1 Semiconductor substrate

[0041] 2 PMOS transistors

[0042] 201 Gate Dielectric Layer

[0043] 202 Gate conductive layer

[0044] 203 Side Wall

[0045] 204 pocket doped region

[0046] 205 lightly doped source / drain regions

[0047] 206 heavily doped source / drain regions

[0048] 3 NMOS transistors

[0049] 4. Isolation Structure

[0050] 5 Deep N-well

[0051] 6 N-well

[0052] 7 P-trap

[0053] 8 Etching Stop Layer

[0054] 9. Silicon nitride buffer layer

[0055] 10 Silicon nitride tensile stress layer Detailed Implementation

[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] Please see Figures 2 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0058] Example 1

[0059] This embodiment provides a method for fabricating a MOS device. Please refer to [link / reference]. Figure 2 The diagram shows the process flow of this method, which includes the following steps:

[0060] S1: A semiconductor substrate is provided, and a basic oxide layer is formed on the surface of the semiconductor substrate using a rapid thermal oxidation method;

[0061] S2: Nitrogen is introduced into the base oxide layer until the average nitrogen concentration in the base oxide layer reaches a preset value, and the point of maximum nitrogen ion concentration is far away from the interface distribution of the base oxide layer / the semiconductor substrate.

[0062] S3: Perform nitriding followed by annealing;

[0063] S4: Fabricate a PMOS transistor, the PMOS transistor including a gate structure on the semiconductor substrate, sidewalls on both sides of the gate structure and source / drain regions in the semiconductor substrate, the gate structure including a gate dielectric layer and a gate conductive layer on the gate dielectric layer, the gate dielectric layer being the base oxide layer after nitrogen introduction.

[0064] Specifically, the semiconductor substrate may be a silicon substrate, a silicon-on-insulator substrate, or other suitable semiconductor substrate.

[0065] Specifically, the rapid thermal oxidation method used in step S1 to form the base oxide layer is to reduce the introduction of hydrogen. However, if the base oxide layer is grown using in-situ steam generation (ISSG), a large amount of hydrogen will be introduced. Driven by thermal expansion, this hydrogen will diffuse to the Si / SiO2 interface and combine with Si dangling bonds to form Si-H bonds, thereby exacerbating the NBTI effect.

[0066] As an example, the rapid thermal oxidation method has a temperature range of 950°C to 1200°C and a time range of 30 to 40 seconds, with the atmosphere including dry oxygen. The specific time for performing the rapid thermal oxidation method depends on the required thickness of the base oxide layer.

[0067] Specifically, in step S2, nitrogen is introduced into the base oxide layer to increase the gate oxide dielectric constant and reduce the diffusion of boron (B).

[0068] As an example, a method for introducing nitrogen into the base oxide layer includes performing decoupled plasma nitridation (DPN) treatment in the machine chamber.

[0069] It should be noted that nitrogen at the Si / SiO2 interface lowers the activation energy of the Si-H bond, weakening the Si-H bond to the point of breakage, thus creating an interface trap. + Nitrogen enters the oxide layer and combines with holes, generating oxide layer charge and affecting NBTI lifetime. In order to avoid the introduction of nitrogen affecting NBTI, in some embodiments of the present invention, the working cycle of the machine chamber is adjusted so that the average nitrogen concentration in the base oxide layer reaches the preset value, and the nitrogen ion concentration at the point of maximum concentration is far away from the interface distribution of the base oxide layer / the semiconductor substrate.

[0070] Specifically, during decoupling plasma nitriding in the machine chamber, the parameters set at the machine end include radio frequency power, duty cycle, gas, pressure, and time. The duty cycle describes the ratio of the operating state (typically a high-level or active output signal) within one cycle of the device or system to the total cycle time. In this invention, the process of introducing nitrogen into the base oxide layer is an ion bombardment process. In some embodiments, adjusting the duty cycle includes adjusting the power supply duty cycle for nitrogen molecule dissociation during the DPN treatment process, for example, by reducing the power supply duty cycle.

[0071] In some embodiments, the power supply duty cycle is reduced from the conventional 20% to 5% to 15%, for example, to 10%.

[0072] Specifically, the principle behind this invention, which achieves a nitrogen ion concentration distribution furthest from the interface (Si / SiO2) of the base oxide layer / semiconductor substrate by reducing the power supply duty cycle, is as follows: Nitrogen doping is an ion bombardment process. Reducing the power supply duty cycle decreases the concentration of dissociated nitrogen in the chamber, effectively reducing plasma density per unit time. This reduces damage to the base oxide layer during nitrogen doping. Because the damage to the base oxide layer is minimal, nitrogen entering the base oxide layer is less likely to diffuse to the Si / SiO2 interface, ultimately reducing the nitrogen concentration at the Si / SiO2 interface.

[0073] It should be noted that since the ultimate goal is to achieve a preset value for the average nitrogen concentration in the basic oxide layer, while reducing the power supply duty cycle to reduce the dissociated nitrogen concentration in the machine chamber, it is necessary to appropriately increase the nitrogen doping time, i.e., increase the DPN treatment time. The specific increase time can be set according to the target concentration, and no specific limitation is made in this invention.

[0074] Specifically, the post-nitridation anneal (PNA) treatment in step S3 is to fix the nitrogen doped in step S2. In one embodiment, the post-nitridation anneal can be performed using rapid thermal processing (RTP).

[0075] Thus, after growing the base oxide layer on the surface of the semiconductor substrate through rapid thermal oxidation, by reducing the power supply duty cycle during the DPN process, the average nitrogen concentration in the base oxide layer reaches a preset value, so that the point of maximum nitrogen ion concentration is far away from the interface distribution of the base oxide layer / semiconductor substrate. This reduces the influence of nitrogen on the Si-H bonds at the Si / SiO2 interface, reduces interface defects, and thereby improves NBTI lifetime.

[0076] In some embodiments, the semiconductor substrate is divided into a core region and other functional regions according to a preset rule, and the nitrogen-introduced oxide layer is used as the core oxide layer, such as the gate dielectric layer of a MOS transistor.

[0077] For details, please refer to Figure 3 The diagram shows a schematic of the structure obtained after performing step S4 in one embodiment. The fabricated PMOS transistor 2 includes a gate structure on the semiconductor substrate 1, sidewalls 203 on both sides of the gate structure, and source / drain regions in the semiconductor substrate 1. The gate structure includes a gate dielectric layer 201 and a gate conductive layer 202 on the gate dielectric layer 201. The gate dielectric layer 201 is the base oxide layer after introducing nitrogen. The gate conductive layer 202 may include a polysilicon layer. The sidewalls 203 may be a silicon oxide / silicon nitride stack, a silicon oxide / silicon nitride / silicon oxide / silicon nitride stack, or other suitable stacked structures.

[0078] In some embodiments, the source and drain regions of the PMOS transistor 2 include a pocket doped region 204, a lightly doped source and drain region 205, and a heavily doped source and drain region 206. The pocket doped region 204 is formed by two heavily doped regions of the same type as the channel near the source and drain PN junction in the MOS channel, which can effectively prevent the depletion layer from diffusing into the channel, thereby blocking punch-through.

[0079] Specifically, since the gate dielectric layer 201 of the PMOS transistor 2 adopts the base oxide layer after the introduction of nitrogen as described above, on the one hand, since the base oxide layer is formed by a rapid thermal oxidation method, the introduction of hydrogen can be reduced, and the formation of Si-H bonds at the Si / SiO2 interface can be reduced. On the other hand, since the introduction of nitrogen into the base oxide layer makes the nitrogen ion concentration maximum location far away from the interface distribution of the base oxide layer / semiconductor substrate, the nitrogen concentration at the Si / SiO2 interface is reduced, and the influence of nitrogen on the activation energy of existing Si-H bonds is reduced. The two work together to reduce interface defects, improve the NBTI lifetime of the PMOS transistor, and improve the reliability of the MOS device.

[0080] Specifically, MOS devices typically also include NMOS transistors, such as... Figure 3 As shown, in some embodiments of the present invention, the step of fabricating an NMOS transistor 3 is also included. The NMOS transistor 3 is separated from the PMOS transistor 2 by an isolation structure 4 located in the semiconductor substrate 1. The NMOS transistor 3 also includes a gate structure located on the semiconductor substrate 1, sidewalls located on both sides of the gate structure, and source / drain regions located in the semiconductor substrate 1.

[0081] As an example, the isolation structure 4 can be a shallow trench isolation structure or other suitable isolation structure.

[0082] In some embodiments, the semiconductor substrate 1 is selected as a P-type silicon substrate or a P-type epitaxial layer, wherein a deep N-well 5 is formed, and an N-well 6 and a P-well 7 are formed in the deep N-well 5. The source and drain regions of the PMOS transistor 2 are located in the N-well 6, and the source and drain regions of the NMOS transistor 3 are located in the P-well 7.

[0083] In some embodiments, to improve NMOS performance, the present invention also introduces stress memory technology (SMT), which specifically includes the following steps:

[0084] (1) A silicon nitride tensile stress layer is formed on the semiconductor substrate 1, and the silicon nitride tensile stress layer covers the PMOS transistor 2 and the NMOS transistor 3. The tensile stress is beneficial to the improvement of NMOS mobility. The greater the stress change before and after annealing, the greater the change in mobility.

[0085] (2) Annealing is performed to release the stress in the silicon nitride tensile stress layer;

[0086] (3) Remove the silicon nitride tensile stress layer.

[0087] Specifically, stress memory technology can not only improve the device performance of NMOS, but also activate the implanted dopants in the lightly doped source-drain (LDD) and heavily doped source-drain regions.

[0088] As an example, the method for forming the silicon nitride tensile stress layer includes plasma-enhanced chemical vapor deposition (PECVD).

[0089] It should be noted that PECVD involves a large amount of plasma, and the introduction of plasma can damage the gate oxide quality. Gate oxide defects can cause device degradation, leading to a reduction in NBTI lifetime. To further improve NBTI lifetime, this invention first uses low-pressure chemical vapor deposition (LPCVD) to form a silicon nitride buffer layer covering the PMOS transistor 2 and the NMOS transistor 3 on the semiconductor substrate 1 before forming the silicon nitride tensile stress layer. The LPCVD method does not use plasma during the formation of the silicon nitride buffer layer, thus avoiding damage to the gate oxide quality. Furthermore, the silicon nitride formed by LPCVD has a better density than that deposited by PECVD, effectively blocking the damage to the gate oxide caused by the plasma introduced by PECVD, reducing damage to the gate oxide, and thereby improving NBTI lifetime.

[0090] It should be noted that the silicon nitride buffer layer does not introduce additional stress because the LPCVD process forms a film on both the front and back sides of the wafer, thus the stress on both sides is canceled out and will not affect the normal process. Furthermore, the silicon nitride buffer layer will eventually be removed together with the silicon nitride tensile stress layer formed by the PECVD method.

[0091] The following combination Figures 4-7 The process of using stress memory technology in one embodiment of the present invention will be described in detail below.

[0092] Specifically, Figure 4 The diagram shows the structure obtained after forming an etch stop layer 8 covering the PMOS transistor 2 and the NMOS transistor 3 on the semiconductor substrate 1. The etch stop layer 8 serves as a stop layer when the silicon nitride tensile stress layer is removed later, protecting the silicon nitride sidewalls.

[0093] As an example, a layer of DARC (Double Anti-Reflective Coating) is deposited as the etching stop layer 8.

[0094] Specifically, Figure 5The diagram shows the structure obtained after forming a silicon nitride buffer layer 9 covering the PMOS transistor 2 and the NMOS transistor 3 on the semiconductor substrate 1 using the LPCVD method. The back side of the semiconductor substrate 1 is also deposited with a silicon nitride buffer layer 9, so the stress on the front and back sides will be offset and will not affect the normal process.

[0095] Figure 6 The diagram shows the structure obtained after forming a silicon nitride tensile stress layer 10 covering the PMOS transistor 2 and the NMOS transistor 3 on the semiconductor substrate 1, wherein the silicon nitride buffer layer 9 and the silicon nitride tensile stress layer 10 have a certain thickness ratio.

[0096] Specifically, a thinner LPCVD silicon nitride layer is used as the silicon nitride buffer layer 9 to block plasma and protect the substrate. At the same time, because the silicon nitride buffer layer 9 is thinner, it has less impact on the stress applied to the silicon nitride tensile stress layer 10 formed by PECVD.

[0097] As an example, the thickness ratio of the silicon nitride buffer layer 9 to the silicon nitride tensile stress layer 10 is in the range of 1:3 to 1.5:3.

[0098] As an example, after the silicon nitride tensile stress layer 10 is formed, it is first cleaned, and then spike annealing and laser annealing are performed in sequence. The purpose of spike annealing is to diffuse the implanted ions to achieve the desired device performance, and the purpose of subsequent laser annealing is mainly to release the stress of the silicon nitride tensile stress layer 10.

[0099] Specifically, Figure 7 The diagram shows the structure obtained after removing the silicon nitride tensile stress layer 10 and the silicon nitride buffer layer 9. In some embodiments, the silicon nitride tensile stress layer 10 and the silicon nitride buffer layer 9 can be removed by a phosphoric acid solution, stopping at the etching stop layer 8, after which wet cleaning can be further performed.

[0100] It should be noted that in some embodiments, the crystal plane of the semiconductor substrate is (100), and the tensile stress generated by the annealing of the silicon nitride tensile stress layer on the (100) crystal plane will only affect the NMOS and have no effect on the PMOS. Therefore, although the silicon nitride tensile stress layer is grown on both the NMOS and the PMOS, the stress of the silicon nitride tensile stress layer after annealing will only affect the NMOS and have no effect on the PMOS. Therefore, it is not necessary to remove the silicon nitride tensile stress layer on the PMOS before annealing, but it can be removed uniformly after annealing.

[0101] Thus, the fabrication method of the MOS device of the present invention improves upon the original process method and uses a new process flow, reducing interface defects in the base oxide layer / semiconductor substrate and reducing defects in the gate dielectric layer, thereby achieving the goal of improving device reliability.

[0102] Example 2

[0103] This embodiment provides a MOS device, including a semiconductor substrate and a PMOS transistor. The PMOS transistor includes a gate structure on the semiconductor substrate, sidewalls on both sides of the gate structure, and source / drain regions in the semiconductor substrate. The gate structure includes a gate dielectric layer and a gate conductive layer on the gate dielectric layer. The gate dielectric layer is a base oxide layer with nitrogen introduced. The base oxide layer is formed on the surface of the semiconductor substrate using a rapid thermal oxidation method. The average nitrogen concentration in the base oxide layer reaches a preset value, and the region with the highest nitrogen concentration is far from the interface between the base oxide layer and the semiconductor substrate, thereby reducing interface defects and improving NBTI lifetime. In some embodiments, the MOS device further includes an NMOS transistor, which is separated from the PMOS transistor by an isolation structure in the semiconductor substrate. The NMOS transistor includes a gate structure on the semiconductor substrate, sidewalls on both sides of the gate structure, and source / drain regions in the semiconductor substrate.

[0104] As an example, the MOS device was fabricated using the method described in Embodiment 1.

[0105] In summary, the fabrication method of the MOS device of the present invention employs a rapid thermal oxidation method to form a base oxide layer on the surface of a semiconductor substrate, and introduces nitrogen into the base oxide layer until the average nitrogen concentration in the base oxide layer reaches a preset value. The nitrogen ion concentration is maximized at a point far from the interface between the base oxide layer and the semiconductor substrate. Then, a nitriding and annealing process is performed to fabricate a PMOS transistor. The gate dielectric layer of the PMOS transistor uses the aforementioned nitrogen-introduced base oxide layer. In this invention, the rapid thermal oxidation method for forming the base oxide layer on the semiconductor substrate reduces the introduction of hydrogen. Introducing nitrogen into the base oxide layer and ensuring that the nitrogen ion concentration is maximized at a point far from the interface between the base oxide layer and the semiconductor substrate reduces the impact on Si-H bonds, reduces interface defects, and thus improves NBTI lifetime. In an optional embodiment of the present invention, stress proximity technology can be further introduced to improve NMOS performance. Specifically, before forming the silicon nitride tensile stress layer, an LPCVD method can be used to form a silicon nitride buffer layer to protect the gate dielectric layer. During the subsequent formation of the silicon nitride tensile stress layer via PECVD, this buffer layer can prevent damage to the gate dielectric layer from plasma during PECVD film formation, improving the quality of the gate dielectric layer and further enhancing device reliability. Furthermore, the silicon nitride buffer layer formed by LPCVD does not introduce additional stress because the LPCVD process forms films on both the front and back sides of the wafer; therefore, the stress on both sides is offset, without affecting normal processes. The silicon nitride buffer layer is ultimately removed along with the silicon nitride tensile stress layer formed by PECVD. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0106] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a MOS device, characterized in that, Includes the following steps: A semiconductor substrate is provided, and a basic oxide layer is formed on the surface of the semiconductor substrate using a rapid thermal oxidation method; Nitrogen is introduced into the base oxide layer until the average nitrogen concentration in the base oxide layer reaches a preset value, and the point of maximum nitrogen ion concentration is far from the interface distribution of the base oxide layer / the semiconductor substrate. Perform nitriding followed by annealing; A PMOS transistor is fabricated, the PMOS transistor including a gate structure on the semiconductor substrate, sidewalls on both sides of the gate structure and source / drain regions in the semiconductor substrate, the gate structure including a gate dielectric layer and a gate conductive layer on the gate dielectric layer, the gate dielectric layer being the base oxide layer after the introduction of nitrogen.

2. The method for fabricating a MOS device according to claim 1, characterized in that: The rapid thermal oxidation method has a temperature range of 950℃ to 1200℃ and a time range of 30 seconds to 40 seconds.

3. The method for fabricating a MOS device according to claim 1, characterized in that: The method of introducing nitrogen into the base oxide layer includes performing decoupled plasma nitriding in a machine chamber, wherein, by adjusting the working cycle of the machine chamber, the average nitrogen concentration in the base oxide layer reaches the preset value, and the point of maximum nitrogen ion concentration is far from the interface distribution of the base oxide layer / the semiconductor substrate.

4. The method for fabricating a MOS device according to claim 3, characterized in that: Adjusting the working cycle of the machine chamber includes adjusting the power supply duty cycle for the nitrogen molecule dissociation action, wherein the power supply duty cycle ranges from 5% to 15%.

5. The method for fabricating a MOS device according to claim 4, characterized in that: It also includes the step of fabricating an NMOS transistor, which is separated from the PMOS transistor by an isolation structure located in the semiconductor substrate. The NMOS transistor includes a gate structure located on the semiconductor substrate, sidewalls located on both sides of the gate structure, and source / drain regions located in the semiconductor substrate.

6. The method for fabricating a MOS device according to claim 5, characterized in that, It also includes the following steps: A silicon nitride tensile stress layer is formed on the semiconductor substrate, and the silicon nitride tensile stress layer covers the PMOS transistor and the NMOS transistor; Annealing is performed to release the stress in the silicon nitride tensile layer; Remove the silicon nitride tensile stress layer.

7. The method for fabricating a MOS device according to claim 6, characterized in that: The method for forming the silicon nitride tensile stress layer includes plasma-enhanced chemical vapor deposition.

8. The method for fabricating a MOS device according to claim 6, characterized in that: Before forming the silicon nitride tensile stress layer, a silicon nitride buffer layer covering the PMOS transistor and the NMOS transistor is first formed on the semiconductor substrate using low-pressure chemical vapor deposition. No plasma is used in the formation of the silicon nitride buffer layer.

9. The method for fabricating a MOS device according to claim 8, characterized in that: Before forming the silicon nitride buffer layer, an etch stop layer covering the PMOS transistor and the NMOS transistor is first formed on the semiconductor substrate.

10. The method for fabricating a MOS device according to claim 8, characterized in that: The thickness ratio of the silicon nitride buffer layer to the silicon nitride tensile stress layer is in the range of 1:3 to 1.5:

3.

11. The method for fabricating a MOS device according to claim 6, characterized in that: The annealing process for releasing the stress in the silicon nitride tensile layer includes peak annealing and laser annealing.

12. A MOS device, characterized in that, include: Semiconductor substrate; A PMOS transistor includes a gate structure on a semiconductor substrate, sidewalls on both sides of the gate structure, and source / drain regions in the semiconductor substrate. The gate structure includes a gate dielectric layer and a gate conductive layer on the gate dielectric layer. The gate dielectric layer is a base oxide layer with nitrogen introduced. The base oxide layer is formed on the surface of the semiconductor substrate by a rapid thermal oxidation method. The average nitrogen concentration in the base oxide layer reaches a preset value, and the point where the nitrogen ion concentration is maximum is far away from the interface distribution of the base oxide layer and the semiconductor substrate.

13. The MOS device according to claim 12, characterized in that: The MOS device further includes an NMOS transistor, which is separated from the PMOS transistor by an isolation structure located in the semiconductor substrate. The NMOS transistor includes a gate structure located on the semiconductor substrate, sidewalls located on both sides of the gate structure, and source / drain regions located in the semiconductor substrate.

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