Passivation of photovoltaic devices

Abstract

The present disclosure relates to a photovoltaic device comprising a first contact layer (120) having a first thickness, a first charge transport layer (CTL, CTL ') having a second thickness positioned over a surface of the first contact layer, a semiconductor device (100) includes a first CTL (120) having a first thickness, an absorber layer (140) having a third thickness positioned over a surface of the first CTL, a second CTL (150) having a fourth thickness positioned over a surface of the absorber layer, a second contact layer (170) having a fifth thickness positioned over a surface of the second CTL, a barrier layer (180) having a sixth thickness, an encapsulation layer (190), and a first scribe line (P3) defined by at least one surface.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 428,487, filed November 29, 2022, the contents of which are incorporated herein by reference in their entirety.

[0003] Source of Contract

[0004] This invention was carried out with government support under contract number DE-AC36-08GO28308 granted by the Energy Department. The government holds certain rights to this invention. Background Technology

[0005] Perovskite solar cells have attracted attention due to their ease of construction and ability to produce high conversion efficiencies. However, for the commercialization of this technology, the entire module, not just individual cells, must exhibit long-term durability / stability at each installation location. Large-area modules require the perovskite layers to be precisely scribed into smaller areas and connected in series and / or parallel to deliver usable voltage and minimize resistive losses. Scribe sets are typically spaced 5-10 mm apart and extend the long dimension of the module. “P3” scribing is typically performed with metal styluses or high-power lasers, which essentially removes the back-side electrode and often also the perovskite and the layers in between, creating a core weakness that has been noted as rapidly degrading. Lasers and even mechanical scribing systems expose layers within the stack and can damage the perovskite layers via heating or ablation. Therefore, compositions, devices, and / or methods that can minimize and / or counteract the potential negative consequences of scribing applied to perovskite photovoltaic devices remain in demand. Summary of the Invention

[0006] One aspect of this disclosure is a photovoltaic device comprising a first contact layer having a first thickness, a first charge transport layer (CTL) having a second thickness positioned on the surface of the first contact layer, an absorber layer having a third thickness positioned on the surface of the first CTL, a second CTL having a fourth thickness positioned on the surface of the absorber layer, a second contact layer having a fifth thickness positioned on the surface of the second CTL, a barrier layer having a sixth thickness, an encapsulation layer, and a first scribe line defined by at least one surface. Furthermore, at least a portion of the barrier layer is positioned between the encapsulation layer and the second CTL, at least one surface of the scribe line includes at least a portion of the third, fourth, fifth, and / or at least a portion of the second thickness, and the barrier layer is disposed on at least a portion of the at least one surface formed by the first scribe line.

[0007] In some embodiments of this disclosure, the photovoltaic device may further include a second scribe line defined by at least one surface, wherein at least one surface of the second scribe line includes at least a portion of a second thickness, a third thickness, a fourth thickness, and a fifth thickness, and a barrier layer is disposed over at least a portion of at least one surface of the second scribe line. In some embodiments of the invention, at least one surface of the first scribe line may include a first contact layer, a first CTL layer, an absorbent layer, a second CTL layer, and a portion of the second contact layer.

[0008] In some embodiments of the present invention, the absorbent layer may have a composition comprising ABX3, wherein A is a first cation, B is a second cation, and X comprises at least one halide. In some embodiments of the present disclosure, the second cation may comprise at least one of tin and / or lead. In some embodiments of the present disclosure, the first cation may comprise at least one of formamidinium (FA), methylammonium (MA), and / or cesium.

[0009] In some embodiments of the present invention, the barrier layer may include at least one of a metal oxide, a polymer, a resin, an aryl ammonium halide, an alkyl ammonium halide, and / or lead sulfate. In some embodiments of the present invention, the metal oxide may include at least one of alumina, silicon oxide, tin oxide, zirconium oxide, and / or titanium oxide. In some embodiments of the present invention, the aryl ammonium halide may include at least one of phenylethyl ammonium iodide (PEAI), 1-(acetylammonium)pyrene (PEY), and / or dodecyl ammonium chloride (DACl).

[0010] In some embodiments of the present invention, the thickness of the barrier layer may be between 20 nm and 1500 nm. In some embodiments of the present invention, the barrier layer may have a transmittance greater than 80% at wavelengths greater than 700 nm, as measured by the thickness of the barrier layer. In some embodiments of the present invention, the photovoltaic device may further include a buffer layer located between the absorber layer and the second contact layer, wherein the buffer layer comprises an oxygen-containing salt. In some embodiments of the present invention, the second charge transport layer may comprise a fullerene. In some embodiments of this disclosure, the absorber layer may comprise at least one of perovskite, silicon, III-V alloys, organic photovoltaic materials, dye-sensitized materials, copper indium gallium selenide alloys, and / or cadmium telluride alloys. In some embodiments of the present invention, the barrier layer may comprise a water-insoluble material.

[0011] One aspect of this disclosure is a method of manufacturing a photovoltaic device stack, wherein the method includes forming a barrier layer on the photovoltaic device stack, wherein the device stack includes a first contact layer having a first thickness, a first charge transport layer (CTL) having a second thickness positioned above a surface of the first contact layer, an absorber layer having a third thickness positioned above a surface of the first CTL, a second CTL having a fourth thickness positioned above a surface of the absorber layer, a second contact layer having a fifth thickness positioned above a surface of the second CTL, and a first scribing defined by at least one surface. Furthermore, at least one surface of the first scribing includes at least a portion of the third, fourth, fifth, and / or at least a portion of the second thickness, and the barrier layer includes at least one of a metal oxide, polymer, resin, aryl ammonium halide, alkyl ammonium halide, and / or lead sulfate, and the barrier layer is formed on at least a portion of at least one surface of the first scribing.

[0012] In some embodiments of the present invention, the device stack may further include a second scribe line, wherein the second scribe line may be defined by at least one surface, the at least one surface of the second scribe line comprising a first thickness, a second thickness, a third thickness, a fourth thickness, and / or a fifth thickness, and the barrier layer is located over at least a portion of the at least one surface of the second scribe line. In some embodiments of the present invention, the barrier layer may comprise a metal oxide, and the metal oxide includes aluminum oxide, silicon oxide, tin oxide, zirconium oxide, titanium oxide, or combinations thereof.

[0013] In some embodiments of the invention, the thickness of the barrier layer may be between 20 nm and 1500 nm, and as measured by the thickness of the barrier layer, the barrier layer may have a transmittance greater than 80% at wavelengths greater than 700 nm. In some embodiments of the invention, the barrier layer may comprise a water-insoluble material. Attached Figure Description

[0014] Some embodiments are shown in the accompanying drawings. The embodiments and drawings disclosed herein should be considered illustrative rather than restrictive.

[0015] Figure 1A Exemplary device stacks comprising multiple layers are shown according to some embodiments of the present disclosure, which can be used in fully functional solar cells and / or solar modules.

[0016] Figure 1B Exemplary device stacks, as experimentally tested and described herein, are shown according to some embodiments of this disclosure. Such devices without any scribing lines are referred to herein as "test stacks".

[0017] Figure 2AA test stack with scribe lines P3, including such scribe lines as described herein and in experimental tests, is shown according to some embodiments of this disclosure. This scribe test stack is substantially equivalent to... Figure 1B The “test stack” shown is an example of a stack with P3 scribing lines added, and is referred to herein as a “scibing test stack”.

[0018] Figure 2B Exemplary device stacks according to some embodiments of this disclosure are shown, comprising all layers that can be used in a fully functional solar cell and / or solar module, including scribing lines P1, P2, and P3. A similar device having at least one scribing line P3 and two cells electrically connected in series is referred to herein as a “test module”. In the experiments described herein, the first CTL 130 is configured as an HTL, and the second CTL 150 is configured as an ETL. However, this is not limiting; the first CTL 130 may be either an ETL or an HTL, and the second CTL 150 may be either an HTL or an ETL.

[0019] Figure 2C A schematic side cross-sectional view of scribe lines according to some embodiments of the present disclosure is shown.

[0020] Figure 3 Test stacks of glass substrate / ITO / PTAA / perovskite / Al2O3 stacks according to some embodiments of the present disclosure are shown (see [link]). Figure 1B Optical transmittance data in the ultraviolet and visible light range (UV-VIS). Test conditions were as follows: the test stack was evaluated at intervals for 0 to 10¹⁰ hours in ambient air (relative humidity [RH] ~30-40%) without additional heating or cooling, under light equivalent to approximately 0.7 AM 1.5 sun intensity.

[0021] Figure 4 Test stacks of glass substrate / ITO / PTAA / perovskite / polystyrene stacks according to some embodiments of this disclosure are shown (see [link]). Figure 1B The UV-VIS data were obtained. The test conditions were as follows: the test stack was evaluated at intervals of 0 to 10¹⁰ hours under ambient air conditions (RH ~ 30-40%) without additional heating or cooling, at an intensity equivalent to approximately 0.7 AM 1.5 sunlight.

[0022] Figure 5 Test stacks of glass substrate / ITO / PTAA / perovskite stacks (without a barrier layer) according to some embodiments of this disclosure are shown (see [link]). Figure 1BThe UV-VIS data were obtained. The test conditions were as follows: the test stack was evaluated intermittently for 0 to 10¹⁰ hours under ambient air (RH ~ 30-40%) without additional heating or cooling, and under light equivalent to approximately 0.7 AM 1.5 sunlight intensity.

[0023] Figure 6 Various test stacks of glass substrate / ITO / PTAA / perovskite / barrier layer according to some embodiments of this disclosure were compared (see [link]). Figure 1B The performance of the light, such as that measured over time by UV-VIS optical density (OP). The test conditions are as follows: optical density coefficient measured at a wavelength of 700 nm, obtained from percentage transmittance data, such as... Figure 3 , 4 As shown in Figure 5. When placed in ambient air (RH ~30-40%) without additional heating or cooling, the test stack was evaluated at intervals for 0 to 10¹⁰ hours under light equivalent to approximately 0.7 AM 1.5 sunlight intensity.

[0024] Figure 7 The test stack control and a method according to some embodiments of the present invention are shown. Photographs of the test stack of the initial superbarrier combined with PEIE, the superbarrier being the first barrier layer to withstand 85°C for over 100 hours, and representing as Figures 3 to 6 The obvious differences between the control and barrier layer test stacks are shown because they appeared after the test was completed.

[0025] Figure 8-10 The test stack containing perovskite is shown in the diagram (see [link]). Figure 2A (and initial testing of eight selected barrier layer materials). Figure 8 The test stack is depicted after being subjected to a water droplet test. Figure 9 The test stack was depicted with scratches on a hot plate at 85°C for 192 to 672 hours, and it was a thermal test. Figure 10 The test stack was depicted under ambient air (RH ~ 30-40%) and sunlight intensity of 0.7 AM 1.5 for 192 to 672 hours, and was subjected to light testing. Figure 8-10 The test results of eight initially selected barrier materials according to some embodiments of this disclosure are shown, resulting in the removal of PMMA, PS, SiO, etc. x Al2O3 and CYTOP PEIE superbarrier materials were selected as the best barrier material options, as described in this article.

[0026] Figure 11This illustration shows ten IZO top-contact perovskite test modules preceding the deposition of a barrier layer material, according to some embodiments of this disclosure (see [link]). Figure 2B The same module after the deposition of the corresponding barrier layer material, and the control that remained uncoated.

[0027] Figure 12A This invention illustrates coatings with various barrier materials (Al2O3, PMMA, PS, and SiO2) according to some embodiments of the present disclosure. x And fill the perovskite-containing test module with the scribing lines of P2 and P3 (see) Figure 2B SEM images of the following films: Image A): SEM image (30K magnification) of the Al2O3 film completely covering the bottom and sidewalls of the P2 scribings, with a known thickness of 50 nm. Image B): SEM image of the PMMA film filling the P3 scribings, with thicknesses ranging from 1.33 μm at the top of the module to 1.59 μm within the scribings (20K magnification). Image C): SEM image of the PS film filling the P2 scribings, with thicknesses ranging from 1.40 μm at the top of the module to 2.07 μm within the scribings (20K magnification). Image D): SEM image of the SiO2 film filling the P3 scribings. x SEM image of the membrane with a known thickness of 1000 nm (20K magnification).

[0028] Figure 12B The invention illustrates some embodiments of SiO2. x A larger version of the SEM image of the test module for the blocking layer, with the scribing lines P3, annotated (call out) various layers.

[0029] Figure 12C A test module according to some embodiments of this disclosure is shown (the module is shown using SiO2). x SEM images of P3 scribings filled with PMMA were used to depict the barrier material uniformly and completely filling the entire width of the scribings, with the width of the P3 scribings marked.

[0030] Figure 13 From left to right, four barrier materials Al2O3, SiO2, and SiO2 are shown on blank glass / ITO microscope slides according to some embodiments of the present invention. x PMMA and PS.

[0031] Figure 14A A schematic plan view of a photovoltaic device assembly according to some embodiments of the present disclosure is shown.

[0032] Figure 14B A schematic side cross-sectional view of a portion of a photovoltaic device array according to some embodiments of the present disclosure is shown.

[0033] Figure 14C A schematic side cross-sectional view of a portion of a photovoltaic device array according to some embodiments of the present disclosure is shown.

[0034] Figure 15 Methods for manufacturing photovoltaic device modules according to some embodiments of the present disclosure are shown.

[0035] Figure 16A-16L A schematic diagram of the photovoltaic device stack during various stages of manufacturing a photovoltaic device according to the method disclosed herein is shown.

[0036] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is contemplated that elements and features of one embodiment can be advantageously incorporated into other embodiments without further description.

[0037] Figure Labels

[0038] 100......................devices 110......................First substrate layer 115......................Second substrate layer 120......................First Contact Layer 130......................First Charge Transport Layer (CTL) 140......................Absorbent layer 150......................Second Charge Transport Layer (CTL) 160...................... Buffer layer 170......................Second Contact Layer 180......................one or more barrier layers 190......................Encapsulation layer Pl.......................First engraving line P2.......................Second clef P3.......................Third clef P4.......................Fourth puncture line Specific implementation plan

[0039] The embodiments described herein should not necessarily be construed as limiting oneself to solving any particular problem or defect discussed herein. References to “an embodiment,” “an embodiment,” “an exemplary embodiment,” “some embodiments,” etc., in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic; however, each embodiment may not necessarily include that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is considered that incorporating other embodiments to affect that feature, structure, or characteristic is within the knowledge of those skilled in the art, regardless of whether it is explicitly described.

[0040] As used herein, the term "basic" is used to indicate a precise value that may not be readily available. For example, those skilled in the art will understand that in some chemical reactions, 100% conversion of reactants is possible, but unlikely. Most reactants can be converted into products, and the conversion rate of reactants can asymptotically approach 100% conversion. Therefore, although 100% conversion of reactants is practically possible, from a technical point of view, a small and sometimes difficult-to-define amount remains. In this example of a chemical reactant, this amount can be relatively easily defined by the detection limits of the instrument used to test it. However, in many cases, this amount may not be easily defined, hence the use of the term "basic." In some embodiments of the invention, the term "basic" is defined as within 20%, 15%, 10%, 5%, or 1% of a specific value or target. In a further embodiment of the invention, the term "basic" is defined as being close to a specific value or target within 1%, 0.9%, 0.8%, 0.7%, 0.6%, 0.5%, 0.4%, 0.3%, 0.2%, or 0.1% of that value or target.

[0041] As used herein, the term "about" is used to indicate a precise value that may not be readily available. Therefore, the term "about" is used to indicate the limit of uncertainty. In some embodiments of the invention, the term "about" is used to indicate an uncertainty limit of less than or equal to ±20%, ±15%, ±10%, ±5%, or ±1% for a specific numerical value or target. In some embodiments of the invention, the term "about" is used to indicate an uncertainty limit of less than or equal to ±1%, ±0.9%, ±0.8%, ±0.7%, ±0.6%, ±0.5%, ±0.4%, ±0.3%, ±0.2%, or ±0.1% for a specific numerical value or target.

[0042] This disclosure relates to barrier layers, or absorbent layers, for devices comprising a perovskite active layer. In particular, some barrier layers described herein protect the underlying perovskite structure from degradation due to undesirable exposure to moisture. Furthermore, some barrier layers are highly effective in preventing and / or minimizing degradation of the perovskite when exposed to heat, light, and / or moisture. Additionally, as shown herein, some materials tested on barrier layers are also highly effective in protecting perovskite-containing devices with scribe lines.

[0043] Generally, the term "perovskite" refers to a composition having a shared-angle BX6 octahedral network, which produces the general stoichiometry of ABX3. Perovskites, such as metal halide perovskites, can be organized into a three-dimensional (3D) cubic crystal structure (i.e., α-phase or α-ABX3) consisting of multiple shared-angle BX6 octahedra. In the general stoichiometry of perovskite ABX3, X is an anion, while A and B are cations, typically of different sizes. Perovskites with an α-phase structure are also characterized by eight BX6 octahedra surrounding a central A-cation, wherein each octahedron is formed by six X-anions surrounding the central B-cation, and each octahedron is connected together by the "shared-angle" connection of the anions X.

[0044] In the α-phase, perovskite can be viewed as a cubic unit cell, with B cations located at the center of the cube, A cations at each corner, and X anions face-centered on each face. The X-anions and B-cations in the α-phase perovskite are aligned along axes; for example, the angle between two adjacent B cations and the X anion is exactly 180 degrees, referred to here as the tilt angle. However, perovskite can exhibit other co-angular crystalline phases with tilt angles not equal to the angle. For example, perovskite can also exhibit a tetragonal phase (i.e., β-ABX3) and / or an orthorhombic phase (i.e., γ-ABX3), where adjacent octahedrons are tilted relative to reference axes a, b, and c. Furthermore, as described above, the elements used to construct perovskite, A-cations, B-cations, and X-anions, can produce 3D non-perovskite structures; i.e., structures where adjacent BX6 octahedrons are not co-angularly connected by X-anions and / or do not have a unit cell structure simplified to ABX3 stoichiometry. One instance of a non-perovskite structure is characterized by coplanar BX6 octahedra, resulting in a hexagonal crystalline structure, while a second instance of a non-perovskite structure is characterized by edge-sharing BX6 octahedra, resulting in an orthorhombic crystalline structure.

[0045] Furthermore, as described above, the elements used to construct perovskites, A-cations, B-cations, and X-anions, can produce non-3D (i.e., lower-dimensional structures) perovskite-like structures, such as two-dimensional (2D), one-dimensional (1D), and / or zero-dimensional (0D) structures. For simplicity, as used herein, the term "perovskite" refers to each of these various structures. Therefore, unless otherwise specified, the term "perovskite" as used herein includes every true co-angularly connected ABX3 perovskite, as well as perovskite-like compositions having 0D, 1D, and / or 2D structures. Some of the barrier layers described herein have been shown to be highly effective in preventing perovskites from degrading to non-perovskite structures due to prolonged exposure to moisture, heat, and / or light. Furthermore, while much of this disclosure focuses on the use of barrier layers to benefit perovskite-containing devices, at least some of the same barrier layers have been designed to protect other semiconductor and / or photovoltaic materials from moisture, heat, and / or light.

[0046] Figure 1A An exemplary device stack comprising multiple layers is shown, which can be used in a fully functional solar cell and / or solar module. In some embodiments of the invention, a device 100, such as a solar cell, having an absorber layer 140 (protected by one or more barrier layers 180), may also have one or more additional layers in addition to the absorber layer 140 and one or more barrier layers 180. The device is illustrated for illustrative purposes, showing various layers that may be included in a solar cell device stack. For example, device 100 may sequentially include a first substrate layer 110, a first contact layer 120, a first charge transport layer 130, an absorber layer 140 (e.g., a perovskite layer), a second charge transport layer 150, a second contact layer 170, one or more barrier layers 180, an encapsulation layer 190, and a second substrate layer 115.

[0047] Refer again Figure 1A The illustrated device 100 may be a solar cell rather than a module, as the illustrated device may lack scribing lines, which typically separate the absorber layer and / or other layers into individual cells on a module. In some embodiments of this disclosure, one or more barrier layers 180 may be deposited after the deposition of the absorber layer 140. Therefore, the barrier layer 180 described herein can be used in inverted or conventional solar cells as well as pin or nip solar cells. Furthermore, the barrier layer 180 described herein can be used in single-junction or multi-junction solar cells. In some embodiments of this disclosure, one or more barrier layers 180 of the solar cell may be positioned adjacent to the hole transport layer (HTL), electron transport layer (ETL), and / or absorber layer 140 (e.g., a perovskite layer).

[0048] Therefore, a device 100, such as a solar cell, utilizing a barrier layer 180 similar to those described herein, can be a stacked device. For example, a solar cell may sequentially include an absorber layer 140 (e.g., a perovskite layer), a second charge transport layer (CTL) 150 as an ETL, a second contact layer 170, and one or more barrier layers 180.

[0049] Figure 1B An exemplary device is shown for simulating a portion (without scribe lines) of a solar cell used to test the protective effectiveness of various barrier layers, as described in more detail below. Reference Figure 1B A barrier layer 180 is disposed in direct contact with the underlying perovskite absorber layer 140, without any additional layers in between, such as a second contact layer and / or a second charge transport layer. This simplification of the device stack eliminates the potential protection provided by layers other than the barrier layer and simplifies the analysis of direct comparative studies of the various barrier materials tested. (See again...) Figure 1B Devices that use this architecture and are tested in the laboratory are referred to here as "test stacks".

[0050] Figure 2A A simplified device stack similar to that used for testing "scribe-based test stacks" is shown. Scribbled test stacks are essentially the same as conventional test stacks, such as... Figure 1B As shown, but with the addition of a scribing line marked P3. A simplified scribing test stack architecture is constructed, as follows. Figure 1B The test stack shown simplifies the evaluation of the effectiveness of various barrier layers that not only coat the surface of the underlying perovskite layer but also protect the perovskite exposed by the P3 scribing lines.

[0051] In addition, tests were conducted using a barrier layer similar to... Figure 1A The device shown is a fully functional device, but it lacks the encapsulation layer 190 or the second substrate layer 115, and has added scribing lines.

[0052] Figure 2B Exemplary device stacks according to some embodiments of this disclosure are shown, comprising all layers that can be used in a fully functional solar cell and / or solar module, and including two additional scribing lines P1 and P2 in addition to P3. A similar device having at least scribing line P3 and two cells connected in series is referred to herein as a "test module". In the experiments described herein, the first CTL 130 is configured as an HTL and the second CTL 150 is configured as an ETL. However, this is not limiting; the first CTL 130 may be either an ETL or an HTL, and the second CTL 150 may be either an HTL or an ETL.

[0053] In this example, a barrier layer 180 is used to cover, coat, and / or fill the scribing line P3, which is mechanically and / or laser-cut into device 100, thereby creating a solar cell module with two series-connected cells. The device utilizing this stacked design is referred to herein as a "test module," and each includes each of the first scribing line P1, the second scribing line P2, and the third scribing line P3, and two solar cells connected in series. Reference Figure 2B In this example, the third scribing line P3 is filled with one or more barrier materials as described herein, and the third scribing line P3 completely penetrates several layers of device 100, penetrates at least the thickness of the second contact layer 170, and more specifically also penetrates the second CTL 150, absorbent layer 140, first CTL 130, and possibly some portions of the first contact layer 120. Although Figure 2B The third scribe line P3 shown is at least partially filled with a barrier material, but depending on the specific solar cell module design, in some embodiments of this disclosure, other scribe lines may be at least partially filled with one or more barrier layers as described herein.

[0054] Figure 2C Part A shows Figure 2B A portion of the device shown highlights the P3 scribing line. In this example, the scribing line is shown as a channel passing through the thickness of each of the first CTL 130, absorbent layer 140, second CTL 150, and second contact layer 170. Furthermore, this exemplary scribing line is shown as having walls and / or surfaces positioned substantially perpendicular to the alignment of the layers constituting the device stack. Figure 2C The exemplary scribing line shown in sub-figure A is characterized by having a top width w1 equal to the bottom width w2, and all intermediate widths of the scribing line are also equal to w1. Therefore, Figure 2C The scribing line shown in Figure A can be described as having a cross-section or profile defined by a first width w1 at a first reference point located along the reference axis y and a second width w2 at a second reference point located along the reference axis y, wherein w1 is equal to w2, and wherein the two endpoints are connected by a straight line, and the resulting sidewalls and / or surface of the scribing line are defined by a flat plane. In some embodiments of the invention, the scribing line, such as scribing line P3, may have a surface and / or sidewalls aligned with the y-axis, wherein the y-axis is perpendicular to the x-axis. However, Figure 2C The scribing shown in Figure A is only one possible example of the P3 scribing and / or any other scribing described herein and shown for illustrative purposes.

[0055] Refer again Figure 2CIn Figure A, a barrier layer 180 is deposited on the outer surface of the second contact layer 170, forming a conformal layer that prevents any lower surface of the second contact layer from being exposed to the environment. Furthermore, in this example, the material constituting the barrier layer 180 completely fills the scribing lines and completely covers all surfaces defining the groove-like features of the scribing lines, including the bottom surface and sidewalls. However, as described below, the barrier layer 180 may be conformally coated and only partially fill the formed scribing lines.

[0056] However, scribing lines produced by laser and / or mechanical etching may rarely have a surface that is perfectly straight and perpendicular to the layer through which the scribing lines penetrate. Figure 2C Subplot BD shows three additional exemplary contours with scribing lines. Subplot C shows contours with... Figure 2C The scribing lines shown in Figure A have a very similar profile, except that the second width w2 is smaller than the first width w1. However, as in the previous example, the two endpoints are connected by a straight line, and the resulting sidewalls defining the scribing lines are flat surfaces. Figure 2C Subplots B and C show examples of scribe lines defined by a width that varies as a function of the scribe line depth (relative to the y-axis). For example... Figure 2C As shown in Figure B, the scribing line can have sidewalls defined by a continuous curve, resulting in a non-linearly curved surface on the sidewalls. In this example, the width of the scribing line decreases as a function of the scribing line depth. Figure 2C As shown in sub-figure D, the scribing line can have sidewalls defined by irregularly shaped curves, resulting in a non-linear curved surface on the sidewalls, and in some cases forming a scribing line with a width w2 greater than the first width w1. However, as Figure 12B As shown in the SEM images, the sidewalls of the scribing line may be irregular and not easily described by a simple profile fitted with a linear and / or nonlinear function. However, in each instance, for the scribing line to serve its intended purpose, the empty spaces, voids, and / or channels formed by the scribing process will have a cross-section defined by a first width w1 and a second width w2, i.e., a profile located in the XY plane, such that the empty space extends from the first width to the second width without any physical barrier preventing the empty space from being filled with a barrier layer material. For the purpose of clarity of discussion, as used herein, the term "width of the scribing line" is intended to refer to the first width w1 in order to describe the measurable characteristics of the scribing line. The first width w1 is typically defined by an opening formed at the uppermost portion of the scribing line, as measured relative to a plane (e.g., the XZ plane) parallel to the uppermost surface through which the scribing line is formed. In one instance, as Figure 2C As shown in Figure A, the first width w1 is measured at the opening formed at the top surface of the second contact layer 170.

[0057] Refer again Figure 1Aand 2B An exemplary device having all elements for a fully functional solar cell and / or module, such as a first contact / HTL / absorbent layer / ETL / second contact, is shown, illustrating a barrier layer deposited on the outermost surface of the device. This is not intended to be limiting, and the barrier material / layer as described herein may be located in and / or elsewhere on the device stack. For example, in some embodiments of this disclosure, the barrier layer / material may be located between a perovskite layer and an adjacent charge transport layer ETL and / or HTL. In some embodiments of this disclosure, the barrier layer / material may be located between a charge transport layer and a contact layer. The location of the barrier layer / material will depend on the specific device stack architecture and the intended use of the device.

[0058] Examples of materials shown herein that provide excellent barrier properties for test cells and test modules, as measured by exposure to moisture, heat, and / or light, include polystyrene (PS), polydimethylsiloxane (PDMS), polyethyleneimine (PEIE), polymethyl methacrylate (PMMA), lead sulfate, phenylethyl ammonium iodide (PEAI), fluorinated hydrocarbon polymers, and / or metal oxides, such as silica and / or alumina. In some embodiments of this disclosure, the device may incorporate at least two barrier layers disposed adjacent to each other, wherein at least one barrier layer is made of a material different from the materials of the remaining barrier layers.

[0059] Any suitable material can be used for other layers in the device stack, solar cell, and / or solar module, and will vary depending on the intended use. For example, at least one substrate layer, first substrate layer 110, second substrate layer 115, or both, can be constructed using metal foil, glass, and / or polymer substrates. In some embodiments of this disclosure, at least one contact layer, first contact layer 120, second contact layer 170, or both, can be constructed using transparent conductive oxides, such as indium zinc oxide, indium tin oxide, tin oxide, or fluorine-doped tin oxide. In some embodiments of this disclosure, at least one of the contact layers, first contact layer 120, second contact layer 170, or both, can be constructed using metals such as aluminum, copper, silver, and / or gold. In some embodiments of this disclosure, one of the charge transport layers (CTLs), the first CTL 130 and the second CTL 150, can be constructed using hole transport materials, such as poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA), [N,N'-bis(4-butylphenyl)-N,N'-bis(phenyl)-benzidine] (polyTPD), NiO xSelf-assembled monolayers (SAMs) of molecules, wherein the SAM may include functional groups having carbazole and phosphorus on the listed transparent conductive oxide (TCO) or hole transport material. Some examples of SAMs include at least one of [2-(9H-carbazole-9-yl)ethyl]phosphonic acid (2PACz), [4-(9H-carbazole-9-yl)ethyl]phosphonic acid (4PACz), 2-(3,6-dimethyl-9H-carbazole-9-yl)ethyl)phosphonic acid (Me-2PACz), [4-(3,6-dimethyl-9H-carbazole-9-yl)butyl]phosphonic acid (Me-4PACz), [2-(3,6-dimethoxy-9H-carbazole-9-yl)ethyl]phosphonic acid (MeO-2PACz), and / or (4-(3,6-dimethoxy-9H-carbazole-9-yl)butyl)phosphonic acid (MeO-4PACz). In some embodiments of this disclosure, other CTLs not composed of hole transport materials, such as the first CTL 130 and the second CTL 150, can be composed of electron transport materials, such as metal oxides, like at least one of TiO2, SnO2, Al2O3, and ZnO, or carbon contactors such as carbon nanotubes and fullerenes (e.g., C4N4). 60 and or C 70 ), fullerene derivatives [6,6]-phenyl-C 61 1,4-methyl butyrate, and fullerenes (PCBM) used alone or in combination with copper bath (BCP) or SnO2 or other metal oxides. All these materials are provided as examples and should not be considered limiting.

[0060] In some embodiments of this disclosure, the indium tin oxide (ITO) layer may have a thickness between 50 nm and 1000 nm. In some embodiments of this disclosure, the PTAA layer or nickel oxide layer may have a thickness between 5 nm and 100 nm. In some embodiments of this disclosure, the absorber layer, such as perovskite, may have a thickness between 200 nm and 1500 nm. In some embodiments of this disclosure, C... 60 The layer may have a thickness between 15 nm and 35 nm. In some embodiments of this disclosure, the BCP layer may have a thickness between 4 nm and 20 nm. In some embodiments of this disclosure, the SnO2 layer may have a thickness between 4 nm and 30 nm. In some embodiments of this disclosure, the IZO layer may have a thickness between 50 nm and 500 nm. In some embodiments of this disclosure, the third scribing line P3 may have a width between 5 μm and 200 μm. In some embodiments of this disclosure, the third scribing line P3 may have a depth between 100 nm and 3 μm. Furthermore, other materials may be used as required or required by a particular application or use. Figure 1A Any of the layers shown in 1B, 2A and / or 2B.

[0061] Refer again Figure 1A In some embodiments of this disclosure, device 100 may include an encapsulation layer 190 positioned adjacent to barrier layer 180. Alumina, SiO2, or similar materials may be used. x Poly(methyl methacrylate) (PMMA), polystyrene (PS), (See Structure 1 below) or at least one of PEIE to construct the encapsulation layer 190, wherein x is greater than zero and less than or equal to two.

[0062]

[0063] In some embodiments of this disclosure, the absorber layer 140 of devices such as solar cells and / or solar modules may use a perovskite structure as described herein. However, devices using other light-absorbing photovoltaic materials may also utilize the concepts and materials described herein, and perovskite is not intended to be limiting. Other examples of absorber materials that can be combined with the barrier layers described herein include silicon (amorphous and crystalline), III-V materials (amorphous and crystalline), organic photovoltaic materials (OPV), dye-sensitized solar cells (DSSC), copper indium gallium selenide solar cells (CIGS), and / or cadmium telluride solar cells (CdTe). The barrier layers described herein can be applied to single-junction solar cells, tandem solar cells, and multi-junction solar cells.

[0064] In some embodiments of this disclosure, a barrier layer can be provided using an ink applied using a solution processing method. This ink may include materials and / or precursor materials required to form the barrier layer, such as at least one of polystyrene (PS), polydimethylsiloxane (PDMS), polyethyleneimine (PEIE); polymethyl methacrylate (PMMA), lead sulfate, phenylethyl ammonium iodide (PEAI), and / or fluorinated hydrocarbon polymers. Furthermore, in some embodiments of this disclosure, the ink used to form the barrier layer may include at least one liquid component that suspends and / or dissolves (at least one) barrier layer material and / or precursors / reactants required to form the barrier layer. In some embodiments of this disclosure, such a liquid may include acetates, such as at least one of ethyl acetate and / or methyl acetate. In some embodiments of this disclosure, the ink formulation may include one or more additives, such as one or more viscosity modifiers. The ink used to form one or more barrier layers can be applied using various solution processing methods, including, for example, doctor blade application, inkjet printing, slot die coating, spraying, and / or roll-to-roll gravure printing.

[0065] Initially, ink was developed for applying the material used to construct the barrier layer via inkjet printing, and a test module was developed for directly applying the material to fill perovskite-containing scribings (see [link]). Figure 2BHowever, difficulties and problems with printing reliability led to the need for blanket coating of barrier materials on perovskite surfaces. Therefore, a list of new inks to be cured as barrier layers as blanket coatings was ultimately designed, as described herein. Barrier materials 1-8 (listed below) were solution-treated and scraped onto test cells (scribed and unscribed) and test modules. Barrier materials 7 and 8, SiO2... x Al2O3 and Al2O3 are deposited through thermal evaporation and atomic layer deposition, respectively.

[0066] To test the effectiveness of various barrier layers, three different tests were envisioned to accelerate the degradation of the test cells. The first test is a water droplet test, which involves directly dropping deionized water (DI) droplets onto both a bare perovskite layer and a perovskite layer covered with at least one barrier layer to visually assess how quickly degradation occurs due to exposure to DI water, with each droplet having a total volume of approximately 12 μL. The second barrier material test is a thermal test, which involves placing perovskite samples (bare and protected) directly on a hot plate set to approximately 85°C and measuring the corresponding time for the transition from black to yellow (or transparent). The envisioned third barrier test is a light immersion test, which is conducted by placing perovskite samples (bare and protected) under an AM1.5 spectral lamp (at approximately 0.7 solar irradiance) in ambient air conditions and measuring the respective time for the transition from a black phase to a yellow (or transparent) phase, indicating the degradation of the perovskite crystal phase. These three tests provide a means of quantitatively measuring and comparing the effectiveness of various barrier materials in reducing the degradation of the underlying perovskite, such as by the transformation of perovskite to lead iodide, which corresponds to the material’s appearance changing from black to light yellow or transparent.

[0067] When exposed to water droplet testing, as shown in Table 1 below, the bare perovskite degrades and transforms from a first black perovskite phase to a second yellow degradation phase containing lead iodide within approximately 3 to 4 seconds. However, with repeated testing and ink formulation, the blocking layer on the test cells and scratched test cells began to show encouraging results. Many different blocking materials and formulations were conceived. However, for many months of testing, the blocking material was effective in one test but ineffective in another. Some blocking materials (in the form of layers) were able to slow the yellowing of perovskite in water droplet testing from a few seconds to a few minutes, and many blocking materials were able to effectively reduce degradation in light immersion testing. However, for these initial tests, many blocking materials did not significantly reduce degradation caused by exposure to heat (85°C on a hot plate). One exception was… A commercially manufactured fluoropolymer. Its own... All three tests ran well. However, it is worth noting that... The layer is formed by applying a solution of terpineol and polyethyleneimine (TERPEIE) to... Layer (perovskite / The combination of layers obtained on TERPEIE produces a very effective barrier layer combination. TERPEIE and Test each individually and in different combinations: PEIE then (One floor for each, two floors in total) Then it's PEIE, and then PEIE... Then it's PEIE, and then... (Two layers each, four layers in total), and Then it's PEIE, and then... Then there's PEIE (four layers in total). The first discovery of an effective thermal barrier is shown in Figure 7 In, and in the device stack-up The blocking combination with TERPEIE (two layers each): ITO / PTAA / perovskite / / TERPEIE / / TERPEIE. A combination of two or more blocking layers, such as... And TERPEIE, referred to herein as a superbarrier layer (SB). This is achieved by depositing a liquid solution of 10 wt% PEIE in terpineol onto... On TERPEIE, using These devices were coated with TERPEIE, and the liquid layer was then annealed to... A second PEIE polymer layer is formed on the fluoropolymer layer.

[0068] The / TERPEIE SB is highly effective for all three tests: water droplet test, heating test, and light immersion test. Water droplets cannot completely penetrate the barrier film, and the surface tension on the outer TERPEIE surface is low enough that water will slide off the surface when the sample is tilted at approximately 45 degrees. Furthermore, even in the extreme case where water is left on the device surface until it completely evaporates and the surface is dry, the water droplets cause only negligible damage.

[0069] Figure 8 An example of this latter experiment is shown. When tests were conducted under heating and light immersion conditions, / TERPEIE SB also performed very well. Even after many hours of heating and light immersion testing (performed independently and not continuously or simultaneously), the performance of the TERPEIE SB was excellent. The perovskite sample protected by TERPEIE SB still exhibits visually inconspicuous changes.

[0070] In addition to the three stress tests mentioned above (heat, light, and water), a fourth test was developed to demonstrate the effectiveness of the barrier material when the sample, test cell, scratched test cell, and / or test module are placed in an environment of 85°C and 85% relative humidity (RH). This stress test is referred to herein as the "85 / 85 test".

[0071] In discovery After / TERPEIE SB succeeds, confirm. It may be too expensive. Therefore, other potential barrier materials were evaluated, which could be compared with... / TERPEIE SB works just as well, but is cheaper and more scalable. However, it will... / TERPEIE SB is included as a baseline exemplifying an effective barrier in these subsequent studies. As described herein, using... Figure 2A The scratched test cell shown developed and tested eight barrier materials, with the key objective of verifying their compatibility with the device's perovskite layer, charge transport layers (HTL and ETL), and contact layer. In these initial tests, reference was made again... Figure 2A Devices with a structure consisting of a first substrate layer 110 (glass substrate / ITO), a first contact layer 120 / PTAA, a first CTL 130 (PTAA-HTL), an absorber layer 140 (perovskite), and one or more barrier layers 180 were tested (ITO = indium tin oxide; PTAA = poly(triarylamine) hole transport layer). Each test cell was scribed using at least one of laser and / or mechanical scribing prior to the deposition of the various barrier layers, with scribing lines penetrating the perovskite and HTL layers to the ITO layer. Eight barrier materials were included:

[0072] 1. Polystyrene (PS);

[0073] 2. Polydimethylsiloxane (PDMS);

[0074] 3. Polyethyleneimine (PEIE) and ( / TERPEIE SB) dual-block system;

[0075] 4. Polymethyl methacrylate (PMMA);

[0076] 5. Lead sulfate;

[0077] 6. Phenylethyl ammonium iodide (PEAI);

[0078] 7. SiO x (0 < x ≤ 2); and

[0079] 8. Al2O3.

[0080] Table 1 summarizes the eight barrier layer materials tested using a scratch-on test cell, along with the thickness of each material and the time elapsed before perovskite degradation occurred, as indicated by a color change from black to transparent in each of the four tests performed for each barrier layer material. As mentioned above, all solution-treated barriers were deposited by scratch coating, and each ink underwent optimization experiments to ensure optimal film formation for each test. Table 1 also shows the final results of all tests and the time it took for perovskite degradation to occur (indicated by a change from dark to light yellow or transparent). These barrier test results relative to a control on the eight different barrier materials are shown below. Figure 8 , 9 Table 10 summarizes the results, showing photographs taken from 192 to 627 hours. A total of 1176 hours of testing was conducted on each material, and the results are summarized in Table 1. The results of the four barrier layer tests compared to the perovskite control provide insights into the optimal barrier material and determine which material to choose for further testing. Among the barrier materials tested, PS, PMMA, and PEIE / SB, SiO x And Al2O3 to further study perovskite modules.

[0081] Table 1: Comparison of eight barrier materials coated on perovskite-scratched test cells in four tests for each barrier material.

[0082]

[0083] After testing these eight barrier materials in a scratched test cell, it was clear that five outperformed the rest. Although PEIE / SB works well, but cost and complexity issues prevent the material from being practically scaled up to commercial production levels. However, due to the high effectiveness of the combination, PEIE / SB was compared with the effectiveness of other barrier materials. Four barrier materials that not only passed stress tests but were also economically and commercially available were PS, PMMA, and SiO2. x And Al2O3. The performance of these blocking materials was then further tested on test cells and test modules containing perovskite to assess how they affect solar cell performance, whether they fill or completely cover the exposed scribing lines, and their optical properties.

[0084] To gain a more qualitative understanding of the differences in the effectiveness of barrier materials, a new set of test stacks (see [link to test stack]) were tested. Figure 1B A new experiment was conducted using percentage optical transmittance data, which compared the five most successful blocking materials to date with an uncoated test stack. Figure 3-6 The experimental results obtained from these experiments are explained. These tests included, first, a control perovskite without a protective barrier layer, and then perovskites covered with various barrier layer materials (Al₂O₃, SiO₂). x PMMA, PS or / TERPEIE) perovskite layer device stacks. Each device stack tested has the following architecture: glass substrate - first substrate layer 110 / ITO - first contact layer 120 / PTAA - first charge transport layer 130 (HTL) / absorber layer 140 (perovskite) / one or more barrier layers 180. The effectiveness of the barrier layer was quantified using UV-Vis (UV-VIS) transmittance percentage data. Each dataset was acquired periodically between 0 hours and 10¹⁰ hours. Figure 3-6 UV-VIS clearly illustrates the effect derived from the aforementioned experiments. Figure 7 , 8 Visually observable in cases 9 and 10: After 96 hours of sunlight at 0.7 AM and 1.5 PM, the control perovskite (without a protective barrier layer) completely transformed into a nearly transparent film, while the film covered with Al2O3 and SiO2... x PMMA, PS and / TERPEIE's perovskite does not undergo a phase transition and retains its perovskite crystalline phase. To quantify this change, the absolute values ​​of the changes in optical density and transmittance percentage at 700 nm were calculated, thus comparing the original transmittance percentage scan with 10¹⁰ hours of exposure to ambient light at 0.7 AM and 1.5 lux. These values ​​are shown in Table 2 and indicate that the barrier layers reduce the degradation of the perovskite by several orders of magnitude, with alumina and silicon oxide barrier layers showing the greatest improvement. (An attenuation constant Σ(abs(Δ%T)) equal to zero indicates no attenuation.)

[0085] Table 2: From Figure 3-6 Results of the barrier layer of the unscratched test battery

[0086] Material Attenuation constant Improvement in control Σ(Abs(Δ%T)) Improvement in control <![CDATA[Al2O3]]> -0.0031 98.4 711.58 53.57 <![CDATA[SiO x ]]> -0.01 30.5 651.25 58.53 PMMA -0.0265 11.5 1867.16 20.41 PS -0.0351 8.7 1908.79 19.97 CP SB -0.0177 17.2 1570.3 24.27 Unblocking layer -0.03051 1.0 38115.87 1.0

[0087] The test modules were then tested. Each layer within a perovskite module is susceptible to degradation due to interaction with the barrier material or its solvent; therefore, the barrier layer described herein is important not only from the perspective of the perovskite layer itself but also for preserving other layers in perovskite-containing solar cells and / or modules. The perovskite test modules were fabricated on a 1-inch × 3-inch substrate (ITO sputtered onto glass). Selected barrier materials were then scraped onto the perovskite test modules, and degradation was examined. Crucially, the PCE of the test modules using a minimum floor PCE of 10% must remain within 1% (absolute) of the initial efficiency (e.g., after coating, a 12% module must be above 11%). The stack was then studied under solar simulation using optical microscopy, optical profilometry, scanning electron microscopy (SEM), stylus profilometry, and JV scanning. The third scribing line P3 and the fourth scribing line P4 were studied using stylus profilometry and SEM to confirm that they were filled with barrier material with a minimum thickness greater than 50 nm. The optical constants of the blocking film are determined by measuring the optical constants using elliptic photometry.

[0088] The aim of these studies was to determine satisfactory barrier layers and / or combinations of barrier layers for coated perovskite solar cells, which could maintain their original PCE within 1% of the performance of the original uncoated perovskite devices. To meet this requirement, two separate batches of ten 1×3” IZO translucent modules with seven sub-modules were fabricated. Each sub-module had two cells connected in series via a third scribe line P3 (e.g., ...). Figure 2B (As shown). Each of the 70 submodules tested was tested individually. The results of testing one batch (70 submodules) of 10 modules from two batches are shown below. Figure 11 As shown. These 10 modules were then aged for five days. On the fifth day, all barrier materials were applied to their respective modules. All ten modules (70 sub-modules) were measured for pre-deposition measurements before any barrier layer treatment was applied. After the initial testing was completed, barrier materials were applied. Two modules were coated with PS and two modules with PMMA. Two modules were coated with Al2O3 with a thickness of approximately 50 nm by atomic layer deposition (ALD). SiO2 with a thickness of 1000 nm was applied by thermal evaporation. x Thickness of SiO x Two modules were coated. As a control, the latter two modules remained uncoated without the barrier material to be measured. The two control modules were kept in the same container as the coated modules to experience the same ambient environment throughout the process. After all modules were coated with their respective barrier materials, their post-deposition properties were measured again.

[0089] Figure 11Photographs of the test modules before and after the deposition of the barrier material are shown. Each module includes vertical and horizontal scribings. The vertical scribings are the previously mentioned first scribing P1, second scribing P2, and third scribing P3, used to electrically connect two solar cells in series to create sub-modules. The horizontal scribings are referred to herein as the fourth scribing P4 and divide each module substrate into seven sub-modules. It is important to note that no visible degradation of any scribings was observed after the application of the appropriate barrier material. Furthermore, Figure 11 Only the first batch of modules tested is shown. A full second batch was also prepared to demonstrate reproducibility for a total of 20 test modules, with four modules processed each time.

[0090] Next, the PCE of each submodule was evaluated to determine any numerical degradation when comparing the PCE after barrier layer deposition with the module's performance before deposition. Table 3 below shows a pruned version of the JV scan data before and after barrier layer deposition on the module. Table 3 shows the average values ​​before and after deposition of each barrier material. For the first batch, PS and SiO x There was no impact on PCE, but the PMMA layer reduced PCE by 0.43%, and the Al2O3 layer reduced PCE by 0.97%. In the second batch, the only change made was reducing the Al2O3 deposition temperature from 60°C to 50°C, which also reduced the PCE performance loss from 0.97% to 0.74%. The second batch showed that PMMA, PS, and SiO2 had no impact on PCE. x None of these changes led to performance variations, and each variation remained within the measurement error range. Table 3 summarizes the performance of the barrier materials PS, PMMA, and SiO2. x Both Al2O3 and Al2O3 affect module performance by less than 1% of PCE. Furthermore, the average performance of each module is significantly higher than the minimum requirement of 10% PCE.

[0091]

[0092] The next objective is to demonstrate the contact between the tested barrier material and the scribing wall, either by completely filling the third scribing line P3 and the fourth scribing line P4 or by providing a material layer at least 50 nm thick coated within the walls of the scribing lines. Optical microscopy and optical profilometry are insufficient methods to demonstrate scribing filling because both methods involve imaging the material. Stylus profilometry is also insufficient to demonstrate scribing filling because, since all barrier layers are fully coated, the coating follows a similar geometry to the scribing lines. The best method to confirm filling and complete scribing wall passivation is cross-sectional SEM.

[0093] Figure 12A , 12BFigures 12C and 12C show SEM images of four exemplary barrier materials within the second scribing line P2 and the third scribing line P3 of the four test modules. These four images show each barrier material completely covering the sidewalls of the scribing lines, thus eliminating perovskite exposure. Subplot A of Figure 12 illustrates that Al2O3 does not fill the scribing lines but maintains precise thickness and film uniformity around the edges and surface of the scribing lines. Subplots B, C, and D of Figure 12 show PMMA, PS, and SiO2, respectively. x Each of the three barrier materials completely fills the scribing lines and surrounds the surface of the scribing line sidewalls with barrier material. Furthermore, each barrier layer film in the SEM images maintains uniformity around the scribing angle, thus providing neither an inlet nor an outlet. The behavior and quality of the films shown below represent their behavior and quality across the entire 1 inch × 3 inch module substrate. Figure 12B This shows the submodule stack-up with specified layers (such as...). Figure 2B (As shown) is a magnified version of the SEM image. HTL and CTL are too thin to be recognized. Figure 12C The SEM image in the image shows the entire width of the third scribing line P3 and provides evidence that the scribing lines were completely enclosed in their respective blocking materials.

[0094] This paper demonstrates that the barrier film's impact on PCE performance is less than 1%, and that the barrier film completely surrounds the exposed perovskite within the module's scribing lines. The optical properties of the barrier film are then evaluated. Ellipsometry measurements were performed to determine the refractive index n and extinction coefficient k of the barrier film. The film was scraped onto a blank 1”×3” microscope slide, using another blank microscope slide as the substrate baseline for n and k calculations. Figure 13 Four exemplary blocking materials are shown on a blank microscope slide. From left to right, the blocking layers are Al2O3, SiO2, and SiO2. x PMMA and PS. Except for SiO x All the barrier layers are transparent. Table 4 summarizes the Cauchy model using Al2O3 and SiO2. x The values ​​of n and k were calculated by elliptic photometry using the Cody Lorentz model, the Cauchy model of PMMA, and the GenOsc model of PS. The values ​​shown in Table 4 represent values ​​at wavelengths of 371 nm and 1596 nm. Stability and gradual variations between these values ​​occur within the wavelength range of 372 nm to 1595 nm, and are within the range of the listed values. Elliptic photometry calculations of n and k indicate that SiO2... x It has the highest refractive index and extinction coefficient.

[0095] Table 4: Calculated values ​​of refractive index n and extinction coefficient k.

[0096]

[0097] Photovoltaic processing sequence examples

[0098] Figure 14A A schematic plan view of a photovoltaic module 1400 including a photovoltaic device array 1401 is shown. The photovoltaic device array 1401 includes a plurality of photovoltaic devices 1402 connected in series. The photovoltaic device array 1401 includes a plurality of features, such as a plurality of first scribe lines P1, a plurality of second scribe lines P2, and a plurality of third scribe lines P3 (which are used to form the photovoltaic devices 1402 connected in series), and a plurality of fourth scribe lines P4 (which are used to separate and isolate the photovoltaic devices 1402 connected in series from the edge regions of the photovoltaic module 1400). Figure 14A As shown, the fourth scribe line P4 surrounds the photovoltaic device array 1401.

[0099] Figure 14B A schematic side cross-sectional view of a portion of a photovoltaic device array 1401 is shown, which includes components made of... Figure 14A The dividing lines 14B-14B shown represent the segmented portion of the photovoltaic device array 1401. Figure 14B The segmented portion of the photovoltaic device array 1401 shown illustrates the construction of several features, such as the first scribe line P1, the second scribe line P2, the third scribe line P3, and the fourth scribe line P4, as further described below. Figure 14B The photovoltaic device array 1401 shown includes a first substrate layer 110, a first contact layer 120, a first charge transport layer 130, an absorbent layer 140, a second charge transport layer 150, a second contact layer 170, multiple features, one or more barrier layers 180, an encapsulation layer 190, and a second substrate layer 115.

[0100] Figure 14C A schematic side cross-sectional view of a portion of an alternatingly configured photovoltaic device array 1401 is shown, which includes... Figure 14A The dividing line 14C-14C shown represents the segmented portion of the photovoltaic device array 1401. Figure 14C The cross-sectional view of the photovoltaic device array 1401 shown illustrates a construction including alternative photovoltaic device stacks, which similarly includes... Figure 14B Several features are shown and described. Figure 14C The photovoltaic device array 1401 shown also includes a buffer layer 160, which can be disposed between the absorbent layer 140 and the second charge transport layer 150, or between the second charge transport layer 150 and the second contact layer 170.

[0101] To avoid limiting the scope of the disclosed content provided herein, and for ease of discussion, the following discussion will primarily focus on content configured to include... Figure 14CThe photovoltaic device array 1401 of the photovoltaic device stack described herein. However, other photovoltaic device stack configurations, such as Figure 14B The photovoltaic device stack shown can also benefit from the various embodiments of the present disclosure provided herein.

[0102] Photovoltaic device stacked structure

[0103] In some embodiments, the photovoltaic device stack includes a first substrate layer 110, a first contact layer 120, a first charge transport layer 130, an absorber layer 140, a second charge transport layer 150, a buffer layer 160, a second contact layer 170, multiple features, one or more barrier layers 180, an encapsulation layer 190, and a second substrate layer 115. In one configuration, such as Figure 14C As shown, the buffer layer 160 is disposed between the absorber layer 140 and the second charge transport layer 150, but other photovoltaic device stack-up structures can benefit from the disclosure provided herein.

[0104] Figure 15 A method 1500 for manufacturing a photovoltaic device stack within a photovoltaic module 1400 according to one or more embodiments of the present disclosure is shown. Figure 16A-16L A schematic cross-sectional view of the photovoltaic device stack during various stages of the manufacture of photovoltaic module 1400 is shown, which relates to... Figure 15 The operation found in method 1500 is shown.

[0105] refer to Figure 16A The photovoltaic device stack includes a first substrate layer 110. The first substrate layer 110 has a first substrate thickness between about 50 μm and about 10 mm. In some embodiments, as described above, the first substrate layer 110 may comprise one or more materials selected from the group consisting of metal foil, silicon, glass, and / or polymer substrates. In some embodiments, the first substrate layer 110 may comprise glass with a thickness between about 1 mm and 5 mm, more preferably between 2 mm and 3.2 mm. In some embodiments, the first substrate layer 110 may comprise metal foil and / or polymer with a thickness between about 50 μm and 500 μm, more preferably between 40 μm and 150 μm. The first substrate layer 110 may include a roughened surface on which the various layers of the photovoltaic device stack are formed, wherein the roughened surface has a peak-valley roughness between about 1 nm and about 10 μm. For example, the peak-valley roughness is about 1 micrometer (μm).

[0106] like Figure 16BAs shown, in operation 1505 of method 1500, a first contact layer 120 is formed on a first surface of the first substrate layer 110. The first contact layer 120 includes an electrical contact layer material. The electrical contact layer material may include any suitable material, including but not limited to copper, silver, gold, indium tin oxide (ITO), fluorine-doped tin oxide (FTO), or any combination thereof. In some embodiments, the first contact layer 120 may include one or more layers, wherein each of the multiple layers includes a contact layer material, such as a transparent conductive oxide layer. The first contact layer 120 may have a first contact thickness between about 5 nanometers (nm) and about 1000 nm. The first contact layer 120 may be formed by any suitable process, including but not limited to physical vapor deposition (PVD) processes (e.g., sputtering or evaporation processes), chemical vapor deposition (CVD) processes, plasma-enhanced chemical vapor deposition (PECVD) processes, atomic layer deposition (ALD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, or other suitable deposition techniques.

[0107] In operation 1510, such as Figure 16B As shown, the first contact layer 120 is patterned by performing a first scribing process, in which first scribing lines P1 are formed in the first contact layer 120. The first scribing lines P1 are formed such that each P1 scribing line extends through the first contact layer 120 and at least extends to the surface of the first substrate layer 110 to form an electrically isolated region 120A including a portion of the first contact layer 120. Figure 16B As shown, the first scribing line P1 divides the first contact layer 120 into two separate electrically isolated regions 120A. The first scribing line P1 can be formed by any suitable process, including but not limited to mechanical scribing systems, laser ablation, or combinations thereof.

[0108] like Figure 16C As shown, in operation 1515, a first charge transport layer (CTL) 130 is formed over a patterned first contact layer 120. The first CTL 130 is disposed over the patterned portion of the first contact layer 120, the exposed sidewall surface of the first scribe line P1, and the exposed portion of the first substrate layer 110. The first CTL 130 has a thickness between about 0.1 nm and about 10 μm, preferably between about 1 and 100 nm, and more preferably between 10 and 70 nm. The first CTL 130 can be formed by any suitable process, including but not limited to chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD) (e.g., evaporation process), or other suitable deposition techniques.

[0109] In some embodiments, the first CTL 130 may be configured to act as a hole transport layer (HTL) comprising a hole transport material, or as an electron transport layer (ETL) comprising an electron transport material. In some embodiments, the first CTL 130 may comprise multiple layers, each of which may comprise a different material depending on the configuration of the first CTL 130 (e.g., HTL versus ETL). The first CTL 130 is an HTL, which includes, but is not limited to, PTAA, Poly-TPD, nickel oxide, molybdenum oxide, OMATD, self-assembled monolayer (SAM), or combinations thereof. As described above, in some embodiments, the first CTL 130 configured to act as an HTL may comprise multiple layers, each of which may comprise a different hole transport material.

[0110] In operation 1520, such as Figure 16D As shown, an absorbent layer 140 is formed on the first CTL 130. In some embodiments, the absorbent layer 140 is disposed on the first CTL 130. The absorbent layer 140 includes an absorbent material, which may include a perovskite material as described above. In one example, the absorbent layer includes a stoichiometric ABX3 perovskite material, wherein A is a first cation, B is a second cation, and X includes at least one halide (e.g., a chloride, bromide, or iodide). In another example, the absorber layer 140 comprises a stoichiometric perovskite of ABX3, wherein A comprises at least one of formamidine (FA), methylammonium (MA), or cesium, and B comprises at least one of tin or lead, and X comprises at least one of a halide, lead triiodide methylammonium (MAPbI3), cesium formamidine methylammonium triiodide (CsFAMAPbI3), silicon (amorphous and / or crystalline), group II and IV materials (amorphous and / or crystalline), organic photovoltaic (OPV), dye-sensitized solar cells (DSSX), copper indium gallium selenide (CIGS), cadmium telluride (CdTe), or combinations thereof. The absorber layer 140 may be formed by any suitable solution-based deposition process, including but not limited to printing, stencil coating, spraying, gravure printing, or any combination thereof.

[0111] The deposited absorbent layer 140 has an absorbent layer thickness between about 300 nm and about 1000 nm. For example, the absorbent thickness is between about 450 nm and about 950 nm, preferably between about 500 nm and about 650 nm. In some embodiments, the absorbent layer 140 may have an absorbent thickness between about 1000 nm and about 2000 nm.

[0112] In operation 1525, in some embodiments, a buffer layer 160 is formed on top of the absorbent layer 140. For example... Figure 16EAs shown, in some cases, the buffer layer 160 is directly disposed on or formed on the absorber layer 140. The buffer layer 160 has a first buffer layer thickness between about 0.1 nm and about 20 nm. The buffer layer 160 may include a material with a band gap typically larger than that of the absorber layer 140, which can passivate the perovskite surface and / or slow down the surface recombination rate, create a tunneling barrier, and / or otherwise alter the interfacial properties between the absorber layer 140 and the second charge transport layer 150. Due to the material properties and location of the buffer layer 160 within the photovoltaic device, typically between the absorber layer 140 and the second contact layer 170, the buffer layer 160 is able to perform enhancement functions for these different devices and thus improve the performance of the photovoltaic device. The buffer layer 160 may include, but is not limited to, oxides, oxygen-containing salts, sulfates, organics, organic salts, and fluorides. The buffer layer 160 can be formed by any suitable process, including but not limited to solution-based deposition processes, chemical vapor deposition (CVD) processes, plasma-enhanced chemical vapor deposition (PECVD) processes, atomic layer deposition (ALD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, physical vapor deposition (PVD) processes (e.g., evaporation processes), or other suitable deposition techniques. In one example, the deposited buffer layer 160 has a total thickness between about 0.4 nm and about 40 nm.

[0113] In operation 1530, such as Figure 16F As shown, a second charge transport layer (CTL) 150 is deposited over a buffer layer 160 and an absorbent layer 140. However, as described above, in some embodiments, the second charge transport layer (CTL) 150 is formed over the absorbent layer 140 before the buffer layer 160 is formed over the absorbent layer 140, thus the second charge transport layer (CTL) 150 is disposed between the buffer layer 160 and the absorbent layer 140. The second CTL 150 can be configured to serve as a hole transport layer (HTL) including a hole transport material, or as an electron transport layer (ETL) including an electron transport material. In some embodiments, the second CTL 150 can include multiple layers, wherein each of the multiple layers can include a different material depending on the configuration of the second CTL 150 (e.g., HTL versus ETL). In one example, the second CTL 150 is an ETL, which includes, but is not limited to, metal oxides such as at least one of TiO2, SnO2, Al2O3, ZnO, or carbon contactors such as carbon nanotubes, fullerenes (e.g., C4O4), etc. 60 and / or C 70 ), fullerene derivatives [6,6]-phenyl-C 61methyl butyrate (PCBM), or fullerenes used alone or in combination with copper bath (BCP) or SnO2 or other metal oxides, or combinations thereof. As described above, in some embodiments, the second CTL 150 configured to be used as an ETL may comprise multiple layers, each of which may comprise a different electron transport material. The second CTL 150 has a second CTL thickness between about 0.1 nm and about 1 μm. The second CTL 150 may be formed by any suitable process, including but not limited to vacuum evaporation, atomic layer deposition, sputtering, chemical vapor deposition, or combinations thereof.

[0114] In operation 1535, such as Figure 16G As shown, a plurality of second scribing lines P2 are formed through the first CTL 130, absorbent layer 140, buffer layer 160, and second CTL 150, and expose a portion of the first contact layer 120. In some embodiments, each formed second scribing line P2 may extend into a portion of the first contact layer 120. Each second scribing line P2 includes a surface containing a portion of the second CTL 150, buffer layer 160, absorbent layer 140, first CTL 130, and first contact layer 120. The second scribing lines P2 can be formed by any suitable process, including but not limited to mechanical scribing systems, laser ablation, or combinations thereof.

[0115] In operation 1540, such as Figure 16H As shown, a second contact layer 170 is formed over a second CTL 150, a buffer layer 160, an absorbent layer 140, a first CTL 130, a first contact layer 120, and a first substrate layer 110. The second contact layer 170 is disposed over the second CTL 150 and fills at least most or all of the second scribing line P2. The second contact layer 170 can be formed from any suitable contact layer material as described above. In one example, the second contact layer 170 includes an IZO or ITO layer. The second contact layer 170 has a first thickness between about 5 nm and about 1000 nm. The second contact layer 170 can be formed by any suitable process, including but not limited to chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD), printing, spraying, or other suitable deposition techniques.

[0116] In operation 1545, such as Figure 16IAs shown, a plurality of third scribing lines P3 and a plurality of fourth scribing lines P4 are formed to penetrate a portion of the photovoltaic device stack. Each of the third scribing lines P3 extends through the second contact layer 170, the second CTL 150, and at least a majority of the absorber layer 140. In some embodiments, the third scribing line P3 extends through the second contact layer 170, the second CTL 150, the absorber layer 140, and the first CTL 130, and exposes a portion of the first contact layer 120. In some embodiments, the third scribing line P3 may extend into a portion of the first contact layer 120. Each of the third scribing lines P3 includes a surface that contains a portion of the second contact layer 170, the second CTL 150, the buffer layer 160, the absorber layer 140, the first CTL 130, and the first contact layer 120. The third scribing lines P3 can be formed by any suitable process, including but not limited to mechanical scribing systems, laser ablation, or combinations thereof. In some examples of this disclosure, the third scribe line P3 and the fourth scribe line P4 may each have a width between 5 μm and 200 μm.

[0117] During operation 1545, a plurality of fourth scribing lines P4 are formed to penetrate the device stack. The fourth scribing lines P4 extend through the second contact layer 170, the second CTL 150, the absorbent layer 140, the first CTL 130, and the first contact layer 120, and generally extend to the top surface of the first substrate layer 110. In some embodiments, the fourth scribing lines P4 may extend into the first substrate layer 110. The fourth scribing lines P4 are separate from the third scribing line P3 and serve to isolate the photovoltaic device array 1401 from unusable edge portions of the photovoltaic module 1400 formed at the edge of the first substrate layer 110 of the photovoltaic module 1400. In some embodiments, the fourth scribing lines P4 may be wide enough to extend to the edge of the photovoltaic module 1400. Each of the fourth scribing lines P4 includes a surface containing portions of the second contact layer 170, the second CTL 150, the buffer layer 160, the absorbent layer 140, the first CTL 130, the first contact layer 120, and the first substrate layer 110. The fourth scribing line P4 can be formed by any suitable process, including but not limited to mechanical scribing systems, laser ablation, or combinations thereof.

[0118] When operating 1550, such as Figure 16JAs shown, one or more barrier layers 180 are formed on top of the previously formed device stack. The one or more barrier layers 180 are deposited on the exposed surfaces of the second contact layer 170 and the third scribing P3 and the fourth scribing P4, and partially fill the openings formed by the third scribing P3 and the fourth scribing P4. As previously described, the formed one or more barrier layers 180 are typically configured to encapsulate the device stack to prevent one or more layers within the device stack from being exposed to one or more environmental elements (such as water) that would damage one or more layers within the device stack and reduce the lifetime of the photovoltaic device.

[0119] One or more barrier layers 180 include a barrier material. Each of the one or more barrier layers 180 may include a different barrier material. The barrier material of the one or more barrier layers 180 may include a metal oxide. In one example, the one or more barrier layers 180 include, but are not limited to, materials comprising alumina, silicon oxide, tin oxide, titanium oxide, zirconium oxide, or combinations thereof. The barrier material of the one or more barrier layers 180 may include styrene-based polymers, polysiloxanes, amine-containing polymers, polyacrylates, aryl ammonium halides, alkyl ammonium halides, fluorinated hydrocarbon polymers, or combinations thereof. In another example, the one or more barrier layers 180 include, but are not limited to, styrene-based polymers, such as polystyrene (PS), acrylonitrile-butadiene-styrene (ABS), acrylonitrile-styrene-acrylate (ASA), or styrene-butadiene rubber (SBR). In yet another example, the one or more barrier layers 180 include, but are not limited to, polysiloxanes, such as poly(dimethylsiloxane), poly(diethylsiloxane), or poly(methylphenylsiloxane). In another example, one or more barrier layers 180 include, but are not limited to, amine-containing polymers such as polyethyleneimine (PEIE), poly(ethyleneamine) hydrochloride (PVH), or poly(ethylene glycol) bis(amine) (PEG-amine). In another example, one or more barrier layers 180 include, but are not limited to, polyacrylates such as polymethyl methacrylate (PMMA) or polyethyl acrylate. In another example, one or more barrier layers 180 include, but are not limited to, aryl ammonium halides such as phenylethyl ammonium iodide (PEAI), 1-(acetylammonium)pyrene (PEY), or dodecyl ammonium chloride (DACl). In another example, one or more barrier layers 180 include, but are not limited to, alkyl ammonium halides such as n-propylammonium iodide (PAI), ethane-1,2-diammonium (EDA), 2-chloroethylamine (CEA), or 2-bromoethylamine (BEA). In another example, one or more barrier layers 180 include, but are not limited to, fluorinated hydrocarbon polymers such as Nafion. TMThe barrier layers 180 are made of polytetrafluoroethylene, polyvinylidene fluoride, or trifluoroethylene. One or more barrier layers 180 have a barrier thickness between about 1 nm and about 5 μm, preferably between about 10 nm and 1500 nm, more preferably between about 20 nm and 1000 nm, and even more preferably between about 25 nm and 75 nm. For example, the thickness is greater than about 50 nm. For example, the thickness is about 1000 nm. One or more barrier layers 180 can be conformally deposited by any suitable process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD) (e.g., thermal evaporation), or solution treatment methods, such as inkjet printing, stencil coating, spraying, gravure printing, or full-coverage coating. In some embodiments, the solution treatment method includes an annealing process. In some embodiments, one or more barrier layers 180 are optically transparent to one or more wavelengths of light. In some embodiments, the formed one or more blocking layers 180 are at least semi-transparent for light wavelengths greater than about 730 nm. In one example, the formed one or more blocking layers 180 have a transmittance of >80% at a wavelength of 700 nm. In some embodiments, the one or more blocking layers 180 comprise an aluminum oxide layer.

[0120] When operating 1555, such as Figure 16K As shown, an encapsulation layer 190 is disposed and / or formed on top of the device stack. For example... Figure 16K As shown, the encapsulation layer 190 is disposed above one or more barrier layers 180 and fills any remaining opening areas of the third scribe line P3 and the fourth scribe line P4. The encapsulation layer 190 includes an encapsulation material. The encapsulation material may include, but is not limited to, ethylene vinyl acetate (EVA), polyolefins, polyurethanes, polyvinyl butyral, ionomers, or combinations thereof. The encapsulation layer 190 has an encapsulation thickness between about 0.1 mm and about 5 mm. The encapsulation layer 190 may be formed by any suitable process, including but not limited to lamination, casting, autoclave processes, or other common deposition and / or attachment techniques.

[0121] When operating 1560, such as Figure 16L As shown, a second substrate layer 115 is disposed on and / or coupled to the encapsulation material. The second substrate layer 115 has a second substrate thickness between about 0.05 mm and about 5 mm. In some embodiments, as described above, the second substrate layer 115 may comprise one or more materials selected from the group consisting of metal foil, silicon, glass, and / or polymer substrates. In some embodiments, as described above, the second substrate layer 115 is glass with a thickness between about 1 mm and 3 mm.

[0122] Device Examples

[0123] Example 1. A photovoltaic device comprising: a first contact layer having a first thickness; a first charge transport layer (CTL) having a second thickness positioned above the surface of the first contact layer; an absorber layer having a third thickness positioned above the surface of the first CTL; a second CTL having a fourth thickness positioned above the surface of the absorber layer; a second contact layer having a fifth thickness positioned above the surface of the second CTL; and a barrier layer, wherein: the barrier layer is positioned adjacent to and in contact with at least a portion of at least one surface of the first contact layer, the first CTL, the absorber layer, the second CTL, or the second contact layer, and the barrier layer comprises a water-insoluble material. As cited herein, water-insoluble materials are generally considered to include materials having a water vapor transmission rate (WVTR) of less than about 6 g / (m²) for materials such as PEIE / CYTOP. 2 For example, for materials like alumina, the water vapor transmission rate is less than about 4 × 10⁻⁶ days. -2 g / (m 2 (days), as measured using a standard WVTR test (e.g., the ASTM WVTR standard test).

[0124] Example 2. The photovoltaic device of Example 1 further includes: a first scribing line defined by at least one surface, wherein the at least one surface of the first scribing line includes at least a portion of at least one of the first thickness, the second thickness, the third thickness, the fourth thickness, or the fifth thickness, and the material of the barrier layer is disposed on at least a portion of the at least one surface of the first scribing line.

[0125] Example 3. A photovoltaic device of Example 1 or Example 2, wherein at least one surface formed by a first scribe line is positioned substantially perpendicular to at least one surface of a first contact layer, a first CTL, an absorbent layer, a second CTL, or a second contact layer.

[0126] Example 4. A photovoltaic device of any one of Examples 1-3, wherein the first scribe line has a width between 5 μm and 200 μm.

[0127] Example 5. A photovoltaic device according to any one of Examples 1-4, further comprising: a second scribe line defined by at least one surface, wherein at least one surface of the second scribe line includes at least a portion of at least one of the first thickness, the second thickness, the third thickness, the fourth thickness, or the fifth thickness, and the material of the barrier layer is disposed on at least a portion of at least one surface of the second scribe line.

[0128] Example 6. A photovoltaic device of any one of Examples 1-5, wherein at least one surface formed by the second scribing line is positioned substantially perpendicular to the surface of at least one of the first contact layer, the first CTL, the absorbent layer, the second CTL, or the second contact layer.

[0129] Example 7. A photovoltaic device of any one of Examples 1-6, wherein the second scribe line has a width between 5 μm and 200 μm.

[0130] Example 8. The photovoltaic device of any one of Examples 1-7, wherein the material of the barrier layer includes at least one of metal oxide, polymer, resin, aryl ammonium halide, alkyl ammonium halide or lead sulfate.

[0131] Example 9. The photovoltaic device of any one of Examples 1-8, wherein the metal oxide comprises at least one of aluminum oxide, silicon oxide, tin oxide, zirconium oxide or titanium oxide.

[0132] Example 10. The photovoltaic device of any one of Examples 1-9, wherein the aryl ammonium halide includes at least one of phenylethyl ammonium iodide (PEAI), 1-(acetylammonium)pyrene (PEY) or dodecyl ammonium chloride (DACl).

[0133] Example 11. The photovoltaic device of any one of Examples 1-10, wherein the alkyl ammonium halide comprises at least one of n-propylammonium iodide (PAI), ethane-1,2-diammonium (EDA), 2-chloroethylamine (CEA) or 2-bromoethylamine (BEA).

[0134] Example 12. A photovoltaic device of any one of Examples 1-11, wherein the polymer comprises at least one of styrene polymers, polysiloxanes, amine polymers, polyacrylates, or fluorinated hydrocarbon polymers.

[0135] Example 13. The photovoltaic device of any one of Examples 1-12, wherein the amine-containing polymer comprises at least one of polyethyleneimine (PEIE), poly(ethylene amine) hydrochloride (PVH), or poly(ethylene glycol) bis(amine) (PEG-amine).

[0136] Example 14. The photovoltaic device of any one of Examples 1-13, wherein the polysiloxane comprises at least one of poly(dimethylsiloxane), poly(diethylsiloxane), or poly(methylphenylsiloxane).

[0137] Example 15. The photovoltaic device of any one of Examples 1-14, wherein the polyacrylate includes at least one of polymethyl methacrylate (PMMA), polymethyl methacrylate (PMA), or ethyl polyacrylate.

[0138] Example 16. A photovoltaic device of any one of Examples 1-15, wherein the styrene polymer includes at least one of polystyrene (PS), acrylonitrile-butadiene-styrene (ABS), acrylonitrile-styrene-acrylate (ASA), or styrene-butadiene rubber (SBR).

[0139] Example 17. The photovoltaic device of any one of Examples 1-16, wherein the fluorinated hydrocarbon polymer comprises Nafion TM At least one of polytetrafluoroethylene, polyvinylidene fluoride, or trifluoroethylene.

[0140] Example 18. The photovoltaic device of any one of Examples 1-17, wherein the fluorinated hydrocarbon polymer has a structure as defined in (I).

[0141]

[0142] And 100 < n < 1,250.

[0143] Example 19. A photovoltaic device of any one of Examples 1-18, wherein the material of the barrier layer at least partially fills at least one of the first scribing line or the second scribing line.

[0144] Implementation Scheme 20. The photovoltaic device of any one of Examples 1-19, wherein the barrier layer has a thickness between 20 nm and 1500 nm.

[0145] Implementation Scheme 21. The photovoltaic device of any one of Examples 1-20, wherein, as measured by the thickness of the barrier layer, the material of the barrier layer has a transmittance of greater than 80% at wavelengths greater than 700 nm.

[0146] Implementation Scheme 22. The photovoltaic device of any one of Examples 1-21, wherein the thickness of the barrier layer is between 1 nm and 2 μm.

[0147] Implementation Scheme 23. The photovoltaic device of any one of Examples 1-22, wherein the thickness of the barrier layer is between 1 nm and 2 μm.

[0148] Implementation Scheme 24. The photovoltaic device of any one of Examples 1-23, wherein the thickness of the barrier layer is between 50 nm and 100 nm.

[0149] Implementation Scheme 25. The photovoltaic device of any one of Examples 1-24, wherein: the barrier layer includes at least a first layer and a second layer, the first layer includes a first material, and the second layer includes a second material different from the first material.

[0150] Implementation Scheme 26. The photovoltaic device of any one of Examples 1-25, wherein the first material comprises a first metal oxide and the second material comprises a second metal oxide.

[0151] Example 27. The photovoltaic device of any one of Examples 1-26, wherein the first metal oxide comprises silicon oxide and the second metal oxide comprises aluminum oxide.

[0152] Example 28. The photovoltaic device of any one of Examples 1-27, wherein the first material comprises a first polymer and the second material comprises a second polymer.

[0153] Example 29. The photovoltaic device of any one of Examples 1-28, wherein the first polymer comprises at least one of PMMA, PS, PEIE or fluorinated hydrocarbon polymers.

[0154] Example 30. The photovoltaic device of any one of Examples 1-29, wherein the second polymer comprises at least one of PMMA, PS, PEI or a fluorinated hydrocarbon polymer.

[0155] Example 31. The photovoltaic device of any one of Examples 1-30, wherein the first polymer comprises PEIE and the second polymer comprises a fluorinated hydrocarbon polymer.

[0156] Example 32. The photovoltaic device of any one of Examples 1-31, wherein the first contact layer comprises at least one of aluminum, copper, silver, gold, indium tin oxide (ITO), fluorine-doped tin oxide (FTO), or indium zinc oxide (IZO).

[0157] Example 33. The photovoltaic device of any one of Examples 1-32, wherein the second contact layer comprises at least one of aluminum, copper, silver, gold, indium tin oxide (ITO), fluorine-doped tin oxide (FTO), or indium zinc oxide (IZO).

[0158] Example 34. The photovoltaic device described in any one of Examples 1-33 further includes a buffer layer positioned between the absorbent layer and the second contact layer.

[0159] Example 35. In the photovoltaic device of any one of Examples 1-34, the buffer layer comprises an oxygen-containing salt. The term "oxygen-containing salt" generally refers to a compound or substance having at least one cation and at least one anion associated with each other via ionic bonds, wherein at least one anion contains an oxygen atom (O) in its chemical formula. In one embodiment, the oxygen-containing salt may be characterized as an oxyacid. The oxygen-containing salt may comprise an organic cation and / or an H+ cation.

[0160] Example 36. The photovoltaic device of any one of Examples 1-35, wherein the second charge transport layer comprises a fullerene.

[0161] Example 37. A photovoltaic device according to any one of Examples 1-36, wherein the absorber layer includes at least one of perovskite, silicon, III-V alloy, organic photovoltaic material, dye sensitized material, copper indium gallium selenide alloy or cadmium telluride alloy.

[0162] Example 38. A photovoltaic device according to any one of Examples 1-37, wherein the absorber layer comprises a perovskite, said perovskite comprising at least one three-dimensional (3D) structure, two-dimensional (2D) structure, one-dimensional (1D) structure or zero-dimensional (0D) structure.

[0163] Example 39. The photovoltaic device of any one of Examples 1-38, wherein: the 3D structure comprises ABX3, A comprises a first cation, B comprises a second cation, and X comprises an anion.

[0164] Example 40. The photovoltaic device of any one of Examples 1-39, wherein the first cation includes at least one of formamidine (FA), methylammonium (MA) or cesium.

[0165] Example 41. The photovoltaic device of any one of Examples 1-40, wherein the second cation comprises at least one of tin or lead.

[0166] Example 42. The photovoltaic device of any one of Examples 1-41, wherein the anion comprises a halide.

[0167] Example 43. The photovoltaic device of any one of Examples 1-42, wherein the first scribing line passes through the third thickness and at least a portion of the second thickness.

[0168] Example 44. The photovoltaic device of any one of Examples 1-43, wherein the third thickness is between 200 nm and 1500 nm.

[0169] Example 45. The photovoltaic device of any one of Examples 1-44, wherein the second thickness is between 1 nm and 1000 nm.

[0170] Example 46. The photovoltaic device of any one of Examples 1-45, wherein the first scribing line passes through the fourth thickness and the fifth thickness.

[0171] Example 47. The photovoltaic device of any one of Examples 1-46, wherein the fourth thickness is between 1 nm and 1000 nm.

[0172] Example 48. The photovoltaic device of any one of Examples 1-47, wherein the fifth thickness is between 1 nm and 1000 nm.

[0173] Example 49. The photovoltaic device of any one of Examples 1-48 further includes an encapsulation layer, wherein the barrier layer is positioned between the encapsulation layer and the second contact layer.

[0174] Example 50. The photovoltaic device of any one of Examples 1-49, wherein the encapsulation layer comprises at least one of alumina, silicon oxide, PMMA, PS, fluorinated hydrocarbon polymer or PEIE.

[0175] Example 51. A photovoltaic device according to any one of Examples 1-50, wherein the barrier layer has a sufficiently thin thickness to allow charge tunneling when the barrier layer is positioned between the absorber layer and the second contact layer.

[0176] Example 52. The photovoltaic device of any one of Examples 1-51, wherein the barrier layer is positioned between the absorber layer and the second contact layer.

[0177] Example 53. The photovoltaic device of any one of Examples 1-52, wherein the barrier layer is positioned between the absorber layer and the second CTL.

[0178] Example 54. The photovoltaic device of any one of Examples 1-53, wherein the second contact layer is positioned between the barrier layer and the absorber layer.

[0179] Example 55. The photovoltaic device of any one of Examples 1-54, wherein the second CTL is positioned between the barrier layer and the absorber layer.

[0180] Example 56. A photovoltaic device comprising: a first contact layer having a first thickness; a first charge transport layer (CTL) having a second thickness positioned above the surface of the first contact layer; an absorber layer having a third thickness positioned above the surface of the first CTL; a second CTL having a fourth thickness positioned above the surface of the absorber layer; a second contact layer having a fifth thickness positioned above the surface of the second CTL; a barrier layer comprising a metal oxide; an encapsulation layer; and a first scribing defined by at least one surface, wherein: the absorber layer comprises ABX3, where A is a first cation, B is a second cation, and X comprises at least one halide; at least a portion of the barrier layer is positioned between the encapsulation layer and the second CTL; the scribing passes through the third thickness, the fourth thickness, the fifth thickness, and at least a portion of the second thickness; and the metal oxide is disposed above at least a portion of the at least one surface formed by the first scribing.

[0181] Method Implementation Examples

[0182] Example 57. A method of manufacturing a photovoltaic device stack, comprising: forming a barrier layer on the photovoltaic device stack, wherein the device stack comprises: a first contact layer having a first thickness; a first charge transport layer (CTL) having a second thickness positioned above a surface of the first contact layer; an absorber layer having a third thickness positioned above a surface of the first CTL; a second CTL having a fourth thickness positioned above a surface of the absorber layer; a second contact layer having a fifth thickness positioned above a surface of the second CTL; and a scribing line defined by at least one surface, wherein: at least one surface of the scribing line includes at least a portion of the third thickness, the fourth thickness, the fifth thickness and at least a portion of the second thickness, the barrier layer comprises at least one of a metal oxide, a polymer, a resin, an aryl ammonium halide, an alkyl ammonium halide or lead sulfate, and the barrier layer is formed on at least a portion of the at least one surface of the first scribing line.

[0183] Example 58. The method of Example 57, wherein: the device stack further includes a second scribing line defined by at least one surface, the at least one surface of the second scribing line including at least a portion of a first thickness, a second thickness, a third thickness, a fourth thickness or a fifth thickness, and the barrier layer is disposed on at least a portion of at least one surface of the second scribing line.

[0184] Example 59. The method according to Example 57 or Example 58 further includes forming an encapsulation layer on the second contact layer, wherein at least a portion of the barrier layer is positioned between the encapsulation layer and the second contact layer.

[0185] Example 60. The method according to any one of Examples 57 to 59, wherein the barrier layer comprises the metal oxide, and the metal oxide comprises aluminum oxide, silicon oxide, tin oxide, zirconium oxide, titanium oxide, or a combination thereof.

[0186] Example 61. The method according to any one of Examples 57 to 60, wherein the barrier layer has a thickness between 20 nm and 1500 nm.

[0187] Example 62. The method according to any one of Examples 57-61, wherein the blocking layer has a transmittance of greater than 80% at a wavelength greater than 700 nm, as measured through the thickness of the blocking layer.

[0188] Example 63. The method of any one of Examples 57-62, wherein: the formation includes at least one of a solution processing step or a gas phase processing step, and the processing step deposits at least one of a barrier layer material or a barrier layer material precursor onto the photovoltaic device stack.

[0189] Example 64. The method according to any one of Examples 57-63, wherein the vapor phase processing step includes at least one of atomic layer deposition (ALD) or thermal evaporation.

[0190] Example 65. The method according to any one of Examples 57-63, wherein the metal oxide comprises Al2O3 deposited by ALD.

[0191] Example 66. The method according to any one of Examples 57-65, wherein the metal oxide comprises silicon oxide deposited by thermal evaporation.

[0192] Example 67. The method according to any one of Examples 57-66, wherein: the solution treatment step includes applying an ink comprising a polymer and a liquid, and the liquid is at least one of a suspension barrier layer material or a dissolution barrier layer material.

[0193] Example 68. The method according to any one of Examples 57-67, wherein the barrier layer material comprises at least one of polystyrene, polydimethylsiloxane (PDMS), polyethyleneimine (PEI); polymethyl methacrylate (PMMA), lead sulfate, phenylethyl ammonium iodide (PEAI), or a fluorinated hydrocarbon polymer.

[0194] Example 69. An ink according to any one of Examples 57-68, wherein the liquid comprises an acetate.

[0195] Example 70. The ink according to any one of Examples 57 to 69, wherein the acetate comprises at least one of ethyl acetate or methyl acetate.

[0196] For purposes of illustration and description, the foregoing discussion and examples have been given. The foregoing is not intended to limit aspects, embodiments, or configurations to one or more forms disclosed herein. In the detailed description above, various features of these aspects, embodiments, or configurations are grouped together in one or more embodiments, configurations, or aspects to facilitate the flow of this disclosure. Features of these aspects, embodiments, or configurations may be combined in alternative aspects, embodiments, or configurations other than those described above. The approach of this disclosure should not be construed as reflecting an intention that an aspect, embodiment, or configuration requires more features than expressly recited in each claim. Rather, as reflected in the appended claims, inventive aspects consist of fewer than all features of a single foregoing disclosed embodiment, configuration, or aspect. While certain aspects of conventional art have been discussed to facilitate the disclosure of some embodiments of this disclosure, the applicant does not waive these aspects, and it is contemplated that the claimed invention may cover one or more of the conventional art aspects discussed herein. Therefore, the following claims are thus incorporated into this detailed description, wherein each claim is independently presented as a separate aspect, embodiment, or configuration.

Claims

1. A photovoltaic device, comprising: A first contact layer having a first thickness; A first charge transport layer (CTL) with a second thickness is positioned above the surface of the first contact layer; An absorbent layer of third thickness is positioned above the surface of the first CTL; A second CTL with a fourth thickness is positioned above the surface of the absorbent layer; A second contact layer with a fifth thickness is positioned above the surface of the second CTL; A barrier layer with a sixth thickness; Encapsulation layer; as well as A first scribing line defined by at least one surface, wherein: At least a portion of the barrier layer is positioned between the encapsulation layer and the second CTL. At least one surface of the scribing line includes at least a portion of a third thickness, a fourth thickness, a fifth thickness, and at least a portion of a second thickness, and The barrier layer is disposed on at least a portion of the at least one surface formed by the first scribe line.

2. The photovoltaic device according to claim 1, further comprising: A second scribing line defined by at least one surface, wherein: The at least one surface of the second scribe line includes at least a portion of a second thickness, a third thickness, a fourth thickness, and a fifth thickness. The barrier layer is disposed on at least a portion of the at least one surface of the second scribe line.

3. The photovoltaic device according to claim 2, wherein the at least one surface of the first scribe line comprises a portion of a first contact layer, a first CTL layer, an absorbent layer, a second CTL layer, and a second contact layer.

4. The photovoltaic device according to claim 1, wherein the absorber layer comprises ABX3, wherein A is a first cation, B is a second cation, and X comprises at least one halide.

5. The photovoltaic device according to claim 4, wherein the second cation comprises at least one of tin or lead.

6. The photovoltaic device according to claim 5, wherein the first cation comprises at least one of formamidine (FA), methylammonium (MA), or cesium.

7. The photovoltaic device according to claim 1, wherein the barrier layer comprises at least one of a metal oxide, a polymer, a resin, an aryl ammonium halide, an alkyl ammonium halide, or lead sulfate.

8. The photovoltaic device according to claim 7, wherein the metal oxide comprises at least one of aluminum oxide, silicon oxide, tin oxide, zirconium oxide, or titanium oxide.

9. The photovoltaic device according to claim 7, wherein the aryl ammonium halide comprises at least one of phenylethyl ammonium iodide (PEAI), 1-(acetylammonium)pyrene (PEY), or dodecyl ammonium chloride (DACl).

10. The photovoltaic device of claim 1, wherein the barrier layer has a thickness between 20 nm and 1500 nm.

11. The photovoltaic device of claim 10, wherein, as measured by the thickness of the barrier layer, the barrier layer has a transmittance of greater than 80% at wavelengths greater than 700 nm.

12. The photovoltaic device of claim 1, further comprising a buffer layer positioned between the absorbent layer and the second contact layer, wherein the buffer layer comprises an oxygen-containing salt.

13. The photovoltaic device of claim 1, wherein the second charge transport layer comprises a fullerene.

14. The photovoltaic device according to claim 1, wherein the absorber layer comprises at least one of perovskite, silicon, III-V alloy, organic photovoltaic material, dye sensitizing material, copper indium gallium selenide alloy or cadmium telluride alloy.

15. The photovoltaic device of claim 1, wherein the barrier layer comprises a material insoluble in water.

16. A method for manufacturing a photovoltaic device stack, the method comprising: A barrier layer is formed on a photovoltaic device stack, wherein the device stack comprises: A first contact layer having a first thickness; A first charge transport layer (CTL) with a second thickness is positioned above the surface of the first contact layer; An absorbent layer of third thickness is positioned above the surface of the first CTL; A second CTL having a fourth thickness is positioned above the surface of the absorbent layer; A second contact layer having a fifth thickness is positioned above the surface of the second CTL; and A first scribing line defined by at least one surface, wherein: The at least one surface of the first scribed line includes at least a portion of a third thickness, a fourth thickness, a fifth thickness, and at least a portion of a second thickness. The barrier layer comprises at least one of a metal oxide, polymer, resin, aryl ammonium halide, alkyl ammonium halide, or lead sulfate, and A barrier layer is formed on at least a portion of the at least one surface of the first scribe line.

17. The method of claim 16, wherein: The device stack also includes a second scribing line. The second scribe line is defined by at least one surface. The at least one surface of the second scribe line includes at least a portion of a first thickness, a second thickness, a third thickness, a fourth thickness, or a fifth thickness, and The barrier layer is disposed on at least a portion of the at least one surface of the second scribe line.

18. The method according to any one of claims 16-17, wherein the barrier layer comprises the metal oxide, and the metal oxide comprises aluminum oxide, silicon oxide, tin oxide, zirconium oxide, titanium oxide, or a combination thereof.

19. The method according to any one of claims 16-18, wherein the blocking layer has a thickness between 20 nm and 1500 nm, and as measured by the thickness of the blocking layer, the blocking layer has a transmittance of greater than 80% at wavelengths greater than 700 nm.

20. The method according to any one of claims 16-19, wherein the barrier layer comprises a material insoluble in water.

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