Apparatus, method, and storage medium for out-of-order execution-based vector register write back

Abstract

The application is suitable for the field of processor technology, and particularly relates to a vector register write-back device based on out-of-order execution, a method and a storage medium. The vector register write-back device comprises a dispatch module, a scoreboard module, a launch queue module, a read module, a register file module, an execution module and a write-back module; the launch queue module is used for applying for allocating a corresponding second entry to the write-back module according to a received to-be-executed instruction, the second entry is used for recording a destination register number corresponding to the to-be-executed instruction, and the write-back module sends a corresponding write-back queue number to the launch queue module after completing the allocation of the second entry. Compared with the prior art, the application effectively avoids the huge area power consumption caused by the introduction of the renaming mechanism, does not need a large number of physical registers to consume many circuit areas and power consumption resources, and improves the parallel degree of instruction execution compared with the scheme without supporting out-of-order execution, thereby effectively improving the performance of the vector processor.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of processors, and particularly relates to a vector register write-back device based on out-of-order execution, a method and a storage medium. BACKGROUND

[0002] In existing processor architectures, data processing is mostly in the form of scalars, that is, only a single data element is processed each time. For example, when performing mathematical operations and data processing tasks, a large-scale data set needs to be processed element by element in sequence, which causes the processing efficiency to be significantly reduced as the data volume increases. In the fields of image, audio, video processing and scientific computing, there are many scenarios of matrix operations and vector operations involving massive data, and the traditional scalar processing mode is difficult to meet the real-time and high-efficiency requirements, which has become a key bottleneck restricting the development of such applications. In order to improve the computing performance and efficiency, many high-performance processors introduce a vector extension instruction set, so that the processor can execute the same operation on multiple data elements (forming a vector) simultaneously in one instruction cycle according to the instruction requirements, such as simultaneously performing addition, multiplication and other mathematical operations on a group of vector data. The hardware architecture includes multiple vector registers for storing these vector data, cooperating with a special vector operation unit to perform high-speed operations, and the instruction pipeline is optimized to efficiently process a sequence of vector instructions to reduce the instruction execution delay and improve the overall performance. Similar to scalar processors, vector processors can be divided into front ends (responsible for instruction fetching), back ends (responsible for scheduling and execution), memory (interacting with memory) and other components, and the register write-back behavior occurs in the back end, which refers to writing the result data of the execution to the register after the instruction is executed in the back end functional unit, and updating the state of the processor.

[0003] In order to further improve the vector performance of the processor, the processor usually uses an out-of-order execution technology similar to the scalar in the vector micro-architecture design part. Out-of-order execution refers to that the instructions are no longer executed one by one according to the original order of the computer program, but are intelligently scheduled and executed according to the dependencies between the instructions and the availability of the execution unit, so as to improve the execution efficiency of the instructions; and when the instructions are submitted, the program semantic order is ensured to ensure the consistency of the data.

[0004] The processor supporting out-of-order execution is generally equipped with a renaming technology to solve data conflicts, so as to reduce the stall time of the instructions in the pipeline and improve the performance of the processor. The implementation manner is that the processor is equipped with a plurality of physical registers for renaming, and these physical registers are dynamically allocated to the logical registers of the instructions during the execution of the instructions. After the execution of the instructions is completed and the result is written back to the physical register, it is confirmed that the mapping of the logical register and the physical register is changed, which is equivalent to writing the result to the logical register.

[0005] For example, there are the following three instructions:

[0006] 1. ADD R1, R2, R3; add the values of registers R2 and R3 and store the result in R1;

[0007] 2. MUL R1, R4, R5; multiply the values of registers R1 and R5 and store the result in R4;

[0008] 3. SUB R1, R8, R7; subtract the values of registers R1 and R7 and store the result in R8;

[0009] Without renaming, instructions 2 and 3 must wait for instruction 1 to finish execution and write the result to R1 before they can start execution, because they both change the value of logical register R1 and must follow the program semantics to execute and write back in order.

[0010] With the use of renaming technology, the logical register R1 of instruction 1 is mapped (speculatively, to be confirmed in the commit stage) to a physical register (assuming P1), and the logical registers R1 of instructions 2 and 3 are mapped to physical registers P2 and P3, respectively. Even if the three instructions are executed out of order, because their physical registers are different, the program semantics will not be affected, and only the mapping relationship between the logical register and the physical register needs to be confirmed in the instruction commit stage according to the program order to ensure the program semantics and improve the instruction parallelism.

[0011] However, although the out-of-order execution implementation based on renaming can improve the performance of the processor, it requires a large amount of hardware resources to support, such as renaming circuit, renaming table, free list, and a large number of physical registers. Especially, the physical registers consume a lot of circuit area space. For example, in the case of the vector extension of RISC-V, the instruction set defines 32 logical registers, each supporting a maximum of 512 bits wide. If renaming is implemented in a three-way issue processor, at least 64 physical registers are needed to achieve good results, and the area consumed by the physical register stack is at least 64*512=32768 bits. In addition to the area of the renaming table and the free list and some circuits to implement the corresponding logic, this implementation method constitutes a large circuit overhead.

[0012] Therefore, there is an urgent need for a new vector register write-back device, method and storage medium based on out-of-order execution to solve the above technical problems. SUMMARY

[0013] The present application provides a vector register write-back device, method and storage medium based on out-of-order execution, aiming to improve the performance of the vector processor when executing out-of-order and avoid the huge area power consumption caused by introducing the renaming mechanism.

[0014] In a first aspect, the present application provides a vector register write-back device based on out-of-order execution, which comprises a dispatch module, a scoreboard module, a launch queue module, a read module, a register file module, an execution module and a write-back module.

[0015] The dispatch module is configured to send a to-be-executed instruction to the launch queue module and apply for allocation of a first entry corresponding to the to-be-executed instruction in the scoreboard module; wherein the first entry is configured to record a register number corresponding to the to-be-executed instruction.

[0016] The scoreboard module is configured to send a corresponding scoreboard number to the dispatch module according to the first entry, and the dispatch module sends the corresponding scoreboard number to the launch queue module when sending the to-be-executed instruction.

[0017] The launch queue module is configured to apply for allocation of a second entry corresponding to the to-be-executed instruction to the write-back module according to the received to-be-executed instruction, and the second entry is configured to record a destination register number corresponding to the to-be-executed instruction; after the write-back module allocates the second entry, the write-back module sends a corresponding write-back queue number to the launch queue module; at the same time, the launch queue module sends the received to-be-executed instruction, the scoreboard number and the write-back queue number to the read module in an out-of-order manner.

[0018] The register file module is configured to store the source operand.

[0019] The read module is configured to read a corresponding source operand from the register file module according to the received to-be-executed instruction, and send the to-be-executed instruction, the scoreboard number, the write-back queue number and the source operand to the execution module.

[0020] The execution module is configured to perform a corresponding operation process according to the received source operand and the to-be-executed instruction, obtain execution result data, and send the execution result data, the scoreboard number and the write-back queue number to the write-back module.

[0021] The write-back module is configured to perform write-back processing according to the received execution result data, the scoreboard number and the write-back queue number.

[0022] Preferably, the write-back module is further configured to find a third entry corresponding to the execution result data according to the write-back queue number, and write the execution result data and the scoreboard number into the third entry, and mark the third entry as a data valid mark.

[0023] Preferably, the write-back module is further configured to send a valid transmission flag of the second target entry to the scoreboard module when the execution instruction is sent to the read module by the transmission queue module.

[0024] Preferably, the scoreboard module is further configured to send write-after-read data conflict resolved information to the transmission queue module; and the transmission queue module is further configured to reorder and send the execution instruction without write-after-read data conflict, the scoreboard number and the write-back queue number to the read module according to the write-after-read data conflict resolved information received.

[0025] Preferably, the scoreboard module is further configured to send a write enable signal to the write-back module every cycle; wherein the write enable signal is generated by confirming that the execution result data in the third entry in the write-back module eliminates write-after-write data conflict and write-after-read data conflict.

[0026] Preferably, when the second entry, the third entry and the write enable signal are all preset values, the write-back module writes back to the corresponding register in the register stack module according to the execution result data in the third entry and the destination register number in the second entry, and marks the first entry with write-back completion in the scoreboard module according to the scoreboard number.

[0027] Preferably, the scoreboard module is further configured to unload the first entry with write-back completion flag.

[0028] In a second aspect, the present application further provides a vector register write-back method based on out-of-order execution, which is based on the vector register write-back device based on out-of-order execution according to any one of the above embodiments. The vector register write-back method comprises the following steps:

[0029] S1, according to the execution instruction in the dispatch module, the corresponding first entry is applied for distribution to the scoreboard module, and the scoreboard module returns the corresponding scoreboard module to the dispatch module; wherein the first entry is used to record the register number corresponding to the execution instruction;

[0030] S2, the dispatch module sends the execution instruction and the scoreboard number to the transmission queue module, and the transmission queue module applies for distribution of the corresponding second entry to the write-back module according to the execution instruction, and the write-back module returns the corresponding write-back queue number to the transmission queue module; wherein the second entry is used to record the destination register number corresponding to the execution instruction;

[0031] S3, the sending module sends the to-be-executed instruction without the read-after-write data conflict, the corresponding scorecard number and the write-back queue number to a reading module in a disordered manner, the reading module reads corresponding source operands from a register heap module according to the received to-be-executed instruction, and sends the to-be-executed instruction, the scorecard number, the write-back queue number and the source operands to an execution module;

[0032] S4, the execution module is used for executing corresponding operation processing according to the received source operands and the to-be-executed instruction, obtaining execution result data, and sending the execution result data, the scorecard number and the write-back queue number to the write-back module;

[0033] S5, the write-back module finds a third entry corresponding to the execution result data according to the write-back queue number, and writes the execution result data and the scorecard number into the third entry;

[0034] S6, the scorecard module sends a write enable signal to the write-back module every period; wherein the write enable signal is generated by confirming that the execution result data in the third entry in the write-back module eliminates the write-after-write data conflict and the read-after-write data conflict;

[0035] S7, when the second entry, the third entry and the write enable signal are all preset values, the write-back module writes back the execution result data and the corresponding destination register number into the corresponding register in the register heap module; and according to the scorecard number corresponding to the execution result data, marks the first entry in the scorecard module as write-back completion, and the scorecard module unloads the first entry with the write-back completion mark.

[0036] In a third aspect, the present application further provides a vector register write-back device based on out-of-order execution, comprising a memory, a processor and a vector register write-back program based on out-of-order execution stored on the memory and executable on the processor, wherein the processor implements the steps of the vector register write-back method based on out-of-order execution when executing the vector register write-back program based on out-of-order execution.

[0037] In a fourth aspect, the present application further provides a storage medium, wherein the storage medium stores a vector register write-back program based on out-of-order execution, and the vector register write-back program based on out-of-order execution implements the steps of the vector register write-back method based on out-of-order execution when executed by a processor.

[0038] Compared with the prior art, the application effectively avoids huge area power consumption caused by introducing a renaming mechanism, and does not need a large number of physical registers to consume many circuit areas and power consumption resources, and compared with a scheme without supporting out-of-order execution, the application improves the parallelism of instruction execution and effectively improves the performance of a vector processor. BRIEF DESCRIPTION OF DRAWINGS

[0039] The above and other aspects of the present application will become more apparent and more readily appreciated from the following detailed description of the application, taken in conjunction with the accompanying drawings in which:

[0040] Figure 1 is a structural schematic diagram of a vector register write-back device based on out-of-order execution according to Embodiment One of the application;

[0041] Figure 2 is a data structure schematic diagram of a write-back module of the vector register write-back device based on out-of-order execution according to Embodiment One of the application;

[0042] Figure 3 is a flowchart of a vector register write-back method based on out-of-order execution according to an embodiment of the application;

[0043] Figure 4 is a structural schematic diagram of a vector register write-back device based on out-of-order execution according to Embodiment Three of the application. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0045] Embodiment One

[0046] The embodiment of the application further provides a vector register write-back device 100 based on out-of-order execution, which comprises a dispatching module 001, a scoreboard module 002, a launch queue module 003, a read module 004, an execution module 005, a write-back module 006 and a register file module 007.

[0047] Specifically, please refer to Figure 1 , Figure 1Figure 1 is a structural schematic diagram of the vector register write-back device based on out-of-order execution according to Embodiment One of the present application. The output end of the dispatch module 001 is connected to the input end of the scoreboard module 002 and the input end of the launch queue module 003 respectively; the output end of the scoreboard module 002 is connected to the input end of the dispatch module 001, the input end of the launch queue module 003 and the input end of the write-back module 006 respectively; the output end of the launch queue module 003 is connected to the input end of the read module 004 and the input end of the write-back module 006 respectively; the output end of the read module 004 is connected to the input end of the execution module 005; the output end of the execution module 005 is connected to the input end of the write-back module 006; the output end of the write-back module 006 is connected to the input end of the scoreboard module 002, the input end of the launch queue module 003 and the input end of the register file module 007 respectively; the output end of the register file module 007 is connected to the input end of the read module 004.

[0048] The dispatch module 001 is configured to send an instruction to be executed to the launch queue module 003 and apply for allocation of a first entry corresponding to the instruction to be executed in the scoreboard module 002; wherein the first entry is configured to record register number information corresponding to the instruction to be executed. Specifically, the first entry is stored in the scoreboard module 002 for subsequent processing of data dependency (such as write-after-read, write-after-write and read-after-write) between instructions. The scoreboard number is the number corresponding to the instruction to be executed and the first entry, which is transmitted in the pipeline all the time. Specifically, an entry is a kind of independent storage unit used to describe data structure.

[0049] The scoreboard module 002 is configured to send a corresponding scoreboard number to the dispatch module 001 according to the first entry; when the dispatch module 001 sends the instruction to be executed, the corresponding scoreboard number is sent to the launch queue module 003 together;

[0050] In the embodiment of the present application, the scoreboard module 002 is further configured to send write-after-read data conflict resolution information to the launch queue module 003; the launch queue module 003 is further configured to send the instruction to be executed, the scoreboard number and the write-back queue number of which do not exist write-after-read data conflict to the read module 004 in disorder according to the received write-after-read data conflict resolution information.

[0051] In the embodiment of the present application, the scoreboard module 002 is further configured to send a write enable signal to the write back module 006 every cycle; wherein the write enable signal is generated after confirming that the execution result data of the third entry in the write back module 006 eliminates the write-after-write data conflict and the write-after-read data conflict. The write enable signal is a control signal used to control the timing of writing data from the write back module 006 to the register file module 007, and its core function is to ensure that the final write back operation is allowed only after the data conflict (such as write-after-write data conflict and write-after-read data conflict) is completely resolved, thereby guaranteeing the consistency and correctness of the data.

[0052] In the embodiment of the present application, the scoreboard module 002 is further configured to unload the first entry with a write back completion flag. Releasing the memory, storage, port and other resources occupied by the marked object can avoid resource leakage, optimize system performance, and ensure the closed loop of the process.

[0053] The transmit queue module 003 is configured to apply for and allocate a corresponding second entry to the write back module 006 according to the received to-be-executed instruction, wherein the second entry is used to record the destination register number corresponding to the to-be-executed instruction, and the write back module 006 sends a corresponding write back queue number to the transmit queue module 003 after allocating the second entry; at the same time, the transmit queue module 003 transmits the received to-be-executed instruction, the scoreboard number and the write back queue number to the read module 004 in a disordered manner.

[0054] The register file module 007 is configured to store the source operand.

[0055] The read module 004 is configured to read the corresponding source operand from the register file module 007 according to the received to-be-executed instruction, and send the to-be-executed instruction, the scoreboard number, the write back queue number and the source operand to the execution module 005 together;

[0056] The execution module 005 is configured to execute corresponding operation processing according to the received source operand and to-be-executed instruction, obtain execution result data, and send the execution result data, the scoreboard number and the write back queue number to the write back module 006;

[0057] The write back module 006 is configured to perform write back processing according to the received execution result data, the scoreboard number and the write back queue number.

[0058] In the embodiment of the present application, the write-back module 006 is further configured to find a third entry corresponding to the execution result data according to the write-back queue number, and write the execution result data and the scoreboard number into the third entry, and mark the third entry as a data valid mark.

[0059] In the embodiment of the present application, the write-back module 006 is further configured to mark the second entry as a valid launch mark when the launch queue module 003 sends the to-be-executed instruction to the read module 004.

[0060] In the embodiment of the present application, when the second entry, the third entry and the write enable signal are all preset values, the write-back module 006 writes back the execution result data in the third entry and the destination register number in the second entry into the corresponding register of the register file module 007, and marks the first entry in the scoreboard module 002 as a write-back completion according to the scoreboard number. For details, please refer to Figure 2 , Figure 2 is a data structure diagram of the write-back module 006 of the embodiment one of the vector register write-back device based on out-of-order execution provided by the embodiment of the present application. As shown in Figure 2 , the write-back module 006 includes a plurality of entries, a second entry recording an entry valid mark (entry_valid, i.e. a valid launch mark) and a destination register number, and a third entry recording a data valid mark (data_vaild), execution result data and a scoreboard number respectively.

[0061] Specifically, when a to-be-executed instruction is executed in the vector register write-back device based on out-of-order execution, the following processes are included:

[0062] When the to-be-executed instruction is sequentially dequeued from the dispatch module 001, the dispatch module 001 applies for allocating a first entry to the scoreboard module 002, records the register number of the to-be-executed instruction and other information, and uses it for subsequent processing of data dependency between instructions. The scoreboard module 002 returns a corresponding scoreboard number to the to-be-executed instruction dequeued from the dispatch module 001, and the scoreboard number is transmitted in the main pipeline together with the to-be-executed instruction.

[0063] When the dispatch module 001 sends the to-be-executed instruction, the wait scoreboard module 002 provides information that the write-after-read data conflict has been resolved. If it has been resolved, the to-be-executed instruction without the write-after-read data conflict can be reordered and sent to the read module 004 based on the age-first principle (i.e., the instruction entering the dispatch queue first is more preferred). When the dispatch queue module 003 sends the to-be-executed instruction, it applies for the allocation of the second entry to the write-back module 006, marks the second entry valid and records the relevant information (such as the destination register number) of the to-be-executed instruction, and then the write-back module 006 returns a corresponding write-back queue number to the dispatch queue module 003, which is transmitted in the main pipeline along with the to-be-executed instruction.

[0064] The data structure of the write-back module 006 is a variant of the eight-depth FIFO (first-in, first-out), which is controlled by the read pointer and the write pointer for the out and in respectively, and the content of each entry in the write-back module 006 is updated according to the corresponding write-back queue number. For example, when the to-be-executed instruction is dequeued from the dispatch queue module 003, the write-back module 006 allocates the write pointer to point to the entry valid of the second entry, marks the entry valid, and records the destination register number in the second entry, and then the write pointer points to the next entry (i.e., the third entry data_valid, execution result data, and scoreboard number).

[0065] When the execution module 005 sends the execution result data, the scoreboard number and the write-back queue number to the write-back module 006, the write-back module 006 finds the corresponding third entry according to the write-back queue number, and writes the execution result data and the scoreboard number into the third entry, and marks data_valid.

[0066] When the read pointer of the write back module 006 points to an entry, and the following conditions exist simultaneously: entry_valid, data_valid and write enable signal are high (i.e. preset value, entry_valid, data_valid and write enable signal are valid at the same time), the write back module 006 will write the execution result data stored in the entry in the data structure back to the corresponding register in the register heap module 007 according to the recorded destination register number; at the same time, write back to the corresponding first entry in the scoreboard module 002 according to the scoreboard number recorded in the third entry, and the subsequent scoreboard module 002 will unload the corresponding first entry according to this flag; after the above two operations, the read pointer in the write back module 006 is incremented by one, and entry_valid and data_valid are lowered, and the write back operation is completed, so that the vector processor device obtains the performance improvement of out-of-order execution, while avoiding the huge area power consumption caused by introducing the renaming mechanism. The present application takes an eight-depth write back module 006, 512-bit wide 32 logical registers as an example, compared with the traditional scheme of 64 physical registers, it effectively saves (64-32-8)*512=12288 bit width.

[0067] Compared with the prior art, the present application effectively avoids the huge area power consumption caused by introducing the renaming mechanism, without a large number of physical registers and a large amount of circuit area and power consumption resources, compared with the scheme without supporting out-of-order execution, the present application improves the parallelism of instruction execution, and effectively improves the performance of the vector processor.

[0068] Embodiment two

[0069] Please refer to Figure 3 The present application provides a vector register write back method based on out-of-order execution, which is based on the vector register write back device based on out-of-order execution in any one of the above embodiments, and the vector register write back method comprises the following steps:

[0070] S1, according to the to-be-executed instruction in the dispatch module 001, apply for allocating the corresponding first entry to the scoreboard module 002, and the scoreboard module 002 returns the corresponding scoreboard module 002 to the dispatch module 001; wherein, the first entry is used for recording the register number corresponding to the to-be-executed instruction;

[0071] S2, the sending module 001 sends the to-be-executed instruction and the scorecard number to the launch queue module 003, the launch queue module 003 applies for allocating a corresponding second item to the write-back module 006 according to the to-be-executed instruction, and the write-back module 006 returns a corresponding write-back queue number to the launch queue module 003; wherein the second item is used to record the destination register number corresponding to the to-be-executed instruction;

[0072] S3, the launch queue module 003 sends the to-be-executed instruction without write-after-read data conflict and the corresponding scorecard number and write-back queue number to the read module 004 in disorder, the read module 004 reads the corresponding source operand from the register heap module 007 according to the received to-be-executed instruction, and sends the to-be-executed instruction, the scorecard number, the write-back queue number and the source operand to the execution module 005;

[0073] S4, the execution module 005 is used for executing corresponding operation processing according to the received source operand and the to-be-executed instruction, obtaining execution result data, and sending the execution result data, the scorecard number and the write-back queue number to the write-back module 006;

[0074] S5, the write-back module 006 finds a third item corresponding to the execution result data according to the write-back queue number, and writes the execution result data and the scorecard number into the third item;

[0075] S6, the scorecard module 002 sends a write enable signal to the write-back module 006 every period; wherein the write enable signal is generated by confirming that the execution result data in the third item in the write-back module 006 eliminates write-after-write data conflict and write-after-read data conflict;

[0076] S7, when the second item, the third item and the write enable signal are all preset values, the write-back module 006 writes back the execution result data and the corresponding destination register number into the corresponding register in the register heap module 007; and according to the scorecard number corresponding to the execution result data, marks the first item in the scorecard module 002 as write-back completion, and the scorecard module 002 unloads the first item with write-back completion mark.

[0077] Specifically, when a to-be-executed instruction is executed in the vector register write-back device based on out-of-order execution, the following process is included:

[0078] The pending instruction is dequeued from the dispatch module 001 in sequence, and the dispatch module 001 applies for allocation of a first entry from the scoreboard module 002, records the register number of the pending instruction, and the like, for subsequent processing of data dependency between instructions. The scoreboard module 002 returns a corresponding scoreboard number to the pending instruction dequeued from the dispatch module 001, and the scoreboard number is transmitted in the main pipeline along with the pending instruction.

[0079] When the launch queue module 003 receives the pending instruction sent by the dispatch module 001, it waits for the scoreboard module 002 to provide information that the write-after-read data conflict has been resolved. If it has been resolved, the pending instruction without the write-after-read data conflict can be launched into the read number module 004 in a disordered manner based on the age priority (i.e., the instruction that enters the launch queue first is more preferred). When the launch queue module 003 launches the pending instruction, it applies for allocation of a second entry from the write-back module 006, marks the second entry as valid and records the relevant information (such as the destination register number) of the pending instruction, and then the write-back module 006 returns a corresponding write-back queue number to the launch queue module 003, and the write-back queue number is transmitted in the main pipeline along with the pending instruction.

[0080] The data structure of the write-back module 006 is a variant of the eight-depth FIFO (first-in, first-out), as shown in Figure 2 The read pointer and the write pointer control the dequeue and the enqueue, respectively, and update the content of each entry in the write-back module 006 according to the corresponding write-back queue number. For example, when the pending instruction is dequeued from the launch queue module 003, the write-back module 006 allocates the entry valid flag (entry_valid) of the second entry to mark the entry as valid, records the destination register number in the second entry, and then the write pointer points to the next entry (i.e., the third entry data_valid).

[0081] When the execution module 005 sends the execution result data, the scoreboard number, and the write-back queue number to the write-back module 006, the write-back module 006 finds the corresponding third entry according to the write-back queue number, writes the execution result data and the scoreboard number into the third entry, and marks data_valid.

[0082] When the entry pointed by the read pointer of the write back module 006 meets the following conditions: entry_valid, data_valid and write enable signal are high, the write back module 006 writes the execution result data stored in the entry in the data structure into the corresponding register in the register heap module 007 according to the recorded destination register number, and writes the completion of the corresponding first entry in the scoreboard module 002 according to the recorded scoreboard number, and the subsequent scoreboard module 002 unloads the corresponding first entry according to the flag; after the above two operations, the read pointer in the write back module 006 is incremented by one, and the entry_valid and data_valid are lowered, and the write back operation is completed, so that the vector processor device obtains the performance improvement of out-of-order execution, and the huge area power consumption caused by the introduction of the renaming mechanism is avoided. The present application takes the write back module 006 of eight depth, 512 bit width of 32 logical registers as an example, compared with the traditional scheme of 64 physical registers, it effectively saves (64-32-8)*512=12288 bit width.

[0083] The vector register write back method based on out-of-order execution is based on the vector register write back device 100 based on out-of-order execution in the above embodiment, and can achieve the same technical effects. Please refer to the description in the above embodiment, which will not be repeated here.

[0084] Embodiment three

[0085] The embodiment of the present application also provides a vector register write back device 200 based on out-of-order execution, please refer to Figure 4 , Figure 4 is a structure diagram of the vector register write back device based on out-of-order execution of embodiment three provided by the embodiment of the present application, the vector register write back device 200 based on out-of-order execution comprises a memory 202, a processor 201 and a vector register write back program based on out-of-order execution stored in the memory 202 and capable of running on the processor 201.

[0086] The processor 201 calls the vector register write back program based on out-of-order execution stored in the memory 202, and executes the steps in the vector register write back method based on out-of-order execution provided by the embodiment of the present application, please combine Figure 4 , specifically comprising the following steps:

[0087] S1, according to the to-be-executed instruction in the dispatch module 001, apply for allocating the corresponding first entry to the scoreboard module 002, and the scoreboard module 002 returns the corresponding scoreboard module 002 to the dispatch module 001; wherein, the first entry is used for recording the register number corresponding to the to-be-executed instruction;

[0088] S2, the sending module 001 sends the to-be-executed instruction and the scorecard number to the launch queue module 003, the launch queue module 003 applies for allocating a corresponding second item to the write-back module 006 according to the to-be-executed instruction, and the write-back module 006 returns a corresponding write-back queue number to the launch queue module 003; wherein the second item is used to record the destination register number corresponding to the to-be-executed instruction;

[0089] S3, the launch queue module 003 sends the to-be-executed instruction without write-after-read data conflict and the corresponding scorecard number and write-back queue number to the read module 004 in disorder, the read module 004 reads the corresponding source operand from the register heap module 007 according to the received to-be-executed instruction, and sends the to-be-executed instruction, the scorecard number, the write-back queue number and the source operand to the execution module 005;

[0090] S4, the execution module 005 is used for executing corresponding operation processing according to the received source operand and the to-be-executed instruction, obtaining execution result data, and sending the execution result data, the scorecard number and the write-back queue number to the write-back module 006;

[0091] S5, the write-back module 006 finds a third item corresponding to the execution result data according to the write-back queue number, and writes the execution result data and the scorecard number into the third item;

[0092] S6, the scorecard module 002 sends a write enable signal to the write-back module 006 every period; wherein the write enable signal is generated by confirming that the execution result data in the third item in the write-back module 006 eliminates write-after-write data conflict and write-after-read data conflict;

[0093] S7, when the second item, the third item and the write enable signal are all preset values, the write-back module 006 writes back the execution result data and the corresponding destination register number into the corresponding register in the register heap module 007; and according to the scorecard number corresponding to the execution result data, marks the first item in the scorecard module 002 as write-back completion, and the scorecard module 002 unloads the first item with write-back completion mark.

[0094] Specifically, when a to-be-executed instruction is executed in the vector register write-back device based on out-of-order execution, the following process is included:

[0095] When the instruction is dequeued from the dispatch module 001, the dispatch module 001 applies to the scoreboard module 002 for allocating a first entry to record the register number of the instruction, for later processing of data dependency among instructions. The scoreboard module 002 returns a corresponding scoreboard number to the instruction dequeued from the dispatch module 001, and the scoreboard number is passed along with the instruction in the main pipeline.

[0096] When the instruction is received by the issue queue module 003 sent by the dispatch module 001, the issue queue module 003 waits for the scoreboard module 002 to provide information that the read-after-write data conflict has been resolved. If the conflict has been resolved, the instruction without the read-after-write data conflict can be reordered and issued to the read module 004 based on the age-first principle (i.e. the instruction that enters the issue queue first is given higher priority). When the instruction is issued by the issue queue module 003, the write-back module 006 is applied to allocate a second entry to mark the second entry as valid and record the relevant information (e.g. the destination register number) of the instruction. Then the write-back module 006 returns a corresponding write-back queue number to the issue queue module 003, and the write-back queue number is passed along with the instruction in the main pipeline.

[0097] The data structure of the write-back module 006 is a variant of the eight-depth FIFO (first-in-first-out), which is controlled by a read pointer and a write pointer for dequeuing and enqueuing respectively, and the content of each entry in the write-back module 006 is updated according to the corresponding write-back queue number. For example, when the instruction is dequeued from the issue queue module 003, the write-back module 006 allocates the write pointer to point to the second entry, marks the second entry as valid (entry_valid), and records the destination register number in the second entry. Then the write pointer points to the next entry (i.e. the third entry data_valid).

[0098] When the execution module 005 sends the execution result data, the scoreboard number and the write-back queue number to the write-back module 006, the write-back module 006 finds the corresponding third entry according to the write-back queue number, and writes the execution result data and the scoreboard number into the third entry, and marks data_valid.

[0099] When the entry pointed by the read pointer of the write back module 006 has the following conditions: entry_valid, data_valid and write enable signal are high, the write back module 006 writes the execution result data stored in the entry in the data structure into the corresponding register in the register heap module 007 according to the recorded destination register number, and writes the completion of the corresponding first entry in the scoreboard module 002 according to the recorded scoreboard number, and the subsequent scoreboard module 002 unloads the corresponding first entry according to the flag; after the above two operations, the read pointer in the write back module 006 is incremented by one, and the entry_valid and data_valid are lowered, and the write back operation is completed, so that the vector processor device obtains the performance improvement of out-of-order execution, and the huge area power consumption caused by the introduction of the renaming mechanism is avoided. The present application takes the eight-depth write back module 006 and 512-bit-wide 32 logical registers as an example, compared with the traditional scheme of 64 physical registers, it effectively saves (64-32-8)*512=12288 bit width.

[0100] The vector register write back device based on out-of-order execution 200 provided by the embodiment of the present application can realize the steps in the vector register write back method based on out-of-order execution in the above embodiment, and can realize the same technical effects. For the description in the above embodiment, details are not repeated here.

[0101] Embodiment four

[0102] The embodiment of the present application also provides a storage medium, which is a computer readable storage medium, and the storage medium stores a vector register write back program based on out-of-order execution. The vector register write back program based on out-of-order execution is executed by a processor to realize each process and step in the vector register write back method based on out-of-order execution provided by the embodiment of the present application, and can realize the same technical effects. To avoid repetition, details are not repeated here.

[0103] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by a computer program instructing related hardware. The vector register write back program based on out-of-order execution can be stored in a computer readable storage medium. When the program is executed, it can include the processes of the above-mentioned embodiment of each method. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM).

[0104] It should be noted that, in this document, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0105] Those skilled in the art can clearly understand the above-mentioned embodiment method can be realized by means of software and necessary general hardware platform, of course, also can be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of software product, and the computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a plurality of instructions to make a terminal (which can be a mobile phone, computer, server, air conditioner, or network equipment, etc.) execute the method described in each embodiment of the present application.

[0106] The embodiments of the present application are described above in conjunction with the drawings, the disclosed is only the preferred embodiment of the present application, but the present application is not limited to the above specific embodiments, the above specific embodiments are only illustrative, but not restrictive, those skilled in the art can make many equivalent changes without departing from the purpose of the present application and the scope of the claims, all of which are within the protection of the present application.

Claims

1. A vector register write-back device based on out-of-order execution, characterized in that, The vector register write back device comprises a dispatch module, a scoreboard module, a launch queue module, a read module, a register file module, an execution module and a write back module; The dispatch module is configured to send a to-be-executed instruction to the launch queue module, and apply for allocation of a first entry corresponding to the to-be-executed instruction in the scoreboard module; wherein the first entry is configured to record a register number corresponding to the to-be-executed instruction. The scoreboard module is configured to send a corresponding scoreboard number to the dispatch module according to the first entry, and the dispatch module sends the corresponding scoreboard number to the launch queue module when sending the to-be-executed instruction. The launch queue module is configured to apply for allocation of a second entry corresponding to the to-be-executed instruction to the write back module, and the second entry is configured to record a destination register number corresponding to the to-be-executed instruction; after the write back module allocates the second entry, the write back module sends a corresponding write back queue number to the launch queue module; at the same time, the launch queue module sends the received to-be-executed instruction, the scoreboard number and the write back queue number to the read module in a disordered manner. The register file module is configured to store source operands. The read module is configured to read corresponding source operands from the register file module according to the received to-be-executed instruction, and send the to-be-executed instruction, the scoreboard number, the write back queue number and the source operands to the execution module. The execution module is configured to perform corresponding operation processing according to the received source operands and the to-be-executed instruction, obtain execution result data, and send the execution result data, the scoreboard number and the write back queue number to the write back module. The write back module is configured to perform write back processing according to the received execution result data, the scoreboard number and the write back queue number.

2. The out-of-order execution based vector register write back apparatus of claim 1, wherein, The write back module is further configured to find a third entry corresponding to the execution result data according to the write back queue number, and write the execution result data and the scoreboard number into the third entry, and mark the third entry as a data valid flag.

3. The out-of-order execution based vector register write back apparatus of claim 2, wherein, The write back module is further configured to mark the second entry as a valid launch flag when the launch queue module sends the to-be-executed instruction to the read module.

4. The out-of-order execution based vector register write back apparatus of claim 3, wherein, The scoreboard module is further configured to send write-after-read data conflict resolved information to the launch queue module; the launch queue module is further configured to send the to-be-executed instruction, the scoreboard number and the write back queue number, which do not have write-after-read data conflict, to the read module in a disordered manner according to the received write-after-read data conflict resolved information.

5. The out-of-order execution based vector register write back apparatus of claim 4, wherein, The scoreboard module is further configured to send a write enable signal to the write back module every period; wherein the write enable signal is generated by confirming that the execution result data in the third entry in the write back module eliminates write-after-write data conflict and write-after-read data conflict.

6. The out-of-order execution based vector register write back apparatus of claim 5, wherein, When the second entry, the third entry and the write enable signal are preset values, the write back module writes back the execution result data in the third entry and the destination register number in the second entry into the corresponding register of the register file module, and marks the corresponding first entry in the scoreboard module as write back completion according to the scoreboard number.

7. The out-of-order execution based vector register write back apparatus of claim 6, wherein, The scoreboard module is further used to unload the first entry with the write back completion mark.

8. A method of write back of vector registers based on out-of-order execution, characterized in that, The out-of-order execution based vector register write back method is based on the out-of-order execution based vector register write back device in any one of claims 1-7, and the vector register write back method comprises the following steps: S1, a first entry corresponding to a to-be-executed instruction in a dispatch module is applied for allocation to a scoreboard module, and the scoreboard module returns a corresponding scoreboard number to the dispatch module; wherein, the first entry is used to record a register number corresponding to the to-be-executed instruction; S2, the dispatch module sends the to-be-executed instruction and the scoreboard number to a launch queue module, the launch queue module applies for allocation of a second entry corresponding to the to-be-executed instruction to a write back module, and the write back module returns a corresponding write back queue number to the launch queue module; wherein, the second entry is used to record a destination register number corresponding to the to-be-executed instruction; S3, the launch queue module sends the to-be-executed instruction and the corresponding scoreboard number and write back queue number without write-after-read data conflict in disorder to a read number module, the read number module reads corresponding source operands from a register file module according to the received to-be-executed instruction, and sends the to-be-executed instruction, the scoreboard number, the write back queue number and the source operands to an execution module; S4, the execution module is used to execute corresponding operation processing according to the received source operands and the to-be-executed instruction, obtain execution result data, and send the execution result data, the scoreboard number and the write back queue number to the write back module; S5, the write back module finds a third entry corresponding to the execution result data according to the write back queue number, and writes the execution result data and the scoreboard number into the third entry; S6, the scoreboard module sends a write enable signal to the write back module every period; wherein, the write enable signal is generated by confirming that the execution result data of the third entry in the write back module eliminates write-after-write data conflict and write-after-read data conflict; S7, when the second entry, the third entry and the write enable signal are preset values, the write back module writes back the execution result data and the corresponding destination register number into the corresponding register of the register file module; and marks the corresponding first entry in the scoreboard module as write back completion according to the scoreboard number corresponding to the execution result data, and the scoreboard module unloads the first entry with the write back completion mark.

9. A vector register write-back device based on out-of-order execution, characterized in that, Comprise: A memory, a processor, and an out-of-order execution based vector register write back program stored on the memory and executable on the processor, the processor implementing the steps of the out-of-order execution based vector register write back method as claimed in claim 8 when executing the out-of-order execution based vector register write back program.

10. A storage medium, characterized by A storage medium having stored thereon an out-of-order execution based vector register write back program, the out-of-order execution based vector register write back program implementing the steps of the out-of-order execution based vector register write back method as claimed in claim 8 when executed by a processor.

Images