Offline algorithm core chip computing power scheduling method, system and storage medium

Abstract

This application relates to the technical field of data processing, and discloses a chip computing power scheduling method, system, and storage medium for an offline algorithm body. The method obtains the main body of data to be computed and available computing power. A first algorithm calculates the total data processing volume, and a second algorithm calculates the data processing time based on the available computing power. If the total processing volume exceeds a reference total volume or the processing time exceeds a reference time, a data splitting processing instruction is generated. In response to the instruction, a schedulable chip is obtained, and its combined computing power is calculated. The data is split into two parts according to the available computing power and the combined computing power, and processed separately to obtain two outputs. The correspondence between the two outputs is verified; if successful, they are merged into the main output, and the schedulable chip is released. This application enables flexible scheduling of chip computing power in offline scenarios, improves data processing efficiency, and ensures the accuracy of processing results.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a chip computing power scheduling method, system and storage medium for an offline algorithm. Background Technology

[0002] The vehicle control system for new energy vehicles is undergoing architectural innovation, with decoupling the controller and actuator becoming a core development trend. Traditional integrated vehicle control architectures, due to the hard binding of the controller and actuator, require simultaneous hardware replacement for functional upgrades, resulting in high adaptation costs and difficulty in compatibility with different powertrain configurations. Decoupling design, through standardized interfaces, enables modular development of the controller and flexible matching of the actuator. This allows for rapid response to vehicle model iteration needs, reduces maintenance costs, and improves system reconfigurability, making it a key direction for supporting the intelligent and integrated upgrade of vehicle control systems.

[0003] To achieve high-precision dynamic control of vehicles, the vehicle control system has constructed an integrated technical system comprising a motion controller, a power controller, and an artificial intelligence algorithm architecture. The motion controller is responsible for attitude and trajectory correction, while the power controller precisely regulates motor power and energy distribution. Combined with advanced algorithm architectures such as model prediction and AI environmental perception and decision-making modules, the three work together to achieve real-time linkage between steering, braking, and power, effectively optimizing handling stability and energy efficiency, and enhancing adaptability to intelligent driving scenarios.

[0004] The efficient operation of the aforementioned technical system relies on a multi-module collaborative control algorithm after training. This algorithm needs to process multi-dimensional data such as environmental perception, vehicle status, and actuator feedback in parallel, resulting in a continuous increase in computational complexity. However, existing vehicle control chips are limited by power consumption, size, and cost, and their computing power density and parallel processing capabilities cannot meet the real-time operation requirements of the algorithm, which can easily lead to risks such as control delays and decision lags. Summary of the Invention

[0005] To optimize computing power allocation and task scheduling and compensate for the shortcomings of chip computing power, this application provides a chip computing power scheduling method, system and storage medium for offline algorithm subjects.

[0006] Firstly, this application provides a chip computing power scheduling method for an offline algorithm, employing the following technical solution:

[0007] A chip computing power scheduling method for an offline algorithm body includes the following steps:

[0008] Obtain the main data to be computed and the available computing power;

[0009] The total amount of data to be processed is calculated using a first algorithm based on the data subject, and the data processing time is calculated using a second algorithm based on the total amount of data to be processed and the available computing power.

[0010] If the total amount of data to be processed is greater than a preset reference total amount or the data processing time is greater than a preset reference time, then a data split processing instruction is generated.

[0011] In response to the data splitting processing instruction, a schedulable chip is acquired, and the combined computing power of the schedulable chip is calculated; the data body is divided into a first data segment and a second data segment based on the available computing power and the combined computing power.

[0012] The first sub-data is processed based on the available computing power to obtain a first output, and the second sub-data is processed based on the joint computing power to obtain a second output;

[0013] Verify the correspondence between the first output and the second output;

[0014] If the verification passes, the first output and the second output are merged into the main output, and the schedulable chip is released.

[0015] By adopting the above technical solution, the system obtains the main data to be calculated and the available computing power, calculates the total data processing volume using the first algorithm, and calculates the data processing time using the second algorithm, thus enabling the prediction of the computing workload and time consumption. When the total data processing volume exceeds the preset reference total volume or the processing time exceeds the preset reference time, a data splitting processing instruction is generated and a schedulable chip is invoked. By calculating the joint computing power, the main data is divided into the first sub-data and the second sub-data. The available computing power and the joint computing power are used for parallel processing, effectively breaking through the single-chip computing power bottleneck, significantly improving data processing efficiency, and helping to alleviate the latency problem caused by insufficient computing power in the collaborative control algorithm. By verifying the correspondence between the first output and the second output, the consistency and accuracy of the sub-data processing are ensured, and the merged main output meets the accuracy requirements of the vehicle control system. After processing, the schedulable chip is released, improving the reuse rate of computing power resources, balancing processing efficiency and cost control, and adapting to the intelligent needs of the new energy vehicle control terminal.

[0016] Optionally, the step of calculating the total amount of data to be processed using the first algorithm based on the data subject further includes the following sub-steps:

[0017] Obtain the data size information of the data body;

[0018] Based on the data subject, a processing subject is matched from a preset algorithm library, and the corresponding processing step information is retrieved based on the processing subject;

[0019] The mapping components are matched from the preset first mapping library based on the data size information;

[0020] The mapping multiple is matched from the preset second mapping library according to the processing step information;

[0021] The total amount of data processed is calculated based on the mapping components and the mapping multiple.

[0022] By adopting the above technical solution, combining the information of the processing subject and processing steps with the preset algorithm library, and then using the preset first mapping library to match the mapping components and the preset second mapping library to match the mapping multiples to calculate the total amount of data processing, the data characteristics and processing requirements are correlated.

[0023] Optionally, the step of calculating the data processing time using the second algorithm based on the total amount of data to be processed and the available computing power further includes the following sub-steps:

[0024] The computing power is calculated based on the available computing power and the preset computing power loss.

[0025] The computation time is calculated based on the total amount of data processed and the computing power.

[0026] The data processing time is calculated based on the calculation time and the preset priority occupancy ratio.

[0027] By adopting the above technical solutions, the available computing power is corrected by calculating computing power loss, resulting in computing power that is more in line with the actual computing scenario; the computing time is adjusted by combining the priority occupancy ratio, so that the data processing time assessment is more adapted to the actual load state of the chip.

[0028] Optionally, the judgment condition for generating the data split processing instruction may also include the following:

[0029] The total value is calculated based on the total amount of data processed and the reference total amount.

[0030] The time correspondence value is calculated based on the data processing time and the reference time;

[0031] The processing value is calculated based on the total value and the time value.

[0032] If the processing value is greater than the preset reference value, then the data splitting processing instruction is generated.

[0033] By adopting the above technical solution, the judgment logic calculates and processes the corresponding value by comprehensively considering the total amount and the corresponding value of time, which reduces the pass rate of single condition judgment and improves the applicability of generating data split processing instructions.

[0034] Optionally, the step of acquiring schedulable chips in response to the data splitting processing instruction and calculating the joint computing power of the schedulable chips further includes the following sub-steps:

[0035] Based on the data splitting processing instructions, a bypass chip is searched to establish a connection;

[0036] Perform a computing power scheduling handshake with the bypass chip;

[0037] If the computing power scheduling handshake is successful, the bypass chip will be marked as the schedulable chip.

[0038] Send the preset schedulable command to the schedulable chip;

[0039] Obtain the schedulable computing power returned by the schedulable chip in response to the schedulable instruction;

[0040] The combined computing power is calculated based on the schedulable computing power of all the schedulable chips.

[0041] By adopting the above technical solution, the connected bypass chips are searched in a targeted manner, and the scheduling efficiency can be effectively improved based on the computing power scheduling handshake mechanism; then the joint computing power is calculated by combining the schedulable computing power of each schedulable chip.

[0042] Optionally, the step of dividing the data body into a first data segment and a second data segment based on the available computing power and the combined computing power further includes the following sub-steps:

[0043] The same type of data to be processed in the data body is divided into a first data segment and a second data segment. The comparison relationship between the first data segment and the second data segment corresponds to the comparison relationship between the available computing power and the joint computing power.

[0044] Calculate the comparison relationship between the schedulable computing power, and distribute the second data to the corresponding schedulable chip according to the comparison relationship between the schedulable computing power.

[0045] By adopting the above technical solution, data of the same type is segmented, and computing power is matched with data volume to achieve comprehensive utilization of computing resources. The second part of the data is distributed according to the schedulable computing power, which can balance the computing load of each schedulable chip.

[0046] Optionally, the step of verifying the correspondence between the first output and the second output further includes the following sub-steps:

[0047] Randomly select first verification data from the first data segment and send it to one of the schedulable chips;

[0048] Upon receiving the first verification data, the schedulable chip randomly selects second verification data from the acquired second sub-data and returns it.

[0049] The first verification result is calculated based on the second verification data, and the schedulable chip calculates the second verification result based on the first verification data;

[0050] Perform consistency verification between the first verification result and the second verification result;

[0051] If the consistency verification passes, then the correspondence between the first output and the second output is verified.

[0052] By adopting the above technical solution, bidirectional random selection of verification data and carrying out consistency verification can effectively ensure the matching accuracy of the first and second outputs after split processing, avoid the result deviation problem caused by data segmentation, and the bidirectional cross-validation mode is conducive to ensuring the reliability of the calculation results.

[0053] Optionally, the step of releasing the schedulable chip further includes the following sub-steps:

[0054] Send a schedulable interrupt flag to the schedulable chip;

[0055] Based on the interrupt set response of the schedulable interrupt identifier returned by the schedulable chip, the computing power scheduling handshake with the schedulable chip is disconnected.

[0056] By adopting the above technical solution, interruption identification interaction and response confirmation are realized, avoiding the problem of additional resource occupation caused by residual computing power scheduling connections; and enabling schedulable chips to return to the waiting-to-schedule state in a timely manner, which is conducive to the initiation of subsequent computing power scheduling tasks.

[0057] Secondly, this application provides an offline algorithm core chip computing power scheduling system, which adopts the following technical solution:

[0058] A chip computing power scheduling system for an offline algorithm entity includes a processor, wherein the processor executes the steps of the chip computing power scheduling method for an offline algorithm entity as described in any one of the preceding claims.

[0059] Thirdly, this application provides a storage medium, which adopts the following technical solution:

[0060] A storage medium storing a program, wherein when the program is executed by a processor, the program implements the steps of the chip computing power scheduling method for the offline algorithm body described in any one of the above claims.

[0061] In summary, this application includes at least one of the following beneficial technical effects: By predicting the computational workload and time consumption, and combining a split processing mechanism to overcome the single-chip computing power bottleneck, it significantly improves data processing efficiency, effectively alleviates latency issues caused by insufficient computing power, and adapts to the needs of high real-time scenarios. It constructs a collaborative mechanism for data segmentation and joint computing power scheduling to achieve dynamic adaptation and load balancing of computing resources, improve resource reuse, and balance processing efficiency and cost control. It adopts a bidirectional cross-validation mode to ensure the consistency and accuracy of the data processing results, avoids deviations that may occur during segmentation processing, and ensures that the output results meet the requirements of high-precision application scenarios. It establishes a standardized chip scheduling and release process, and improves the reliability and flexibility of computing power scheduling through handshake interaction and interrupt response mechanisms, providing stable and efficient computing power support for offline algorithm components. Attached Figure Description

[0062] Figure 1 This is a flowchart illustrating the steps of a chip computing power scheduling method based on an offline algorithm.

[0063] Figure 2 This is a flowchart illustrating the steps of calculating the total amount of data to be processed using the first algorithm based on the data subject.

[0064] Figure 3 This is a flowchart illustrating the steps of calculating the data processing time using a second algorithm based on the total amount of data to be processed and the available computing power. Detailed Implementation

[0065] The embodiments of this application are described in detail below, and examples of the embodiments are shown in the accompanying drawings.

[0066] In the description of this specification, the references to "certain embodiments," "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples" refer to specific features, structures, materials, or characteristics described in connection with the described embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0067] This application discloses a chip computing power scheduling method for an offline algorithm, referring to... Figure 1 It includes the following steps:

[0068] Before the offline algorithm body starts the data processing task, the data body to be calculated is obtained through the sensor data acquisition module or storage data call interface preset on the vehicle control terminal. The data body can be vehicle condition monitoring data, battery management data or autonomous driving decision-related data generated during the operation of new energy vehicles. At the same time, the available computing power of the main chip is read in real time through the chip computing power monitoring unit. Available computing power refers to the computing power resources of the main chip that can be used for the current data processing task after excluding its own basic operation consumption. Its value is obtained through the computing power monitoring API provided by the chip manufacturer or a custom computing power statistical algorithm to ensure the accuracy and timeliness of the data body and available computing power information.

[0069] After obtaining the main data set and available computing power, the process proceeds to the data processing volume calculation stage. This stage uses the first algorithm to accurately assess the total amount of data processing tasks. The specific process is detailed below. Figure 2 The data parsing module extracts the data size information of the data subject, including quantifiable basic characteristic parameters such as data file size, data dimension, and number of data records. Based on the type of data subject, such as vehicle condition monitoring data or battery management data, the corresponding processing subject is matched from a preset algorithm library. The algorithm library pre-stores standard processing algorithm frameworks corresponding to different types of data. For example, the SOC (State of Charge) calculation algorithm framework for battery management data. Through the matched processing subject, the processing step information under the algorithm framework is further queried. The processing step information includes specific operation steps such as data preprocessing, feature extraction, model calculation, and result output, as well as the resource consumption coefficient of each step.

[0070] Based on the extracted data size information, corresponding mapping components are matched from a pre-set first mapping library. The first mapping library establishes a correspondence table between data size parameters and mapping components. For example, when the number of data records is 1000, the corresponding mapping component is 0.8, and when the data file size is 10MB, the corresponding mapping component is 1.2. The values ​​of the mapping components are obtained by fitting a large amount of experimental data and can reflect the degree of influence of data size on the total processing volume. At the same time, based on the queried processing step information, corresponding mapping multiples are matched from a pre-set second mapping library. The second mapping library stores the correlation between different combinations of processing steps and mapping multiples. For example, processing steps that include data preprocessing and model calculation correspond to a mapping multiple of 1.5, and processing steps that include feature extraction correspond to a mapping multiple increase of 0.3. The mapping multiple can reflect the influence of processing complexity on the total processing volume.

[0071] The total data processing volume is calculated using the preset formula: Total data processing volume = Mapping component × Mapping multiple × Data base coefficient, where the data base coefficient is a fixed parameter set according to the data type. For example, the base coefficient for battery management data is 1.0, and the base coefficient for vehicle condition monitoring data is 0.9. This value can quantitatively reflect the total amount of computation required to complete the processing of the current main data, thus achieving a precise correlation between data characteristics and processing requirements.

[0072] After calculating the total amount of data to be processed, the data processing time is calculated using a second algorithm based on the total amount of data to be processed and the available computing power obtained in the early stages. The specific process is as follows: Figure 3 Considering the computing power loss that occurs during actual chip operation, such as the decrease in computing power due to insufficient heat dissipation and the resource contention loss during multi-task parallelism, a preset computing power loss parameter is introduced. The computing power loss parameter is dynamically adjusted according to factors such as chip model, operating environment temperature, and current load rate. For example, the computing power loss parameter is 0.15 when the ambient temperature is 40℃ and 0.2 when the load rate is 80%. The actual computing power available for data processing is calculated using the formula: Computing power = Available computing power × (1 - Computing power loss parameter). This value is closer to the actual computing scenario of the chip than the available computing power, avoiding time evaluation deviations caused by ignoring losses.

[0073] Based on the fundamental relationship between computing power and time, the theoretical computing time is initially calculated using the formula: Computation Time = Total Data Processing ÷ Computing Power. Considering that the chip may simultaneously handle other higher-priority tasks, such as emergency braking signal processing in vehicle control, a preset priority occupancy ratio is introduced. The priority occupancy ratio refers to the maximum proportion of computing power that the current task can occupy. For example, a priority occupancy ratio of 0.7 corresponds to a normal data processing task, and a priority occupancy ratio of 0.9 corresponds to an important task. Using the formula: Data Processing Time = Computation Time ÷ Priority Occupancy Ratio, the final data processing time is calculated. This time value comprehensively considers computing power consumption and task priority, and can more accurately reflect the processing time under the actual load of the chip.

[0074] After obtaining the total data processing volume and processing time, the process enters the split processing instruction generation stage. A comprehensive judgment based on multiple conditions determines whether to initiate split data processing. The calculated total data processing volume is compared with a preset reference volume, which is set according to the chip's maximum stable processing capacity. For example, if the main chip's maximum daily processing volume is 10,000 units, the reference volume is set to 8,000 units, reserving a 20% redundancy. Simultaneously, the data processing time is compared with a preset reference time, which is set according to the real-time requirements of the vehicle control terminal for data processing. For example, the reference processing time for vehicle condition monitoring data is 5 seconds, and the reference processing time for battery management data is 8 seconds.

[0075] If the total data processing volume exceeds the reference total volume, or the data processing time exceeds the reference time, the possibility of split processing is initially triggered. To further enhance the rationality of the judgment, the calculation logic of the total volume corresponding value, time corresponding value, and processing corresponding value is introduced: The total volume corresponding value is calculated using the formula: Total volume corresponding value = Total data processing volume ÷ Reference total volume. This value reflects the proportion by which the total processing volume exceeds the reference value. For example, when the total data processing volume is 9000 units and the reference total volume is 8000 units, the total volume corresponding value is 1.125. The time corresponding value is calculated using the formula: Time corresponding value = Data processing time ÷ Reference time. For example, if the data processing time is 6 seconds and the reference time is... At 5 seconds, the corresponding time value is 1.2. Subsequently, the corresponding processing value is calculated using the formula: Processing value = (Total corresponding value × 0.6 + Time corresponding value × 0.4). Here, 0.6 and 0.4 are the weighting coefficients for the total amount and time, respectively, which can be adjusted according to actual needs. If the processing value is greater than the preset reference value, such as 1.1, a data splitting processing instruction is officially generated. This judgment logic reduces the one-sidedness of single-condition judgment by comprehensively considering multiple parameters, improves the applicability of instruction generation, avoids unnecessary splitting processing due to occasional total amount or time exceeding the limit, and ensures timely scheduling when computing power expansion is indeed needed.

[0076] In response to the generated data split processing command, the system enters the schedulable chip acquisition and joint computing power calculation stage to realize the call and integration of external computing power resources. Based on the data split processing command, the chip communication module of the vehicle control terminal searches for bypass chips that have established physical or wireless communication connections. Bypass chips can be idle auxiliary chips in the vehicle control system, auxiliary chips in other ECUs (Electronic Control Units), or external chips temporarily connected through the vehicle network. The search scope is limited to a list of chips that have completed security certification to ensure the security of computing power scheduling.

[0077] The main chip initiates a power scheduling handshake with each of the found bypass chips. The specific process is as follows: the main chip sends a handshake request signal to each bypass chip, containing information such as the type of the current task, the required computing power range, and the data transmission protocol. Upon receiving the request signal, if the bypass chip is currently idle and its computing power meets the basic requirements, it returns a handshake response signal, containing information such as the chip model, a preliminary estimate of the currently schedulable computing power, and the communication encryption key. If the power scheduling handshake is successful, i.e., the main chip receives a valid response signal within a preset time, it marks the bypass chip as a schedulable chip and stores its basic information. If the handshake fails, such as due to timeout or insufficient computing power, the bypass chip is excluded, and the search continues for other candidate chips.

[0078] After a successful handshake, the main chip sends preset schedulable instructions to each schedulable chip. These instructions include detailed computing power call parameters, such as call duration, computing power allocation ratio, and data interaction interface address. Upon receiving the instructions, each schedulable chip uses its own computing power detection module to accurately calculate the available schedulable computing power for collaborative processing and returns this value to the main chip. The main chip collects the schedulable computing power of all schedulable chips and calculates the combined computing power using the formula: Combined Computing Power = Σ (Schedulable Computing Power of Each Schedulable Chip × Computing Power Coordination Coefficient). The computational power coordination coefficient is set based on the communication latency between chips; the coefficient is 1.0 when the latency is less than 10ms and 0.9 when the latency is between 10-20ms. This value reflects the total effective computing power during multi-chip collaborative processing and provides a basis for subsequent data segmentation.

[0079] Based on the available computing power (main chip computing power) obtained in the early stage and the calculated joint computing power (total computing power of schedulable chips), the main body of data is divided into the first part of the data and the second part of the data, so as to achieve precise matching between computing power and data volume. The data to be processed in the main data body is classified by type. For example, voltage data, current data, and temperature data in battery management data are classified separately to ensure that the segmented objects are data of the same type to be processed, and to avoid the confusion of processing logic caused by the mixed segmentation of different types of data. According to the ratio of available computing power to joint computing power, the quantity comparison relationship between the first data segment and the second data segment is determined. For example, when the available computing power is 500 units and the joint computing power is 1000 units, the ratio of the two is 1:2. Then the quantity ratio of the first data segment and the second data segment is also set to 1:2. Through data segmentation algorithms, such as uniform segmentation based on the number of data records or equal segmentation based on the size of data blocks, the same type of data is divided into the corresponding first data segment (assigned to the main chip for processing) and second data segment (assigned to the schedulable chip for processing), ensuring that the computing power resources of the main chip and the schedulable chip are fully utilized and avoiding the situation where the computing power of one party is idle or overloaded.

[0080] Meanwhile, considering the differences in schedulable computing power among the schedulable chips, such as chip A having a schedulable computing power of 600 units and chip B having a schedulable computing power of 400 units, the comparison relationship between the schedulable computing power of each schedulable chip is calculated. The ratio of chip A to chip B is 3:2. Based on this ratio, the second part of the data is further distributed to the corresponding schedulable chips. For example, when the total amount of the second part of the data is 1000 records, 600 records are allocated to chip A and 400 records are allocated to chip B. This achieves a balanced computing load among the schedulable chips, avoids processing delays on some chips due to uneven data distribution, and further improves collaborative processing efficiency.

[0081] After data segmentation is completed, the data enters the parallel processing stage: the main chip processes the first data segment according to the preset processing flow based on its available computing power, and performs data cleaning, algorithm calculation, result temporary storage and other operations in sequence to finally obtain the first output; each schedulable chip processes the allocated second data segment or sub-parts of the second data segment synchronously based on its own schedulable computing power, and the processing flow is consistent with that of the main chip. After processing, the results are summarized to the main chip to form the second output.

[0082] To ensure consistency between the first and second outputs after separate processing and to avoid result deviations during data segmentation or computing power collaboration, the correspondence between the two needs to be verified. Specifically, firstly, a portion of the data from the first data segment processed by the main chip is selected as the first verification data using a random number generation algorithm, such as selecting 10% of the first data segment, covering different data time periods or different feature dimensions, and this data is sent to any schedulable chip. The schedulable chip that receives the first verification data then selects a portion of the data from its own processed second data segment as the second verification data using the same random number generation algorithm, and returns this data to the main chip.

[0083] The main chip calculates the first verification result based on the second verification data using the same algorithm logic as the data processing. Simultaneously, the schedulable chip calculates the second verification result based on the received first verification data using the same algorithm logic. The main chip performs consistency verification between the first and second verification results. Verification methods include numerical error comparison (if the error is less than 0.5%, it is considered consistent) and trend consistency analysis (if the data change trends are the same, it is considered consistent). If the consistency verification passes, such as when more than 95% of the verification data are consistent with the results, the correspondence between the first and second outputs is verified to be successful, ensuring the accuracy of the split processing results. If the verification fails, a reprocessing mechanism is triggered, such as re-segmenting the data or re-calling the schedulable chip, until the verification passes.

[0084] Once the correspondence between the first and second outputs is verified, the main chip initiates the result merging process: First, the data formats of the first and second outputs are unified, such as adjusting the numerical precision of outputs from different chips to be consistent and converting the data storage format to a standard format. Then, based on the identification information during data segmentation, such as data record ID and timestamp, the corresponding parts of the first and second outputs are concatenated. For example, the voltage calculation results of the first data segment and the voltage calculation results of the second data segment are merged in chronological order to form a complete main output. This main output can be directly used for decision execution in the vehicle control system, such as adjusting the charging strategy based on the merged battery management data to meet the accuracy requirements of the vehicle control system.

[0085] After the results are merged, the process enters the schedulable chip release phase to improve the reuse rate of computing resources. The main chip first sends a schedulable interrupt flag to each schedulable chip. This flag contains information such as task completion instructions and data transmission termination signals, informing the schedulable chips that the current collaborative task has ended. Upon receiving the interrupt flag, each schedulable chip completes cleanup operations such as clearing its processed data and deleting temporary files, and returns an interrupt set response to the main chip. This response signal includes chip status (e.g., ready to enter the waiting-to-schedule state) and resource release confirmation. After receiving interrupt set responses from all schedulable chips, the main chip disconnects the computing power scheduling handshake connection with each schedulable chip via the communication module, returning the schedulable chips to the waiting-to-schedule state. This allows for rapid mobilization when new computing power is needed, avoiding additional resource occupation caused by residual computing power scheduling connections, thus balancing processing efficiency and cost control.

[0086] In summary, this implementation method achieves flexible scheduling of chip computing power in offline scenarios through the above-mentioned solutions: it breaks through the bottleneck of single-chip computing power by using task prediction and split processing mechanisms, significantly improves data processing efficiency, and alleviates the latency problem caused by insufficient computing power in the vehicle control system; it improves the utilization rate of computing power resources through data segmentation and adaptation and load balancing strategies; it ensures the accuracy of processing results through bidirectional cross-validation; and it improves resource reuse rate through a standardized chip release process.

[0087] This application also discloses an offline algorithm subject chip computing power scheduling system, including a processor, wherein the processor executes the steps of the offline algorithm subject chip computing power scheduling method as described in any of the above embodiments.

[0088] This application also discloses a storage medium storing a program, which, when executed by a processor, implements the steps of the chip computing power scheduling method for the offline algorithm body described in any of the above-mentioned embodiments.

[0089] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A chip computing power scheduling method for an offline algorithm, characterized in that, Includes the following steps: Obtain the main data to be computed and the available computing power; The total amount of data to be processed is calculated using a first algorithm based on the data subject, and the data processing time is calculated using a second algorithm based on the total amount of data to be processed and the available computing power. If the total amount of data to be processed is greater than a preset reference total amount or the data processing time is greater than a preset reference time, then a data split processing instruction is generated. In response to the data splitting processing instruction, obtain schedulable chips and calculate the combined computing power of the schedulable chips; The data body is divided into a first data segment and a second data segment based on the available computing power and the combined computing power. The first sub-data is processed based on the available computing power to obtain a first output, and the second sub-data is processed based on the joint computing power to obtain a second output; Verify the correspondence between the first output and the second output; If the verification passes, the first output and the second output are merged into the main output, and the schedulable chip is released.

2. The chip computing power scheduling method for the offline algorithm body according to claim 1, characterized in that, The step of calculating the total amount of data to be processed using the first algorithm based on the data subject further includes the following sub-steps: Obtain the data size information of the data body; Based on the data subject, a processing subject is matched from a preset algorithm library, and the corresponding processing step information is retrieved based on the processing subject; The mapping components are matched from the preset first mapping library based on the data size information; The mapping multiple is matched from the preset second mapping library according to the processing step information; The total amount of data processed is calculated based on the mapping components and the mapping multiple.

3. The chip computing power scheduling method for the offline algorithm body according to claim 1, characterized in that, The step of calculating the data processing time using the second algorithm based on the total amount of data to be processed and the available computing power further includes the following sub-steps: The computing power is calculated based on the available computing power and the preset computing power loss. The computation time is calculated based on the total amount of data processed and the computing power. The data processing time is calculated based on the calculation time and the preset priority occupancy ratio.

4. The chip computing power scheduling method for the offline algorithm body according to claim 1, characterized in that, The conditions for generating data splitting processing instructions also include the following: The total value is calculated based on the total amount of data processed and the reference total amount. The time correspondence value is calculated based on the data processing time and the reference time; The processing value is calculated based on the total value and the time value. If the processing value is greater than the preset reference value, then the data splitting processing instruction is generated.

5. The chip computing power scheduling method for the offline algorithm body according to claim 1, characterized in that, The step of obtaining schedulable chips in response to the data splitting processing instruction and calculating the joint computing power of the schedulable chips further includes the following sub-steps: Based on the data splitting processing instructions, a bypass chip is searched to establish a connection; Perform a computing power scheduling handshake with the bypass chip; If the computing power scheduling handshake is successful, the bypass chip will be marked as the schedulable chip. Send the preset schedulable command to the schedulable chip; Obtain the schedulable computing power returned by the schedulable chip in response to the schedulable instruction; The combined computing power is calculated based on the schedulable computing power of all the schedulable chips.

6. The chip computing power scheduling method for the offline algorithm body according to claim 5, characterized in that, The step of dividing the data body into a first data segment and a second data segment based on the available computing power and the combined computing power further includes the following sub-steps: The same type of data to be processed in the data body is divided into a first data segment and a second data segment. The comparison relationship between the first data segment and the second data segment corresponds to the comparison relationship between the available computing power and the joint computing power. Calculate the comparison relationship between the schedulable computing power, and distribute the second data to the corresponding schedulable chip according to the comparison relationship between the schedulable computing power.

7. The chip computing power scheduling method for the offline algorithm body according to claim 1, characterized in that, The step of verifying the correspondence between the first output and the second output further includes the following sub-steps: Randomly select first verification data from the first data segment and send it to one of the schedulable chips; Upon receiving the first verification data, the schedulable chip randomly selects second verification data from the acquired second sub-data and returns it. The first verification result is calculated based on the second verification data, and the schedulable chip calculates the second verification result based on the first verification data; Perform consistency verification between the first verification result and the second verification result; If the consistency verification passes, then the correspondence between the first output and the second output is verified.

8. The chip computing power scheduling method for the offline algorithm body according to claim 1, characterized in that, The step of releasing the schedulable chip further includes the following sub-steps: Send a schedulable interrupt flag to the schedulable chip; Based on the interrupt set response of the schedulable interrupt identifier returned by the schedulable chip, the computing power scheduling handshake with the schedulable chip is disconnected.

9. A chip computing power scheduling system for an offline algorithm, characterized in that, Includes a processor, wherein the processor performs the steps of the chip computing power scheduling method of the offline algorithm body as described in any one of claims 1-8.

10. A storage medium, characterized in that, The storage medium stores a program, which, when executed by a processor, implements the steps of the chip computing power scheduling method for the offline algorithm body as described in any one of claims 1-8.

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