Data coding and decoding method, device and system

Abstract

The embodiment of the invention discloses a data coding and decoding method, device and system. The invention discloses a device and a system. A coding method comprises the following steps: acquiring a first bit sequence containing k bits; the first bit sequence is coded to obtain a code word containing n bits, the code word comprises p = n-k check bits, and the result of multiplying the code word by a check matrix H is 0; wherein the check matrix H is a binary matrix with m + 1 rows and n columns. The coding method can be used for high-speed transmission scenes such as 800Gbps, 1.6 Tbps and the like. Meanwhile, in combination with the characteristics of the four-level pulse amplitude modulation (PAM4), the complexity of FEC coding and decoding can be reduced.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a data encoding and decoding method, apparatus and system. Background Technology

[0002] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards higher capacity, packetization, and intelligence. Coherent optical communication systems utilize the amplitude, phase, polarization, and frequency of light waves to carry information. To combat optical signal distortion caused by dispersion, polarization-related impairments, noise, nonlinear effects, and other factors during transmission and to maintain long-distance transmission, coherent optical communication systems typically employ efficient forward error correction (FEC) codes to combat optical impairments during optical transmission, ensuring a sufficiently low bit error rate over long distances.

[0003] Hamming code is a complete code with a simple hard-decision decoding scheme. It can detect and correct error patterns caused by a single bit error and is widely used in practical systems. The codeword length of Hamming code is n = 2^n. m -1, information bit length k = 2 m -m-1, the parity bit length is m, where m is an integer greater than or equal to 3, also known as Hamming (2^m-1). m -1,2 m -m-1) code. For example, when m=7 and n=2 m -1 = 127, k = 2 m -m-1 = 120, i.e., Hamming (127, 120) code. To detect and correct error patterns with one bit error, and to detect error patterns with two bit errors, the Hamming (2...) code can be modified... m -1,2 m -m-1) code each contains 2 m Adding 1 bit parity to a 1-bit codeword yields the extended Hamming (2^35) codeword. m ,2 m -m-1) code. In practical system design, the code length is usually not 2. m q bits. At this point, a technique of shortening q information bits can be used to obtain a shortened q-bit extended Hamming (2^q) bit. m -q,2 m -m-1-q) codes. For poor channel quality, the receiver performs soft-decision decoding on the received codeword sequence. For high-speed applications, such as 800Gbps and 1.6Tbps, designing codes with low encoding and decoding complexity is a pressing issue. Summary of the Invention

[0004] This application provides a data encoding and decoding method, apparatus, and system, which have the advantages of low complexity and low power consumption, and can be used in transmission scenarios such as 800Gbps, 1.6Tbps, or even higher speeds.

[0005] In a first aspect, embodiments of this application provide an encoding method, comprising: obtaining a first bit sequence containing k bits; encoding the first bit sequence to obtain a codeword containing n bits, wherein the codeword includes p = nk parity bits, and the result of multiplying the codeword and the parity check matrix H is 0;

[0006] The check matrix H is an m+1 row n column binary matrix, p = m+1; H = [g(0), g(1), g(2), ..., g(i-1), g(i), ..., g(n-1)], whose i-th column contains m+1 bits. and Any one of them; where α is a primitive element of the finite field, α i For the finite field GF(2) m An element in the array is an m-bit column vector, where 0 ≤ i ≤ n-1, n < 2. m -2, m≥3, and i, m, p, k, n are all positive integers.

[0007] The encoding method proposed in this application can detect and correct one bit error, two bit errors, or even some three bit errors. It has low encoding and decoding complexity and can be used in transmission scenarios such as 800Gbps, 1.6Tbps, or even higher speeds.

[0008] In conjunction with the first aspect, in a first possible implementation of the first aspect, the finite field GF(2) m element α on ) i Represented as a column vector containing m bits or Where, α i =b 0,i ×α 0 +b 1,i ×α 1 +b 2,i ×α 2 +…+b (m-1),i ×α m-1 It should be understood that the g(i) function uses element-wise representation over a finite field, which is simpler to implement than traditional encoding schemes under the same performance conditions.

[0009] In conjunction with the first aspect and the first possible implementation of the first aspect, in the second possible implementation of the first aspect, m = 7, k = 60, p = 8, n = 68.

[0010] In conjunction with the second possible implementation of the first aspect, in the third possible implementation of the first aspect, the i-th column of the 8-row, 68-column verification matrix H is

[0011] or, or, or,

[0012] Where, α i =b 0,i +b 1,i ×α+b 2,i ×α 2 +b 3,i ×α 3 +b 4,i ×α 4 +b 5,i ×α 5 +b 6,i ×α 6 This application provides a representation of the g(i) function, which also utilizes elements over a finite field and gives α. i Specifically, compared with traditional encoding schemes, it is simpler to implement under the same performance conditions.

[0013] In conjunction with the first aspect and the above-described possible implementations of the first aspect, in the fourth possible implementation of the first aspect, 1+α 3 +α 7 =0.

[0014] In conjunction with the first aspect and the above-described possible implementations of the first aspect, in a fifth possible implementation of the first aspect, the finite field GF(2) 7 ) is derived from the primitive polynomial p(x) = x 7 +x 3 +1 is generated, that is, the finite field GF(2) 7 The corresponding primitive polynomial is p(x) = x. 7 +x 3 +1. This application selects a suitable primitive polynomial p(x) and codeword length n, and systematizes the parity check matrix H without changing the column positions, which can make the designed FEC code have low encoding and decoding complexity and save power consumption.

[0015] In conjunction with the first aspect and the above-described possible implementations of the first aspect, in the sixth possible implementation of the first aspect, the verification matrix H is: H = [g(0), g(1), g(2), ..., g(66), g(67)].

[0016] In conjunction with the first aspect and the above-described possible implementations of the first aspect, in the seventh possible implementation of the first aspect, the specific values ​​of the element H(i0,j0) in the i0-th row and j0-th column of the verification matrix H are as follows:

[0017]

[0018]

[0019] This application provides a specific representation of the parity check matrix H, which is simpler to implement and less complex than traditional encoding schemes under the same performance conditions.

[0020] In conjunction with the first aspect and the above-described possible implementations of the first aspect, in the eighth possible implementation of the first aspect, obtaining a first bit sequence containing k bits specifically includes: obtaining a second bit sequence containing k1 bits, where k1 = 2 × k; XORing every two bits in the second bit sequence to obtain 1 bit, thus obtaining a first bit sequence containing k bits in total.

[0021] In conjunction with the first aspect and the above-described possible implementations of the first aspect, in a ninth possible implementation of the first aspect, the method further includes: outputting the second bit sequence of the k1 bits and the p parity bits. The encoding method provided in this application, compared with the traditional scheme of encoding k1 bits to obtain p parity bits, has lower implementation complexity and lower power consumption under PAM4 modulation.

[0022] Secondly, embodiments of this application provide a decoding method, including: obtaining a first sequence;

[0023] Based on the parity check matrix H and the first sequence, a corrector containing p bits is obtained; wherein, the parity check matrix H is a binary matrix of m+1 rows and n columns, p = m+1; H = [g(0), g(1), g(2), ..., g(i-1), g(i), ..., g(n-1)], and its i-th column containing m+1 bits is... and Any one of them; where α is the finite field GF(2 m The fundamental element of α i For the finite field GF(2) m An element in the array is an m-bit column vector, where 0 ≤ i ≤ n-1, n < 2.m -2, m≥3, and i, m, p, n are all positive integers; decode the first sequence according to the corrector.

[0024] The decoding method provided in this application uses a parity check matrix H for decoding, which allows for the use of simple logic circuits to calculate the corrector, error correction and error detection, thus reducing the complexity of error correction and error detection at the receiving end.

[0025] In conjunction with the second aspect, in a first possible implementation of the second aspect, the corrector is obtained by multiplying the check matrix H and the first sequence.

[0026] In conjunction with the second aspect and the above possible implementations, in a second possible implementation of the second aspect, the finite field GF(2) m element α on ) i Represented as a column vector containing m bits or Where, α i =b 0,i ×α 0 +b 1,i ×α 1 +b 2,i ×α 2 +…+b (m-1),i ×α m-1 It should be understood that the g(i) function uses element-wise representation over a finite field, which is simpler to implement than traditional encoding schemes under the same performance conditions.

[0027] In conjunction with the second aspect and the above possible implementation methods, in the third possible implementation method of the second aspect, m = 7, p = 8, n = 68.

[0028] In conjunction with the second aspect and the above possible implementations, in the fourth possible implementation of the second aspect, the i-th column of the 8-row, 68-column verification matrix H is...

[0029] or, or, or,

[0030] Where, α i =b 0,i +b 1,i ×α+b 2,i ×α 2 +b 3,i ×α 3 +b 4,i ×α 4 +b 5,i ×α 5 +b6,i ×α 6 This application provides a representation of the g(i) function, which also utilizes elements over a finite field and gives α. i Specifically, compared with traditional encoding schemes, it is simpler to implement under the same performance conditions.

[0031] In conjunction with the second aspect and the above-described possible implementations, in the fifth possible implementation of the second aspect, 1+α 3 +α 7 =0.

[0032] In conjunction with the second aspect and the above possible implementations, in the sixth possible implementation of the second aspect, the finite field GF(2) 7 The corresponding primitive polynomial is p(x) = x. 7 +x 3 +1. This application selects a suitable primitive polynomial p(x) and codeword length n, and systematizes the parity check matrix H without changing the column positions, which can make the designed FEC code have low encoding and decoding complexity and save power consumption.

[0033] In conjunction with the second aspect and the above-described possible implementations of the second aspect, in the seventh possible implementation of the second aspect, the verification matrix H is: H = [g(0), g(1), g(2), ..., g(66), g(67)].

[0034] In conjunction with the second aspect and the above possible implementations, in the eighth possible implementation of the second aspect, the specific values ​​of the element H(i0,j0) in the i0th row and j0th column of the verification matrix H are as follows:

[0035]

[0036]

[0037] This application provides a specific representation of the parity check matrix H, which is simpler to implement and less complex than traditional encoding schemes under the same performance conditions.

[0038] Thirdly, embodiments of this application provide an encoding apparatus, comprising: an acquisition unit for acquiring a first bit sequence containing k bits; and an encoding unit for encoding the first bit sequence to obtain a codeword containing n bits, wherein the codeword includes p = nk parity bits, and the result of multiplying the codeword and the parity check matrix H is 0;

[0039] The check matrix H is an m+1 row n column binary matrix, p = m+1; H = [g(0), g(1), g(2), ..., g(i-1), g(i), ..., g(n-1)], whose i-th column contains m+1 bits. and Any one of them; where α is a primitive element of the finite field, α i For the finite field GF(2) m An element in the array is an m-bit column vector, where 0 ≤ i ≤ n-1, n < 2. m -2, m≥3, and i, m, p, k, n are all positive integers.

[0040] The encoding method proposed in this application can detect and correct one bit error, two bit errors, or even some three bit errors. It has low encoding and decoding complexity and can be used in transmission scenarios such as 800Gbps, 1.6Tbps, or even higher speeds.

[0041] In conjunction with the third aspect, in the first possible implementation of the third aspect, the finite field GF(2) m element α on ) i Represented as a column vector containing m bits or Where, α i =b 0,i ×α 0 +b 1,i ×α 1 +b 2,i ×α 2 +…+b (m-1),i ×α m-1 It should be understood that the g(i) function uses element-wise representation over a finite field, which is simpler to implement than traditional encoding schemes under the same performance conditions.

[0042] In conjunction with the third aspect and the possible implementations of the third aspect described above, in the second possible implementation of the third aspect, m = 7, k = 60, p = 8, and n = 68.

[0043] In conjunction with the third aspect and the possible implementations described above, in the third possible implementation of the third aspect, the i-th column of the 8-row, 68-column verification matrix H is...

[0044] or, or, or,

[0045] Where, α i =b 0,i+b 1,i ×α+b 2,i ×α 2 +b 3,i ×α 3 +b 4,i ×α 4 +b 5,i ×α 5 +b 6,i ×α 6 This application provides a representation of the g(i) function, which also utilizes elements over a finite field and gives α. i Specifically, compared with traditional encoding schemes, it is simpler to implement under the same performance conditions.

[0046] In conjunction with the third aspect and the possible implementations described above, in the fourth possible implementation of the third aspect, 1+α 3 +α 7 =0.

[0047] In conjunction with the third aspect and the possible implementations described above, in the fifth possible implementation of the third aspect, the finite field GF(2) 7 The corresponding primitive polynomial is p(x) = x. 7 +x 3 +1. This application selects a suitable primitive polynomial p(x) and codeword length n, and systematizes the parity check matrix H without changing the column positions, which can make the designed FEC code have low encoding and decoding complexity and save power consumption.

[0048] In conjunction with the third aspect and the above-described possible implementations of the third aspect, in the sixth possible implementation of the third aspect, the verification matrix H is: H = [g(0), g(1), g(2), ..., g(66), g(67)].

[0049] In conjunction with the third aspect and the possible implementations described above, in the seventh possible implementation of the third aspect, the specific values ​​of the element H(i0,j0) in the i0th row and j0th column of the verification matrix H are as follows:

[0050]

[0051]

[0052]

[0053] This application provides a specific representation of the parity check matrix H, which is simpler to implement and less complex than traditional encoding schemes under the same performance conditions.

[0054] In conjunction with the third aspect and the above-described possible implementations of the third aspect, in the eighth possible implementation of the third aspect, obtaining a first bit sequence containing k bits specifically includes: obtaining a second bit sequence containing k1 bits, where k1 = 2 × k; XORing every two bits in the second bit sequence to obtain 1 bit, thus obtaining a first bit sequence containing k bits in total.

[0055] In conjunction with the third aspect and the above-described possible implementations of the third aspect, in a ninth possible implementation of the third aspect, the method further includes: outputting the second bit sequence of the k1 bits and the p parity bits. The encoding method provided in this application, compared with the traditional scheme of encoding k1 bits to obtain p parity bits, has lower implementation complexity and lower power consumption under PAM4 modulation.

[0056] Fourthly, embodiments of this application provide a decoding apparatus, including: an acquisition unit, configured to acquire a first sequence;

[0057] The decoding unit is used to obtain a corrector containing p bits based on the parity check matrix H and the first sequence; wherein the parity check matrix H is an m+1 row n column binary matrix, p=m+1; H=[g(0),g(1),g(2),…,g(i-1),g(i),…,g(n-1)], and its i-th column containing m+1 bits is... and Any one of them; where α is a primitive element of the finite field, α i For the finite field GF(2) m An element in the array is an m-bit column vector, where 0 ≤ i ≤ n-1, n < 2. m -2, m≥3, and i, m, p, n are all positive integers; the decoding unit is further configured to decode the first sequence according to the corrector.

[0058] The decoding method provided in this application uses a parity check matrix H for decoding, which allows for the use of simple logic circuits to calculate the corrector, error correction and error detection, thus reducing the complexity of error correction and error detection at the receiving end.

[0059] In conjunction with the fourth aspect, in a first possible implementation of this application, the corrector is obtained by multiplying the check matrix H and the first sequence.

[0060] In conjunction with the fourth aspect and the possible implementations described above, in a second possible implementation of this application, the finite field GF(2) m element α on ) i Represented as a column vector containing m bits or Where, α i =b 0,i ×α 0 +b 1,i ×α 1 +b 2,i ×α 2 +…+b (m-1),i ×α m-1 It should be understood that the g(i) function uses element-wise representation over a finite field, which is simpler to implement than traditional encoding schemes under the same performance conditions.

[0061] In conjunction with the fourth aspect and the possible implementations described above, in the third possible implementation of this application, m = 7, p = 8, and n = 68.

[0062] In conjunction with the fourth aspect and the possible implementations described above, in the fourth possible implementation of this application, the i-th column of the 8-row, 68-column verification matrix H is

[0063] or, or, or,

[0064] Where, α i =b 0,i +b 1,i ×α+b 2,i ×α 2 +b 3,i ×α 3 +b 4,i ×α 4 +b 5,i ×α 5 +b 6,i ×α 6 This application provides a representation of the g(i) function, which also utilizes elements over a finite field and gives α. i Specifically, compared with traditional encoding schemes, it is simpler to implement under the same performance conditions.

[0065] In conjunction with the fourth aspect and the possible implementations described above, in a fifth possible implementation of this application, 1+α 3 +α 7 =0.

[0066] In conjunction with the fourth aspect and the possible implementations described above, in the sixth possible implementation of this application, the finite field GF(2) 7 The corresponding primitive polynomial is p(x) = x. 7 +x 3+1. This application selects a suitable primitive polynomial p(x) and codeword length n, and systematizes the parity check matrix H without changing the column positions, which can make the designed FEC code have low encoding and decoding complexity and save power consumption.

[0067] In conjunction with the fourth aspect and the above possible implementations of the fourth aspect, in the seventh possible implementation of the fourth aspect, the verification matrix H is: H = [g(0), g(1), g(2), ..., g(66), g(67)].

[0068] In conjunction with the fourth aspect and the possible implementations described above, in the eighth possible implementation of this application, the specific values ​​of the element H(i0,j0) in the i0th row and j0th column of the verification matrix H are as follows:

[0069]

[0070]

[0071] This application provides a specific representation of the parity check matrix H, which is simpler to implement and less complex than traditional encoding schemes under the same performance conditions.

[0072] Fifthly, embodiments of this application provide a chip for performing the methods described in any of the first or second aspects.

[0073] Sixthly, embodiments of this application provide an optical module. The optical module includes a processor and an interface. The processor is used to execute the methods described in any of the first or second aspects and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0074] In a seventh aspect, embodiments of this application provide a communication device. The communication device includes a host-side device and an optical module as described in any embodiment of the sixth aspect, the optical module being connected to the host-side device.

[0075] Eighthly, embodiments of this application provide another device. This device includes a processor and an interface. The processor is used to perform the methods described in any of the embodiments of the first or second aspect, and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor. The device may be a router, switch, server, or optical transport network equipment, etc.

[0076] Ninthly, embodiments of this application provide a communication system including a first communication device and a second communication device, wherein at least one of the first communication device and the second communication device is a communication device as described in any embodiment of the seventh aspect, and the first communication device and the second communication device are connected.

[0077] In a tenth aspect, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in any of the embodiments of the first or second aspect to be implemented.

[0078] In the eleventh aspect, this application provides a computer program product including program instructions that, when executed, implement the method described in any of the embodiments of the first or second aspect above. Attached Figure Description

[0079] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application;

[0080] Figure 2 for Figure 1 A schematic diagram of a data transmission process in the communication system shown.

[0081] Figure 3 This is a schematic diagram of another communication system used in an embodiment of this application;

[0082] Figure 4 (a) in the figure is a diagram of a verification matrix provided in this application;

[0083] Figure 4 (b) is a diagram of a systematic check matrix provided in this application;

[0084] Figure 4 (c) in the figure is a diagram of another verification matrix provided in this application;

[0085] Figure 4 (d) in the figure is a diagram of another type of check matrix provided in this application;

[0086] Figure 4 (e) in the figure is a diagram of another parity check matrix provided in this application;

[0087] Figure 5 A flowchart of a decoding method provided in this application;

[0088] Figure 6 A flowchart illustrating another decoding method provided in this application;

[0089] Figure 7A flowchart illustrating an encoding method provided in this application;

[0090] Figure 8 A schematic diagram of the structure of an encoding device provided in this application;

[0091] Figure 9 A schematic diagram of a decoding device provided in this application;

[0092] Figure 10 A schematic diagram of the structure of an optical module provided in this application;

[0093] Figure 11 This is a schematic diagram of the structure of a communication device provided in this application. Detailed Implementation

[0094] This application provides a coding and decoding method and apparatus with advantages such as low complexity and low power consumption, which can be used in high-speed transmission scenarios such as 800Gbps and 1.6Tbps. Furthermore, by combining the characteristics of Four-Level Pulse Amplitude Modulation (PAM4), a coding and decoding method with extremely low complexity is provided.

[0095] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be used interchangeably where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0096] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application. Figure 1As shown, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device at the transmitting end, and the receiving device 05 is also called a client device at the receiving end. The channel transmission medium 03 can be optical fiber. The client device is sometimes also called a host device. The client device includes a client chip and an interface. The client chip is also called a host chip. The connection interface between the transmitting device 01 and the transmitting processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can also be connected through an AUI. The transmitting processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be an LR optical module, such as a 1600LR module (a coherent optical module). Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04, and receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific support is not limited here.

[0097] Figure 2 for Figure 1 The diagram illustrates a data transmission process in the communication system shown. Figure 2 As shown, during the data transmission process from transmitting device 01 to receiving device 05, transmitting device 01 performs external code encoding on the data and then transmits the externally encoded data to transmitting processing module 02. Transmitting processing module 02 performs internal code encoding on the externally encoded data to obtain data with both external and internal code encoding, and transmits the externally and internally encoded data to channel transmission medium 03. Channel transmission medium 03 transmits the externally and internally encoded data to receiving processing module 04. Receiving processing module 04 performs internal code decoding on the externally and internally encoded data and transmits the internally decoded data to receiving device 05. Receiving device 05 performs external code decoding on the internally decoded data.

[0098] It should be understood that the distinction between "internal" in "internal code" and "external" in "external code" is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity operating on the internal code is closer to the channel transmission medium, while the entity operating on the external code is farther away. In this embodiment, after data is sent from the transmitting device 01, it is transmitted to the channel transmission medium 03 via the transmitting processing module 02, and then from the channel transmission medium 03 via the receiving processing module 04 to the receiving device 05. The data encoded by the transmitting device 01 is farther from the channel transmission medium 03 than the data encoded by the transmitting processing module 02, and the data decoded by the receiving device 05 is farther from the channel transmission medium 03 than the data decoded by the receiving processing module 04. Therefore, the data encoded by the transmitting device 01 is called data encoded with the external code, the data encoded by the transmitting processing module 02 is called data encoded with the internal code, the data decoded by the receiving device 05 is called data decoded with the external code, and the data decoded by the receiving processing module 04 is called data decoded with the internal code. In one possible implementation, both the internal and external code encoding described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Hamming code for internal code encoding. As another example, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Bose-Chaudhuri-Hocquenghem (BCH) code for internal code encoding. A BCH code correcting a single error is equivalent to a Hamming code.

[0099] Alternatively, there may be no internal or external code. The transmitting device 01 sends data to the transmitting processing module 02; the transmitting processing module 02 encodes the received data to obtain encoded data and transmits the encoded data to the channel transmission medium 03. The channel transmission medium 03 transmits the encoded data to the receiving processing module 04; the receiving processing module 04 decodes the encoded data and transmits the decoded data to the receiving device 05; the receiving device 05 receives the decoded data.

[0100] Figure 3 This is a schematic diagram of another communication system used in an embodiment of this application. For example... Figure 3As shown, the communication system includes a transmitting device 01, a channel transmission medium 03, and a receiving device 05. The transmitting device 01 encodes the data (which may include external code encoding and internal code encoding, or only one type of encoding). The encoded data is sent to the transmission medium 03, and the receiving device 05 decodes the data received from the transmission medium 03. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client-side device or host-side device located at the transmitting end, and the receiving device 05 is also called a client-side chip located at the receiving end. The channel transmission medium 03 can be optical fiber. The client-side device includes a client-side chip and an interface. The client-side chip is also called a host-side chip. The transmitting device 01, the channel transmission medium 03, and the receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here. That is to say, Figure 3 The transmitting device 01 shown also integrates Figure 2 The function of the sending processing module 02 shown is as follows: Figure 3 The receiving device 05 shown also integrates Figure 2 The receiving end processing module 04 is shown to have the following functions. At this time, the transmitting end device 01 may also employ linear pluggable optics (LPO), co-packaged optics (CPO), or near packaged optics (NPO) technology.

[0101] It should also be noted that the above content is an exemplary description of the application scenarios of the data processing method provided in the embodiments of this application, and does not constitute a limitation on the application scenarios of the data processing method. As those skilled in the art know, as business needs change, the application scenarios can be adjusted according to the application needs, and the embodiments of this application do not list them one by one.

[0102] The encoding method provided in this application can be applied to, for example... Figure 2 The sending processing module 02 shown encodes the received data, and can also be applied to, for example... Figure 3 The transmitting device 01 shown encodes the data. Similarly, the corresponding decoding method can be applied to, for example... Figure 2 The receiving end processing module 04 shown decodes the received data and can also be applied to, for example, Figure 3The receiving device 05 shown decodes the data. The encoding method provided in this application is described below. For traditional Hamming codes, the minimum Hamming distance is 3, which can detect and correct error patterns involving a single bit error. The codeword length of the Hamming code is n = 2. m -1, information bit length k = 2 m -m-1, the parity bit length is m, where m is an integer greater than or equal to 3, also known as Hamming (2^m-1). m -1,2 m -n-1) code. For example, when m=7 and n=2 m -1 = 127, k = 2 m -m-1 = 120, i.e., Hamming (127, 120) code. To detect and correct error patterns with one bit error, and to detect error patterns with two bit errors, the Hamming (2...) code can be modified... m -1,2 m In the -m-1) code, each contains 2 m Add a 1-bit parity bit to each 1-bit codeword to obtain the extended Hamming (2^35) codeword. m ,2 m -m-1) code, which corresponds to a 2-row code containing m+1 rows. m The column parity-check matrix, also known as the parity-check matrix, is shown below:

[0103]

[0104] Among them, there are m rows 2 m A matrix with -1 columns For the traditional Han-Ming (2) m -1,2 m The parity check matrix corresponding to the -m-1) code, where 1…1 represents a set of 2... m -1 row vectors, each consisting of 1 bit. It is a column vector containing m bits, all of which are 0 bits.

[0105] It should be noted that the parity check matrix can also be represented as containing 2 m The binary matrix with m+1 rows and 1 column is equivalent to the transpose of the above parity check matrix. The elements in the parity check matrix can be adjusted accordingly, which will not be elaborated further in this application.

[0106] In practical system design, the code length is usually not 2. m q bits. At this point, a technique of shortening q information bits can be used to obtain a shortened extended Hamming (2^q bits). m -q,2 m -n-1-q) code, that is, delete the above The leftmost column q, where 0 <q<2m -m-1, and q is an integer. In practical applications, a systematic code is usually considered, which means that the parity check matrix needs to be systematized to obtain a systematic parity check matrix; typically, systematizing the parity check matrix requires swapping the positions of some columns in the parity check matrix. This swapping of column positions increases the decoding complexity.

[0107] This application proposes an FEC code that can detect and correct error patterns with one bit error and error patterns with two bit errors, and has the advantage of low encoding and decoding complexity.

[0108] Consider a function g that maps an integer i to a binary column vector containing m+1 bits, as shown below.

[0109]

[0110] Where α is the primitive element of the finite field (Galois Field), 0≤i≤2 m -2, where i is an integer, α i Let be an element of the finite field. Specifically, it includes 2. m A set of elements It is called a finite field, also known as a Galois field, denoted as GF(2). m ). α 0 It can also be simply represented as 1, α 1 It can also be simply denoted as α. Finite field GF(2 m ) element α i This can be represented by a column vector containing m bits, which is expressed as:

[0111]

[0112] At this time, α i =b 0,i ×α 0 +b 1,i ×α 1 +b 2,i ×α 2 +…+b (m-1),i ×α m-1 It can also be simply written as α i =b 0,i +b 1,i ×α+b 2,i ×α 2 +…+b (m-1),i ×α m-1 For ease of representation, the column vector containing m bits can also be written as (b 0,i ,b 1,i ,b2,i ,…,b (m-1),i At this time, there are

[0113]

[0114] Given a primitive polynomial p(x) of degree m over GF(2), the finite field GF(2) m ) element α i It can be represented as α 0 α 1 α 2 α 3 ..., α m-1 A linear combination, that is, α i =b 0,i ×α 0 +b 1,i ×α 1 +b 2,i ×α 2 +…+b (m-1),i ×α m-1 At this point, the finite field GF(2) can be obtained. m ) element α i =b 0,i ×α 0 +b 1,i ×α 1 +b 2,i ×α 2 +…+b (m-1),i ×α m-1 The corresponding column vector (b) 0,i ,b 1,i ,b 2,i ,…,b (m-1),i The specific value to be obtained is α. i With column vector (b) 0,i ,b 1,i ,b 2,i ,…,b (m-1),i The mapping relationship. For example, consider the primitive polynomial p(x) = x of degree m = 7. 7 +x 3 +1, finite field GF(2) m ) element α 7 =b 0,i +b 1,i ×α+b 2,i ×α 2 +b 3,i ×α 3 +b 4,i ×α 4 +b 5,i ×α 5 +b6,i ×α 6 =1+α 3 Therefore α 7 The corresponding column vector (b) 0,i＝7 ,b 1,i＝7 ,b 2,i＝7 ,b 3,i＝7 ,b 4,i＝7 ,b 5,i＝7 ,b 6,i＝7 ) = (1,0,0,1,0,0,0); For example, the finite field GF(2) = (1,0,0,1,0,0,0); 7 ) element α 8 =b 0,i +b 1,i ×α+b 2,i ×α 2 +b 3,i ×α 3 +b 4,i ×α 4 +b 5,i ×α 5 +b 6,i ×α 6 =α+α 4 Therefore α 8 The corresponding column vector (b) 0,i＝7 ,b 1,i＝7 ,b 2,i＝7 ,b 3,i＝7 ,b 4,i＝7 ,b 5,i＝7 ,b 6,i＝7 ) = (0,1,0,0,1,0,0).

[0115] For simplicity, element α i With column vector (b) 0,i ,b 1,i ,b 2,i ,…,b (m-1),i The mapping relationship between integer i and column vector (b) can also be considered as the mapping relationship between integer i and column vector (b). 0,i ,b 1,i ,b 2,i ,…,b (m-1),i The mapping relationship of ).

[0116] Different primitive polynomials p(x), element α i (or integer i) and column vector (b) 0,i ,b 1,i ,b 2,i ,…,b (m-1),i The mapping relationships are usually different. Below are several primitive polynomials p(x) of degree m = 7:

[0117] p(x) = x 7 +x 3+1

[0118] p(x)=x 7 +x+1

[0119] p(x)=x 7 +x 3 +x 2 +x+1

[0120] p(x)=x 7 +x 4 +1

[0121] p(x)=x 7 +x 4 +x 3 +x 2 +1

[0122] p(x)=x 7 +x 5 +x 2 +x+1

[0123] p(x)=x 7 +x 5 +x 3 +x+1

[0124] p(x)=x 7 +x 5 +x 4 +x 3 +1

[0125] p(x)=x 7 +x 5 +x 4 +x 3 +x 2 +x+1

[0126] p(x)=x 7 +x 6 +1

[0127] p(x)=x 7 +x 6 +x 3 +x+1

[0128] p(x)=x 7 +x 6 +x 4 +x+1

[0129] p(x)=x 7 +x 6 +x 4 +x 2 +1

[0130] p(x)=x 7+x 6 +x 5 +x 2 +1

[0131] p(x) = x 7 +x 6 +x 5 +x 3 +x 2 +x+1

[0132] p(x) = x 7 +x 6 +x 5 +x 4 +1

[0133] p(x) = x 7 +x 6 +x 5 +x 4 +x 2 +x+1

[0134] p(x) = x 7 +x 6 +x 5 +x 4 +x 3 +x 2 +1.

[0135] Typically, FEC codes are defined using a parity-check matrix, and a parity-check matrix H0 of size (m+1)×(n) (i.e., the parity-check matrix H in the claims) is represented as follows:

[0136] H0=[g(0),g(1),g(2),…,g(i-1),g(i),…,g(n-1)]

[0137] Among them, 7 <n<2 m -2, m is an integer greater than or equal to 3, and n is an integer. That is, the i-th column vector of the parity check matrix H0 is g(i). The parity check matrix H0 can also be expressed as:

[0138]

[0139] H contains m rows and n columns α for:

[0140] H α =[α 0 ,α 1 ,α 2 ,…,α i-1 ,α i- 2,…,α n-1 ]

[0141] The parity check matrix H0 is systematized to obtain a systematized parity check matrix.

[0142] H sys =[P;I m+1 ]

[0143] Among them, I m+1 Let P be an identity matrix of size (m+1)×(m+1), and let P be a matrix of size (m+1)×(nm-1). Its corresponding generator matrix is ​​as follows:

[0144] G = [I n-m-1 ;P T ]

[0145] Where P T I is the transpose of P. n-m-1 This represents an identity matrix of size (nm-1)×(nm-1).

[0146] It should be noted that this application selects a suitable primitive polynomial p(x) and codeword length n, and the systematization of the parity-check matrix H0 does not require column swapping, which can result in a lower encoding and decoding complexity for the designed FEC code. In this case, the leftmost nm-1 column of the matrix H0 is selected to obtain a matrix H of size (m+1)×(nn-1). left , is represented as:

[0147] H left =[g(0),g(1),g(2),…,g(nm-3),g(nm-2)]

[0148] Select the rightmost (n+1)th column of the matrix H0 to obtain a matrix H of size (m+1)×(m+1). right , is represented as:

[0149] H right =[g(nm-1),g(nm),…,g(n-1)]

[0150] have

[0151] P = B·H left =(H right ) -1 ·H left

[0152] =([g(nm-1),g(nm),…,g(n-1)]) -1 ·[g(0),g(1),g(2),…,g(nm-3),g(nm-2)]

[0153] in()-1 The symbol · represents the matrix inversion operation, and · represents the matrix multiplication operation. B = (H right ) -1 For matrix H right The inverse matrix.

[0154] It should be noted that the above P = B·H left It can be directly written as P = BH left The above G = [I n-m-1 ;P T It can also be written directly as G = [I] n-m-1 P T ] or G = [I n-m-1 ,P T ], representing matrix I n-m-1 Sum of matrix P T splicing.

[0155] It should be understood that the above-mentioned parity check matrix H0 is a binary matrix represented in the form of m+1 rows and n columns. It can also be transformed by simple methods, such as representing it as the transpose of the current binary matrix; in this case, the parity check matrix H0 can be represented as an n-row, m+1-column binary matrix.

[0156]

[0157] Here, the function g represents mapping an integer i to a binary row vector containing m+1 bits, for example, g(i) = [α i ,1], or g(i)=[1,α i ], or g(i) = [α n-1-i ,1], or g(i)=[1,α n-1-i ], where α i =b 0,i ×α 0 +b 1,i ×α 1 +b 2,i ×α 2 +…+b (m-1),i ×α m-1 α i A row vector containing m bits can also be denoted as (b 0,i ,b 1,i ,b 2,i ,…,b (m-1),i ), or (b (m-1),i ,b (m-2),i ,…,b 1,i ,b 0,i ).

[0158] Consider a systematic FEC code that encodes k0 information bits U to obtain p0 parity bits V. The information bits and parity bits form a codeword C of length n0 = i0 + p0. Here, consider n0 = 68, k0 = 60, and p0 = 8. Consider m = 7, and the primitive polynomial p(x) = x 7 +x 3 +1, α is the finite field GF(2 7 The fundamental element of ). At this time, there is α 7 +α 3 +1 = 0. Integer i (or element α) i ) and column vector (b 0, i,b 1,i ,b 2,i ,b 3,i ,b 4,i ,b 5,i ,b 6,i The mapping relationship is shown in Table 1 below. For example, for i = 0, we have α i =α 0 , its (b 0,i ,b 1,i ,b 2,i ,b 3,i ,b 4,i ,b 5,i ,b 6,i The specific value is taken from the parameter combination (1,0,0,0,0,0,0,0) in the row where i=0; for example, for i=7, we have α i =α 7 , its (b 0,i ,b 1,i ,b 2,i ,b 3,i ,b 4,i ,b 5,i ,b 6,i The specific value is taken from the parameter combination (1,0,0,1,0,0,0) in the row where i=7.

[0159] Table 1

[0160]

[0161]

[0162]

[0163]

[0164] The FEC code (n0 = 68, k0 = 60) corresponds to an 8×68 parity check matrix H0, which is represented as follows:

[0165]

[0166] Where 0 ≤ i ≤ 67,

[0167]

[0168] Column vector (b) 0,i ,b 1,i ,b 2,i ,b 3,i ,b 4,i ,b 5,i ,b 6,i ) corresponds to the finite field GF(2 7 ) element α i That is, α i For α 0 α 1 α 2 α 3 α 4 α 5 α 6 A linear combination, i.e., α i =b 0,i +b 1,i ×α+g 2,i ×α 2 +b 3,i ×α 3 +g 4,i ×α 4 +g 5,i ×α 5 +b 6,i ×α 6 Here, m = 7, and the primitive polynomial p(x) = x 7 +x 3 +1, α is the finite field GF(2 7 The fundamental element of ) has α 7 +α 3 +1 = 0. Integer i (or element α) i ) and column vector (b 0,i ,b 1,i ,b 2,i ,b 3,i ,b 4,i ,b 5,i ,b 6,i The mapping relationship can be referred to in Table 1. The specific values ​​of the element H0(i0,j0) in the i0th row and j0th column of the verification matrix H0 are shown in Table 2 below:

[0169] Table 2

[0170]

[0171]

[0172] The verification matrix H0 can be referenced. Figure 4 Understand (a) in the text.

[0173] Select the leftmost 60 columns of the matrix H0 to obtain a matrix H of size 8×60. left ,like Figure 4 As shown in (a) in the figure, it is represented as

[0174] H left =[g(0),g(1),g(2),…,g(58),g(59)]

[0175] Select the rightmost 8 columns of the matrix H0 to obtain a matrix H of size 8×8. right ,like Figure 4 As shown in (a) in the figure, it is represented as

[0176] H right =[g(60),g(61),g(62),g(63),g(64),g(65),g(66),g(67)]

[0177] To obtain the encoding matrix G, we calculate

[0178] P = B·H left =(H right ) -1 ·H left

[0179] =([g(60),g(61),g(62),g(63),g(64),g(65),g(66),g(67)]) -1 ·[g(0),g(1),g(2),…,g(58),g(59)]

[0180] in,() -1 The dot (·) represents the matrix inversion operation, and the dot (·) represents the matrix multiplication operation. B = (H right ) -1 For matrix H right The inverse matrix. The generator matrix of size 60×68 corresponding to the designed FEC(68,60) code is as follows:

[0181] G = [I 60 ;P T ]

[0182] Among them, P T I is the transpose of P. 60 This represents an identity matrix of size 60×60. The P... T The size is 60×8.

[0183] It should be noted that the above P = B·H left It can be directly written as P = BH left The above G = [I 60 ;P T It can be directly written as G = [I] 60 P T ] or G = [I 60 ,P T ], representing matrix I 60 Sum of matrix P T splicing.

[0184] Table 3 below shows the specific values ​​of the rightmost 8 columns of the generated matrix G, denoted as P. T (i1,j1). That is, the specific values ​​of the element G(i1,j1+60) in the i1th row and j1+60th column of the generated matrix are shown in Table 3 below:

[0185] Table 3

[0186]

[0187]

[0188] It should be noted that the above P = B·H left After the operation, a systematic verification matrix is ​​obtained.

[0189] H sys =[P;I8]

[0190] Where I8 represents an 8×8 identity matrix. The systematic check matrix H... sys The size is 8×68 (see reference). Figure 4 To understand (b) in the text. For example... Figure 4 The systematization of the parity check matrix H0 described in (a) does not require column position swapping, which can reduce the encoding and decoding complexity of the designed FEC code.

[0191] It should be noted that the aforementioned FEC(68,60) code is also called a Hamming(68,60) code. The Hamming(68,60) code can be considered as shortening the Hamming(127,120) code by 59 bits to obtain a shortened Hamming(68,61) code. Then, the odd-weight codewords in the shortened Hamming(68,61) code are exurgated, leaving only the even-weight codewords, resulting in the corresponding Hamming(68,60) code. This exurgation technique can be considered as adding one or more parity checks to the FEC code, i.e., adding one or more rows to the parity check matrix. The exurgation of odd-weighted codewords in the shortened Hamming (68,61) code can be achieved as follows: Add a row containing 68 bits all 1 to the 7×68 parity-check matrix of the shortened Hamming (68,61) code, resulting in an 8×68 parity-check matrix. This 8×68 parity-check matrix corresponds to the Hamming (68,60) code. In some specific applications, the Hamming (127,120) code is a cyclic Hamming (127,120) code, also known as a BCH code that corrects single erroneous bits.

[0192] It should be noted that the Hamming (68,60) code can also be considered as deleting the codewords with odd weights from the Hamming (127,120) code, that is, keeping only the codewords with even weights, to obtain the corresponding Hamming (127,119) code. Then, the Hamming (127,119) code is shortened by 59 bits to obtain the corresponding Hamming (68,60) code. The deletion of the codewords with odd weights from the Hamming (127,120) code can be achieved as follows: add a row containing 127 bits all 1 to the 7×127 parity check matrix of the Hamming (127,120) code to obtain an 8×127 parity check matrix, which corresponds to the Hamming (127,119) code. In some specific applications, the Hamming (127,120) code is a cyclic Hamming (127,120) code, also known as a BCH code that corrects a single erroneous bit.

[0193] The aforementioned k0 information bits U are encoded to obtain p0 parity bits V, where V = U·P T The information bits and check bits constitute a codeword C = [U; V] with a bit length of n0 = k0 + p0. Here, [U; V] represents the concatenation of U and V. Considering the codeword as a row vector, it satisfies the following conditions:

[0194] H0·(C) T =0

[0195] It should be noted that the above conditions can also be written as

[0196] C·(H0) T =0

[0197] It should be noted that when the codeword is represented using a column vector, the above condition is H0·C = 0 or (C). T ·(H0) T =0.

[0198] In this application, "the result of multiplying the codeword and the parity check matrix H is 0" can be understood as one of the four cases mentioned above, and this application does not make further limitations. In the subsequent description of this application, the codeword will be described as a row vector.

[0199] The codeword C is modulated and sent to the receiving end via the channel, where it is demodulated and decoded. The receiving end obtains the corresponding received sequence R0, consisting of n0 bits, and calculates a syndrome containing p0 bits. The syndrome is obtained by multiplying the received sequence R0 by the designed parity check matrix H0. The receiving end can obtain the received sequence R0 by demodulating the received data. In some specific applications, the syndrome is represented by a column vector, in which case S = H0·(R0). T In other specific applications, the corrector is represented by a row vector, in which case S = R0·(H0) T Here, we will take the example of using a column vector to represent the calibrator.

[0200] Considering the received sequence R0 = C + e, where e is the error pattern, we have S = H0·(R0) T =H0·(C+e) T =H0·(e) T Because the designed verification matrix H0 has a special structure, that is, the i-th column is... This allows the receiver to use simple logic circuits to calculate the corrector. Based on the corrector, error correction and detection can be performed. When only one error occurs in error mode e, for example, the i-th position is an error bit, the corrector... The error location can be determined from the corrector as being in the received sequence C. r The i-th position in the error pattern. When only two errors occur in error mode e, the last bit (corresponding to the extension bit) in the corrector S is 0. This property can be used to detect error modes with two-bit errors. The calculation process can be found in [reference]. Figure 5 To understand. Because of α iThe correspondence with i can be implemented using simple logic circuits, making error correction and detection at the receiving end less complex; that is, the designed check matrix allows the receiving end to use simple logic circuits to calculate the corrector, and to perform error correction and detection, making error correction and detection at the receiving end less complex.

[0201] It should be noted that in some specific applications, the receiver uses soft-decision decoding, such as Chase decoding. In this case, the received sequence R0 contains 68 real numbers. Figure 6 As shown, the Chase soft-decision decoding uses sequence R0 and the adopted decoding test pattern to obtain a corrector, and performs error correction based on the corrector to obtain possible decoding sequences. Given a decoding test pattern, at most one decoding sequence can be obtained; multiple decoding test patterns can obtain multiple decoding sequences. The Chase soft-decision decoding calculates based on sequence R0 and the multiple obtained decoding sequences to obtain the most likely FEC(68,60) codeword. The key step in the Chase decoding process is obtaining the corrector, followed by error correction and detection operations based on the corrector. This step accounts for a significant portion of the complexity in the entire soft-decision decoding process. The designed parity-check matrix can greatly simplify the hardware implementation of corrector calculation, error correction, and error detection at the receiver, resulting in lower complexity for the receiver.

[0202] It should be noted that the g(i) function considered in the above description is

[0203]

[0204] For FEC(68,60) codes, the corresponding parity-check matrix H0 is shown in Table 2 or Figure 4 As shown in (a) in the figure.

[0205] In some specific applications, the g(i) function used can be represented in other forms, such as

[0206]

[0207] At this point, for the FEC(68,60) code, the corresponding parity-check matrix H0 is as follows: Figure 4 As shown in (c) in the figure.

[0208] In other specific applications, the g(i) function used is have

[0209]

[0210] At this point, for the FEC(68,60) code, the corresponding parity-check matrix H0 is as follows: Figure 4 As shown in (d) in the figure.

[0211] In other specific applications, the g(i) function used is

[0212]

[0213] At this point, for the FEC(68,60) code, the corresponding parity-check matrix H0 is as follows: Figure 4 As shown in (e) in the diagram.

[0214] It should be noted that, regarding the above or After systematization, the corresponding parity-check matrices all produce identical generator matrices. For example, the... Figure 4 (a) Figure 4 (c) Figure 4 (d) and Figure 4 The parity check matrix H0 shown in (e) is different, but the corresponding system parity check matrix after systematization is the same as shown in the figure. Figure 4 H shown in (b) sys .

[0215] It should be noted that in some specific applications, the g(i) function used can be represented in other forms, for example, have

[0216] or

[0217] For example, have

[0218] or

[0219] It should be noted that, regarding the above or The corresponding parity-check matrices, after being systematized, all produce identical generated matrices.

[0220] In some specific applications, the codewords obtained after encoding using the encoding method provided in this application are PAM4 modulated, that is, every 2 bits are mapped to obtain 1 PAM4 symbol. At the receiving end, after demapping (i.e., demodulating) a received symbol, in the resulting 2 bits, usually only 1 bit is erroneous or there is no error, and it is extremely rare for both bits to be erroneous. The encoding and decoding complexity of FEC codes can be further reduced by combining the above-mentioned PAM4 modulation characteristics. A possible FEC encoding scheme is given below.

[0221] Consider an FEC code that encodes k1 information bits to obtain p1 parity bits. The information bits and parity bits form a codeword of length n1 = k1 + p1. Here, consider n1 = 128, k1 = 120, and p1 = 8. Figure 7 As shown, obtain k1 = 120 information bits U1. Perform an exclusive OR operation on every two bits in U1 to obtain 60 bits U0, where U0(i2) = U1(2×i2)∧U1(2×i2+1), and ∧ represents the XOR operation. Here, U0(i2) represents the i2th bit in U0, U1(2×i2) represents the 2×i2th bit in U1, and U1(2×i2+1) represents the 2×i2+1th bit in U1. Encode using the above FEC(68,60) code to obtain an 8-bit parity bit V0, i.e., V0 = U0·P T The information bits and check bits constitute an FEC(68,60) codeword C0 = [U0; V0] with a bit length of n0 = k0 + p0.

[0222] H0·(C0) T =0

[0223] The 120 information bits U1, combined with the 8 parity bits V0, constitute the codeword C1 = [U1; V0] of the FEC(128,120) code. The codeword C1 is PAM4 modulated to obtain 64 PAM4 symbols, which are then transmitted to the receiver via the channel. The receiver demodulates the received PAM4 symbols to obtain the received sequence R1. Typically, the receiver uses Chase soft-decision decoding, and the received sequence is a sequence containing 128 real numbers. A sequence R0 containing 68 real numbers is obtained from the received sequence R1. Chase soft-decision decoding uses the sequence R0 and the chosen decoding test mode to obtain a corrector, and performs error correction based on the corrector to obtain possible decoding sequences. Given a decoding test mode, at most one decoding sequence is obtained; multiple decoding test modes can obtain multiple decoding sequences. Chase soft-decision decoding calculates the most probable FEC(68,60) codeword based on the sequence R0 and the multiple obtained decoding sequences. Further obtain possible FEC(128,120) codewords The key step in the Chase decoding process is obtaining the corrector, followed by error correction and detection operations based on the corrector. This step accounts for a significant portion of the complexity in the entire soft-decision decoding process. The designed parity-check matrix can greatly simplify the hardware implementation of corrector calculation, error correction, and error detection at the receiver, resulting in lower complexity for the receiver.

[0224] It should be noted that in some specific applications, the aforementioned FEC(128,120) code is also combined with Reed-Solomon (RS) code to form a concatenated code, wherein the FEC(128,120) code serves as the inner code and the RS code serves as the outer code. To improve the performance of the concatenated code, convolutional interleaving can be performed after the RS encoding step and before the FEC(128,120) inner code encoding step, resulting in an overall performance of approximately 4.5E-3 pre-correction bit error rate, which is better than using RS code alone. This allows the concatenated code to be applied in future 800G, 1.6T, 3.2T, and even higher speed transmission scenarios.

[0225] Figure 8 This is a schematic diagram of the encoding device in one embodiment of this application. Figure 8 As shown, the encoding device includes an acquisition unit 801 and an encoding unit 802. The acquisition unit 801 acquires a first bit sequence containing k bits, which includes the information bits to be encoded. The encoding unit 802 performs an encoding operation on the acquired first bit sequence. The encoding unit 802 can also modulate the encoded codeword, for example, using PAM4 modulation or 16QAM modulation, to obtain a symbol sequence to be transmitted. Specific encoding methods have been described in detail in the preceding embodiments and will not be repeated here.

[0226] Figure 9 This is a schematic diagram of one structure of the decoding device in an embodiment of this application. Figure 9 As shown, the decoding apparatus includes: an acquisition unit 901, configured to acquire a first sequence, which is the received sequence obtained through channel transmission; and a decoding unit 902, configured to acquire a corrector containing p bits based on a parity check matrix and the first sequence, and to decode the first sequence based on the corrector. It should be understood that the acquisition unit 901 can also be used to demodulate the received symbol sequence to obtain the first sequence. The specific decoding method has been described in detail in the previous embodiments and will not be repeated here.

[0227] It should be understood that the encoding and decoding apparatus provided in this application can also be implemented in other ways. For example, the unit division in the above apparatus is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the various embodiments of this application may be integrated into one processing unit, or they may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated units described above can be implemented in hardware or as software functional units.

[0228] Figure 10This is a schematic diagram of one structure of the optical module in an embodiment of this application. Figure 10 As shown, the optical module includes a processor 1001 and an interface 1002. The processor 1001 is used to perform the operations performed by the encoding or decoding device in the above embodiments. In one possible implementation, the processor 1001 includes the above-described... Figure 8 The encoding unit 802 shown or the above Figure 9 The decoding unit 902 is shown. Interface 1002 can be a transceiver or an input / output interface. Interface 1002 is used to receive signals from other devices and transmit them to processor 1001, or to send signals from processor 1001 to other devices. As an example, after processor 1001 performs the FEC encoding process to obtain an encoded data stream, it sends the encoded data stream through interface 1002. In this example, interface 1002 specifically refers to an electrical interface. As another example, after processor 1001 performs the FEC encoding process to obtain an encoded data stream, it performs symbol mapping to obtain a symbol stream to be transmitted. The modulator in the optical module performs electro-optical conversion and other signal processing based on the symbol stream to be transmitted to obtain an optical signal, and then sends the optical signal through interface 1002. In this example, interface 1002 specifically refers to an optical interface. Optionally, the optical module may also include a memory 1003, wherein the memory 1003 is used to store program instructions and / or data.

[0229] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0230] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules connect to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packages and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0231] Figure 11 This is a schematic diagram of the structure of a communication device in an embodiment of this application. Figure 11 As shown, the communication device includes a host-side device 1101 and an optical module 1102. The host-side device 1101 sends data to the optical module 1102, and the optical module 1102 generates an optical signal based on the data sent by the host-side device 1101 and transmits the optical signal through the channel. For example, the host-side device can be a switch, router, or server. This communication device can be a communication device that includes the host-side device 1101 and the optical module 1102.

[0232] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. The processor is used to execute the encoding or decoding methods described in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices outside the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices outside the line-side equipment.

[0233] This application also provides a chip. The chip integrates circuitry for implementing the functions of the aforementioned processor and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the foregoing embodiments based on program code stored in the memory.

[0234] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0235] This application also provides a computer-readable storage medium, including a program or instructions that, when run on a computer, cause the method performed as described in the above method embodiments to be implemented.

[0236] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0237] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0238] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0239] In the above embodiments, it can be implemented entirely or partially by software, hardware, firmware, or any combination thereof.

[0240] When implemented in hardware, the data processing method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0241] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server integrating one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0242] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An encoding method, characterized in that, include: Obtain the first bit sequence containing k bits; The first bit sequence is encoded to obtain a codeword containing n bits, wherein the codeword includes p = nk parity bits, and the result of multiplying the codeword and the parity check matrix H is 0; The check matrix H is an m+1 row n column binary matrix, p = m+1; H = [g(0), g(1), g(2), ..., g(i-1), g(i), ..., g(n-1)], whose i-th column contains m+1 bits. and Any one of them; Where α is the primitive element of the finite field, α i Let i be an element of the finite field GF(2m) and be a column vector containing m bits, 0≤i≤n-1, n<2m-2, m≥3, and i, m, p, k, n are all positive integers.

2. The method according to claim 1, characterized in that, The finite field GF(2) m ) element α i Represented as a column vector containing m bits or Where, α i =b 0，i ×α 0 +b 1，i ×α 1 +b 2，i ×α 2 +…+b (m-1)，i ×α m-1 .

3. The method according to claim 1 or 2, characterized in that, m=7, k=60, p=8, n=68.

4. The method according to claim 3, characterized in that, The i-th column of the 8-row, 68-column verification matrix H is or, or, or, Among them, a i =b 0，i +b 1，i ×a+b 2，i ×a 2 +b 3，i ×a 3 +b 4，i ×a 4 +b 5，i ×a 5 +b 6，i ×a 6 。 5. The method according to claim 3 or 4, characterized in that, 1+α 3 +α 7 ＝0。 6. The method according to any one of claims 3-5, characterized in that, The finite field GF(2) 7 The corresponding primitive polynomial is p(x) = x. 7 +x 3 +1.

7. The method according to any one of claims 3-6, characterized in that, The verification matrix H is: H=[g(0), g(1), g(2),..., g(66), g(67)].

8. The method according to any one of claims 3-7, characterized in that, The specific values ​​of the element H(i0, j0) in the i0th row and j0th column of the verification matrix H are as follows:

9. The method according to any one of claims 1-8, characterized in that, Obtain the first bit sequence containing k bits, specifically including: Obtain the second bit sequence containing k1 bits, where k1 = 2 × k; XORing every two bits in the second bit sequence yields one bit, resulting in a first bit sequence containing a total of k bits.

10. The method according to claim 9, characterized in that, The method further includes: Output the second bit sequence of the k1 bits and the p parity bits.

11. A decoding method, characterized in that, include: Obtain the first sequence; Based on the parity check matrix H and the first sequence, a corrector containing p bits is obtained; wherein, the parity check matrix H is a binary matrix of m+1 rows and n columns, p = m+1; H = [g(0), g(1), g(2), ..., g(i-1), g(i), ..., g(n-1)], and its i-th column containing m+1 bits is... Any one of them; Where α is the finite field GF(2 m The fundamental element of α i For the finite field GF(2) m A column vector containing m bits, where 0 ≤ i ≤ n-1, n < 2m-2, m ≥ 3, and i, m, p, n are all positive integers; The first sequence is decoded according to the corrector.

12. The method according to claim 11, characterized in that, The corrector is obtained by multiplying the verification matrix H and the first sequence.

13. The method according to claim 11 or 12, characterized in that, The finite field GF(2) m ) element α i Represented as a column vector containing m bits or Where, α i =b 0,i ×α 0 +b 1,i ×α 1 +b 2,i ×α 2 +…+b (m-1),i ×α m-1 .

14. The method according to any one of claims 11-13, characterized in that, m = 7, p = 8, n = 68.

15. The method according to claim 14, characterized in that, The i-th column of the 8-row, 68-column verification matrix H is Among them, a i =b 0,i +b 1,i ×a+b 2,i ×a 2 +b 3,i ×a 3 +b 4,i ×a 4 +b 5,i ×a 5 +b 6,i ×a 6 。 16. The method according to claim 14 or 15, characterized in that, 1+α 3 +α 7 ＝0。 17. The method according to any one of claims 14-16, characterized in that, The verification matrix H is: H=[g(0),g(1),g(2),…,g(66),g(67)].

18. The method according to any one of claims 14-17, characterized in that, The finite field GF(2) 7 The corresponding primitive polynomial is p(x) = x. 7 +x 3 +1.

19. The method according to any one of claims 14-18, characterized in that, The specific values ​​of the element H(i0,j0) in the i0th row and j0th column of the verification matrix H are as follows:

20. An encoding device, characterized in that, include: The acquisition unit is used to acquire a first bit sequence containing k bits; The encoding unit is used to encode the first bit sequence to obtain a codeword containing n bits, wherein the codeword includes p = nk parity bits, and the result of multiplying the codeword and the parity check matrix H is 0; The check matrix H is an m+1 row n column binary matrix, p = m+1; H = [g(0), g(1), g(2), ..., g(i-1), g(i), ..., g(n-1)], whose i-th column contains m+1 bits. and Any one of them; Where α is the primitive element of the finite field, α i For the finite field GF(2) m An element in the array is a column vector containing m bits, where 0 ≤ i ≤ n-1, n < 2. m -2, m≥3, and i, m, p, k, n are all positive integers.

21. The apparatus according to claim 20, characterized in that, The finite field GF(2) m ) element α i Represented as a column vector containing m bits or Where, α i =b 0,i ×α 0 +b 1,i ×α 1 +b 2,i ×α 2 +…+b (m-1),i ×α m-1 .

22. The apparatus according to claim 20 or 21, characterized in that, m=7, k=60, p=8, n=68.

23. The apparatus according to claim 22, characterized in that, The i-th column of the 8-row, 68-column verification matrix H is Among them, a i =b 0,i +b 1,i ×a+b 2,i ×a 2 +b 3,i ×a 3 +b 4,i ×a 4 +b 5,i ×a 5 +b 6,i ×a 6 。 24. The apparatus according to claim 22 or 23, characterized in that, 1+α 3 +α 7 ＝0。 25. The apparatus according to any one of claims 22-24, characterized in that, The finite field GF(2) 7 The corresponding primitive polynomial is p(x) = x. 7 +x 3 +1.

26. The apparatus according to any one of claims 22-25, characterized in that, The verification matrix H is: H=[g(0),g(1),g(2),…,g(66),g(67)].

27. The apparatus according to any one of claims 22-26, characterized in that, The specific values ​​of the element H(i0,j0) in the i0th row and j0th column of the verification matrix H are as follows:

28. A decoding device, characterized in that, include: The acquisition unit is used to acquire the first sequence; The decoding unit is used to obtain a corrector containing p bits based on the parity check matrix H and the first sequence; wherein the parity check matrix H is an n+1 row n column binary matrix, p=m+1; H=[g(0),g(1),g(2),…,g(i-1),g(i),…,g(n-1)], which contains The i-th column of m+1 bits is and Any one of them; Where α is the primitive element of the finite field, α i For the finite field GF(2) m An element in the array is a column vector containing m bits, where 0 ≤ i ≤ n-1, n < 2. m -2, m≥3, and i, m, p, n are all positive integers; The decoding unit is further configured to decode the first sequence according to the corrector.

29. The apparatus according to claim 28, characterized in that, The corrector is obtained by multiplying the verification matrix H and the first sequence.

30. The apparatus according to claim 28 or 29, characterized in that, The finite field GF(2) m ) element α i Represented as a column vector containing m bits or Where, α i =b 0,i ×α 0 +b 1,i ×α 1 +b 2,i ×α 2 +…+b (m-1),i ×α m-1 .

31. The apparatus according to any one of claims 28-30, characterized in that, m=7, p=8, n=68.

32. The apparatus according to claim 31, characterized in that, The i-th column of the 8-row, 68-column verification matrix H is or, or, or, Among them, a i =b 0,i +b 1,i ×a+b 2,i ×a 2 +b 3,i ×a 3 +b 4,i ×a 4 +b 5,i ×a 5 +b 6,i ×a 6 。 33. The apparatus according to claim 31 or 32, characterized in that, 1+α 3 +α 7 ＝0。 34. The apparatus according to any one of claims 31-33, characterized in that, The finite field GF(2) 7 The corresponding primitive polynomial is p(x) = x. 7 +x 3 +1.

35. The apparatus according to any one of claims 31-34, characterized in that, The verification matrix H is: H=[g(0),g(1),g(2),…,g(66),g(67)].

36. The apparatus according to any one of claims 31-35, characterized in that, The specific values ​​of the element H(i0,j0) in the i0th row and j0th column of the verification matrix H are as follows:

37. A chip, characterized in that, The chip is used to perform the method as described in any one of claims 1 to 19.

38. An optical module, characterized in that, The optical module includes a processor and an interface, the processor being used to perform the method as described in any one of claims 1 to 19, and to transmit and receive signals through the interface.

39. A communication device, characterized in that, The transmitting device includes a host-side device and an optical module as described in claim 38, wherein the optical module is connected to the host-side device.

40. A communication system, characterized in that, include: A first communication device and a second communication device, wherein at least one of the first communication device and the second communication device is the communication device as described in claim 39, and the first communication device and the second communication device are connected.

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