Multimedia data transmission method and device based on multiplexing XDMA, and storage medium

Abstract

The application discloses a multimedia data transmission method and device based on multiplexing XDMA and a storage medium, relates to the technical field of data transmission, and discloses a multimedia data transmission method based on multiplexing XDMA, which comprises the following steps: encapsulating multiple paths of multimedia data into a combined transmission frame, each path of multimedia data is divided into multiple logical data segments containing data source identifiers and time sequence identifiers; transmitting the combined transmission frame to a host memory through a single XDMA channel, and establishing virtual channels corresponding to the multiple paths of multimedia data; analyzing the received combined transmission frame according to the data source identifiers and the time sequence identifiers, determining the distribution position of the logical data segment in the memory block through address calculation; based on the distribution position, the data source identifiers and the time sequence identifiers, the combined transmission frame is split and reorganized into each path of multimedia data; and each path of multimedia data is output to an application layer through the corresponding virtual channel, so that multiplexing of multiple paths of multimedia data based on a single channel is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, and particularly relates to a multimedia data transmission method, device and storage medium based on multiplexing XDMA. BACKGROUND

[0002] The traditional XDMA multimedia data transmission process is affected by the PCIE bandwidth, and each XDMA channel can only transmit one multimedia data stream. When the system needs to realize single-input data distribution to multiple-output ends, an independent XDMA channel must be established for each output, which causes the PCIE bus bandwidth to be seriously occupied by multiple concurrent transmissions. Due to the limited PCIe bus bandwidth, in the case of not upgrading the hardware, increasing the number of transmission paths will cause the available bandwidth of a single path to decrease, thereby affecting the real-time performance and stability of data transmission.

[0003] The above content is only used to assist in understanding the technical solutions of the present application and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0004] The main purpose of the present application is to provide a multimedia data transmission method, device and storage medium based on multiplexing XDMA, aiming at solving the technical problem that a single physical channel cannot transmit multiple independent multimedia data streams simultaneously in the traditional XDMA architecture.

[0005] To achieve the above purpose, the present application provides a multimedia data transmission method based on multiplexing XDMA, which comprises:

[0006] The multiple multimedia data is packaged into a combined transmission frame according to a preset format, wherein each multimedia data is divided into multiple logical data segments containing data source identification and timing identification;

[0007] The combined transmission frame is transmitted to the host memory through a single XDMA channel, and a virtual channel corresponding to the multiple multimedia data is established for the single XDMA channel;

[0008] According to the data source identification and the timing identification, the received combined transmission frame is analyzed, and the distribution position of the logical data segment in the memory block is determined through address calculation;

[0009] Based on the distribution position, the data source identification and the timing identification, the combined transmission frame is split and reorganized into each multimedia data;

[0010] Each multimedia data is output to the application layer through the corresponding virtual channel.

[0011] In an embodiment, the step of encapsulating the multiple multimedia data into a combined transmission frame according to a preset format comprises:

[0012] dividing each of the multimedia data into multiple multimedia slice data, and adding a frame header containing the data source identifier and the timing identifier to the head of each of the multimedia slice data to obtain the logical data segment, wherein the timing identifier is used to mark the cycle round in which the logical data segment is located;

[0013] arranging the logical data segment corresponding to each of the multimedia data in sequence according to the data source identifier in each cycle round according to a preset cycle number to generate a single-cycle round data sequence, wherein the single-cycle round data sequence contains one logical data segment of each of the multimedia data;

[0014] splicing multiple single-cycle round data sequences in sequence according to the timing identifier to obtain the combined transmission frame.

[0015] In an embodiment, the step of parsing the received combined transmission frame according to the data source identifier and the timing identifier, and determining the distribution position of the logical data segment in the memory block through address calculation comprises:

[0016] parsing the frame header at the head of each of the logical data segments in the combined transmission frame to obtain the data source identifier and the timing identifier corresponding to the logical data segment;

[0017] determining the cycle round in which the logical data segment is located through the timing identifier;

[0018] determining the target memory block to which the logical data segment belongs based on the cycle round, a preset memory block size, the frame header length of the frame header, and the data length of the logical data segment, and calculating the in-page offset of the logical data segment in the target memory block;

[0019] obtaining the distribution position of the logical data segment in the memory block based on the target memory block, the data length, and the in-page offset.

[0020] In an embodiment, before the step of splitting and recombining the combined transmission frame into each of the multimedia data based on the distribution position, the data source identifier, and the timing identifier, the method further comprises:

[0021] determining the multimedia slice data in the same cycle round according to the timing identifier;

[0022] performing cross-page data splicing operation when the multimedia slice data in the same cycle round crosses the memory block boundary.

[0023] In an embodiment, when the multimedia slice data in the same cycle round crosses the memory block boundary, the step of performing a cross-page data splicing operation comprises:

[0024] According to the order of the data source identification, when the end address of the previous multimedia slice data and the start address of the next multimedia slice data are detected to be in the same memory block, the memory block containing the two multimedia slice data is determined as a to-be-spliced memory block;

[0025] The remaining data in the to-be-spliced memory block belonging to the previous multimedia slice data is spliced to the end of the previous memory block adjacent to the to-be-spliced memory block.

[0026] In an embodiment, the step of splitting and recombining the combined transmission frame into each multimedia data based on the distribution position, the data source identification and the timing identification comprises:

[0027] According to the data source identification, the number of multimedia paths to which each multimedia slice data in the combined transmission frame belongs is determined;

[0028] The multimedia slice data in the combined transmission frame is data segmented according to the number of multimedia paths to form independent multimedia slice data queues of each path;

[0029] According to the order of the cycle round determined by the timing identification, the multimedia slice data queues of each path are time-sequentially recombined to reconstruct the multimedia data of each path.

[0030] In an embodiment, the step of transmitting the combined transmission frame to the host memory through a single XDMA channel and establishing a virtual channel corresponding to the multimedia data of multiple paths for the single XDMA channel comprises:

[0031] Based on the number of data source identifications, a corresponding number of virtual channels are established for the single XDMA channel, and an independent memory buffer is allocated for each virtual channel.

[0032] In an embodiment, before the step of outputting each multimedia data to the application layer through the corresponding virtual channel, it further comprises:

[0033] According to the timing identification, data verification is performed on each recombined multimedia data;

[0034] When it is detected that the data of the recombined multimedia data is not continuous, a data retransmission mechanism corresponding to the virtual channel is triggered.

[0035] The embodiment of the present application also provides a multimedia data transmission device based on multiplexing XDMA, which comprises a memory, a processor and a computer program stored in the memory and executable on the processor, and the computer program is configured to implement the steps of the multimedia data transmission method based on multiplexing XDMA.

[0036] The embodiment of the present application also provides a storage medium, which is a computer readable storage medium, and the storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the multimedia data transmission method based on multiplexing XDMA.

[0037] The one or more technical solutions provided by the present application have at least the following technical effects:

[0038] The present application encapsulates multiple multimedia data into a combination transmission frame of multiple logical data segments containing identification information, avoids the problems of data confusion, inability to distinguish the data sources and the time sequence order in mixed transmission of multiple data, establishes a corresponding virtual channel to provide an independent transmission path for each multimedia data and ensure that the data transmission does not interfere with each other, determines the distribution position of the logical data segment in the memory block by means of address calculation, accurately locates the storage range after the data is transmitted to the memory, provides a spatial index for efficient splitting and reorganization, and finally splits and reorganizes the combination transmission frame into each multimedia data based on the distribution position, the data source identification and the time sequence identification, and outputs to the application layer through the corresponding virtual channel, which not only restores the integrity and time sequence of each multimedia data, but also realizes efficient multiplexing of a single physical channel and improves the overall transmission efficiency and stability. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 A flowchart of a first embodiment of the multimedia data transmission method based on multiplexing XDMA involved in the embodiment of the present application is shown.

[0040] Figure 2 A general framework flowchart of the first embodiment of the multimedia data transmission method based on multiplexing XDMA involved in the embodiment of the present application is shown.

[0041] Figure 3 An XDMA driving flowchart of the first embodiment of the multimedia data transmission method based on multiplexing XDMA involved in the embodiment of the present application is shown.

[0042] Figure 4 A flowchart of a second embodiment of the multimedia data transmission method based on multiplexing XDMA involved in the embodiment of the present application is shown.

[0043] Figure 5 Figure 2 is a schematic diagram of a combined transmission frame structure according to a second embodiment of the multimedia data transmission method based on multiplexing XDMA involved in the embodiment of the present application;

[0044] Figure 6 Figure 3 is a flowchart of a third embodiment of the multimedia data transmission method based on multiplexing XDMA involved in the embodiment of the present application;

[0045] Figure 7 Figure 4 is a flowchart of a fourth embodiment of the multimedia data transmission method based on multiplexing XDMA involved in the embodiment of the present application;

[0046] Figure 8 Figure 5 is a schematic diagram of memory block splicing according to the fourth embodiment of the multimedia data transmission method based on multiplexing XDMA involved in the embodiment of the present application;

[0047] Figure 9 Figure 6 is a flowchart of a fifth embodiment of the multimedia data transmission method based on multiplexing XDMA involved in the embodiment of the present application;

[0048] Figure 10 Figure 7 is a schematic diagram of a multimedia data transmission device based on multiplexing XDMA involved in the embodiment of the present application.

[0049] The object, function features and advantages of the present application will be further explained in combination with the embodiments and with reference to the drawings. DETAILED DESCRIPTION

[0050] It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0051] In order to better understand the technical solutions of the present application, the specific embodiments will be described in detail below in combination with the drawings and the specific embodiments.

[0052] The conventional XDMA multimedia data transmission process is affected by the PCIE bandwidth, and each XDMA channel can only transmit one multimedia data stream. When the system needs to realize single input data distribution to multiple output ends, an independent XDMA channel must be established for each output, resulting in that the PCIE bus bandwidth is seriously occupied by multiple concurrent transmissions. Due to the limited PCIe bus bandwidth, in the case of not upgrading the hardware, increasing the number of transmission paths will cause the available bandwidth of a single path to decrease, thereby affecting the real-time performance and stability of data transmission.

[0053] In view of the above problems, the present application provides a multimedia data transmission method based on multiplexing XDMA. The method includes the following steps: encapsulating multiple multimedia data into a combined transmission frame according to a preset format, wherein each of the multimedia data is divided into multiple logical data segments containing data source identification and timing identification; transmitting the combined transmission frame to a host memory through a single XDMA channel, and establishing a virtual channel corresponding to the multiple multimedia data for the single XDMA channel; analyzing the received combined transmission frame according to the data source identification and the timing identification, determining the distribution position of the logical data segment in the memory block through address calculation; based on the distribution position, the data source identification and the timing identification, splitting and recombining the combined transmission frame into each of the multimedia data; and outputting each of the multimedia data to an application layer through the corresponding virtual channel.

[0054] The present application provides a solution by encapsulating multiple multimedia data into a combined transmission frame containing multiple logical data segments with identification information, avoiding the problems of data confusion, inability to distinguish data sources and timing sequence when multiple data are mixed and transmitted; by establishing a corresponding virtual channel, an independent transmission path can be provided for each multimedia data, ensuring that the data transmission does not interfere with each other; by means of address calculation to determine the distribution position of the logical data segment in the memory block, the storage range can be accurately located after the data is transmitted to the memory, providing a spatial index for efficient splitting and recombination; finally, based on the distribution position, the data source identification and the timing identification, the combined transmission frame is split and recombined into each multimedia data, and output to the application layer through the corresponding virtual channel, not only restoring the integrity and timing of each multimedia data, but also realizing efficient multiplexing of a single physical channel, improving the overall transmission efficiency and stability.

[0055] It should be noted that the execution subject of the present embodiment can be a computing service device with data processing, network communication and program running functions, such as an industrial computer integrated with FPGA, a multimedia processing terminal, a video server, etc., or an electronic device capable of realizing the above functions, a multimedia data transmission system based on multiplexing XDMA, etc. The present embodiment and the following embodiments will be described below taking the multimedia data transmission system based on multiplexing XDMA as an example.

[0056] The first embodiment of the present application provides a multimedia data transmission method based on multiplexing XDMA, which is described in detail in the following Figure 1 , the method includes steps S10-S50:

[0057] Step S10: encapsulating multiple multimedia data into a combined transmission frame according to a preset format, wherein each of the multimedia data is divided into multiple logical data segments containing data source identification and timing identification.

[0058] It should be noted that the data source identifier is identification information for distinguishing different multimedia data, and is usually represented by digital coding to represent different multimedia data sources. The timing identifier is identification information for marking the cycle round of the logical data segment. The logical data segment refers to a data unit obtained by dividing continuous multimedia data into fixed sizes, and a transmission basic unit formed after adding identification information to each data unit.

[0059] In the embodiment, an FPGA (Field Programmable Gate Array) synchronously collects video data streams output by multiple image acquisition devices through multiple parallel interfaces. Each image acquisition device corresponds to an independent multimedia data, and the multimedia data forms multiple multimedia data to be transmitted after being received by the FPGA.

[0060] To realize efficient multiplexing transmission of the multiple multimedia data on a single XDMA channel, the FPGA is used to encapsulate and process the multiple multimedia data according to a preset frame structure. Specifically, first, continuous multimedia data of each channel is divided into multiple continuous multimedia slice data according to a preset fixed length, and then frame header information containing identification information is added to the header of each multimedia slice data, thereby obtaining a logical data segment containing identification information and payload data. The identification information at least includes a data source identifier and a timing identifier, the data source identifier is used to distinguish the multimedia data of different physical channels, and the timing identifier is used to mark the cycle round of the logical data segment in the overall transmission process, thereby providing a timing reference for subsequent recombination of the multimedia data.

[0061] Based on the preset cycle rotation scheduling mechanism, the FPGA selects a logical data segment of each multimedia data in sequence according to the fixed ordering of the data source identifier in each transmission cycle, and sequentially splices to obtain a single cycle data sequence. Then, multiple single cycle data sequences are spliced in sequence according to the timing identifier, and finally encapsulated into a combined transmission frame conforming to the XDMA transmission format.

[0062] It can be understood that the embodiment integrates the originally independent multiple multimedia data into a single combined transmission frame conforming to the XDMA transmission specification by adding the data source identifier and the timing identifier in each multimedia slice data. This encapsulation processing can not only fully utilize the high bandwidth characteristics of the XDMA to realize parallel multiplexing transmission of the multiple multimedia data at the physical layer, but also construct a clear logical boundary through the identification information in the frame header, so that the receiving end can accurately identify the multimedia channel number and timing relationship of each multimedia slice data based on the identification information, thereby completing the recombination of the multiple multimedia data, and finally realizing the multiplexing of the multiple multimedia data based on a single channel.

[0063] Step S20: transmitting the combined transmission frame to the host memory through a single XDMA channel, and establishing a virtual channel corresponding to the multiple pieces of multimedia data for the single XDMA channel.

[0064] It should be noted that XDMA refers to a high-performance direct memory access controller based on a PCIe bus, and its function is to realize high-speed data transmission between a device and a host memory by configuring multiple DMA (Direct Memory Access) channels. XDMA is widely used in scenarios requiring high-speed data transmission (such as memory interaction between FPGAs and hosts, and between internal modules of FPGAs), and XDMA performs high-speed reading and writing of data through a PCIe interface and supports the establishment of multiple parallel DMA channels. Each DMA channel can perform memory-to-memory, device-to-memory, and memory-to-device transmission tasks to adapt to different system architecture requirements.

[0065] In addition, it should be noted that a virtual channel is a logical channel simulated by software. On a physical level, virtual channels share the same XDMA channel, but on a logical level, the independence of the data path is maintained through data source identification, independent buffer, and other mechanisms to achieve logical isolation of multiple pieces of multimedia data.

[0066] It should be noted that the XDMA channel referred to in this embodiment essentially refers to a physical hardware DMA channel based on a PCIe bus.

[0067] In this embodiment, a corresponding number of virtual channels are established for a single XDMA channel based on the number of data source identifications, and an independent memory buffer is allocated for each virtual channel.

[0068] As a feasible implementation, a virtual channel manager implemented by a driver program can be used. The virtual channel manager includes a channel allocation module, a buffer management module, and a transmission scheduling module. The channel allocation module creates a corresponding virtual channel according to the number of data source identifications, i.e., one virtual channel for one piece of multimedia data; the buffer management module allocates an independent memory buffer for each virtual channel; and the transmission scheduling module uses a time division multiplexing mechanism to coordinate data transmission of each virtual channel.

[0069] Step S30: parsing the received combined transmission frame according to the data source identification and the timing identification, and determining the distribution position of the logical data segment in the memory block through address calculation.

[0070] It should be noted that the address calculation refers to a calculation process of determining the storage address of the logical data segment in the host memory according to the identification information of the frame header, the memory block size, the data length of the logical data segment and the like. The memory block refers to a fixed-size memory block in the host memory, and the memory block size in the XDMA driver is usually 4096 bytes. The distribution position refers to the storage interval of the logical data segment in the memory block, including the target memory block to which the logical data segment belongs, the page offset and the data length.

[0071] As a feasible implementation, the frame header of each logical data segment in the combined transmission frame is first parsed to obtain the data source identification and the timing identification of each logical data segment, then the cycle round in which the logical data segment is located is determined through the timing identification, and then the target memory block to which each logical data segment belongs is determined based on the cycle round, the preset memory block size, the frame header length and the data length of the logical data segment, and the page offset is calculated, and finally the distribution position is obtained based on the target memory block, the data length and the page offset.

[0072] Step S40: based on the distribution position, the data source identification and the timing identification, the combined transmission frame is split and reorganized into each of the multimedia data.

[0073] It should be noted that the split and reorganization refers to data segmentation of the logical data segment in the combined transmission frame according to the number of multimedia paths to which it belongs, and splicing into complete multimedia data of each path in the original time sequence.

[0074] As a feasible implementation, after the host end receives the combined transmission frame, the frame header is first separated according to the distribution position, and only the multimedia slice data is retained; then each multimedia slice data in the combined transmission frame is inserted into the linked list corresponding to its data source identification with the data source identification as the hash key, and the linked list nodes are arranged in ascending order according to the timing identification, so as to ensure that all multimedia slice data of the same data source maintains the original time sequence, and the reorganization of each multimedia data is completed. When it is detected that all multimedia slice data under the same data source identification has arrived, that is, the linked list contains all multimedia slice data with timing identification, the content of the linked list is written into the ring buffer of the path (according to the data source identification) pre-allocated once, and the application layer is notified through the epoll event, so that the user process can directly read, thereby completing the split and reorganization and transmission of the combined transmission frame.

[0075] Step S50: output each of the multimedia data to the application layer through the corresponding virtual channel.

[0076] It should be noted that the application layer refers to a user layer software module that receives and processes multimedia data for playing or other operations, such as a video player or audio processing software. In this embodiment, the application layer can read the multimedia data of each virtual channel after path reorganization by calling the read function.

[0077] As a feasible implementation, step S50 further includes steps S501-S502 before step S50:

[0078] Step S501: According to the timing identifier, data verification is performed on each path of the reorganized multimedia data.

[0079] Step S502: When detecting that the data of the reorganized multimedia data is not continuous, triggering the data retransmission mechanism corresponding to the virtual channel.

[0080] It should be noted that data verification refers to a process of verifying data transmission integrity by analyzing the timing continuity of reorganized multimedia data. The timing identifier, as the cycle count information embedded in the original data, provides a time dimension reference for verification.

[0081] As a feasible implementation, a timing verification queue is maintained for each path of multimedia data, and the timing identifier of the received data segment is recorded in order of cycle round. When traversing the reorganized data stream, the timing identifier of each data segment is extracted and compared with the expected identifier in the queue. If the identifiers are continuous and there is no missing, it is determined that the data is complete; if there is identifier skipping or repetition, it is determined that the data is not continuous.

[0082] This embodiment encapsulates multiple multimedia data into a combined transmission frame, transmits and establishes a corresponding virtual channel using a single XDMA channel, and combines identifier analysis, address calculation, cross-page splicing, and reorganization steps to solve the problem that one physical channel can only transmit one multimedia data in traditional XDMA transmission. It realizes the transmission of multiple multimedia data through a single XDMA channel under the limitation of PCIE bandwidth, without the need to increase equipment or upgrade PCIE bandwidth, thereby reducing user cost and improving data transmission efficiency.

[0083] To help understand the implementation process of the multimedia data transmission method based on multiplexing XDMA in this embodiment, please refer to Figure 2 , Figure 2 An overall framework process schematic diagram of a multimedia data transmission method based on multiplexing XDMA is provided, specifically:

[0084] The multi-channel multimedia data output by a multi-channel multimedia data source (such as a device for collecting) is first connected to the XDMA channel (xdma0 channel and xdma1 channel) of the FPGA end, and the parallel processing capability of the FPGA is used to receive and send the multi-channel input data.

[0085] The multi-channel multimedia data is then transmitted to the CPU (host end) side in the XDMA transmission protocol through the PCIe link (the link corresponding to the xdma0 channel and the xdma1 channel), and the efficient multiplexing characteristics of the XDMA are used to enable the multi-channel data to be transmitted in order and concurrently on the PCIe bus.

[0086] After the multi-channel multimedia data reaches the CPU side, it is written into the corresponding memory area for temporary storage, and the CPU performs segmentation and reorganization processing on the received data in the memory based on the multi-channel multiplexing XDMA-based multimedia data transmission method (frame header identification analysis, memory distribution positioning, cross-page splicing, and data reorganization) in the embodiments of the present application; each piece of multi-channel multimedia data obtained by reorganization is sent from the CPU side memory to the terminal device (such as a plurality of display terminals) through the multi-channel output interface (virtual channel), thereby realizing efficient collection, transmission, and distribution of multi-channel multimedia data. The entire process is based on the heterogeneous architecture of FPGA+CPU, cooperates with the XDMA multiplexing mechanism, guarantees the high bandwidth and low delay of parallel transmission of multi-channel data, and adapts to the multimedia data processing needs of multi-terminal scenarios.

[0087] Further, Figure 3 An XDMA driving flowchart of the multi-channel multiplexing XDMA-based multimedia data transmission method is provided, and specifically:

[0088] The user layer triggers the kernel layer XDMA driving work by means of the Read operation of the interface calling layer through the real device node (such as xdma0_c2h_0 and xdma0_c2h_1) and the virtual device node (such as xdma0_c2h_vir_0, xdma0_c2h_vir_1, xdma0_c2h_vir_2, and xdma0_c2h_vir_3). The XDMA driving first performs reset to enable the FPGA to synchronously acquire the FPGA configuration parameters (information such as the number of cycles of each channel in a frame and the data size of each channel in a single cycle), and then completes the Xdma engine initialization based on these configuration parameters, starts the engine, and automatically loads the interrupt service thread to build the data transmission basic environment. A frame in the embodiments refers to a combined transmission frame.

[0089] The multi-path multimedia data output by a multi-path multimedia data source (such as a device for capturing) is preprocessed by hardware logic at an FPGA end, and then enters an XDMA channel queue of a kernel layer XDMA driver. The XDMA driver schedules the data in the queue according to a preconfigured multiplexing rule, encapsulates the multi-path multimedia data into a transmission unit conforming to a PCIe protocol, that is, a combined transmission frame.

[0090] Subsequently, the transmission unit transmits the data to a CPU (host end) through a PCIe link. The XDMA driver waits for the FPGA to finish sending a frame of data, and then acquires a frame of data transmitted by the FPGA. Then, the XDMA driver is responsible for analyzing the PCIe data packet on the CPU side, writes the data of the combined transmission frame into a specified area of the CPU memory, and performs other processing according to the memory distribution position in the above embodiment.

[0091] Meanwhile, the XDMA driver monitors the data transmission state. If cross-memory block fragmentation occurs, a cross-page splicing operation is triggered. According to the data source identifier and the timing identifier in the frame header, the logical data segments are spliced, the complete multimedia slice data is extracted after removing the frame header, and the reconstruction of each path of multimedia data is completed.

[0092] Finally, the multi-path multimedia data obtained by reconstruction is released from the memory and transmitted to the user layer through data replication, that is, distributed to the corresponding upper-layer application or terminal device through different drive interfaces. The combined transmission frame is divided according to the distribution position, data source identifier, and timing identifier, and the payload data of each path of multimedia data is extracted. Then, after each path of multimedia data is reconstructed, the data is transmitted to the user layer through data replication.

[0093] Based on the above embodiments of the present application, in the second embodiment of the present application, the same or similar contents as the above first embodiment can be referred to the above description, and will not be described in detail. On this basis, please refer to Figure 4 , in the multi-path multiplexing XDMA-based multimedia data transmission method, step S10 includes steps S110-S130:

[0094] Step S110: dividing each path of the multimedia data into a plurality of multimedia slice data, and adding a frame header containing the data source identifier and the timing identifier to the head of each multimedia slice data to obtain the logical data segment, wherein the timing identifier is used to mark the cycle round in which the logical data segment is located.

[0095] It should be noted that the multimedia slice data refers to a data unit divided by a continuous multimedia data stream according to a fixed length, and the size is usually aligned with the memory block size. The frame header is identification information attached to the head of the multimedia slice data, including data source identification and timing identification. The logical data segment is a transmission basic unit composed of the frame header and the multimedia slice data.

[0096] As a feasible implementation, the hardware logic resources of the FPGA can be used to generate the multimedia slice data by using the shift register, the counter and the multiplexer to intercept the input multi-channel multimedia data stream according to a fixed byte number, and then the frame header format is constructed by using the display look-up table (Look-Up-Table, LUT) to splice the data source identification and the timing identification to the head of the multimedia slice data to form the logical data segment. The data source identification can be assigned by the external configuration register, and the timing identification can be generated in real time by the cyclic counter.

[0097] Step S120: According to the preset cycle number, in each cycle, the logical data segments corresponding to each channel of the multimedia data are arranged in sequence according to the order of the data source identification, to generate a single-cycle data sequence, and the single-cycle data sequence contains one logical data segment of each channel of the multimedia data.

[0098] It should be noted that the preset cycle number refers to the transmission cycle number for controlling the cyclic scheduling transmission of the multi-channel multimedia data. The single-cycle data sequence refers to the collection of the logical data segments of each channel of the multimedia data arranged in a predetermined order (such as the order of the data source identification) within a transmission cycle.

[0099] Step S130: According to the timing identification, the multiple single-cycle data sequences are spliced in sequence to obtain the combined transmission frame.

[0100] It should be noted that the combined transmission frame is a complete data packet formed by connecting the heads and tails of the multiple single-cycle data sequences in the order of the timing identification. The data packet can be directly transmitted through the XDMA channel for efficient transmission. The timing identification is used in this embodiment to ensure that the logical data segments of different cycles can still maintain the correct timing relationship after splicing.

[0101] It should be noted that one combined transmission frame (hereinafter referred to as “one frame”) in this embodiment is not a traditional picture data amount, such as 1080p 1920x1080x3 bytes (rgb format), but refers to the data amount transmitted by the FPGA to the driver layer at a time. The specific data amount can be confirmed according to the number of parallel transmission multimedia channels, the cycle number, and the input amount of single-channel multimedia data set in the actual application.

[0102] Exemplarily, in order to help understand the implementation flow of the multiplexing XDMA-based multimedia data transmission method obtained after the first embodiment is combined with the above-mentioned embodiment, please refer to Figure 5 , Figure 5 A structure diagram of a combined transmission frame in a multiplexing XDMA-based multimedia data transmission method is provided, and specifically:

[0103] In order to facilitate understanding, the embodiment is set to transmit 4-way multimedia data in parallel, and a frame is set to 60 cycles. The input amount of single-way multimedia data in each cycle (i.e. the data amount of one multimedia slice data in one way of multimedia data) is 1024x16 bytes, and the data amount of one frame is 4x60x(16+1024x16) bytes.

[0104] As shown in Figure 5 , first, each way of multimedia data is divided into a plurality of multimedia slice data, and the size of each multimedia slice data is 1024x16 bytes. The header of each multimedia slice data is added with a frame header containing data source identification and timing identification, forming a standard logical data segment. Among them, "multimedia data input 1 frame header" represents the frame header of multimedia slice data, "multimedia data input 1 data" represents one multimedia slice data, and "multimedia data input 1 frame header" and "multimedia data input 1 data" together form a logical data segment. In addition, the frame header adopts a fixed format of "0000 0000 cycle number+data source identification 55aa aa55 0000 0000 0000".

[0105] Taking the multimedia data input 1 data of the fifth cycle as an example, the format of the frame header is "0000 0000 040155aa aa55 0000 0000 0000", wherein 04 represents the 5th cycle (the cycle in the embodiment is counted from 0), 01 represents multimedia data input 1 data, i.e. distinguishing the data from which way of multimedia data, and 55aa aa55 represents the frame header mark of the combined transmission frame, which is used to distinguish whether it belongs to the same combined transmission frame.

[0106] The arrangement of the multimedia slice data in the combined transmission frame follows the cycle rotation sequence: according to the preset cycle number, in each cycle, the logical data segment corresponding to each way of multimedia data is arranged in sequence according to the order determined by the data source identification (such as fixedly in the order of multimedia data input 1 to 4), to form a single-cycle data sequence. Specifically:

[0107] In the first cycle, first, arrange the first logical data segment corresponding to the first multimedia data (including the first multimedia slice data frame header and payload data), and then arrange the first logical data segment corresponding to the second multimedia data, and so on to complete the logical data segment arrangement of the four multimedia data, and then start the data arrangement of the next cycle.

[0108] In the second cycle, first, arrange the second logical data segment corresponding to the first multimedia data, and then arrange the second logical data segment corresponding to the second multimedia data, and so on.

[0109] The combination mode of the multimedia slice data in the embodiment enables the host end to accurately restore the original timing relationship of the multimedia slice data corresponding to each multimedia data by analyzing the "cycle number" and "data source identification" fields in the frame header, thereby realizing efficient multiplexing transmission of multiple data on a single physical channel.

[0110] Based on the above embodiments of the application, in the third embodiment of the application, the same or similar contents as the above embodiments can be referred to the above introduction, and will not be described in detail. On this basis, please refer to Figure 6 , in the multimedia data transmission method based on multiplexing XDMA, step S30 includes steps S310-S340:

[0111] Step S310: Analyze the frame header of the head of each logical data segment in the combined transmission frame, and obtain the data source identification and the timing identification corresponding to the logical data segment.

[0112] It should be noted that the logical data segment refers to a transmission unit formed by adding the frame header to the multimedia slice data. The frame header is fixed format data at the head of the logical data segment, and is used to carry identification information related to transmission.

[0113] As a feasible implementation manner, the driver layer scans the memory data of the combined transmission frame, locates the frame header position of each logical data segment according to the fixed starting identification (such as a specific byte sequence) of the frame header, and then extracts the data source identification and timing identification according to the frame header format, such as reading the corresponding code from the specified byte position of the frame header to determine the data source and transmission timing.

[0114] Step S320: Determine the cycle round of the logical data segment through the timing identification.

[0115] It should be noted that the cycle round refers to the transmission cycle number of the logical data segment in the transmission process of the combined transmission frame.

[0116] As a feasible implementation, the timing identifier extracted in step S310 corresponds to a preset cycle round encoding rule. For example, the cycle round number starts from 0. When the timing identifier is N, the current cycle round is N+1.

[0117] For example, the timing identifier "0001" corresponds to the second cycle round, and "0002" corresponds to the third cycle round. The cycle round of each logical data segment is determined through the corresponding relationship.

[0118] In step S330, based on the cycle round, a preset memory block size, a frame header length of the frame header, and a data length of the logical data segment, a target memory block to which the logical data segment belongs is determined, and an in-page offset of the logical data segment in the target memory block is calculated.

[0119] It should be noted that the memory block size refers to a fixed size of each memory block in system memory management. For example, the memory block size in XDMA drive is usually 4096 bytes. The header length refers to the number of bytes occupied by the frame header. The data length of the logical data segment refers to the total number of bytes of the logical data segment (including the frame header and the multimedia slice data). The target memory block refers to the memory block to which the logical data segment belongs when stored in the memory. The in-page offset refers to the byte distance of the starting storage position of the logical data segment in the target memory block relative to the starting position of the memory block.

[0120] As a feasible implementation, the overall offset position of the logical data segment in the combined transmission frame is calculated according to the cycle round, the number of logical data segments transmitted in each cycle round (i.e. the number of parallel multimedia data transmission), and the data length (data amount) of each logical data segment. Then, the memory block (i.e. the target memory block) corresponding to the offset position is determined in combination with the preset memory block size, and the byte number of the offset position relative to the starting position of the target memory block is calculated to obtain the in-page offset.

[0121] For example, the embodiment sets 4-way parallel transmission of multimedia data, and 4 logical data segments (corresponding to 4 ways) are synchronously transmitted in each cycle round. A combined transmission frame contains 60 cycles, the input amount of single-way multimedia data in each cycle (i.e. the data amount of one multimedia slice data) is 1024*16 bytes, the frame header is fixed at 16 bytes, and the data amount of one frame is 4*60*(16+1024*16) bytes. The memory block size in XDMA drive is usually 4096 bytes. Then, the overall offset position and the storage position of the second-way logical data segment in the first cycle round in the combined transmission frame are calculated as follows:

[0122] Firstly, the base offset of the first round of cycles is determined to be 0 (as it is the first round of cycles, there is no other cycle in the prologue, so the data amount of the prologue cycle does not need to be accumulated). Secondly, the single-round-in-cycle offset of the second logical data segment in the first round of cycles is calculated. Since the logical data segments of each logical data segment are arranged in order in each round of cycles, the second logical data segment is preceded by the first logical data segment, so the single-round-in-cycle offset of the second logical data segment in the first round of cycles is 1 data length of the logical data segment (the data length of the first logical data segment), i.e. 16+1024x16=16400 bytes. Therefore, the overall offset position of the second logical data segment = the base offset of the prologue cycle + the single-round-in-cycle offset, i.e. the overall offset position = 0+1x(16+1024x16) = 16400 bytes. And the memory block size is 4096 bytes.

[0123] Then the memory block distribution is calculated, memory block distribution = overall offset position / memory block size, the quotient is the number of occupied memory blocks, and the remainder is the in-page offset. Therefore, the number of occupied memory blocks is 4, and the in-page offset is 16 bytes. Therefore, the overall offset position of the second logical data segment in the first round of cycles is 16400 bytes, and the storage position starts from the 5th (4+1) memory block, and the in-page offset in the 5th memory block is 16 bytes.

[0124] Step S340: Based on the target memory block, the data length and the in-page offset, the distribution position of the logical data segment in the memory block is obtained.

[0125] It should be noted that the distribution position refers to the specific storage range of the logical data segment in the memory block, including all target memory blocks involved, the in-page offset in each target memory block and the byte length occupied in the block.

[0126] It should be noted that the distribution position is determined by the physical base address of the target memory block and the in-page offset, and the logical address needs to be converted into the physical address for hardware access.

[0127] Exemplarily, based on the target memory block (starting from the 5th memory block), the data length (16400 bytes) and the in-page offset (16 bytes) of the second logical data segment of the first round of the cycle determined in step S330, the specific distribution of the logical data segment in the memory block is further analyzed: in the 5th memory block, the data is stored starting from the offset of 16 bytes, and since the total size of the memory block is 4096 bytes, the number of bytes that can be stored in the 5th block is 4096-16=4080 bytes; the remaining data length is 16400-4080=12320 bytes, which is continuously stored in the subsequent memory blocks, the 6th memory block can be stored full of 4096 bytes, the remaining 12320-4096=8224 bytes; the 7th memory block is full of 4096 bytes again, and the remaining 8224-4096=4128 bytes; the 8th memory block stores 4128 bytes, and the logical data segment is stored.

[0128] As a feasible implementation, the address mapping table (such as MMU page table) can be used to record the distribution position of each logical data segment, and the actual physical address can be calculated by the base register + offset (physical address=target page base address+in-page offset).

[0129] Based on the above embodiments of the present application, in the fourth embodiment of the present application, the same or similar contents as the above embodiments can be referred to the above introduction, and the following will not be repeated. On this basis, please refer to Figure 7 , before step S40, the multimedia data transmission method based on multiplexing XDMA includes steps S401-S402:

[0130] Step S401: according to the timing identifier, determine the multimedia slice data in the same cycle round.

[0131] It should be noted that the multimedia slice data in the same cycle round refers to each road of multimedia data sent in the same transmission period, and the cycle number field value in the timing identifier is the same.

[0132] Step S402: when the multimedia slice data in the same cycle round crosses the memory block boundary, perform cross-page data splicing operation.

[0133] It should be noted that the memory block boundary is the start address or end address of the basic unit of system memory management. When the data length of a logical data segment exceeds the capacity of a single memory block, the logical data segment will be stored in at least two adjacent memory blocks, that is, part of the data of the logical data segment is stored in the current memory block, and the remaining part is stored in the next adjacent memory block. The target of the cross-page data splicing operation is to combine the data divided by the memory block boundary into a complete logical data segment, so as to ensure the continuity and integrity of the data.

[0134] It should be noted that in the embodiment, the trigger condition of the cross-page data splicing operation has particularity: when the data segments of two logical data segments belonging to different data source identifiers (such as multimedia data input 1 data and multimedia data input 2 data) exist in the same memory block at the same time, the cross-page splicing operation needs to be performed. Specifically, if only a logical data segment of a single data source identifier is stored in a memory block (even if the logical data segment is stored in adjacent memory blocks in fragments), splicing is not required.

[0135] When it is detected that the data segments of the logical data segments of multiple data source identifiers are contained in the same memory block, for example, the first 16 bytes of the memory block 5 belong to the tail of the logical data segment of the multimedia data input 1 data, and all the parts behind the memory block 5 belong to the head of the logical data segment of the multimedia data input 2 data, the data segments across the data sources need to be reorganized according to the data source identifier and the time sequence identifier, so as to ensure that the logical data segments of each multimedia data remain independent and time sequence correct after reorganization.

[0136] As a feasible implementation manner, when the kernel driver layer performs data segmentation for multimedia data reorganization, after obtaining the logical data segment corresponding to each route of multimedia data, the kernel driver layer performs a frame header removing operation on each route of logical data segment according to the distribution position, and only the multimedia slice data in the logical data segment is retained.

[0137] As another feasible implementation manner, step S402 includes steps S4021-S4022:

[0138] Step S4021: According to the order of the data source identifier, when it is detected that the end address of the previous route of the multimedia slice data and the start address of the next route of the multimedia slice data are located in the same memory block, the memory block containing the two routes of the multimedia slice data is determined as a to-be-spliced memory block.

[0139] It should be noted that the to-be-spliced memory block refers to a memory block surface containing cross-page stored multimedia slice data, wherein the tail segment of the previous route of multimedia slice data and the head segment of the next route of multimedia slice data are stored at the same time.

[0140] Step S4022: Splice the remaining data belonging to the previous one of the multimedia slice data in the to-be-spliced memory block to the end of the previous memory block adjacent to the to-be-spliced memory block.

[0141] As a feasible implementation, the splicing can be implemented by using a descriptor-based DMA engine, which includes a descriptor generator and a data moving unit. The descriptor generator automatically creates a splicing operation descriptor according to the memory block boundary detection result, and the data moving unit performs actual DMA transmission to copy the to-be-spliced data segment to the target position.

[0142] Exemplarily, in order to facilitate understanding of the implementation process of the multiplexing XDMA-based multimedia data transmission method obtained after the above embodiment, please refer to Figure 8 , Figure 8 A memory block splicing schematic diagram in a multiplexing XDMA-based multimedia data transmission method is provided, and specifically:

[0143] In the XDMA driver, each memory block is fixed as 4096 bytes. In order to facilitate understanding, the embodiment sets the data amount of each loop of each multimedia slice data as 16x1024 bytes. From the data amount calculation, 16KB of single multimedia slice data needs exactly 4 memory blocks (4x4096=16384 bytes). However, in the actual process of packaging and combining the transmission frame, 16 bytes of frame header information are additionally added to each multimedia slice data, so that the total length of the single logical data segment (frame header+single multimedia slice data) reaches 16400 bytes (16x1024+16).

[0144] When the combined transmission frame is transmitted to the host memory through a single XDMA channel, the driver layer recognizes the combined transmission frame stored in the continuous memory block. Each logical data segment in the combined transmission frame includes 16 bytes of frame header and payload data (referring to multimedia slice data). Taking the first logical data segment of the first loop as an example, the 16384 bytes of payload data fill the first 4 memory blocks, but due to the existence of the frame header, there are still 16 bytes of data extending to the first 16 bytes of the fifth memory block. At this time, the frame header of the second logical data segment is stored from the 17th byte of the fifth memory block.

[0145] Since the frame header is only used for routing and timing control in the transmission process, and does not contain actual multimedia content, retaining these control information will lead to complex data processing logic and may affect the accuracy of the final data parsing. Therefore, when the driver layer receives the combined transmission frame transmitted through the XDMA channel, it needs to perform frame header removal and cross-memory block data splicing operations. Specifically, when the driver layer starts processing each road of data, it will first remove the 16-byte frame header at the head of the logical data segment, and then perform cross-memory block data splicing. Specifically, taking the first logical data segment of the first loop as an example, the tail 16 bytes of the payload data share the 5th memory block with the frame header of the second data. If the frame header is removed directly, the tail content of the first data will be lost.

[0146] Therefore, when the driver layer obtains each road of data, it parses the frame header information at the head of each logical data segment to obtain the data source identifier and timing identifier, and then performs address calculation based on these identifiers to locate the memory block boundary to be spliced and perform cross-page data splicing operation, and then removes the frame header to only retain the multimedia slice data.

[0147] Specifically, taking the first logical data segment of the first loop as an example, when the first logical data segment of the first loop is obtained, the driver layer first reads the "0000 0001 aa55 55aa 0000 0000 0000" information in the frame header, confirms that it is the starting segment of the first data (identifier 01), and then finds that the 16384-byte payload data theoretically occupies 4 memory blocks, but due to the existence of the frame header, the last 16 bytes of the first logical data segment extend to the first 16 bytes of the 5th memory block. At this time, the driver layer will perform memory block splicing to splice the first 16 bytes of the 5th memory block to the end of the 4th memory block to make the first multimedia slice data complete, and ensure the integrity and continuity of the single multimedia slice data when the data block is segmented in the subsequent multimedia data reorganization, according to the cycle and data source identifier in the frame header. When retaining the first multimedia slice data of the first loop.

[0148] Based on the above embodiments of the present application, in the fifth embodiment of the present application, the same or similar contents as the above embodiments can be referred to the above introduction, and will not be described in detail. On this basis, please refer to Figure 9 , in the multimedia data transmission method based on multiplexing XDMA, step S40 includes steps S410-S430:

[0149] Step S410: According to the data source identifier, determine the number of multimedia paths to which each multimedia slice data in the combined transmission frame belongs.

[0150] It should be noted that the multimedia channel refers to the source channel of the parallel transmission of the multimedia data distinguished by the data source identifier in the frame header. These source channels can correspond to different input devices (such as a camera, a microphone) or different data streams (such as different format data output by the same device). The driver layer can identify the data source identifier to determine which channel each multimedia slice data comes from, thereby accurately distinguishing the parallel data.

[0151] As a feasible implementation, the driver layer establishes a mapping table of the data source identifier and the multimedia slice data by analyzing the data source identifier of each logical data segment in the combined transmission frame (the corresponding relationship has been recorded before the frame header is removed), for example, the identifier "01" is mapped to the first multimedia data, to determine the specific channel to which each multimedia slice data belongs.

[0152] Step S420: The multimedia slice data in the combined transmission frame is data segmented according to the multimedia channel to form independent multimedia slice data queues of each channel.

[0153] It should be noted that data segmentation is to classify the multimedia slice data alternately stored in the combined transmission frame according to the data source identifier carried in the frame header, and collect the multimedia slice data belonging to the same data source identifier into the corresponding data queue, thereby realizing the separation and independent management of the multi-channel multimedia data. The independent multimedia slice data queue of each channel refers to an ordered set formed by all multimedia slice data of the same multimedia data according to the transmission time sequence (i.e., the time sequence identifier).

[0154] As a feasible implementation, based on the multimedia channel determined in step S410, all multimedia slice data is traversed, and the data belonging to the same channel is sequentially stored in the corresponding queue, for example, four queues are created for four multimedia data, and all multimedia slice data with the data source identifier "01" is stored in the first queue.

[0155] Step S430: The multimedia slice data queues of each channel are time sequence reorganized according to the order of the cycle round determined by the time sequence identifier, to reconstruct the multimedia data of each channel.

[0156] It should be noted that the order of the cycle round determined by the time sequence identifier is the round number arranged according to the cycle in the transmission of the combined transmission frame. Time sequence reorganization is an operation of splicing the multimedia slice data of the same channel into a complete data stream according to the original transmission time sequence. The multimedia data of each channel is the independent multimedia data stream recovered after reorganization, which is consistent with the data before transmission.

[0157] As a feasible implementation, for each multimedia slice data queue, the slice data corresponding to the time sequence identifier (cyclic round) in the queue is sorted, for example, 60 cycles are set for a frame, the multimedia slice data with time sequence identifiers 0, 1, …, 59 in the first queue are extracted in sequence, and the first multimedia data stream is obtained by concatenating the head and tail through a memory copy operation.

[0158] The embodiment first separates the mixed data in the combined transmission frame according to the data source identifier, and then ensures the correct order of multimedia data reorganization according to the time sequence identifier, thereby avoiding the problems of mixed storage and time sequence disorder that are prone to occur when a single XDMA channel transmits multiple data, and ensuring the accuracy of data separation and the integrity of reorganization through clear identifier corresponding and sequence control, so as to finally restore the combined transmission frame of mixed transmission to multiple independent and continuous multimedia data streams. This process not only fully utilizes the bandwidth advantage of the XDMA channel, but also realizes the ordered transmission and restoration of multiple data through logical layer splitting and reorganization, and meets the use demand of the application layer for multiple independent multimedia data.

[0159] The embodiment of the present application provides a multimedia data transmission device based on multiplexing XDMA, which comprises at least one processor and a memory in communication connection with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the multimedia data transmission method based on multiplexing XDMA in the above embodiment one.

[0160] Reference will be made to the following Figure 10 which shows a structural schematic diagram of the multimedia data transmission device based on multiplexing XDMA suitable for being used to implement the embodiment of the present application. The multimedia data transmission device based on multiplexing XDMA in the embodiment of the present application can comprise various hardware and software components for implementing the multimedia data transmission method based on multiplexing XDMA. Figure 10 The multimedia data transmission device based on multiplexing XDMA shown is only an example, and should not bring any limitation to the function and use range of the embodiment of the present application.

[0161] As Figure 10As shown, the multiplexed XDMA based multimedia data transmission device can include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to programs stored in a read only memory (ROM) 1002 or loaded from a storage device 1003 into a random access memory (RAM) 1004. Various programs and data required for operation of the multiplexed XDMA based multimedia data transmission device are also stored in the random access memory 1004. The processing device 1001, the read only memory 1002, and the random access memory 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, etc.; an output device 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; the storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the multiplexed XDMA based multimedia data transmission device to communicate with other devices wirelessly or by wire to exchange data. Although the multiplexed XDMA based multimedia data transmission device having various systems is shown in the figure, it should be understood that all of the shown systems are not required to be implemented or provided. More or less systems can be alternatively implemented or provided.

[0162] In particular, the processes described above with reference to the flowcharts can be implemented as a computer software program according to embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer readable medium, the computer program containing program code for performing the methods illustrated by the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network through the communication device, or installed from the storage device 1003, or installed from the read only memory 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the methods of embodiments of the present disclosure are performed.

[0163] The multimedia data transmission device based on multiplexing XDMA provided by the application adopts the multimedia data transmission method based on multiplexing XDMA in the above embodiment, and can solve the technical problem that a single physical channel cannot simultaneously transmit multiple independent multimedia data streams in the traditional XDMA architecture. Compared with the prior art, the multimedia data transmission device based on multiplexing XDMA provided by the application has the same beneficial effects as the multimedia data transmission method based on multiplexing XDMA provided by the above embodiment, and other technical features in the multimedia data transmission device based on multiplexing XDMA are the same as the features disclosed in the previous embodiment method, which will not be repeated here.

[0164] It should be understood that parts of the present application can be realized by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0165] The above is merely specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0166] The embodiment of the present application provides a computer readable storage medium having computer readable program instructions (i.e. computer programs) stored thereon, and the computer readable program instructions are used to execute the multimedia data transmission method based on multiplexing XDMA in the above embodiment.

[0167] The computer readable storage medium provided in the application may, for example, be a U disk, but is not limited to an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, system, or device, or any combination of the above. More specific examples of the computer readable storage medium may include, but are not limited to, an electrical connection with one or more conductive wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the embodiment, the computer readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer readable storage medium can be transmitted by any suitable medium, including but not limited to an electrical wire, an optical cable, a radio frequency (RF), and the like, or any suitable combination of the above.

[0168] The above computer readable storage medium may be contained in a multiplex XDMA-based multimedia data transmission device, or may exist separately and not be assembled into a multiplex XDMA-based multimedia data transmission device.

[0169] The above computer readable storage medium carries one or more programs, which, when executed by the multiplex XDMA-based multimedia data transmission device, cause the multiplex XDMA-based multimedia data transmission device to: encapsulate multiple multimedia data into a combined transmission frame according to a preset format, wherein each piece of multimedia data is divided into a plurality of logical data segments containing a data source identifier and a timing identifier; transmit the combined transmission frame to a host memory through a single XDMA channel, and establish a virtual channel corresponding to the multiple multimedia data for the single XDMA channel; analyze the received combined transmission frame according to the data source identifier and the timing identifier, determine the distribution position of the logical data segment in the memory block through address calculation; based on the distribution position, the data source identifier, and the timing identifier, split and reorganize the combined transmission frame into each piece of multimedia data; and output each piece of multimedia data to an application layer through the corresponding virtual channel.

[0170] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0171] The flow diagrams and the block diagrams in the drawings are illustrations of architectures, functionalities, and operations of possible implementations of systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flow diagrams or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may

[0172] The modules involved in the embodiments of the present application can be implemented in software or hardware. In some cases, the names of the modules do not constitute a limitation on the modules themselves.

[0173] The readable storage medium provided by the present application is a computer readable storage medium, which stores computer readable program instructions (i.e., a computer program) for executing the above-mentioned multimedia data transmission method based on multiplexing XDMA, and can solve the technical problem that a single physical channel cannot simultaneously transmit multiple independent multimedia data streams in a traditional XDMA architecture. Compared with the prior art, the computer readable storage medium provided by the present application has the same beneficial effects as the above-mentioned multimedia data transmission method based on multiplexing XDMA, and will not be described here.

[0174] The embodiment of the present application provides a computer program product, comprising a computer program which, when executed by a processor, implements the steps of the multimedia data transmission method based on multiplexed XDMA.

[0175] The computer program product provided by the present application can solve the technical problem that a single physical channel cannot simultaneously transmit multiple independent multimedia data streams in the conventional XDMA architecture. Compared with the prior art, the beneficial effects of the computer program product provided by the embodiment of the present application are the same as those of the multimedia data transmission method based on multiplexed XDMA provided by the above embodiment, and are not described herein.

[0176] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings of the present application, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

[0177] It should be noted that in this paper, the term "comprise", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or system including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or system. Without more limitations, the element defined by the statement "comprises a" does not exclude the existence of another identical element in the process, method, article or system including the element.

[0178] From the above description of the embodiments, those skilled in the art can clearly understand that the above embodiment method can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment.

[0179] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings of the present application, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for transmitting multimedia data based on multiplexed XDMA, characterized by, The multimedia data transmission method based on multiplexing XDMA comprises: The multi-channel multimedia data is packaged into a combined transmission frame according to a preset format, wherein each channel of the multimedia data is divided into a plurality of logical data segments containing data source identification and timing identification; The combined transmission frame is transmitted to the host memory through a single XDMA channel, and a virtual channel corresponding to the multi-channel multimedia data is established for the single XDMA channel; According to the data source identification and the timing identification, the received combined transmission frame is parsed, and the distribution position of the logical data segment in the memory block is determined through address calculation; Based on the distribution position, the data source identification and the timing identification, the combined transmission frame is split and reorganized into each channel of the multimedia data; Each channel of the multimedia data is output to the application layer through the corresponding virtual channel.

2. The multiplexed XDMA-based multimedia data transmission method of claim 1, wherein, The step of packaging the multi-channel multimedia data into a combined transmission frame according to a preset format comprises: Each channel of the multimedia data is divided into a plurality of multimedia slice data, and a frame header containing the data source identification and the timing identification is added to the head of each multimedia slice data to obtain the logical data segment, wherein the timing identification is used to mark the cycle round in which the logical data segment is located; According to a preset cycle number, in each cycle, the logical data segments corresponding to each channel of the multimedia data are arranged in order according to the data source identification to generate a single-cycle data sequence, and the single-cycle data sequence contains one logical data segment of each channel of the multimedia data; According to the timing identification, a plurality of single-cycle data sequences are continuously spliced to obtain the combined transmission frame.

3. The multiplexed XDMA-based multimedia data transmission method of claim 1, wherein, The step of parsing the received combined transmission frame according to the data source identification and the timing identification, and determining the distribution position of the logical data segment in the memory block through address calculation comprises: Parsing the frame header at the head of each logical data segment in the combined transmission frame to obtain the data source identification and the timing identification corresponding to the logical data segment; Determine the cycle round in which the logical data segment is located through the timing identification; Based on the cycle round, the preset memory block size, the frame header length of the frame header and the data length of the logical data segment, determine the target memory block to which the logical data segment belongs, and calculate the page offset of the logical data segment in the target memory block; Based on the target memory block, the data length and the page offset, the distribution position of the logical data segment in the memory block is obtained.

4. The multiplexed XDMA-based multimedia data transmission method of claim 1, wherein, Before the step of splitting and reorganizing the combined transmission frame into each channel of the multimedia data based on the distribution position, the data source identification and the timing identification, further comprising: According to the timing identification, determine the multimedia slice data in the same cycle round; When the multimedia slice data in the same cycle round crosses the memory block boundary, perform cross-page data splicing operation.

5. The multiplexed XDMA-based multimedia data transmission method of claim 4, wherein, The step of performing cross-page data splicing operation when the multimedia slice data in the same cycle round crosses the memory block boundary comprises: According to the order of the data source identifiers, when it is detected that the end address of the previous multimedia slice data and the start address of the next multimedia slice data are located in the same memory block, the memory block containing the two multimedia slice data is determined as a to-be-spliced memory block; The remaining data in the to-be-spliced memory block belonging to the previous multimedia slice data is spliced to the end of the previous memory block adjacent to the to-be-spliced memory block.

6. The multiplexed XDMA-based multimedia data transmission method of claim 1, wherein, The step of splitting and recombining the combined transmission frame into each multimedia data based on the distribution position, the data source identifier and the time sequence identifier comprises: According to the data source identifier, the number of multimedia paths to which each multimedia slice data in the combined transmission frame belongs is determined; The multimedia slice data in the combined transmission frame is data segmented according to the number of multimedia paths, forming a queue of independent multimedia slice data of each path; According to the order of the cycle round determined by the time sequence identifier, the queue of multimedia slice data of each path is time sequence recombined to reconstruct the multimedia data of each path.

7. The multiplexed XDMA-based multimedia data transmission method of claim 1, wherein, The step of transmitting the combined transmission frame to the host memory through a single XDMA channel and establishing a virtual channel corresponding to the multimedia data of multiple paths for the single XDMA channel comprises: Based on the number of data source identifiers, a corresponding number of virtual channels are established for the single XDMA channel, and an independent memory buffer is allocated for each virtual channel.

8. The multiplexed XDMA-based multimedia data transmission method of claim 4, wherein, Before the step of outputting each multimedia data to the application layer through the corresponding virtual channel, it further comprises: According to the time sequence identifier, the recombined multimedia data of each path is data checked; When it is detected that the data of the recombined multimedia data is discontinuous, a data retransmission mechanism corresponding to the virtual channel is triggered.

9. A multimedia data transmission apparatus based on multiplexed XDMA, characterized by The multimedia data transmission device based on multiplexing XDMA comprises a memory, a processor and a computer program stored on the memory and executable on the processor, the computer program is configured to implement the steps of the multimedia data transmission method based on multiplexing XDMA as claimed in any one of claims 1 to 8.

10. A storage medium, characterized by The storage medium is a computer readable storage medium, and the storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the multimedia data transmission method based on multiplexing XDMA as claimed in any one of claims 1 to 8.

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