Formation method of semiconductor structure
By forming a first dielectric layer with an etching selectivity on the substrate, the problem of uneven bottom surface of the groove is solved, the consistency of fin height and thickness is achieved, and the performance of the semiconductor structure is improved.
Patent Information
- Application Number
- CN202410513425.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-25
- Publication Date
- 2025-10-31
AI Technical Summary
In existing semiconductor structures, uneven bottom surfaces of grooves cause inconsistencies between the effective height and thickness of the fins, affecting semiconductor performance.
A first dielectric layer with an etch selectivity is formed on the substrate. A groove is formed by using the etch selectivity of the first dielectric layer with the substrate to ensure that the top surface of the substrate is the etch stop position. Then, a flat second channel layer is formed in the groove to ensure that the effective height and thickness of the fin are consistent.
By controlling the flatness of the groove bottom and fins, the performance of the semiconductor structure is improved, and the processing difficulty and probability of electrical failure are reduced.
Smart Images
Figure CN120882023A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.
[0003] Therefore, to reduce the impact of short-channel effects, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. Furthermore, FinFETs have better compatibility with existing integrated circuit manufacturing processes compared to other devices. Summary of the Invention
[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further improve the performance of the semiconductor structure.
[0005] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and an adjacent second region; forming a first dielectric layer on top of the substrate in the second region, the first dielectric layer having an etch selectivity with respect to the substrate; after forming the first dielectric layer, forming a first channel layer on top of the substrate in the first region; removing the first dielectric layer to form a groove surrounded by the sidewalls of the first channel layer and the top surface of the substrate; and forming a second channel layer in the groove.
[0006] Optionally, the step of forming a first dielectric layer on top of the substrate in the second region includes: forming a first dielectric material layer on top of the substrates in the first and second regions; forming a mask layer with a mask opening on top of the first dielectric material layer, the mask opening exposing the top surface of the first dielectric material layer in the first region; using the mask layer as a mask, performing patterning processing on the first dielectric material layer in the first region, and using the first dielectric material layer in the second region as the first dielectric layer.
[0007] Optionally, the step of patterning the first dielectric material layer of the first region includes: removing the first dielectric material layer on the top of the substrate, using the top surface of the substrate of the first region as the etching stop position.
[0008] Optionally, during the patterning process of the first dielectric material layer in the first region, the etching selectivity ratio between the first dielectric material layer and the substrate is greater than 10:1.
[0009] Optionally, the material of the first dielectric layer includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.
[0010] Optionally, the process for forming the first dielectric layer includes a dry etching process.
[0011] Optionally, during the formation of the first channel layer, the top surface of the first channel layer is lower than the top surface of the first dielectric layer.
[0012] Optionally, the top surface of the first channel layer is 50 angstroms to 2000 angstroms below the top surface of the first dielectric layer.
[0013] Optionally, the step of forming the first channel layer includes: growing an epitaxial layer on the substrate surface of the first region by an epitaxial growth process, and using the epitaxial layer as the first channel layer.
[0014] Optionally, the thickness of the first trench layer is 400 angstroms to 1000 angstroms.
[0015] Optionally, after forming the first channel layer and before forming the groove, the method further includes: forming a second dielectric layer on top of the first channel layer; and during the formation of the second channel layer, using the top surface of the second dielectric layer as a stop position.
[0016] Optionally, the step of forming the second dielectric layer includes: thermally oxidizing a surface portion of the first channel layer to form an oxide layer located on the top surface of the first channel layer, and using the oxide layer as the second dielectric layer.
[0017] Optionally, the thickness of the second dielectric layer is 50 angstroms to 300 angstroms in the normal direction of the substrate surface.
[0018] Optionally, the step of forming the second channel layer includes: forming a second channel material layer in the groove, wherein the top surface of the second channel material layer is higher than the top surface of the first channel layer; performing a planarization process on the second channel material layer that is higher than the top surface of the first channel layer; and using the remaining second channel material layer in the groove as the second channel layer.
[0019] Optionally, the process of forming the second channel material layer in the groove includes an epitaxial growth process.
[0020] Optionally, the step of forming the groove includes: using the top surface of the substrate in the first region as the etching stop position, removing the first dielectric layer on the top surface of the substrate in the first region to form a groove surrounded by the sidewalls of the first channel layer and the top surface of the substrate.
[0021] Optionally, with the top surface of the substrate in the first region as the etching stop position, during the process of removing the first dielectric layer on the top surface of the substrate in the first region, the etching selectivity ratio between the first dielectric layer and the substrate is greater than 10:1.
[0022] Optionally, the process for removing the first dielectric layer includes a wet etching process.
[0023] Optionally, the material of the first trench layer includes silicon; the material of the second trench layer includes germanium silicon.
[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0025] This invention provides a method for forming a semiconductor structure. First, a first dielectric layer is formed on top of a substrate in a second region. The first dielectric layer and the substrate have an etching selectivity ratio. Then, a first channel layer is formed on top of the substrate in the first region where the first dielectric layer is exposed. During the process of removing the first dielectric layer to form a groove, the etching selectivity ratio between the first dielectric layer and the substrate can be used to make the top surface of the substrate in the second region serve as the etching stop position, resulting in a high flatness of the bottom surface of the groove. In the subsequent process of forming the second channel layer, the flatness of the bottom surface of the second channel layer can also be high. Correspondingly, in the subsequent process of patterning the second channel layer to form fins, the effective height of the fins can be made consistent with the thickness of the second channel layer, thereby facilitating the control of the effective height of the fins and further improving the performance of the semiconductor structure. Attached Figure Description
[0026] Figures 1 to 3 A schematic diagram of the structural steps corresponding to each step in a method for forming a semiconductor structure.
[0027] Figures 4 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0028] Currently, the performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific method for its formation as an example.
[0029] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step of a semiconductor structure formation method.
[0030] refer to Figure 1 A substrate 10 is provided, the substrate 10 including a first region 10A and a second region 10B adjacent thereto.
[0031] refer to Figure 2 A first channel material layer 11 is formed on the substrate 10.
[0032] refer to Figure 3 Remove the first channel material layer 11 of the second region 10B to form a groove 13 surrounded by the top surface of the substrate 10 and the sidewalls of the remaining first channel material layer 11, and use the remaining first channel material layer 11 in the first region 10A as the first channel layer (not shown).
[0033] There is no etching selectivity between the first channel material layer 11 and the substrate 10.
[0034] Research has revealed that, due to the lack of etch selectivity between the first channel material layer 11 and the substrate 10, the top surface of the substrate 10 cannot be used as an etch stop position during the formation of the groove 13. This increases the probability of unevenness on the bottom surface of the groove 13. Consequently, during the subsequent formation of the second channel layer in the groove 13 and the patterning of the second channel layer to form fins, the height of the second channel layer is inconsistent with the effective height of the fins. This increases the difficulty of controlling the effective height of the fins and affects the performance of the semiconductor structure.
[0035] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and an adjacent second region; forming a first dielectric layer on top of the substrate in the second region, the first dielectric layer having an etching selectivity with respect to the substrate; after forming the first dielectric layer, forming a first channel layer on top of the substrate in the first region; removing the first dielectric layer to form a groove surrounded by the sidewalls of the first channel layer and the top surface of the substrate; and forming a second channel layer in the groove.
[0036] In this embodiment of the invention, a first dielectric layer is first formed on top of the substrate in the second region, with an etching selectivity between the first dielectric layer and the substrate. Then, a first channel layer is formed on top of the substrate in the first region where the first dielectric layer is exposed. During the process of removing the first dielectric layer to form a groove, the etching selectivity between the first dielectric layer and the substrate can be used to make the top surface of the substrate in the second region serve as the etching stop position, resulting in a high flatness of the bottom surface of the groove. In the subsequent process of forming the second channel layer, the flatness of the bottom surface of the second channel layer can also be high. Correspondingly, in the subsequent process of patterning the second channel layer to form fins, the effective height of the fins can be made consistent with the thickness of the second channel layer, thereby facilitating the control of the effective height of the fins and further improving the performance of the semiconductor structure.
[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0038] Figures 4 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0039] refer to Figure 4 A substrate 100 is provided, the substrate 100 including a first region 100A and a second region 100B adjacent thereto.
[0040] Specifically, substrate 100 provides a process platform for the subsequent formation of semiconductor structures.
[0041] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.
[0042] Specifically, the substrate 100 is made of silicon, which provides an epitaxial growth surface for the formation of the first channel layer during the subsequent formation of the first channel layer, facilitating the growth of single-crystal silicon on the surface of silicon through epitaxial growth process.
[0043] It should be noted that the material selected for the substrate 100 has an etching selectivity ratio with the first dielectric layer subsequently formed. During the subsequent formation of the trench, the top surface of the substrate 100 can be used as the etching stop position to completely remove the first dielectric layer, resulting in a high degree of flatness on the top surface of the trench, thus providing a process basis for the subsequent formation of the second channel layer in the trench.
[0044] Specifically, the first region 100A and the second region 100B are used as regions for forming transistors with different conductivity types.
[0045] As an example, the first region 100A is used as an NMOS region, and the second region 100B is used as a PMOS region. In other embodiments, the first region may also be used as a PMOS region, and the second region may also be used as an NMOS region.
[0046] refer to Figures 5 to 7 A first dielectric layer 104 is formed on top of the substrate 100 in the second region 100B, and the first dielectric layer 104 has an etching selectivity with respect to the substrate 100.
[0047] It should be noted that a first dielectric layer 104 is formed on the top of the substrate 100 in the second region 100B. There is an etching selectivity between the first dielectric layer 104 and the substrate 100. During the subsequent removal of the first dielectric layer 104 to form a trench, the etching selectivity between the first dielectric layer 104 and the substrate 100 can be used to make the top surface of the substrate 100 in the second region 100B serve as the etching stop position, resulting in a high flatness of the bottom surface of the trench. During the subsequent formation of the second channel layer, the flatness of the bottom surface of the second channel layer can also be high. Correspondingly, during the subsequent patterning of the second channel layer to form fins, the effective height of the fins can be made consistent with the thickness of the second channel layer, thereby facilitating the control of the effective height of the fins and further improving the performance of the semiconductor structure.
[0048] Reference Figures 5 to 7 The process steps for forming the first dielectric layer 104 on top of the substrate 100 in the second region 100B are described in detail.
[0049] refer to Figure 5 A first dielectric material layer 101 is formed on top of the substrate 100 in the first region 100A and the second region 100B.
[0050] Specifically, the first dielectric material layer 101 serves as the material layer for forming the first dielectric layer 104. Simultaneously, by forming the first dielectric material layer 101, during the subsequent patterning process of the first dielectric material layer 101 in the first region 100A, the angle at the bottom corner of the first dielectric material layer 101 in the second region 100B can be controlled through the etching process, making the angle at the bottom corner of the first dielectric material layer 101 in the second region 100B as close to 90° as possible. After subsequently removing the first dielectric material layer 101 in the second region 100B to form a groove, and forming a second channel layer in the groove, the angle at the bottom corner of the second channel layer can also be made as close to 90° as possible. Correspondingly, during the subsequent patterning process of the second channel layer to form the fin, the entire horizontal direction of the second channel layer can serve as the material layer for forming the fin, thereby increasing the process window for forming the fin and reducing the process difficulty of forming the fin.
[0051] As an example, the process for forming the first dielectric material layer 101 includes a chemical vapor deposition process.
[0052] refer to Figure 6 A mask layer 102 with a mask opening 103 is formed on the top of the first dielectric material layer 101, the mask opening 103 exposing the top surface of the first dielectric material layer 101 of the first region 100A.
[0053] It should be noted that the mask layer 102 is used as an etching mask for forming the first dielectric layer 104.
[0054] It should also be noted that by exposing the top surface of the first dielectric material layer 101 of the first region 100A, it is beneficial to remove the first dielectric material layer 101 of the first region 100A in the future, and then form the second dielectric layer on the top surface of the first channel layer formed subsequently.
[0055] As an example, the material of the mask layer 102 includes photoresist.
[0056] Specifically, photoresist is an organic material with poor stability. After the first dielectric layer 104 is formed, it is easier to remove the mask layer 102 through a chemical reaction, reducing the probability of mask layer 102 remaining on the top of the first dielectric layer 104.
[0057] In other embodiments, the mask layer may also be made of one or both of silicon oxide and silicon nitride.
[0058] refer to Figure 7 Using the mask layer 102 as a mask, the first dielectric material layer 101 in the first region 100A is patterned, and the first dielectric material layer 101 in the second region 100B is used as the first dielectric layer 104.
[0059] Specifically, by patterning the first dielectric material layer 101 of the first region 100A, the surface of the substrate 100 of the first region 100A can be exposed, providing a growth interface for the subsequent formation of the first channel layer.
[0060] As an example, the step of patterning the first dielectric material layer 101 of the first region 100A includes: taking the top surface of the substrate 100 of the first region 100A as the etching stop position, and removing the first dielectric material layer 101 on the top of the substrate 100.
[0061] It should be noted that the material selected for the substrate 100 has an etching selectivity ratio with the first dielectric material layer 101. By using the top surface of the substrate 100 of the first region 100A as the etching stop position, the first dielectric material layer 101 of the first region 100A can be completely removed, providing a better growth interface for subsequent epitaxial growth to form the first channel layer, thereby improving the film formation quality of the first channel layer.
[0062] It should also be noted that during the patterning process of the first dielectric material layer 101 of the first region 100A, the etching selectivity ratio between the first dielectric material layer 101 and the substrate 100 should not be too small. If the etching selectivity ratio between the first dielectric material layer 101 and the substrate 100 is too small, the probability of the substrate 100 of the first region 100A being over-etched during the removal of the first dielectric material layer 101 of the first region 100A increases, thereby making it impossible for the thickness of the subsequently formed first channel layer to meet the process size requirements, and increasing the probability of electrical failure of the semiconductor structure. Therefore, as an example, during the patterning process of the first dielectric material layer 101 of the first region 100A, the etching selectivity ratio between the first dielectric material layer 101 and the substrate 100 is greater than 10:1.
[0063] In this embodiment, the process for forming the first dielectric layer 104 includes a dry etching process.
[0064] Specifically, the dry etching process is an anisotropic dry etching process. Anisotropic dry etching has the characteristics of anisotropic dry etching, with a longitudinal etching rate much greater than a transverse etching rate, and has high sidewall morphology formation quality. By using the dry etching process to form the first dielectric layer 104, the angle at the bottom corner of the first dielectric layer 104 can be controlled, making the angle at the bottom corner of the first dielectric layer 104 as close to 90° as possible. After removing the first dielectric layer 104 of the second region 100B to form a groove and forming a second channel layer in the groove, the angle at the bottom corner of the second channel layer can also be made as close to 90° as possible. Correspondingly, in the subsequent patterning process of the second channel layer to form the fin, the second channel layer in the entire horizontal direction can be used as the material layer for forming the fin, thereby increasing the process window for forming the fin and reducing the process difficulty of forming the fin.
[0065] As an example, the material of the first dielectric layer 104 includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.
[0066] Specifically, silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride have a high etching selectivity with the materials selected for the substrate 100. During the subsequent removal of the first dielectric layer 104 to form a groove, the etching selectivity between the first dielectric layer 104 and the substrate 100 can be utilized to make the top surface of the substrate 100 in the second region 100B serve as the etching stop position, resulting in a high flatness of the bottom surface of the groove.
[0067] refer to Figure 8 After the first dielectric layer 104 is formed, a first channel layer 108 is formed on top of the substrate 100 in the first region 100A.
[0068] It should be noted that the first channel layer 108 is used as a material layer for the subsequent formation of fins in the NMOS region.
[0069] In this embodiment, the step of forming the first channel layer 108 includes: growing an epitaxial layer on the surface of the substrate 100 of the first region 100A by an epitaxial growth process, and using the epitaxial layer as the first channel layer 108.
[0070] Specifically, during the formation of the first channel layer 108, the material selected for the substrate 100 has a high growth selectivity ratio with the material selected for the first dielectric layer 104. During the formation of the epitaxial layer using the epitaxial growth process, the epitaxial layer is only epitaxially grown on the surface of the substrate 100 in the first region 100A.
[0071] In this embodiment, during the formation of the first channel layer 108, the top surface of the first channel layer 108 is lower than the top surface of the first dielectric layer 104.
[0072] It should be noted that the top surface of the first channel layer 108 is lower than the top surface of the first dielectric layer 104, providing a process basis for the subsequent formation of the second dielectric layer on top of the first channel layer 108. In the subsequent formation of the second channel layer, the top surface of the second dielectric layer can be used as the stop position for planarization, thereby improving the flatness of the top surface of the second channel layer.
[0073] It should also be noted that the size range between the top surface of the first channel layer 108 and the top surface of the first dielectric layer 104 should not be too large or too small. If the size range between the top surface of the first channel layer 108 and the top surface of the first dielectric layer 104 is too small, it is easy to result in a smaller thickness of the subsequently formed second dielectric layer. This makes it difficult to use the top surface of the second dielectric layer as the stopping point for planarization during the subsequent formation of the second channel layer, increasing the probability of over-planarization and low flatness of the top surface of the second channel layer. This is not conducive to controlling the effective height of the subsequently formed fins. If the size range between the top surface of the first channel layer 108 and the top surface of the first dielectric layer 104 is too large, even if the height of the first dielectric layer 104 meets the process dimensions, it means that the height of the first channel layer 108 is too low. This results in an insufficient effective height of the fins formed through the first channel layer 108, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the top surface of the first channel layer 108 is 50 angstroms to 2000 angstroms lower than the top surface of the first dielectric layer 104.
[0074] Specifically, the thickness of the first channel layer 108 should not be too large or too small. If the thickness of the first channel layer 108 is too large, it will easily lead to an excessively large overall height of the semiconductor structure, which is not conducive to further size reduction. At the same time, it will also easily lead to the top surface of the first channel layer 108 being too small below the top surface of the first dielectric layer 104. This will easily lead to a smaller thickness of the subsequently formed second dielectric layer, making it less effective to use the top surface of the second dielectric layer as the stop position for planarization during the subsequent formation of the second channel layer. This increases the probability of over-planarization and thus the probability of low flatness of the top surface of the second channel layer, which is not conducive to controlling the effective height of the subsequently formed fins. If the thickness of the first channel layer 108 is too small, it means that the height of the first channel layer 108 is too low, resulting in an excessively low effective height of the fins formed through the first channel layer 108, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the first channel layer 108 is 400 angstroms to 1000 angstroms.
[0075] In this embodiment, the material of the first channel layer 108 includes silicon.
[0076] Specifically, the first channel layer 108 is formed in the first region 100A, which is used as an NMOS region. Silicon is a commonly used conductive channel material in NMOS regions, which can improve the mobility of charge carriers.
[0077] refer to Figure 9 A second dielectric layer 112 is formed on top of the first channel layer 108.
[0078] Specifically, during the subsequent formation of the second channel layer, the top of the second dielectric layer 112 serves as the stop position for planarization. Meanwhile, during the subsequent formation of the groove, the second dielectric layer 112 protects the first channel layer 108, reducing the probability of damage to the surface of the first channel layer 108 caused by the groove formation process, thereby affecting the performance of the semiconductor structure.
[0079] As an example, the step of forming the second dielectric layer 112 includes: thermally oxidizing a surface portion of the first channel layer 108 to form an oxide layer on the top surface of the first channel layer 108, and using the oxide layer as the second dielectric layer 112.
[0080] In other embodiments, a second dielectric layer may also be deposited on top of the first channel layer using other deposition processes.
[0081] It should be noted that the thickness of the second dielectric layer 112 in the normal direction of the substrate 100 surface should not be too small or too large. If the thickness of the second dielectric layer 112 is too large, it means that the second dielectric layer 112 occupies too much of the formation area of the first channel layer 108, making the height of the first channel layer 108 too low, resulting in an insufficient effective height of the fins subsequently formed through the first channel layer 108, thus affecting the performance of the semiconductor structure. If the thickness of the second dielectric layer 112 is too small, the top surface of the second dielectric layer 112 will not be effectively used as the stop position for planarization during the subsequent formation of the second channel layer, increasing the probability of over-planarization and thus increasing the probability of low flatness of the top surface of the second channel layer, which is not conducive to controlling the effective height of the subsequently formed fins. Therefore, in this embodiment, the thickness of the second dielectric layer 112 in the normal direction of the substrate 100 surface is 50 angstroms to 300 angstroms.
[0082] refer to Figure 10 The first dielectric layer 104 is removed to form a groove 198 formed by the sidewalls of the first channel layer 108 and the top surface of the substrate 100.
[0083] Specifically, groove 198 provides the technological basis for the subsequent formation of the second channel layer.
[0084] It should be noted that during the process of removing the first dielectric layer 104 to form the groove 198, the etching selectivity between the first dielectric layer 104 and the substrate 100 can be utilized to make the top surface of the substrate 100 of the second region 100B serve as the etching stop position, resulting in a high flatness of the bottom surface of the groove 198. In the subsequent process of forming the second channel layer, the flatness of the bottom surface of the second channel layer can also be high. Correspondingly, in the subsequent process of patterning the second channel layer to form the fin, the effective height of the fin can be made consistent with the thickness of the second channel layer, thereby facilitating the control of the effective height of the fin and further improving the performance of the semiconductor structure.
[0085] As an example, the step of forming the groove 198 includes: taking the top surface of the substrate 100 of the first region 100A as the etching stop position, removing the first dielectric layer 104 of the top surface of the substrate 100 of the first region 100A, and forming a groove 198 surrounded by the sidewall of the first channel layer 108 and the top surface of the substrate 100.
[0086] It should be noted that, using the top surface of the substrate 100 in the first region 100A as the etching stop position, during the removal of the first dielectric layer 104 on the top surface of the substrate 100 in the first region 100A, the etching selectivity ratio between the first dielectric layer 104 and the substrate 100 should not be too small. If the etching selectivity ratio between the first dielectric layer 104 and the substrate 100 is too small, the probability of the substrate 100 being mistakenly etched during the removal of the first dielectric layer 104 increases, affecting the effectiveness of the top surface of the substrate 100 as the etching stop position. This increases the probability of unevenness on the bottom surface of the groove 198, causing the height of the second channel layer formed in the groove 198 to be inconsistent with the effective height of the fin formed by the subsequent patterning of the second channel layer, thus weakening the control over the effective height of the fin. Therefore, in this embodiment, the top surface of the substrate 100 of the first region 100A is used as the etching stop position. During the process of removing the first dielectric layer 104 on the top surface of the substrate 100 of the first region 100A, the etching selectivity ratio between the first dielectric layer 104 and the substrate 100 is greater than 10:1.
[0087] In this embodiment, the process for removing the first dielectric layer 104 includes a wet etching process.
[0088] It should be noted that wet etching is an isotropic etching process. Isotropic etching has the characteristics of isotropic etching, and its lateral etching rate is close to its longitudinal etching rate. By using wet etching to remove the first dielectric layer 104, the first dielectric layer 104 can be completely removed in both the lateral and longitudinal directions, reducing the risk of residue of the first dielectric layer 104.
[0089] refer to Figures 11 to 12A second channel layer 132 is formed in the groove 198.
[0090] It should be noted that the second channel layer 132 is used as a material layer for the subsequent formation of the fin.
[0091] As an example, the step of forming the second channel layer 132 includes: forming a second channel material layer 130 in the groove 198, the top surface of the second channel material layer 130 being higher than the top surface of the first channel layer 108; planarizing the second channel material layer 130 that is higher than the top surface of the first channel layer 108; and using the remaining second channel material layer 130 in the groove 198 as the second channel layer 132.
[0092] It should be noted that, since a second dielectric layer 112 is formed on the top surface of the first channel layer 108, the material forming the second channel layer 132 is not easily grown on the top surface of the second dielectric layer 112 during the formation of the second channel layer 132, so that the material of the second channel layer 132 is only grown on the top surface of the substrate 100.
[0093] As an example, the process of forming the second channel material layer 130 in the groove 198 includes an epitaxial growth process.
[0094] It should be noted that epitaxial growth is a commonly used process for forming the second channel material layer 130, and the surface of the substrate 100 can provide a high epitaxial growth surface for the second channel material layer 130, thus improving the film deposition quality of the second channel material layer 130.
[0095] As an example, during the formation of the second channel layer 132, the top surface of the second dielectric layer 112 is used as the stopping position.
[0096] Specifically, by using the top surface of the second dielectric layer 112 as the stopping position, the top surface of the second channel layer 132 has a high degree of flatness.
[0097] In this embodiment, the material of the second channel layer 132 includes germanium silicon.
[0098] Specifically, the second channel layer 132 is formed in the second region 100B, which is used as a PMOS region. Germanium and silicon are commonly used conductive channel materials in PMOS regions, which can improve the mobility of charge carriers.
[0099] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region adjacent to it; A first dielectric layer is formed on top of the substrate in the second region, and the first dielectric layer has an etching selectivity with respect to the substrate; After the first dielectric layer is formed, a first channel layer is formed on top of the substrate in the first region; Remove the first dielectric layer to form a groove surrounded by the sidewalls of the first channel layer and the top surface of the substrate; A second channel layer is formed in the groove.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a first dielectric layer on top of a substrate in the second region includes: forming a first dielectric material layer on top of substrates in the first and second regions; forming a mask layer with a mask opening on top of the first dielectric material layer, the mask opening exposing the top surface of the first dielectric material layer in the first region; using the mask layer as a mask, performing patterning processing on the first dielectric material layer in the first region, and using the first dielectric material layer in the second region as the first dielectric layer.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The step of patterning the first dielectric material layer of the first region includes: taking the top surface of the substrate of the first region as the etching stop position, and removing the first dielectric material layer on the top of the substrate.
4. The method for forming a semiconductor structure as described in claim 2, characterized in that, During the patterning process of the first dielectric material layer in the first region, the etching selectivity ratio between the first dielectric material layer and the substrate is greater than 10:
1.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric layer includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the first dielectric layer includes a dry etching process.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, During the formation of the first channel layer, the top surface of the first channel layer is lower than the top surface of the first dielectric layer.
8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The top surface of the first channel layer is 50 angstroms to 2000 angstroms below the top surface of the first dielectric layer.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the first channel layer includes: growing an epitaxial layer on the substrate surface of the first region by an epitaxial growth process, and using the epitaxial layer as the first channel layer.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the first channel layer is 400 angstroms to 1000 angstroms.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the first channel layer and before forming the groove, the method further includes: forming a second dielectric layer on top of the first channel layer; During the formation of the second channel layer, the top surface of the second dielectric layer is used as the stopping position.
12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming the second dielectric layer includes: performing a thermal oxidation treatment on a surface portion of the first channel layer to form an oxide layer located on the top surface of the first channel layer, and using the oxide layer as the second dielectric layer.
13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The thickness of the second dielectric layer is 50 angstroms to 300 angstroms in the normal direction of the substrate surface.
14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the second channel layer includes: forming a second channel material layer in the groove, wherein the top surface of the second channel material layer is higher than the top surface of the first channel layer; performing a planarization process on the second channel material layer that is higher than the top surface of the first channel layer; and using the remaining second channel material layer in the groove as the second channel layer.
15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The process of forming a second channel material layer in the groove includes an epitaxial growth process.
16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the groove includes: using the top surface of the substrate in the first region as the etching stop position, removing the first dielectric layer on the top surface of the substrate in the first region to form a groove surrounded by the sidewalls of the first channel layer and the top surface of the substrate.
17. The method for forming a semiconductor structure as described in claim 16, characterized in that, Using the top surface of the substrate in the first region as the etching stop position, during the process of removing the first dielectric layer on the top surface of the substrate in the first region, the etching selectivity ratio between the first dielectric layer and the substrate is greater than 10:
1.
18. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the first dielectric layer includes a wet etching process.
19. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first trench layer includes silicon; the material of the second trench layer includes germanium silicon.